[keystone-rtos/edma3_lld.git] / packages / ti / sdo / edma3 / rm / sample / src / platforms / sample_tci6498_cfg.c
1 /*
2 * sample_tci6498_cfg.c
3 *
4 * Platform specific EDMA3 hardware related information like number of transfer
5 * controllers, various interrupt ids etc. It is used while interrupts
6 * enabling / disabling. It needs to be ported for different SoCs.
7 *
8 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
9 *
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 *
18 * Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the
21 * distribution.
22 *
23 * Neither the name of Texas Instruments Incorporated nor the names of
24 * its contributors may be used to endorse or promote products derived
25 * from this software without specific prior written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 *
39 */
41 #include <ti/sdo/edma3/rm/edma3_rm.h>
43 /* Number of EDMA3 controllers present in the system */
44 #define NUM_EDMA3_INSTANCES 3u
45 const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;
47 /* Number of DSPs present in the system */
48 #define NUM_DSPS 4u
49 //const unsigned int numDsps = NUM_DSPS;
51 #define CGEM_REG_START (0x01800000)
53 /* Determine the processor id by reading DNUM register. */
54 unsigned short determineProcId()
55 {
56 volatile unsigned int *addr;
57 unsigned int core_no;
59 /* Identify the core number */
60 addr = (unsigned int *)(CGEM_REG_START+0x40000);
61 core_no = ((*addr) & 0x000F0000)>>16;
63 return core_no;
64 }
66 /** Whether global configuration required for EDMA3 or not.
67 * This configuration should be done only once for the EDMA3 hardware by
68 * any one of the masters (i.e. DSPs).
69 * It can be changed depending on the use-case.
70 */
71 unsigned int gblCfgReqdArray [NUM_DSPS] = {
72 0, /* DSP#0 is Master, will do the global init */
73 1, /* DSP#1 is Slave, will not do the global init */
74 1, /* DSP#2 is Slave, will not do the global init */
75 1, /* DSP#3 is Slave, will not do the global init */
76 };
78 unsigned short isGblConfigRequired(unsigned int dspNum)
79 {
80 return gblCfgReqdArray[dspNum];
81 }
83 /* Semaphore handles */
84 EDMA3_OS_Sem_Handle rmSemHandle[NUM_EDMA3_INSTANCES] = {NULL,NULL,NULL};
87 /* Variable which will be used internally for referring number of Event Queues. */
88 unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] = {2u, 4u, 4u};
90 /* Variable which will be used internally for referring number of TCs. */
91 unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] = {2u, 4u, 4u};
93 /**
94 * Variable which will be used internally for referring transfer completion
95 * interrupt. Completion interrupts for all the shadow regions and all the
96 * EDMA3 controllers are captured since it is a multi-DSP platform.
97 */
98 unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = {
99 {
100 38u, 39u, 40u, 41u,
101 42u, 43u, 44u, 45u,
102 },
103 {
104 8u, 9u, 10u, 11u,
105 12u, 13u, 14u, 15u,
106 },
107 {
108 24u, 25u, 26u, 27u,
109 28u, 29u, 30u, 31u,
110 },
111 };
114 /**
115 * Variable which will be used internally for referring channel controller's
116 * error interrupt.
117 */
118 unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {32u, 0u, 16u};
120 /**
121 * Variable which will be used internally for referring transfer controllers'
122 * error interrupts.
123 */
124 unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_TC] = {
125 {
126 34u, 35u, 0u, 0u,
127 0u, 0u, 0u, 0u,
128 },
129 {
130 2u, 3u, 4u, 5u,
131 0u, 0u, 0u, 0u,
132 },
133 {
134 18u, 19u, 20u, 21u,
135 0u, 0u, 0u, 0u,
136 },
137 };
139 /* Driver Object Initialization Configuration */
140 EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
141 {
142 {
143 /* EDMA3 INSTANCE# 0 */
144 /** Total number of DMA Channels supported by the EDMA3 Controller */
145 16u,
146 /** Total number of QDMA Channels supported by the EDMA3 Controller */
147 8u,
148 /** Total number of TCCs supported by the EDMA3 Controller */
149 16u,
150 /** Total number of PaRAM Sets supported by the EDMA3 Controller */
151 128u,
152 /** Total number of Event Queues in the EDMA3 Controller */
153 2u,
154 /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
155 2u,
156 /** Number of Regions on this EDMA3 controller */
157 8u,
159 /**
160 * \brief Channel mapping existence
161 * A value of 0 (No channel mapping) implies that there is fixed association
162 * for a channel number to a parameter entry number or, in other words,
163 * PaRAM entry n corresponds to channel n.
164 */
165 1u,
167 /** Existence of memory protection feature */
168 1u,
170 /** Global Register Region of CC Registers */
171 (void *)0x02700000u,
172 /** Transfer Controller (TC) Registers */
173 {
174 (void *)0x02760000u,
175 (void *)0x02768000u,
176 (void *)NULL,
177 (void *)NULL,
178 (void *)NULL,
179 (void *)NULL,
180 (void *)NULL,
181 (void *)NULL
182 },
183 /** Interrupt no. for Transfer Completion */
184 38u,
185 /** Interrupt no. for CC Error */
186 32u,
187 /** Interrupt no. for TCs Error */
188 {
189 34u,
190 35u,
191 0u,
192 0u,
193 0u,
194 0u,
195 0u,
196 0u,
197 },
199 /**
200 * \brief EDMA3 TC priority setting
201 *
202 * User can program the priority of the Event Queues
203 * at a system-wide level. This means that the user can set the
204 * priority of an IO initiated by either of the TCs (Transfer Controllers)
205 * relative to IO initiated by the other bus masters on the
206 * device (ARM, DSP, USB, etc)
207 */
208 {
209 0u,
210 1u,
211 0u,
212 0u,
213 0u,
214 0u,
215 0u,
216 0u
217 },
218 /**
219 * \brief To Configure the Threshold level of number of events
220 * that can be queued up in the Event queues. EDMA3CC error register
221 * (CCERR) will indicate whether or not at any instant of time the
222 * number of events queued up in any of the event queues exceeds
223 * or equals the threshold/watermark value that is set
224 * in the queue watermark threshold register (QWMTHRA).
225 */
226 {
227 16u,
228 16u,
229 0u,
230 0u,
231 0u,
232 0u,
233 0u,
234 0u
235 },
237 /**
238 * \brief To Configure the Default Burst Size (DBS) of TCs.
239 * An optimally-sized command is defined by the transfer controller
240 * default burst size (DBS). Different TCs can have different
241 * DBS values. It is defined in Bytes.
242 */
243 {
244 128u,
245 128u,
246 0u,
247 0u,
248 0u,
249 0u,
250 0u,
251 0u
252 },
254 /**
255 * \brief Mapping from each DMA channel to a Parameter RAM set,
256 * if it exists, otherwise of no use.
257 */
258 {
259 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
260 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
261 /* DMA channels 16-63 DOES NOT exist */
262 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
263 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
264 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
265 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
266 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
267 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
268 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
269 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
270 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
271 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
272 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
273 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
274 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
275 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
276 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
277 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
278 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
279 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
280 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
281 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
282 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
283 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
284 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
285 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS
286 },
288 /**
289 * \brief Mapping from each DMA channel to a TCC. This specific
290 * TCC code will be returned when the transfer is completed
291 * on the mapped channel.
292 */
293 {
294 0u, 1u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
295 4u, 5u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
296 8u, 9u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
297 12u, 13u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
298 /* DMA channels 16-63 DOES NOT exist */
299 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
300 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
301 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
302 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
303 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
304 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
305 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
306 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
307 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
308 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
309 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
310 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC
311 },
313 /**
314 * \brief Mapping of DMA channels to Hardware Events from
315 * various peripherals, which use EDMA for data transfer.
316 * All channels need not be mapped, some can be free also.
317 */
318 {
319 0x00003333u,
320 0x00000000u
321 }
322 },
324 {
325 /* EDMA3 INSTANCE# 1 */
326 /** Total number of DMA Channels supported by the EDMA3 Controller */
327 64u,
328 /** Total number of QDMA Channels supported by the EDMA3 Controller */
329 8u,
330 /** Total number of TCCs supported by the EDMA3 Controller */
331 64u,
332 /** Total number of PaRAM Sets supported by the EDMA3 Controller */
333 512u,
334 /** Total number of Event Queues in the EDMA3 Controller */
335 4u,
336 /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
337 4u,
338 /** Number of Regions on this EDMA3 controller */
339 8u,
341 /**
342 * \brief Channel mapping existence
343 * A value of 0 (No channel mapping) implies that there is fixed association
344 * for a channel number to a parameter entry number or, in other words,
345 * PaRAM entry n corresponds to channel n.
346 */
347 1u,
349 /** Existence of memory protection feature */
350 1u,
352 /** Global Register Region of CC Registers */
353 (void *)0x02720000u,
354 /** Transfer Controller (TC) Registers */
355 {
356 (void *)0x02770000u,
357 (void *)0x02778000u,
358 (void *)0x02780000u,
359 (void *)0x02788000u,
360 (void *)NULL,
361 (void *)NULL,
362 (void *)NULL,
363 (void *)NULL
364 },
365 /** Interrupt no. for Transfer Completion */
366 8u,
367 /** Interrupt no. for CC Error */
368 0u,
369 /** Interrupt no. for TCs Error */
370 {
371 2u,
372 3u,
373 4u,
374 5u,
375 0u,
376 0u,
377 0u,
378 0u,
379 },
381 /**
382 * \brief EDMA3 TC priority setting
383 *
384 * User can program the priority of the Event Queues
385 * at a system-wide level. This means that the user can set the
386 * priority of an IO initiated by either of the TCs (Transfer Controllers)
387 * relative to IO initiated by the other bus masters on the
388 * device (ARM, DSP, USB, etc)
389 */
390 {
391 0u,
392 1u,
393 2u,
394 3u,
395 0u,
396 0u,
397 0u,
398 0u
399 },
400 /**
401 * \brief To Configure the Threshold level of number of events
402 * that can be queued up in the Event queues. EDMA3CC error register
403 * (CCERR) will indicate whether or not at any instant of time the
404 * number of events queued up in any of the event queues exceeds
405 * or equals the threshold/watermark value that is set
406 * in the queue watermark threshold register (QWMTHRA).
407 */
408 {
409 16u,
410 16u,
411 16u,
412 16u,
413 0u,
414 0u,
415 0u,
416 0u
417 },
419 /**
420 * \brief To Configure the Default Burst Size (DBS) of TCs.
421 * An optimally-sized command is defined by the transfer controller
422 * default burst size (DBS). Different TCs can have different
423 * DBS values. It is defined in Bytes.
424 */
425 {
426 64u,
427 64u,
428 64u,
429 64u,
430 0u,
431 0u,
432 0u,
433 0u
434 },
436 /**
437 * \brief Mapping from each DMA channel to a Parameter RAM set,
438 * if it exists, otherwise of no use.
439 */
440 {
441 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
442 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
443 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
444 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
445 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
446 40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
447 48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
448 56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u
449 },
451 /**
452 * \brief Mapping from each DMA channel to a TCC. This specific
453 * TCC code will be returned when the transfer is completed
454 * on the mapped channel.
455 */
456 {
457 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
458 8u, 9u, 10u, 11u, 12u, 13u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
459 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
460 24u, 25u, 26u, 27u, 28u, 29u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
461 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
462 40u, 41u, 42u, 43u, 44u, 45u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
463 48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
464 56u, 57u, 58u, 59u, 60u, 61u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP
465 },
467 /**
468 * \brief Mapping of DMA channels to Hardware Events from
469 * various peripherals, which use EDMA for data transfer.
470 * All channels need not be mapped, some can be free also.
471 */
472 {
473 0x3FFF3FFFu,
474 0x3FFF3FFFu
475 }
476 },
478 {
479 /* EDMA3 INSTANCE# 2 */
480 /** Total number of DMA Channels supported by the EDMA3 Controller */
481 64u,
482 /** Total number of QDMA Channels supported by the EDMA3 Controller */
483 8u,
484 /** Total number of TCCs supported by the EDMA3 Controller */
485 64u,
486 /** Total number of PaRAM Sets supported by the EDMA3 Controller */
487 512u,
488 /** Total number of Event Queues in the EDMA3 Controller */
489 4u,
490 /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
491 4u,
492 /** Number of Regions on this EDMA3 controller */
493 8u,
495 /**
496 * \brief Channel mapping existence
497 * A value of 0 (No channel mapping) implies that there is fixed association
498 * for a channel number to a parameter entry number or, in other words,
499 * PaRAM entry n corresponds to channel n.
500 */
501 1u,
503 /** Existence of memory protection feature */
504 1u,
506 /** Global Register Region of CC Registers */
507 (void *)0x02740000u,
508 /** Transfer Controller (TC) Registers */
509 {
510 (void *)0x02790000u,
511 (void *)0x02798000u,
512 (void *)0x027A0000u,
513 (void *)0x027A8000u,
514 (void *)NULL,
515 (void *)NULL,
516 (void *)NULL,
517 (void *)NULL
518 },
519 /** Interrupt no. for Transfer Completion */
520 24u,
521 /** Interrupt no. for CC Error */
522 16u,
523 /** Interrupt no. for TCs Error */
524 {
525 18u,
526 19u,
527 20u,
528 21u,
529 0u,
530 0u,
531 0u,
532 0u,
533 },
535 /**
536 * \brief EDMA3 TC priority setting
537 *
538 * User can program the priority of the Event Queues
539 * at a system-wide level. This means that the user can set the
540 * priority of an IO initiated by either of the TCs (Transfer Controllers)
541 * relative to IO initiated by the other bus masters on the
542 * device (ARM, DSP, USB, etc)
543 */
544 {
545 0u,
546 1u,
547 2u,
548 3u,
549 0u,
550 0u,
551 0u,
552 0u
553 },
554 /**
555 * \brief To Configure the Threshold level of number of events
556 * that can be queued up in the Event queues. EDMA3CC error register
557 * (CCERR) will indicate whether or not at any instant of time the
558 * number of events queued up in any of the event queues exceeds
559 * or equals the threshold/watermark value that is set
560 * in the queue watermark threshold register (QWMTHRA).
561 */
562 {
563 16u,
564 16u,
565 16u,
566 16u,
567 0u,
568 0u,
569 0u,
570 0u
571 },
573 /**
574 * \brief To Configure the Default Burst Size (DBS) of TCs.
575 * An optimally-sized command is defined by the transfer controller
576 * default burst size (DBS). Different TCs can have different
577 * DBS values. It is defined in Bytes.
578 */
579 {
580 64u,
581 64u,
582 64u,
583 64u,
584 0u,
585 0u,
586 0u,
587 0u
588 },
590 /**
591 * \brief Mapping from each DMA channel to a Parameter RAM set,
592 * if it exists, otherwise of no use.
593 */
594 {
595 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
596 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
597 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
598 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
599 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
600 40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
601 48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
602 56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u
603 },
605 /**
606 * \brief Mapping from each DMA channel to a TCC. This specific
607 * TCC code will be returned when the transfer is completed
608 * on the mapped channel.
609 */
610 {
611 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
612 8u, 9u, 10u, 11u, 12u, 13u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
613 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
614 24u, 25u, 26u, 27u, 28u, 29u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
615 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
616 40u, 41u, 42u, 43u, 44u, 45u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
617 48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
618 56u, 57u, 58u, 59u, 60u, 61u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP
619 },
621 /**
622 * \brief Mapping of DMA channels to Hardware Events from
623 * various peripherals, which use EDMA for data transfer.
624 * All channels need not be mapped, some can be free also.
625 */
626 {
627 0x3FFF3FFFu,
628 0x3FFF3FFFu
629 }
630 },
631 };
633 EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
634 {
635 /* EDMA3 INSTANCE# 0 */
636 {
637 /* Resources owned/reserved by region 0 */
638 {
639 /* ownPaRAMSets */
640 /* 31 0 63 32 95 64 127 96 */
641 {0xFFFF000Fu, 0x00000FFFu, 0x00000000u, 0x00000000u,
642 /* 159 128 191 160 223 192 255 224 */
643 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
644 /* 287 256 319 288 351 320 383 352 */
645 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
646 /* 415 384 447 416 479 448 511 480 */
647 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
649 /* ownDmaChannels */
650 /* 31 0 63 32 */
651 {0x0000000Fu, 0x00000000u},
653 /* ownQdmaChannels */
654 /* 31 0 */
655 {0x00000003u},
657 /* ownTccs */
658 /* 31 0 63 32 */
659 {0x0000000Fu, 0x00000000u},
661 /* resvdPaRAMSets */
662 /* 31 0 63 32 95 64 127 96 */
663 {0x00000003u, 0x00000000u, 0x00000000u, 0x00000000u,
664 /* 159 128 191 160 223 192 255 224 */
665 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
666 /* 287 256 319 288 351 320 383 352 */
667 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
668 /* 415 384 447 416 479 448 511 480 */
669 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
671 /* resvdDmaChannels */
672 /* 31 0 */
673 {0x00000003u, 0x00000000u},
675 /* resvdQdmaChannels */
676 /* 31 0 */
677 {0x00000000u},
679 /* resvdTccs */
680 /* 31 0 */
681 {0x00000003u, 0x00000000u},
682 },
684 /* Resources owned/reserved by region 1 */
685 {
686 /* ownPaRAMSets */
687 /* 31 0 63 32 95 64 127 96 */
688 {0x000000F0u, 0xFFFFF000u, 0x000000FFu, 0x00000000u,
689 /* 159 128 191 160 223 192 255 224 */
690 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
691 /* 287 256 319 288 351 320 383 352 */
692 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
693 /* 415 384 447 416 479 448 511 480 */
694 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
696 /* ownDmaChannels */
697 /* 31 0 63 32 */
698 {0x000000F0u, 0x00000000u},
700 /* ownQdmaChannels */
701 /* 31 0 */
702 {0x0000000Cu},
704 /* ownTccs */
705 /* 31 0 63 32 */
706 {0x000000F0u, 0x00000000u},
708 /* resvdPaRAMSets */
709 /* 31 0 63 32 95 64 127 96 */
710 {0x00000030u, 0x00000000u, 0x00000000u, 0x00000000u,
711 /* 159 128 191 160 223 192 255 224 */
712 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
713 /* 287 256 319 288 351 320 383 352 */
714 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
715 /* 415 384 447 416 479 448 511 480 */
716 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
718 /* resvdDmaChannels */
719 /* 31 0 63 32 */
720 {0x00000030u, 0x00000000u},
722 /* resvdQdmaChannels */
723 /* 31 0 */
724 {0x00000000u},
726 /* resvdTccs */
727 /* 31 0 63 32 */
728 {0x00000030u, 0x00000000u},
729 },
731 /* Resources owned/reserved by region 2 */
732 {
733 /* ownPaRAMSets */
734 /* 31 0 63 32 95 64 127 96 */
735 {0x00000F00u, 0x00000000u, 0xFFFFFF00u, 0x0000000Fu,
736 /* 159 128 191 160 223 192 255 224 */
737 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
738 /* 287 256 319 288 351 320 383 352 */
739 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
740 /* 415 384 447 416 479 448 511 480 */
741 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
743 /* ownDmaChannels */
744 /* 31 0 63 32 */
745 {0x00000F00u, 0x00000000u},
747 /* ownQdmaChannels */
748 /* 31 0 */
749 {0x00000030u},
751 /* ownTccs */
752 /* 31 0 63 32 */
753 {0x00000F00u, 0x00000000u},
755 /* resvdPaRAMSets */
756 /* 31 0 63 32 95 64 127 96 */
757 {0x00000300u, 0x00000000u, 0x00000000u, 0x00000000u,
758 /* 159 128 191 160 223 192 255 224 */
759 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
760 /* 287 256 319 288 351 320 383 352 */
761 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
762 /* 415 384 447 416 479 448 511 480 */
763 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
765 /* resvdDmaChannels */
766 /* 31 0 63 32 */
767 {0x00000300u, 0x00000000u},
769 /* resvdQdmaChannels */
770 /* 31 0 */
771 {0x00000000u},
773 /* resvdTccs */
774 /* 31 0 63 32 */
775 {0x00000300u, 0x00000000u},
776 },
778 /* Resources owned/reserved by region 3 */
779 {
780 /* ownPaRAMSets */
781 /* 31 0 63 32 95 64 127 96 */
782 {0x0000F000u, 0x00000000u, 0x00000000u, 0xFFFFFFF0u,
783 /* 159 128 191 160 223 192 255 224 */
784 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
785 /* 287 256 319 288 351 320 383 352 */
786 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
787 /* 415 384 447 416 479 448 511 480 */
788 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
790 /* ownDmaChannels */
791 /* 31 0 63 32 */
792 {0x0000F000u, 0x00000000u},
794 /* ownQdmaChannels */
795 /* 31 0 */
796 {0x000000C0u},
798 /* ownTccs */
799 /* 31 0 63 32 */
800 {0x0000F000u, 0x00000000u},
802 /* resvdPaRAMSets */
803 /* 31 0 63 32 95 64 127 96 */
804 {0x00003000u, 0x00000000u, 0x00000000u, 0x00000000u,
805 /* 159 128 191 160 223 192 255 224 */
806 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
807 /* 287 256 319 288 351 320 383 352 */
808 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
809 /* 415 384 447 416 479 448 511 480 */
810 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
812 /* resvdDmaChannels */
813 /* 31 0 63 32 */
814 {0x00003000u, 0x00000000u},
816 /* resvdQdmaChannels */
817 /* 31 0 */
818 {0x00000000u},
820 /* resvdTccs */
821 /* 31 0 63 32 */
822 {0x00003000u, 0x00000000u},
823 },
825 /* Resources owned/reserved by region 4 */
826 {
827 /* ownPaRAMSets */
828 /* 31 0 63 32 95 64 127 96 */
829 {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
830 /* 159 128 191 160 223 192 255 224 */
831 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
832 /* 287 256 319 288 351 320 383 352 */
833 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
834 /* 415 384 447 416 479 448 511 480 */
835 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
837 /* ownDmaChannels */
838 /* 31 0 63 32 */
839 {0x00000000u, 0x00000000u},
841 /* ownQdmaChannels */
842 /* 31 0 */
843 {0x00000000u},
845 /* ownTccs */
846 /* 31 0 63 32 */
847 {0x00000000u, 0x00000000u},
849 /* resvdPaRAMSets */
850 /* 31 0 63 32 95 64 127 96 */
851 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
852 /* 159 128 191 160 223 192 255 224 */
853 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
854 /* 287 256 319 288 351 320 383 352 */
855 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
856 /* 415 384 447 416 479 448 511 480 */
857 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
859 /* resvdDmaChannels */
860 /* 31 0 63 32 */
861 {0x00000000u, 0x00000000u},
863 /* resvdQdmaChannels */
864 /* 31 0 */
865 {0x00000000u},
867 /* resvdTccs */
868 /* 31 0 63 32 */
869 {0x00000000u, 0x00000000u},
870 },
872 /* Resources owned/reserved by region 5 */
873 {
874 /* ownPaRAMSets */
875 /* 31 0 63 32 95 64 127 96 */
876 {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
877 /* 159 128 191 160 223 192 255 224 */
878 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
879 /* 287 256 319 288 351 320 383 352 */
880 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
881 /* 415 384 447 416 479 448 511 480 */
882 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
884 /* ownDmaChannels */
885 /* 31 0 63 32 */
886 {0x00000000u, 0x00000000u},
888 /* ownQdmaChannels */
889 /* 31 0 */
890 {0x00000000u},
892 /* ownTccs */
893 /* 31 0 63 32 */
894 {0x00000000u, 0x00000000u},
896 /* resvdPaRAMSets */
897 /* 31 0 63 32 95 64 127 96 */
898 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
899 /* 159 128 191 160 223 192 255 224 */
900 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
901 /* 287 256 319 288 351 320 383 352 */
902 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
903 /* 415 384 447 416 479 448 511 480 */
904 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
906 /* resvdDmaChannels */
907 /* 31 0 63 32 */
908 {0x00000000u, 0x00000000u},
910 /* resvdQdmaChannels */
911 /* 31 0 */
912 {0x00000000u},
914 /* resvdTccs */
915 /* 31 0 63 32 */
916 {0x00000000u, 0x00000000u},
917 },
919 /* Resources owned/reserved by region 6 */
920 {
921 /* ownPaRAMSets */
922 /* 31 0 63 32 95 64 127 96 */
923 {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
924 /* 159 128 191 160 223 192 255 224 */
925 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
926 /* 287 256 319 288 351 320 383 352 */
927 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
928 /* 415 384 447 416 479 448 511 480 */
929 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
931 /* ownDmaChannels */
932 /* 31 0 63 32 */
933 {0x00000000u, 0x00000000u},
935 /* ownQdmaChannels */
936 /* 31 0 */
937 {0x00000000u},
939 /* ownTccs */
940 /* 31 0 63 32 */
941 {0x00000000u, 0x00000000u},
943 /* resvdPaRAMSets */
944 /* 31 0 63 32 95 64 127 96 */
945 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
946 /* 159 128 191 160 223 192 255 224 */
947 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
948 /* 287 256 319 288 351 320 383 352 */
949 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
950 /* 415 384 447 416 479 448 511 480 */
951 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
953 /* resvdDmaChannels */
954 /* 31 0 63 32 */
955 {0x00000000u, 0x00000000u},
957 /* resvdQdmaChannels */
958 /* 31 0 */
959 {0x00000000u},
961 /* resvdTccs */
962 /* 31 0 63 32 */
963 {0x00000000u, 0x00000000u},
964 },
966 /* Resources owned/reserved by region 7 */
967 {
968 /* ownPaRAMSets */
969 /* 31 0 63 32 95 64 127 96 */
970 {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
971 /* 159 128 191 160 223 192 255 224 */
972 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
973 /* 287 256 319 288 351 320 383 352 */
974 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
975 /* 415 384 447 416 479 448 511 480 */
976 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
978 /* ownDmaChannels */
979 /* 31 0 63 32 */
980 {0x00000000u, 0x00000000u},
982 /* ownQdmaChannels */
983 /* 31 0 */
984 {0x00000000u},
986 /* ownTccs */
987 /* 31 0 63 32 */
988 {0x00000000u, 0x00000000u},
990 /* resvdPaRAMSets */
991 /* 31 0 63 32 95 64 127 96 */
992 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
993 /* 159 128 191 160 223 192 255 224 */
994 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
995 /* 287 256 319 288 351 320 383 352 */
996 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
997 /* 415 384 447 416 479 448 511 480 */
998 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1000 /* resvdDmaChannels */
1001 /* 31 0 63 32 */
1002 {0x00000000u, 0x00000000u},
1004 /* resvdQdmaChannels */
1005 /* 31 0 */
1006 {0x00000000u},
1008 /* resvdTccs */
1009 /* 31 0 63 32 */
1010 {0x00000000u, 0x00000000u},
1011 },
1012 },
1014 /* EDMA3 INSTANCE# 1 */
1015 {
1016 /* Resources owned/reserved by region 0 */
1017 {
1018 /* ownPaRAMSets */
1019 /* 31 0 63 32 95 64 127 96 */
1020 {0x0000FFFFu, 0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu,
1021 /* 159 128 191 160 223 192 255 224 */
1022 0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
1023 /* 287 256 319 288 351 320 383 352 */
1024 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1025 /* 415 384 447 416 479 448 511 480 */
1026 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1028 /* ownDmaChannels */
1029 /* 31 0 63 32 */
1030 {0x0000FFFFu, 0x00000000u},
1032 /* ownQdmaChannels */
1033 /* 31 0 */
1034 {0x00000003u},
1036 /* ownTccs */
1037 /* 31 0 63 32 */
1038 {0x0000FFFFu, 0x00000000u},
1040 /* resvdPaRAMSets */
1041 /* 31 0 63 32 95 64 127 96 */
1042 {0x00003FFFu, 0x00000000u, 0x00000000u, 0x00000000u,
1043 /* 159 128 191 160 223 192 255 224 */
1044 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1045 /* 287 256 319 288 351 320 383 352 */
1046 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1047 /* 415 384 447 416 479 448 511 480 */
1048 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1050 /* resvdDmaChannels */
1051 /* 31 0 63 32 */
1052 {0x00003FFFu, 0x00000000u},
1054 /* resvdQdmaChannels */
1055 /* 31 0 */
1056 {0x00000000u},
1058 /* resvdTccs */
1059 /* 31 0 63 32 */
1060 {0x00003FFFu, 0x00000000u},
1061 },
1063 /* Resources owned/reserved by region 1 */
1064 {
1065 /* ownPaRAMSets */
1066 /* 31 0 63 32 95 64 127 96 */
1067 {0xFFFF0000u, 0x00000000u, 0x00000000u, 0x00000000u,
1068 /* 159 128 191 160 223 192 255 224 */
1069 0x00000000u, 0xFFFF0000u, 0xFFFFFFFFu, 0xFFFFFFFFu,
1070 /* 287 256 319 288 351 320 383 352 */
1071 0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
1072 /* 415 384 447 416 479 448 511 480 */
1073 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1075 /* ownDmaChannels */
1076 /* 31 0 63 32 */
1077 {0xFFFF0000u, 0x00000000u},
1079 /* ownQdmaChannels */
1080 /* 31 0 */
1081 {0x0000000Cu},
1083 /* ownTccs */
1084 /* 31 0 63 32 */
1085 {0xFFFF0000u, 0x00000000u},
1087 /* resvdPaRAMSets */
1088 /* 31 0 63 32 95 64 127 96 */
1089 {0x3FFF0000u, 0x00000000u, 0x00000000u, 0x00000000u,
1090 /* 159 128 191 160 223 192 255 224 */
1091 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1092 /* 287 256 319 288 351 320 383 352 */
1093 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1094 /* 415 384 447 416 479 448 511 480 */
1095 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1097 /* resvdDmaChannels */
1098 /* 31 0 63 32 */
1099 {0x3FFF0000u, 0x00000000u},
1101 /* resvdQdmaChannels */
1102 /* 31 0 */
1103 {0x00000000u},
1105 /* resvdTccs */
1106 /* 31 0 63 32 */
1107 {0x3FFF0000u, 0x00000000u},
1108 },
1110 /* Resources owned/reserved by region 2 */
1111 {
1112 /* ownPaRAMSets */
1113 /* 31 0 63 32 95 64 127 96 */
1114 {0x00000000u, 0x0000FFFFu, 0x00000000u, 0x00000000u,
1115 /* 159 128 191 160 223 192 255 224 */
1116 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1117 /* 287 256 319 288 351 320 383 352 */
1118 0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
1119 /* 415 384 447 416 479 448 511 480 */
1120 0x0000FFFFu, 0x00000000u, 0x00000000u, 0x00000000u,},
1122 /* ownDmaChannels */
1123 /* 31 0 63 32 */
1124 {0x00000000u, 0x0000FFFFu},
1126 /* ownQdmaChannels */
1127 /* 31 0 */
1128 {0x00000030u},
1130 /* ownTccs */
1131 /* 31 0 63 32 */
1132 {0x00000000u, 0x0000FFFFu},
1134 /* resvdPaRAMSets */
1135 /* 31 0 63 32 95 64 127 96 */
1136 {0x00000000u, 0x00003FFFu, 0x00000000u, 0x00000000u,
1137 /* 159 128 191 160 223 192 255 224 */
1138 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1139 /* 287 256 319 288 351 320 383 352 */
1140 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1141 /* 415 384 447 416 479 448 511 480 */
1142 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1144 /* resvdDmaChannels */
1145 /* 31 0 63 32 */
1146 {0x00000000u, 0x00003FFFu},
1148 /* resvdQdmaChannels */
1149 /* 31 0 */
1150 {0x00000000u},
1152 /* resvdTccs */
1153 /* 31 0 63 32 */
1154 {0x00000000u, 0x00003FFFu},
1155 },
1157 /* Resources owned/reserved by region 3 */
1158 {
1159 /* ownPaRAMSets */
1160 /* 31 0 63 32 95 64 127 96 */
1161 {0x00000000u, 0xFFFF0000u, 0x00000000u, 0x00000000u,
1162 /* 159 128 191 160 223 192 255 224 */
1163 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1164 /* 287 256 319 288 351 320 383 352 */
1165 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1166 /* 415 384 447 416 479 448 511 480 */
1167 0xFFFF0000u, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,},
1169 /* ownDmaChannels */
1170 /* 31 0 63 32 */
1171 {0x00000000u, 0xFFFF0000u},
1173 /* ownQdmaChannels */
1174 /* 31 0 */
1175 {0x000000C0u},
1177 /* ownTccs */
1178 /* 31 0 63 32 */
1179 {0x00000000u, 0xFFFF0000u},
1181 /* resvdPaRAMSets */
1182 /* 31 0 63 32 95 64 127 96 */
1183 {0x00000000u, 0x3FFF0000u, 0x00000000u, 0x00000000u,
1184 /* 159 128 191 160 223 192 255 224 */
1185 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1186 /* 287 256 319 288 351 320 383 352 */
1187 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1188 /* 415 384 447 416 479 448 511 480 */
1189 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1191 /* resvdDmaChannels */
1192 /* 31 0 63 32 */
1193 {0x00000000u, 0x3FFF0000u},
1195 /* resvdQdmaChannels */
1196 /* 31 0 */
1197 {0x00000000u},
1199 /* resvdTccs */
1200 /* 31 0 63 32 */
1201 {0x00000000u, 0x3FFF0000u},
1202 },
1204 /* Resources owned/reserved by region 4 */
1205 {
1206 /* ownPaRAMSets */
1207 /* 31 0 63 32 95 64 127 96 */
1208 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1209 /* 159 128 191 160 223 192 255 224 */
1210 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1211 /* 287 256 319 288 351 320 383 352 */
1212 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1213 /* 415 384 447 416 479 448 511 480 */
1214 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1216 /* ownDmaChannels */
1217 /* 31 0 63 32 */
1218 {0x00000000u, 0x00000000u},
1220 /* ownQdmaChannels */
1221 /* 31 0 */
1222 {0x00000000u},
1224 /* ownTccs */
1225 /* 31 0 63 32 */
1226 {0x00000000u, 0x00000000u},
1228 /* resvdPaRAMSets */
1229 /* 31 0 63 32 95 64 127 96 */
1230 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1231 /* 159 128 191 160 223 192 255 224 */
1232 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1233 /* 287 256 319 288 351 320 383 352 */
1234 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1235 /* 415 384 447 416 479 448 511 480 */
1236 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1238 /* resvdDmaChannels */
1239 /* 31 0 63 32 */
1240 {0x00000000u, 0x00000000u},
1242 /* resvdQdmaChannels */
1243 /* 31 0 */
1244 {0x00000000u},
1246 /* resvdTccs */
1247 /* 31 0 63 32 */
1248 {0x00000000u, 0x00000000u},
1249 },
1251 /* Resources owned/reserved by region 5 */
1252 {
1253 /* ownPaRAMSets */
1254 /* 31 0 63 32 95 64 127 96 */
1255 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1256 /* 159 128 191 160 223 192 255 224 */
1257 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1258 /* 287 256 319 288 351 320 383 352 */
1259 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1260 /* 415 384 447 416 479 448 511 480 */
1261 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1263 /* ownDmaChannels */
1264 /* 31 0 63 32 */
1265 {0x00000000u, 0x00000000u},
1267 /* ownQdmaChannels */
1268 /* 31 0 */
1269 {0x00000000u},
1271 /* ownTccs */
1272 /* 31 0 63 32 */
1273 {0x00000000u, 0x00000000u},
1275 /* resvdPaRAMSets */
1276 /* 31 0 63 32 95 64 127 96 */
1277 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1278 /* 159 128 191 160 223 192 255 224 */
1279 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1280 /* 287 256 319 288 351 320 383 352 */
1281 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1282 /* 415 384 447 416 479 448 511 480 */
1283 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1285 /* resvdDmaChannels */
1286 /* 31 0 63 32 */
1287 {0x00000000u, 0x00000000u},
1289 /* resvdQdmaChannels */
1290 /* 31 0 */
1291 {0x00000000u},
1293 /* resvdTccs */
1294 /* 31 0 63 32 */
1295 {0x00000000u, 0x00000000u},
1296 },
1298 /* Resources owned/reserved by region 6 */
1299 {
1300 /* ownPaRAMSets */
1301 /* 31 0 63 32 95 64 127 96 */
1302 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1303 /* 159 128 191 160 223 192 255 224 */
1304 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1305 /* 287 256 319 288 351 320 383 352 */
1306 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1307 /* 415 384 447 416 479 448 511 480 */
1308 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1310 /* ownDmaChannels */
1311 /* 31 0 63 32 */
1312 {0x00000000u, 0x00000000u},
1314 /* ownQdmaChannels */
1315 /* 31 0 */
1316 {0x00000000u},
1318 /* ownTccs */
1319 /* 31 0 63 32 */
1320 {0x00000000u, 0x00000000u},
1322 /* resvdPaRAMSets */
1323 /* 31 0 63 32 95 64 127 96 */
1324 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1325 /* 159 128 191 160 223 192 255 224 */
1326 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1327 /* 287 256 319 288 351 320 383 352 */
1328 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1329 /* 415 384 447 416 479 448 511 480 */
1330 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1332 /* resvdDmaChannels */
1333 /* 31 0 63 32 */
1334 {0x00000000u, 0x00000000u},
1336 /* resvdQdmaChannels */
1337 /* 31 0 */
1338 {0x00000000u},
1340 /* resvdTccs */
1341 /* 31 0 63 32 */
1342 {0x00000000u, 0x00000000u},
1343 },
1345 /* Resources owned/reserved by region 7 */
1346 {
1347 /* ownPaRAMSets */
1348 /* 31 0 63 32 95 64 127 96 */
1349 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1350 /* 159 128 191 160 223 192 255 224 */
1351 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1352 /* 287 256 319 288 351 320 383 352 */
1353 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1354 /* 415 384 447 416 479 448 511 480 */
1355 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1357 /* ownDmaChannels */
1358 /* 31 0 63 32 */
1359 {0x00000000u, 0x00000000u},
1361 /* ownQdmaChannels */
1362 /* 31 0 */
1363 {0x00000000u},
1365 /* ownTccs */
1366 /* 31 0 63 32 */
1367 {0x00000000u, 0x00000000u},
1369 /* resvdPaRAMSets */
1370 /* 31 0 63 32 95 64 127 96 */
1371 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1372 /* 159 128 191 160 223 192 255 224 */
1373 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1374 /* 287 256 319 288 351 320 383 352 */
1375 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1376 /* 415 384 447 416 479 448 511 480 */
1377 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1379 /* resvdDmaChannels */
1380 /* 31 0 63 32 */
1381 {0x00000000u, 0x00000000u},
1383 /* resvdQdmaChannels */
1384 /* 31 0 */
1385 {0x00000000u},
1387 /* resvdTccs */
1388 /* 31 0 63 32 */
1389 {0x00000000u, 0x00000000u},
1390 },
1391 },
1393 /* EDMA3 INSTANCE# 2 */
1394 {
1395 /* Resources owned/reserved by region 0 */
1396 {
1397 /* ownPaRAMSets */
1398 /* 31 0 63 32 95 64 127 96 */
1399 {0x0000FFFFu, 0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu,
1400 /* 159 128 191 160 223 192 255 224 */
1401 0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
1402 /* 287 256 319 288 351 320 383 352 */
1403 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1404 /* 415 384 447 416 479 448 511 480 */
1405 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1407 /* ownDmaChannels */
1408 /* 31 0 63 32 */
1409 {0x0000FFFFu, 0x00000000u},
1411 /* ownQdmaChannels */
1412 /* 31 0 */
1413 {0x00000003u},
1415 /* ownTccs */
1416 /* 31 0 63 32 */
1417 {0x0000FFFFu, 0x00000000u},
1419 /* resvdPaRAMSets */
1420 /* 31 0 63 32 95 64 127 96 */
1421 {0x00003FFFu, 0x00000000u, 0x00000000u, 0x00000000u,
1422 /* 159 128 191 160 223 192 255 224 */
1423 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1424 /* 287 256 319 288 351 320 383 352 */
1425 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1426 /* 415 384 447 416 479 448 511 480 */
1427 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1429 /* resvdDmaChannels */
1430 /* 31 0 63 32 */
1431 {0x00003FFFu, 0x00000000u},
1433 /* resvdQdmaChannels */
1434 /* 31 0 */
1435 {0x00000000u},
1437 /* resvdTccs */
1438 /* 31 0 63 32 */
1439 {0x00003FFFu, 0x00000000u},
1440 },
1442 /* Resources owned/reserved by region 1 */
1443 {
1444 /* ownPaRAMSets */
1445 /* 31 0 63 32 95 64 127 96 */
1446 {0xFFFF0000u, 0x00000000u, 0x00000000u, 0x00000000u,
1447 /* 159 128 191 160 223 192 255 224 */
1448 0x00000000u, 0xFFFF0000u, 0xFFFFFFFFu, 0xFFFFFFFFu,
1449 /* 287 256 319 288 351 320 383 352 */
1450 0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
1451 /* 415 384 447 416 479 448 511 480 */
1452 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1454 /* ownDmaChannels */
1455 /* 31 0 63 32 */
1456 {0xFFFF0000u, 0x00000000u},
1458 /* ownQdmaChannels */
1459 /* 31 0 */
1460 {0x0000000Cu},
1462 /* ownTccs */
1463 /* 31 0 63 32 */
1464 {0xFFFF0000u, 0x00000000u},
1466 /* resvdPaRAMSets */
1467 /* 31 0 63 32 95 64 127 96 */
1468 {0x3FFF0000u, 0x00000000u, 0x00000000u, 0x00000000u,
1469 /* 159 128 191 160 223 192 255 224 */
1470 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1471 /* 287 256 319 288 351 320 383 352 */
1472 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1473 /* 415 384 447 416 479 448 511 480 */
1474 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1476 /* resvdDmaChannels */
1477 /* 31 0 63 32 */
1478 {0x3FFF0000u, 0x00000000u},
1480 /* resvdQdmaChannels */
1481 /* 31 0 */
1482 {0x00000000u},
1484 /* resvdTccs */
1485 /* 31 0 63 32 */
1486 {0x3FFF0000u, 0x00000000u},
1487 },
1489 /* Resources owned/reserved by region 2 */
1490 {
1491 /* ownPaRAMSets */
1492 /* 31 0 63 32 95 64 127 96 */
1493 {0x00000000u, 0x0000FFFFu, 0x00000000u, 0x00000000u,
1494 /* 159 128 191 160 223 192 255 224 */
1495 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1496 /* 287 256 319 288 351 320 383 352 */
1497 0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
1498 /* 415 384 447 416 479 448 511 480 */
1499 0x0000FFFFu, 0x00000000u, 0x00000000u, 0x00000000u,},
1501 /* ownDmaChannels */
1502 /* 31 0 63 32 */
1503 {0x00000000u, 0x0000FFFFu},
1505 /* ownQdmaChannels */
1506 /* 31 0 */
1507 {0x00000030u},
1509 /* ownTccs */
1510 /* 31 0 63 32 */
1511 {0x00000000u, 0x0000FFFFu},
1513 /* resvdPaRAMSets */
1514 /* 31 0 63 32 95 64 127 96 */
1515 {0x00000000u, 0x00003FFFu, 0x00000000u, 0x00000000u,
1516 /* 159 128 191 160 223 192 255 224 */
1517 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1518 /* 287 256 319 288 351 320 383 352 */
1519 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1520 /* 415 384 447 416 479 448 511 480 */
1521 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1523 /* resvdDmaChannels */
1524 /* 31 0 63 32 */
1525 {0x00000000u, 0x00003FFFu},
1527 /* resvdQdmaChannels */
1528 /* 31 0 */
1529 {0x00000000u},
1531 /* resvdTccs */
1532 /* 31 0 63 32 */
1533 {0x00000000u, 0x00003FFFu},
1534 },
1536 /* Resources owned/reserved by region 3 */
1537 {
1538 /* ownPaRAMSets */
1539 /* 31 0 63 32 95 64 127 96 */
1540 {0x00000000u, 0xFFFF0000u, 0x00000000u, 0x00000000u,
1541 /* 159 128 191 160 223 192 255 224 */
1542 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1543 /* 287 256 319 288 351 320 383 352 */
1544 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1545 /* 415 384 447 416 479 448 511 480 */
1546 0xFFFF0000u, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,},
1548 /* ownDmaChannels */
1549 /* 31 0 63 32 */
1550 {0x00000000u, 0xFFFF0000u},
1552 /* ownQdmaChannels */
1553 /* 31 0 */
1554 {0x000000C0u},
1556 /* ownTccs */
1557 /* 31 0 63 32 */
1558 {0x00000000u, 0xFFFF0000u},
1560 /* resvdPaRAMSets */
1561 /* 31 0 63 32 95 64 127 96 */
1562 {0x00000000u, 0x3FFF0000u, 0x00000000u, 0x00000000u,
1563 /* 159 128 191 160 223 192 255 224 */
1564 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1565 /* 287 256 319 288 351 320 383 352 */
1566 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1567 /* 415 384 447 416 479 448 511 480 */
1568 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1570 /* resvdDmaChannels */
1571 /* 31 0 63 32 */
1572 {0x00000000u, 0x3FFF0000u},
1574 /* resvdQdmaChannels */
1575 /* 31 0 */
1576 {0x00000000u},
1578 /* resvdTccs */
1579 /* 31 0 63 32 */
1580 {0x00000000u, 0x3FFF0000u},
1581 },
1583 /* Resources owned/reserved by region 4 */
1584 {
1585 /* ownPaRAMSets */
1586 /* 31 0 63 32 95 64 127 96 */
1587 {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
1588 /* 159 128 191 160 223 192 255 224 */
1589 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1590 /* 287 256 319 288 351 320 383 352 */
1591 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1592 /* 415 384 447 416 479 448 511 480 */
1593 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1595 /* ownDmaChannels */
1596 /* 31 0 63 32 */
1597 {0x00000000u, 0x00000000u},
1599 /* ownQdmaChannels */
1600 /* 31 0 */
1601 {0x00000000u},
1603 /* ownTccs */
1604 /* 31 0 63 32 */
1605 {0x00000000u, 0x00000000u},
1607 /* resvdPaRAMSets */
1608 /* 31 0 63 32 95 64 127 96 */
1609 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1610 /* 159 128 191 160 223 192 255 224 */
1611 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1612 /* 287 256 319 288 351 320 383 352 */
1613 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1614 /* 415 384 447 416 479 448 511 480 */
1615 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1617 /* resvdDmaChannels */
1618 /* 31 0 63 32 */
1619 {0x00000000u, 0x00000000u},
1621 /* resvdQdmaChannels */
1622 /* 31 0 */
1623 {0x00000000u},
1625 /* resvdTccs */
1626 /* 31 0 63 32 */
1627 {0x00000000u, 0x00000000u},
1628 },
1630 /* Resources owned/reserved by region 5 */
1631 {
1632 /* ownPaRAMSets */
1633 /* 31 0 63 32 95 64 127 96 */
1634 {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
1635 /* 159 128 191 160 223 192 255 224 */
1636 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1637 /* 287 256 319 288 351 320 383 352 */
1638 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1639 /* 415 384 447 416 479 448 511 480 */
1640 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1642 /* ownDmaChannels */
1643 /* 31 0 63 32 */
1644 {0x00000000u, 0x00000000u},
1646 /* ownQdmaChannels */
1647 /* 31 0 */
1648 {0x00000000u},
1650 /* ownTccs */
1651 /* 31 0 63 32 */
1652 {0x00000000u, 0x00000000u},
1654 /* resvdPaRAMSets */
1655 /* 31 0 63 32 95 64 127 96 */
1656 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1657 /* 159 128 191 160 223 192 255 224 */
1658 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1659 /* 287 256 319 288 351 320 383 352 */
1660 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1661 /* 415 384 447 416 479 448 511 480 */
1662 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1664 /* resvdDmaChannels */
1665 /* 31 0 63 32 */
1666 {0x00000000u, 0x00000000u},
1668 /* resvdQdmaChannels */
1669 /* 31 0 */
1670 {0x00000000u},
1672 /* resvdTccs */
1673 /* 31 0 63 32 */
1674 {0x00000000u, 0x00000000u},
1675 },
1677 /* Resources owned/reserved by region 6 */
1678 {
1679 /* ownPaRAMSets */
1680 /* 31 0 63 32 95 64 127 96 */
1681 {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
1682 /* 159 128 191 160 223 192 255 224 */
1683 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1684 /* 287 256 319 288 351 320 383 352 */
1685 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1686 /* 415 384 447 416 479 448 511 480 */
1687 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1689 /* ownDmaChannels */
1690 /* 31 0 63 32 */
1691 {0x00000000u, 0x00000000u},
1693 /* ownQdmaChannels */
1694 /* 31 0 */
1695 {0x00000000u},
1697 /* ownTccs */
1698 /* 31 0 63 32 */
1699 {0x00000000u, 0x00000000u},
1701 /* resvdPaRAMSets */
1702 /* 31 0 63 32 95 64 127 96 */
1703 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1704 /* 159 128 191 160 223 192 255 224 */
1705 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1706 /* 287 256 319 288 351 320 383 352 */
1707 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1708 /* 415 384 447 416 479 448 511 480 */
1709 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1711 /* resvdDmaChannels */
1712 /* 31 0 63 32 */
1713 {0x00000000u, 0x00000000u},
1715 /* resvdQdmaChannels */
1716 /* 31 0 */
1717 {0x00000000u},
1719 /* resvdTccs */
1720 /* 31 0 63 32 */
1721 {0x00000000u, 0x00000000u},
1722 },
1724 /* Resources owned/reserved by region 7 */
1725 {
1726 /* ownPaRAMSets */
1727 /* 31 0 63 32 95 64 127 96 */
1728 {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
1729 /* 159 128 191 160 223 192 255 224 */
1730 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1731 /* 287 256 319 288 351 320 383 352 */
1732 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1733 /* 415 384 447 416 479 448 511 480 */
1734 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1736 /* ownDmaChannels */
1737 /* 31 0 63 32 */
1738 {0x00000000u, 0x00000000u},
1740 /* ownQdmaChannels */
1741 /* 31 0 */
1742 {0x00000000u},
1744 /* ownTccs */
1745 /* 31 0 63 32 */
1746 {0x00000000u, 0x00000000u},
1748 /* resvdPaRAMSets */
1749 /* 31 0 63 32 95 64 127 96 */
1750 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1751 /* 159 128 191 160 223 192 255 224 */
1752 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1753 /* 287 256 319 288 351 320 383 352 */
1754 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1755 /* 415 384 447 416 479 448 511 480 */
1756 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1758 /* resvdDmaChannels */
1759 /* 31 0 63 32 */
1760 {0x00000000u, 0x00000000u},
1762 /* resvdQdmaChannels */
1763 /* 31 0 */
1764 {0x00000000u},
1766 /* resvdTccs */
1767 /* 31 0 63 32 */
1768 {0x00000000u, 0x00000000u},
1769 },
1770 },
1771 };
1773 /* End of File */