Adding TCI6498 support in RM sample init lib
[keystone-rtos/edma3_lld.git] / packages / ti / sdo / edma3 / rm / sample / src / platforms / sample_tci6498_int_reg.c
1 /*
2  * sample_tci6498_int_reg.c
3  *
4  * Platform specific interrupt registration and un-registration routines.
5  *
6  * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
7  *
8  *
9  *  Redistribution and use in source and binary forms, with or without
10  *  modification, are permitted provided that the following conditions
11  *  are met:
12  *
13  *    Redistributions of source code must retain the above copyright
14  *    notice, this list of conditions and the following disclaimer.
15  *
16  *    Redistributions in binary form must reproduce the above copyright
17  *    notice, this list of conditions and the following disclaimer in the
18  *    documentation and/or other materials provided with the
19  *    distribution.
20  *
21  *    Neither the name of Texas Instruments Incorporated nor the names of
22  *    its contributors may be used to endorse or promote products derived
23  *    from this software without specific prior written permission.
24  *
25  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36  *
37 */
39 #include <ti/sysbios/ipc/Semaphore.h>
40 #include <ti/sysbios/family/c64p/Hwi.h>
41 #include <ti/sysbios/family/c64p/EventCombiner.h>
42 #include <ti/sysbios/family/c64p/tci6498/CpIntc.h>
44 #include <ti/sdo/edma3/rm/sample/bios6_edma3_rm_sample.h>
46 extern unsigned int ccXferCompInt[][EDMA3_MAX_REGIONS];
47 extern unsigned int ccErrorInt[];
48 extern unsigned int tcErrorInt[][EDMA3_MAX_TC];
49 extern unsigned int numEdma3Tc[];
51 void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(unsigned int arg) =
52                                                 {
53                                                 &lisrEdma3TC0ErrHandler0,
54                                                 &lisrEdma3TC1ErrHandler0,
55                                                 &lisrEdma3TC2ErrHandler0,
56                                                 &lisrEdma3TC3ErrHandler0,
57                                                 &lisrEdma3TC4ErrHandler0,
58                                                 &lisrEdma3TC5ErrHandler0,
59                                                 &lisrEdma3TC6ErrHandler0,
60                                                 &lisrEdma3TC7ErrHandler0,
61                                                 };
63 unsigned int hwiInterrupt = 8;
65 /* Host interrupts for transfer completion */
66 //unsigned int ccXferHostInt[NUM_EDMA3_INSTANCES][NUM_DSPS] = {
67 unsigned int ccXferHostInt[3][4] = {
68                                                                                 {0u, 16u, 32u, 48u},
69                                                                                 {1u, 17u, 33u, 49u},
70                                                                                 {2u, 18u, 34u, 50u},
71                                                                                 };
72 unsigned int edma3ErrHostInt[3][4] = {
73                                                                                 {3u, 19u, 35u, 51u},
74                                                                                 {4u, 20u, 36u, 52u},
75                                                                                 {5u, 21u, 37u, 53u},
76                                                                                 };
79 extern unsigned int dsp_num;
81 /**  To Register the ISRs with the underlying OS, if required */
82 void registerEdma3Interrupts (unsigned int edma3Id)
83     {
84     static UInt32 cookie = 0;
85     Int eventId = 0;    /* GEM event id */
86         unsigned int numTc = 0;
88     /* Disabling the global interrupts */
89     cookie = Hwi_disable();
91         /* Transfer completion ISR */
92         CpIntc_dispatchPlug(ccXferCompInt[edma3Id][dsp_num],
93                                                 lisrEdma3ComplHandler0,
94                                                 edma3Id,
95                                                 TRUE);
96         CpIntc_mapSysIntToHostInt(0, ccXferCompInt[edma3Id][dsp_num],
97                                                                 ccXferHostInt[edma3Id][dsp_num]);
98         CpIntc_enableHostInt(0, ccXferHostInt[edma3Id][dsp_num]);
99     eventId = CpIntc_getEventId(ccXferHostInt[edma3Id][dsp_num]);
100     EventCombiner_dispatchPlug (eventId, CpIntc_dispatch,
101                                 ccXferHostInt[edma3Id][dsp_num], TRUE);
102         EventCombiner_enableEvent(eventId);
104         /* CC Error ISR */
105         CpIntc_dispatchPlug(ccErrorInt[edma3Id], lisrEdma3CCErrHandler0,
106                                                 edma3Id, TRUE);
107         CpIntc_mapSysIntToHostInt(0, ccErrorInt[edma3Id],
108                                                                 edma3ErrHostInt[edma3Id][dsp_num]);
109         /* TC Error ISR */
110     while (numTc < numEdma3Tc[edma3Id])
111             {
112                 CpIntc_dispatchPlug(tcErrorInt[edma3Id][numTc],
113                                                         (CpIntc_FuncPtr )(ptrEdma3TcIsrHandler[numTc]),
114                                                         edma3Id, TRUE);
115                 CpIntc_mapSysIntToHostInt(0, tcErrorInt[edma3Id][numTc],
116                                                                         edma3ErrHostInt[edma3Id][dsp_num]);
117         numTc++;
118         }
119         /* Enable the host interrupt which is common for both CC and TC error */
120         CpIntc_enableHostInt(0, edma3ErrHostInt[edma3Id][dsp_num]);
121     eventId = CpIntc_getEventId(edma3ErrHostInt[edma3Id][dsp_num]);
122     EventCombiner_dispatchPlug (eventId, CpIntc_dispatch,
123                                 edma3ErrHostInt[edma3Id][dsp_num], TRUE);
124         EventCombiner_enableEvent(eventId);
126     Hwi_enableInterrupt(hwiInterrupt);
128     /* enable the 'global' switch */
129     CpIntc_enableAllHostInts(0);
131     /* Restore interrupts */
132     Hwi_restore(cookie);
133     }
135 /**  To Unregister the ISRs with the underlying OS, if previously registered. */
136 void unregisterEdma3Interrupts (unsigned int edma3Id)
137     {
138     static UInt32 cookie = 0;
139     Int eventId = 0;    /* GEM event id */
141     /* Disabling the global interrupts */
142     cookie = Hwi_disable();
144         /* Transfer completion ISR */
145         CpIntc_disableHostInt(0, ccXferHostInt[edma3Id][dsp_num]);
146     eventId = CpIntc_getEventId(ccXferHostInt[edma3Id][dsp_num]);
147         EventCombiner_disableEvent(eventId);
149         /* CC/TC Error ISR */
150         CpIntc_disableHostInt(0, edma3ErrHostInt[edma3Id][dsp_num]);
151     eventId = CpIntc_getEventId(edma3ErrHostInt[edma3Id][dsp_num]);
152         EventCombiner_disableEvent(eventId);
154     /* Restore interrupts */
155     Hwi_restore(cookie);
156     }