[keystone-rtos/edma3_lld.git] / packages / ti / sdo / edma3 / rm / sample / src / platforms / sample_tci6608_cfg.c
1 /*
2 * sample_tci6608_cfg.c
3 *
4 * Platform specific EDMA3 hardware related information like number of transfer
5 * controllers, various interrupt ids etc. It is used while interrupts
6 * enabling / disabling. It needs to be ported for different SoCs.
7 *
8 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
9 *
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 *
18 * Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the
21 * distribution.
22 *
23 * Neither the name of Texas Instruments Incorporated nor the names of
24 * its contributors may be used to endorse or promote products derived
25 * from this software without specific prior written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 *
39 */
41 #include <ti/sdo/edma3/rm/edma3_rm.h>
43 /* Number of EDMA3 controllers present in the system */
44 #define NUM_EDMA3_INSTANCES 3u
45 const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;
47 /* Number of DSPs present in the system */
48 #define NUM_DSPS 8u
49 //const unsigned int numDsps = NUM_DSPS;
51 #define CGEM_REG_START (0x01800000)
53 extern cregister volatile unsigned int DNUM;
57 #define MAP_LOCAL_TO_GLOBAL_ADDR(addr) ((1<<28)|(DNUM<<24)|(((unsigned int)addr)&0x00ffffff))
58 /* Determine the processor id by reading DNUM register. */
59 unsigned short determineProcId()
60 {
61 volatile unsigned int *addr;
62 unsigned int core_no;
64 /* Identify the core number */
65 addr = (unsigned int *)(CGEM_REG_START+0x40000);
66 core_no = ((*addr) & 0x000F0000)>>16;
68 return core_no;
69 }
71 signed char* getGlobalAddr(signed char* addr)
72 {
73 if (((unsigned int)addr & (unsigned int)0xFF000000) != 0)
74 {
75 return (addr); /* The address is already a global address */
76 }
78 return((signed char*)(MAP_LOCAL_TO_GLOBAL_ADDR(addr)));
79 }
80 /** Whether global configuration required for EDMA3 or not.
81 * This configuration should be done only once for the EDMA3 hardware by
82 * any one of the masters (i.e. DSPs).
83 * It can be changed depending on the use-case.
84 */
85 unsigned int gblCfgReqdArray [NUM_DSPS] = {
86 0, /* DSP#0 is Master, will do the global init */
87 1, /* DSP#1 is Slave, will not do the global init */
88 1, /* DSP#2 is Slave, will not do the global init */
89 1, /* DSP#3 is Slave, will not do the global init */
90 1, /* DSP#4 is Slave, will not do the global init */
91 1, /* DSP#5 is Slave, will not do the global init */
92 1, /* DSP#6 is Slave, will not do the global init */
93 1, /* DSP#7 is Slave, will not do the global init */
94 };
96 unsigned short isGblConfigRequired(unsigned int dspNum)
97 {
98 return gblCfgReqdArray[dspNum];
99 }
101 /* Semaphore handles */
102 EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL,NULL,NULL};
105 /* Variable which will be used internally for referring number of Event Queues. */
106 unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] = {2u, 4u, 4u};
108 /* Variable which will be used internally for referring number of TCs. */
109 unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] = {2u, 4u, 4u};
111 /**
112 * Variable which will be used internally for referring transfer completion
113 * interrupt. Completion interrupts for all the shadow regions and all the
114 * EDMA3 controllers are captured since it is a multi-DSP platform.
115 */
116 unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = {
117 {
118 38u, 39u, 40u, 41u,
119 42u, 43u, 44u, 45u,
120 },
121 {
122 8u, 9u, 10u, 11u,
123 12u, 13u, 14u, 15u,
124 },
125 {
126 24u, 25u, 26u, 27u,
127 28u, 29u, 30u, 31u,
128 },
129 };
131 /**
132 * Variable which will be used internally for referring channel controller's
133 * error interrupt.
134 */
135 unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {32u, 0u, 16u};
137 /**
138 * Variable which will be used internally for referring transfer controllers'
139 * error interrupts.
140 */
141 unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_TC] = {
142 {
143 34u, 35u, 0u, 0u,
144 0u, 0u, 0u, 0u,
145 },
146 {
147 2u, 3u, 4u, 5u,
148 0u, 0u, 0u, 0u,
149 },
150 {
151 18u, 19u, 20u, 21u,
152 0u, 0u, 0u, 0u,
153 },
154 };
156 /* Driver Object Initialization Configuration */
157 EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
158 {
159 {
160 /* EDMA3 INSTANCE# 0 */
161 /** Total number of DMA Channels supported by the EDMA3 Controller */
162 16u,
163 /** Total number of QDMA Channels supported by the EDMA3 Controller */
164 8u,
165 /** Total number of TCCs supported by the EDMA3 Controller */
166 16u,
167 /** Total number of PaRAM Sets supported by the EDMA3 Controller */
168 128u,
169 /** Total number of Event Queues in the EDMA3 Controller */
170 2u,
171 /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
172 2u,
173 /** Number of Regions on this EDMA3 controller */
174 8u,
176 /**
177 * \brief Channel mapping existence
178 * A value of 0 (No channel mapping) implies that there is fixed association
179 * for a channel number to a parameter entry number or, in other words,
180 * PaRAM entry n corresponds to channel n.
181 */
182 1u,
184 /** Existence of memory protection feature */
185 1u,
187 /** Global Register Region of CC Registers */
188 (void *)0x02700000u,
189 /** Transfer Controller (TC) Registers */
190 {
191 (void *)0x02760000u,
192 (void *)0x02768000u,
193 (void *)NULL,
194 (void *)NULL,
195 (void *)NULL,
196 (void *)NULL,
197 (void *)NULL,
198 (void *)NULL
199 },
200 /** Interrupt no. for Transfer Completion */
201 38u,
202 /** Interrupt no. for CC Error */
203 32u,
204 /** Interrupt no. for TCs Error */
205 {
206 34u,
207 35u,
208 0u,
209 0u,
210 0u,
211 0u,
212 0u,
213 0u,
214 },
216 /**
217 * \brief EDMA3 TC priority setting
218 *
219 * User can program the priority of the Event Queues
220 * at a system-wide level. This means that the user can set the
221 * priority of an IO initiated by either of the TCs (Transfer Controllers)
222 * relative to IO initiated by the other bus masters on the
223 * device (ARM, DSP, USB, etc)
224 */
225 {
226 0u,
227 1u,
228 0u,
229 0u,
230 0u,
231 0u,
232 0u,
233 0u
234 },
235 /**
236 * \brief To Configure the Threshold level of number of events
237 * that can be queued up in the Event queues. EDMA3CC error register
238 * (CCERR) will indicate whether or not at any instant of time the
239 * number of events queued up in any of the event queues exceeds
240 * or equals the threshold/watermark value that is set
241 * in the queue watermark threshold register (QWMTHRA).
242 */
243 {
244 16u,
245 16u,
246 0u,
247 0u,
248 0u,
249 0u,
250 0u,
251 0u
252 },
254 /**
255 * \brief To Configure the Default Burst Size (DBS) of TCs.
256 * An optimally-sized command is defined by the transfer controller
257 * default burst size (DBS). Different TCs can have different
258 * DBS values. It is defined in Bytes.
259 */
260 {
261 128u,
262 128u,
263 0u,
264 0u,
265 0u,
266 0u,
267 0u,
268 0u
269 },
271 /**
272 * \brief Mapping from each DMA channel to a Parameter RAM set,
273 * if it exists, otherwise of no use.
274 */
275 {
276 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
277 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
278 /* DMA channels 16-63 DOES NOT exist */
279 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
280 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
281 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
282 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
283 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
284 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
285 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
286 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
287 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
288 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
289 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
290 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
291 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
292 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
293 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
294 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
295 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
296 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
297 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
298 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
299 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
300 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
301 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
302 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS
303 },
305 /**
306 * \brief Mapping from each DMA channel to a TCC. This specific
307 * TCC code will be returned when the transfer is completed
308 * on the mapped channel.
309 */
310 {
311 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
312 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
313 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
314 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
315 /* DMA channels 16-63 DOES NOT exist */
316 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
317 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
318 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
319 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
320 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
321 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
322 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
323 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
324 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
325 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
326 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
327 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC
328 },
330 /**
331 * \brief Mapping of DMA channels to Hardware Events from
332 * various peripherals, which use EDMA for data transfer.
333 * All channels need not be mapped, some can be free also.
334 */
335 {
336 0x00000000u,
337 0x00000000u
338 }
339 },
341 {
342 /* EDMA3 INSTANCE# 1 */
343 /** Total number of DMA Channels supported by the EDMA3 Controller */
344 64u,
345 /** Total number of QDMA Channels supported by the EDMA3 Controller */
346 8u,
347 /** Total number of TCCs supported by the EDMA3 Controller */
348 64u,
349 /** Total number of PaRAM Sets supported by the EDMA3 Controller */
350 512u,
351 /** Total number of Event Queues in the EDMA3 Controller */
352 4u,
353 /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
354 4u,
355 /** Number of Regions on this EDMA3 controller */
356 8u,
358 /**
359 * \brief Channel mapping existence
360 * A value of 0 (No channel mapping) implies that there is fixed association
361 * for a channel number to a parameter entry number or, in other words,
362 * PaRAM entry n corresponds to channel n.
363 */
364 1u,
366 /** Existence of memory protection feature */
367 1u,
369 /** Global Register Region of CC Registers */
370 (void *)0x02720000u,
371 /** Transfer Controller (TC) Registers */
372 {
373 (void *)0x02770000u,
374 (void *)0x02778000u,
375 (void *)0x02780000u,
376 (void *)0x02788000u,
377 (void *)NULL,
378 (void *)NULL,
379 (void *)NULL,
380 (void *)NULL
381 },
382 /** Interrupt no. for Transfer Completion */
383 8u,
384 /** Interrupt no. for CC Error */
385 0u,
386 /** Interrupt no. for TCs Error */
387 {
388 2u,
389 3u,
390 4u,
391 5u,
392 0u,
393 0u,
394 0u,
395 0u,
396 },
398 /**
399 * \brief EDMA3 TC priority setting
400 *
401 * User can program the priority of the Event Queues
402 * at a system-wide level. This means that the user can set the
403 * priority of an IO initiated by either of the TCs (Transfer Controllers)
404 * relative to IO initiated by the other bus masters on the
405 * device (ARM, DSP, USB, etc)
406 */
407 {
408 0u,
409 1u,
410 2u,
411 3u,
412 0u,
413 0u,
414 0u,
415 0u
416 },
417 /**
418 * \brief To Configure the Threshold level of number of events
419 * that can be queued up in the Event queues. EDMA3CC error register
420 * (CCERR) will indicate whether or not at any instant of time the
421 * number of events queued up in any of the event queues exceeds
422 * or equals the threshold/watermark value that is set
423 * in the queue watermark threshold register (QWMTHRA).
424 */
425 {
426 16u,
427 16u,
428 16u,
429 16u,
430 0u,
431 0u,
432 0u,
433 0u
434 },
436 /**
437 * \brief To Configure the Default Burst Size (DBS) of TCs.
438 * An optimally-sized command is defined by the transfer controller
439 * default burst size (DBS). Different TCs can have different
440 * DBS values. It is defined in Bytes.
441 */
442 {
443 128u,
444 64u,
445 128u,
446 64u,
447 0u,
448 0u,
449 0u,
450 0u
451 },
453 /**
454 * \brief Mapping from each DMA channel to a Parameter RAM set,
455 * if it exists, otherwise of no use.
456 */
457 {
458 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
459 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
460 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
461 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
462 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
463 40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
464 48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
465 56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u
466 },
468 /**
469 * \brief Mapping from each DMA channel to a TCC. This specific
470 * TCC code will be returned when the transfer is completed
471 * on the mapped channel.
472 */
473 {
474 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
475 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
476 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
477 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
478 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
479 40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
480 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
481 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
482 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
483 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP
484 },
486 /**
487 * \brief Mapping of DMA channels to Hardware Events from
488 * various peripherals, which use EDMA for data transfer.
489 * All channels need not be mapped, some can be free also.
490 */
491 {
492 0xFFFFFFFFu,
493 0xFFFF0000u
494 }
495 },
497 {
498 /* EDMA3 INSTANCE# 2 */
499 /** Total number of DMA Channels supported by the EDMA3 Controller */
500 64u,
501 /** Total number of QDMA Channels supported by the EDMA3 Controller */
502 8u,
503 /** Total number of TCCs supported by the EDMA3 Controller */
504 64u,
505 /** Total number of PaRAM Sets supported by the EDMA3 Controller */
506 512u,
507 /** Total number of Event Queues in the EDMA3 Controller */
508 4u,
509 /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
510 4u,
511 /** Number of Regions on this EDMA3 controller */
512 8u,
514 /**
515 * \brief Channel mapping existence
516 * A value of 0 (No channel mapping) implies that there is fixed association
517 * for a channel number to a parameter entry number or, in other words,
518 * PaRAM entry n corresponds to channel n.
519 */
520 1u,
522 /** Existence of memory protection feature */
523 1u,
525 /** Global Register Region of CC Registers */
526 (void *)0x02740000u,
527 /** Transfer Controller (TC) Registers */
528 {
529 (void *)0x02790000u,
530 (void *)0x02798000u,
531 (void *)0x027A0000u,
532 (void *)0x027A8000u,
533 (void *)NULL,
534 (void *)NULL,
535 (void *)NULL,
536 (void *)NULL
537 },
538 /** Interrupt no. for Transfer Completion */
539 24u,
540 /** Interrupt no. for CC Error */
541 16u,
542 /** Interrupt no. for TCs Error */
543 {
544 18u,
545 19u,
546 20u,
547 21u,
548 0u,
549 0u,
550 0u,
551 0u,
552 },
554 /**
555 * \brief EDMA3 TC priority setting
556 *
557 * User can program the priority of the Event Queues
558 * at a system-wide level. This means that the user can set the
559 * priority of an IO initiated by either of the TCs (Transfer Controllers)
560 * relative to IO initiated by the other bus masters on the
561 * device (ARM, DSP, USB, etc)
562 */
563 {
564 0u,
565 1u,
566 2u,
567 3u,
568 0u,
569 0u,
570 0u,
571 0u
572 },
573 /**
574 * \brief To Configure the Threshold level of number of events
575 * that can be queued up in the Event queues. EDMA3CC error register
576 * (CCERR) will indicate whether or not at any instant of time the
577 * number of events queued up in any of the event queues exceeds
578 * or equals the threshold/watermark value that is set
579 * in the queue watermark threshold register (QWMTHRA).
580 */
581 {
582 16u,
583 16u,
584 16u,
585 16u,
586 0u,
587 0u,
588 0u,
589 0u
590 },
592 /**
593 * \brief To Configure the Default Burst Size (DBS) of TCs.
594 * An optimally-sized command is defined by the transfer controller
595 * default burst size (DBS). Different TCs can have different
596 * DBS values. It is defined in Bytes.
597 */
598 {
599 128u,
600 64u,
601 64u,
602 128u,
603 0u,
604 0u,
605 0u,
606 0u
607 },
609 /**
610 * \brief Mapping from each DMA channel to a Parameter RAM set,
611 * if it exists, otherwise of no use.
612 */
613 {
614 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
615 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
616 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
617 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
618 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
619 40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
620 48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
621 56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u
622 },
624 /**
625 * \brief Mapping from each DMA channel to a TCC. This specific
626 * TCC code will be returned when the transfer is completed
627 * on the mapped channel.
628 */
629 {
630 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
631 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
632 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
633 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
634 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
635 40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
636 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
637 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
638 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
639 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP
640 },
642 /**
643 * \brief Mapping of DMA channels to Hardware Events from
644 * various peripherals, which use EDMA for data transfer.
645 * All channels need not be mapped, some can be free also.
646 */
647 {
648 0xFFFFFFFFu,
649 0xFFFF0000u
650 }
651 },
652 };
654 EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
655 {
656 /* EDMA3 INSTANCE# 0 */
657 {
658 /* Resources owned/reserved by region 0 */
659 {
660 /* ownPaRAMSets */
661 /* 31 0 63 32 95 64 127 96 */
662 {0x3FFF0003u, 0x00000000u, 0x00000000u, 0x00000000u,
663 /* 159 128 191 160 223 192 255 224 */
664 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
665 /* 287 256 319 288 351 320 383 352 */
666 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
667 /* 415 384 447 416 479 448 511 480 */
668 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
670 /* ownDmaChannels */
671 /* 31 0 63 32 */
672 {0x00000003u, 0x00000000u},
674 /* ownQdmaChannels */
675 /* 31 0 */
676 {0x00000001u},
678 /* ownTccs */
679 /* 31 0 63 32 */
680 {0x00000003u, 0x00000000u},
682 /* resvdPaRAMSets */
683 /* 31 0 63 32 95 64 127 96 */
684 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
685 /* 159 128 191 160 223 192 255 224 */
686 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
687 /* 287 256 319 288 351 320 383 352 */
688 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
689 /* 415 384 447 416 479 448 511 480 */
690 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
692 /* resvdDmaChannels */
693 /* 31 0 63 32 */
694 {0x00000000u, 0x00000000u},
696 /* resvdQdmaChannels */
697 /* 31 0 */
698 {0x00000000u},
700 /* resvdTccs */
701 /* 31 0 63 32 */
702 {0x00000000u, 0x00000000u},
703 },
705 /* Resources owned/reserved by region 1 */
706 {
707 /* ownPaRAMSets */
708 /* 31 0 63 32 95 64 127 96 */
709 {0xC000000Cu, 0x00000FFFu, 0x00000000u, 0x00000000u,
710 /* 159 128 191 160 223 192 255 224 */
711 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
712 /* 287 256 319 288 351 320 383 352 */
713 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
714 /* 415 384 447 416 479 448 511 480 */
715 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
717 /* ownDmaChannels */
718 /* 31 0 63 32 */
719 {0x0000000Cu, 0x00000000u},
721 /* ownQdmaChannels */
722 /* 31 0 */
723 {0x00000002u},
725 /* ownTccs */
726 /* 31 0 63 32 */
727 {0x0000000Cu, 0x00000000u},
729 /* resvdPaRAMSets */
730 /* 31 0 63 32 95 64 127 96 */
731 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
732 /* 159 128 191 160 223 192 255 224 */
733 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
734 /* 287 256 319 288 351 320 383 352 */
735 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
736 /* 415 384 447 416 479 448 511 480 */
737 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
739 /* resvdDmaChannels */
740 /* 31 0 63 32 */
741 {0x00000000u, 0x00000000u},
743 /* resvdQdmaChannels */
744 /* 31 0 */
745 {0x00000000u},
747 /* resvdTccs */
748 /* 31 0 63 32 */
749 {0x00000000u, 0x00000000u},
750 },
752 /* Resources owned/reserved by region 2 */
753 {
754 /* ownPaRAMSets */
755 /* 31 0 63 32 95 64 127 96 */
756 {0x00000030u, 0x03FFF000u, 0x00000000u, 0x00000000u,
757 /* 159 128 191 160 223 192 255 224 */
758 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
759 /* 287 256 319 288 351 320 383 352 */
760 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
761 /* 415 384 447 416 479 448 511 480 */
762 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
764 /* ownDmaChannels */
765 /* 31 0 63 32 */
766 {0x00000030u, 0x00000000u},
768 /* ownQdmaChannels */
769 /* 31 0 */
770 {0x00000004u},
772 /* ownTccs */
773 /* 31 0 63 32 */
774 {0x00000030u, 0x00000000u},
776 /* resvdPaRAMSets */
777 /* 31 0 63 32 95 64 127 96 */
778 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
779 /* 159 128 191 160 223 192 255 224 */
780 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
781 /* 287 256 319 288 351 320 383 352 */
782 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
783 /* 415 384 447 416 479 448 511 480 */
784 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
786 /* resvdDmaChannels */
787 /* 31 0 63 32 */
788 {0x00000000u, 0x00000000u},
790 /* resvdQdmaChannels */
791 /* 31 0 */
792 {0x00000000u},
794 /* resvdTccs */
795 /* 31 0 63 32 */
796 {0x00000000u, 0x00000000u},
797 },
799 /* Resources owned/reserved by region 3 */
800 {
801 /* ownPaRAMSets */
802 /* 31 0 63 32 95 64 127 96 */
803 {0x000000C0u, 0xFC000000u, 0x000000FFu, 0x00000000u,
804 /* 159 128 191 160 223 192 255 224 */
805 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
806 /* 287 256 319 288 351 320 383 352 */
807 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
808 /* 415 384 447 416 479 448 511 480 */
809 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
811 /* ownDmaChannels */
812 /* 31 0 63 32 */
813 {0x000000C0u, 0x00000000u},
815 /* ownQdmaChannels */
816 /* 31 0 */
817 {0x00000008u},
819 /* ownTccs */
820 /* 31 0 63 32 */
821 {0x000000C0u, 0x00000000u},
823 /* resvdPaRAMSets */
824 /* 31 0 63 32 95 64 127 96 */
825 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
826 /* 159 128 191 160 223 192 255 224 */
827 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
828 /* 287 256 319 288 351 320 383 352 */
829 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
830 /* 415 384 447 416 479 448 511 480 */
831 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
833 /* resvdDmaChannels */
834 /* 31 0 63 32 */
835 {0x00000000u, 0x00000000u},
837 /* resvdQdmaChannels */
838 /* 31 0 */
839 {0x00000000u},
841 /* resvdTccs */
842 /* 31 0 63 32 */
843 {0x00000000u, 0x00000000u},
844 },
846 /* Resources owned/reserved by region 4 */
847 {
848 /* ownPaRAMSets */
849 /* 31 0 63 32 95 64 127 96 */
850 {0x00000300u, 0x00000000u, 0x003FFF00u, 0x00000000u,
851 /* 159 128 191 160 223 192 255 224 */
852 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
853 /* 287 256 319 288 351 320 383 352 */
854 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
855 /* 415 384 447 416 479 448 511 480 */
856 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
858 /* ownDmaChannels */
859 /* 31 0 63 32 */
860 {0x00000300u, 0x00000000u},
862 /* ownQdmaChannels */
863 /* 31 0 */
864 {0x00000010u},
866 /* ownTccs */
867 /* 31 0 63 32 */
868 {0x00000300u, 0x00000000u},
870 /* resvdPaRAMSets */
871 /* 31 0 63 32 95 64 127 96 */
872 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
873 /* 159 128 191 160 223 192 255 224 */
874 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
875 /* 287 256 319 288 351 320 383 352 */
876 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
877 /* 415 384 447 416 479 448 511 480 */
878 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
880 /* resvdDmaChannels */
881 /* 31 0 63 32 */
882 {0x00000000u, 0x00000000u},
884 /* resvdQdmaChannels */
885 /* 31 0 */
886 {0x00000000u},
888 /* resvdTccs */
889 /* 31 0 63 32 */
890 {0x00000000u, 0x00000000u},
891 },
893 /* Resources owned/reserved by region 5 */
894 {
895 /* ownPaRAMSets */
896 /* 31 0 63 32 95 64 127 96 */
897 {0x00000C00u, 0x00000000u, 0xFFC00000u, 0x0000000Fu,
898 /* 159 128 191 160 223 192 255 224 */
899 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
900 /* 287 256 319 288 351 320 383 352 */
901 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
902 /* 415 384 447 416 479 448 511 480 */
903 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
905 /* ownDmaChannels */
906 /* 31 0 63 32 */
907 {0x00000C00u, 0x00000000u},
909 /* ownQdmaChannels */
910 /* 31 0 */
911 {0x00000020u},
913 /* ownTccs */
914 /* 31 0 63 32 */
915 {0x00000C00u, 0x00000000u},
917 /* resvdPaRAMSets */
918 /* 31 0 63 32 95 64 127 96 */
919 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
920 /* 159 128 191 160 223 192 255 224 */
921 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
922 /* 287 256 319 288 351 320 383 352 */
923 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
924 /* 415 384 447 416 479 448 511 480 */
925 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
927 /* resvdDmaChannels */
928 /* 31 0 63 32 */
929 {0x00000000u, 0x00000000u},
931 /* resvdQdmaChannels */
932 /* 31 0 */
933 {0x00000000u},
935 /* resvdTccs */
936 /* 31 0 63 32 */
937 {0x00000000u, 0x00000000u},
938 },
940 /* Resources owned/reserved by region 6 */
941 {
942 /* ownPaRAMSets */
943 /* 31 0 63 32 95 64 127 96 */
944 {0x00003000u, 0x00000000u, 0x00000000u, 0x0003FFF0u,
945 /* 159 128 191 160 223 192 255 224 */
946 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
947 /* 287 256 319 288 351 320 383 352 */
948 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
949 /* 415 384 447 416 479 448 511 480 */
950 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
952 /* ownDmaChannels */
953 /* 31 0 63 32 */
954 {0x00003000u, 0x00000000u},
956 /* ownQdmaChannels */
957 /* 31 0 */
958 {0x00000040u},
960 /* ownTccs */
961 /* 31 0 63 32 */
962 {0x00003000u, 0x00000000u},
964 /* resvdPaRAMSets */
965 /* 31 0 63 32 95 64 127 96 */
966 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
967 /* 159 128 191 160 223 192 255 224 */
968 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
969 /* 287 256 319 288 351 320 383 352 */
970 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
971 /* 415 384 447 416 479 448 511 480 */
972 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
974 /* resvdDmaChannels */
975 /* 31 0 63 32 */
976 {0x00000000u, 0x00000000u},
978 /* resvdQdmaChannels */
979 /* 31 0 */
980 {0x00000000u},
982 /* resvdTccs */
983 /* 31 0 63 32 */
984 {0x00000000u, 0x00000000u},
985 },
987 /* Resources owned/reserved by region 7 */
988 {
989 /* ownPaRAMSets */
990 /* 31 0 63 32 95 64 127 96 */
991 {0x0000C000u, 0x00000000u, 0x00000000u, 0xFFFC0000u,
992 /* 159 128 191 160 223 192 255 224 */
993 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
994 /* 287 256 319 288 351 320 383 352 */
995 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
996 /* 415 384 447 416 479 448 511 480 */
997 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
999 /* ownDmaChannels */
1000 /* 31 0 63 32 */
1001 {0x0000C000u, 0x00000000u},
1003 /* ownQdmaChannels */
1004 /* 31 0 */
1005 {0x00000080u},
1007 /* ownTccs */
1008 /* 31 0 63 32 */
1009 {0x0000C000u, 0x00000000u},
1011 /* resvdPaRAMSets */
1012 /* 31 0 63 32 95 64 127 96 */
1013 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1014 /* 159 128 191 160 223 192 255 224 */
1015 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1016 /* 287 256 319 288 351 320 383 352 */
1017 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1018 /* 415 384 447 416 479 448 511 480 */
1019 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1021 /* resvdDmaChannels */
1022 /* 31 0 63 32 */
1023 {0x00000000u, 0x00000000u},
1025 /* resvdQdmaChannels */
1026 /* 31 0 */
1027 {0x00000000u},
1029 /* resvdTccs */
1030 /* 31 0 63 32 */
1031 {0x00000000u, 0x00000000u},
1032 },
1033 },
1035 /* EDMA3 INSTANCE# 1 */
1036 {
1037 /* Resources owned/reserved by region 0 */
1038 {
1039 /* ownPaRAMSets */
1040 /* 31 0 63 32 95 64 127 96 */
1041 {0x00000000u, 0x00030000u, 0xFFFFFFFFu, 0x00FFFFFFu,
1042 /* 159 128 191 160 223 192 255 224 */
1043 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1044 /* 287 256 319 288 351 320 383 352 */
1045 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1046 /* 415 384 447 416 479 448 511 480 */
1047 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1049 /* ownDmaChannels */
1050 /* 31 0 63 32 */
1051 {0x00000000u, 0x00030000u},
1053 /* ownQdmaChannels */
1054 /* 31 0 */
1055 {0x00000001u},
1057 /* ownTccs */
1058 /* 31 0 63 32 */
1059 {0x00000000u, 0x00030000u},
1061 /* resvdPaRAMSets */
1062 /* 31 0 63 32 95 64 127 96 */
1063 {0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
1064 /* 159 128 191 160 223 192 255 224 */
1065 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1066 /* 287 256 319 288 351 320 383 352 */
1067 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1068 /* 415 384 447 416 479 448 511 480 */
1069 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1071 /* resvdDmaChannels */
1072 /* 31 0 63 32 */
1073 {0xFFFFFFFFu, 0x0000FFFFu},
1075 /* resvdQdmaChannels */
1076 /* 31 0 */
1077 {0x00000000u},
1079 /* resvdTccs */
1080 /* 31 0 63 32 */
1081 {0xFFFFFFFFu, 0x0000FFFFu},
1082 },
1084 /* Resources owned/reserved by region 1 */
1085 {
1086 /* ownPaRAMSets */
1087 /* 31 0 63 32 95 64 127 96 */
1088 {0x00000000u, 0x000C0000u, 0x00000000u, 0xFF000000u,
1089 /* 159 128 191 160 223 192 255 224 */
1090 0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
1091 /* 287 256 319 288 351 320 383 352 */
1092 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1093 /* 415 384 447 416 479 448 511 480 */
1094 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1096 /* ownDmaChannels */
1097 /* 31 0 63 32 */
1098 {0x00000000u, 0x000C0000u},
1100 /* ownQdmaChannels */
1101 /* 31 0 */
1102 {0x00000002u},
1104 /* ownTccs */
1105 /* 31 0 63 32 */
1106 {0x00000000u, 0x000C0000u},
1108 /* resvdPaRAMSets */
1109 /* 31 0 63 32 95 64 127 96 */
1110 {0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
1111 /* 159 128 191 160 223 192 255 224 */
1112 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1113 /* 287 256 319 288 351 320 383 352 */
1114 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1115 /* 415 384 447 416 479 448 511 480 */
1116 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1118 /* resvdDmaChannels */
1119 /* 31 0 63 32 */
1120 {0xFFFFFFFFu, 0x0000FFFFu},
1122 /* resvdQdmaChannels */
1123 /* 31 0 */
1124 {0x00000000u},
1126 /* resvdTccs */
1127 /* 31 0 63 32 */
1128 {0xFFFFFFFFu, 0x0000FFFFu},
1129 },
1131 /* Resources owned/reserved by region 2 */
1132 {
1133 /* ownPaRAMSets */
1134 /* 31 0 63 32 95 64 127 96 */
1135 {0x00000000u, 0x00300000u, 0x00000000u, 0x00000000u,
1136 /* 159 128 191 160 223 192 255 224 */
1137 0x00000000u, 0xFFFF0000u, 0xFFFFFFFFu, 0x000000FFu,
1138 /* 287 256 319 288 351 320 383 352 */
1139 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1140 /* 415 384 447 416 479 448 511 480 */
1141 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1143 /* ownDmaChannels */
1144 /* 31 0 63 32 */
1145 {0x00000000u, 0x00300000u},
1147 /* ownQdmaChannels */
1148 /* 31 0 */
1149 {0x00000004u},
1151 /* ownTccs */
1152 /* 31 0 63 32 */
1153 {0x00000000u, 0x00300000u},
1155 /* resvdPaRAMSets */
1156 /* 31 0 63 32 95 64 127 96 */
1157 {0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
1158 /* 159 128 191 160 223 192 255 224 */
1159 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1160 /* 287 256 319 288 351 320 383 352 */
1161 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1162 /* 415 384 447 416 479 448 511 480 */
1163 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1165 /* resvdDmaChannels */
1166 /* 31 0 63 32 */
1167 {0xFFFFFFFFu, 0x0000FFFFu},
1169 /* resvdQdmaChannels */
1170 /* 31 0 */
1171 {0x00000000u},
1173 /* resvdTccs */
1174 /* 31 0 63 32 */
1175 {0xFFFFFFFFu, 0x0000FFFFu},
1176 },
1178 /* Resources owned/reserved by region 3 */
1179 {
1180 /* ownPaRAMSets */
1181 /* 31 0 63 32 95 64 127 96 */
1182 {0x00000000u, 0x00C00000u, 0x00000000u, 0x00000000u,
1183 /* 159 128 191 160 223 192 255 224 */
1184 0x00000000u, 0x00000000u, 0x00000000u, 0xFFFFFF00u,
1185 /* 287 256 319 288 351 320 383 352 */
1186 0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
1187 /* 415 384 447 416 479 448 511 480 */
1188 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1190 /* ownDmaChannels */
1191 /* 31 0 63 32 */
1192 {0x00000000u, 0x00C00000u},
1194 /* ownQdmaChannels */
1195 /* 31 0 */
1196 {0x00000008u},
1198 /* ownTccs */
1199 /* 31 0 63 32 */
1200 {0x00000000u, 0x00C00000u},
1202 /* resvdPaRAMSets */
1203 /* 31 0 63 32 95 64 127 96 */
1204 {0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
1205 /* 159 128 191 160 223 192 255 224 */
1206 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1207 /* 287 256 319 288 351 320 383 352 */
1208 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1209 /* 415 384 447 416 479 448 511 480 */
1210 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1212 /* resvdDmaChannels */
1213 /* 31 0 63 32 */
1214 {0xFFFFFFFFu, 0x0000FFFFu},
1216 /* resvdQdmaChannels */
1217 /* 31 0 */
1218 {0x00000000u},
1220 /* resvdTccs */
1221 /* 31 0 63 32 */
1222 {0xFFFFFFFFu, 0x0000FFFFu},
1223 },
1225 /* Resources owned/reserved by region 4 */
1226 {
1227 /* ownPaRAMSets */
1228 /* 31 0 63 32 95 64 127 96 */
1229 {0x00000000u, 0x03000000u, 0x00000000u, 0x00000000u,
1230 /* 159 128 191 160 223 192 255 224 */
1231 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1232 /* 287 256 319 288 351 320 383 352 */
1233 0x00000000u, 0xFFFFFFFFu, 0x00FFFFFFu, 0x00000000u,
1234 /* 415 384 447 416 479 448 511 480 */
1235 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1237 /* ownDmaChannels */
1238 /* 31 0 63 32 */
1239 {0x00000000u, 0x03000000u},
1241 /* ownQdmaChannels */
1242 /* 31 0 */
1243 {0x00000010u},
1245 /* ownTccs */
1246 /* 31 0 63 32 */
1247 {0x00000000u, 0x03000000u},
1249 /* resvdPaRAMSets */
1250 /* 31 0 63 32 95 64 127 96 */
1251 {0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
1252 /* 159 128 191 160 223 192 255 224 */
1253 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1254 /* 287 256 319 288 351 320 383 352 */
1255 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1256 /* 415 384 447 416 479 448 511 480 */
1257 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1259 /* resvdDmaChannels */
1260 /* 31 0 63 32 */
1261 {0xFFFFFFFFu, 0x0000FFFFu},
1263 /* resvdQdmaChannels */
1264 /* 31 0 */
1265 {0x00000000u},
1267 /* resvdTccs */
1268 /* 31 0 63 32 */
1269 {0xFFFFFFFFu, 0x0000FFFFu},
1270 },
1272 /* Resources owned/reserved by region 5 */
1273 {
1274 /* ownPaRAMSets */
1275 /* 31 0 63 32 95 64 127 96 */
1276 {0x00000000u, 0x0C000000u, 0x00000000u, 0x00000000u,
1277 /* 159 128 191 160 223 192 255 224 */
1278 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1279 /* 287 256 319 288 351 320 383 352 */
1280 0x00000000u, 0x00000000u, 0xFF000000u, 0xFFFFFFFFu,
1281 /* 415 384 447 416 479 448 511 480 */
1282 0x0000FFFFu, 0x00000000u, 0x00000000u, 0x00000000u},
1284 /* ownDmaChannels */
1285 /* 31 0 63 32 */
1286 {0x00000000u, 0x0C000000u},
1288 /* ownQdmaChannels */
1289 /* 31 0 */
1290 {0x00000020u},
1292 /* ownTccs */
1293 /* 31 0 63 32 */
1294 {0x00000000u, 0x0C000000u},
1296 /* resvdPaRAMSets */
1297 /* 31 0 63 32 95 64 127 96 */
1298 {0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
1299 /* 159 128 191 160 223 192 255 224 */
1300 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1301 /* 287 256 319 288 351 320 383 352 */
1302 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1303 /* 415 384 447 416 479 448 511 480 */
1304 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1306 /* resvdDmaChannels */
1307 /* 31 0 63 32 */
1308 {0xFFFFFFFFu, 0x0000FFFFu},
1310 /* resvdQdmaChannels */
1311 /* 31 0 */
1312 {0x00000000u},
1314 /* resvdTccs */
1315 /* 31 0 63 32 */
1316 {0xFFFFFFFFu, 0x0000FFFFu},
1317 },
1319 /* Resources owned/reserved by region 6 */
1320 {
1321 /* ownPaRAMSets */
1322 /* 31 0 63 32 95 64 127 96 */
1323 {0x00000000u, 0x30000000u, 0x00000000u, 0x00000000u,
1324 /* 159 128 191 160 223 192 255 224 */
1325 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1326 /* 287 256 319 288 351 320 383 352 */
1327 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1328 /* 415 384 447 416 479 448 511 480 */
1329 0xFFFF0000u, 0xFFFFFFFFu, 0x000000FFu, 0x00000000u},
1331 /* ownDmaChannels */
1332 /* 31 0 63 32 */
1333 {0x00000000u, 0x30000000u},
1335 /* ownQdmaChannels */
1336 /* 31 0 */
1337 {0x00000040u},
1339 /* ownTccs */
1340 /* 31 0 63 32 */
1341 {0x00000000u, 0x30000000u},
1343 /* resvdPaRAMSets */
1344 /* 31 0 63 32 95 64 127 96 */
1345 {0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
1346 /* 159 128 191 160 223 192 255 224 */
1347 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1348 /* 287 256 319 288 351 320 383 352 */
1349 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1350 /* 415 384 447 416 479 448 511 480 */
1351 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1353 /* resvdDmaChannels */
1354 /* 31 0 63 32 */
1355 {0xFFFFFFFFu, 0x0000FFFFu},
1357 /* resvdQdmaChannels */
1358 /* 31 0 */
1359 {0x00000000u},
1361 /* resvdTccs */
1362 /* 31 0 63 32 */
1363 {0xFFFFFFFFu, 0x0000FFFFu},
1364 },
1366 /* Resources owned/reserved by region 7 */
1367 {
1368 /* ownPaRAMSets */
1369 /* 31 0 63 32 95 64 127 96 */
1370 {0x00000000u, 0xC0000000u, 0x00000000u, 0x00000000u,
1371 /* 159 128 191 160 223 192 255 224 */
1372 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1373 /* 287 256 319 288 351 320 383 352 */
1374 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1375 /* 415 384 447 416 479 448 511 480 */
1376 0x00000000u, 0x00000000u, 0xFFFFFF00u, 0xFFFFFFFFu},
1378 /* ownDmaChannels */
1379 /* 31 0 63 32 */
1380 {0x00000000u, 0xC0000000u},
1382 /* ownQdmaChannels */
1383 /* 31 0 */
1384 {0x00000080u},
1386 /* ownTccs */
1387 /* 31 0 63 32 */
1388 {0x00000000u, 0xC0000000u},
1390 /* resvdPaRAMSets */
1391 /* 31 0 63 32 95 64 127 96 */
1392 {0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
1393 /* 159 128 191 160 223 192 255 224 */
1394 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1395 /* 287 256 319 288 351 320 383 352 */
1396 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1397 /* 415 384 447 416 479 448 511 480 */
1398 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1400 /* resvdDmaChannels */
1401 /* 31 0 63 32 */
1402 {0xFFFFFFFFu, 0x0000FFFFu},
1404 /* resvdQdmaChannels */
1405 /* 31 0 */
1406 {0x00000000u},
1408 /* resvdTccs */
1409 /* 31 0 63 32 */
1410 {0xFFFFFFFFu, 0x0000FFFFu},
1411 },
1412 },
1414 /* EDMA3 INSTANCE# 2 */
1415 {
1416 /* Resources owned/reserved by region 0 */
1417 {
1418 /* ownPaRAMSets */
1419 /* 31 0 63 32 95 64 127 96 */
1420 {0x00000000u, 0x00030000u, 0xFFFFFFFFu, 0x00FFFFFFu,
1421 /* 159 128 191 160 223 192 255 224 */
1422 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1423 /* 287 256 319 288 351 320 383 352 */
1424 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1425 /* 415 384 447 416 479 448 511 480 */
1426 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1428 /* ownDmaChannels */
1429 /* 31 0 63 32 */
1430 {0x00000000u, 0x00030000u},
1432 /* ownQdmaChannels */
1433 /* 31 0 */
1434 {0x00000001u},
1436 /* ownTccs */
1437 /* 31 0 63 32 */
1438 {0x00000000u, 0x00030000u},
1440 /* resvdPaRAMSets */
1441 /* 31 0 63 32 95 64 127 96 */
1442 {0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
1443 /* 159 128 191 160 223 192 255 224 */
1444 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1445 /* 287 256 319 288 351 320 383 352 */
1446 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1447 /* 415 384 447 416 479 448 511 480 */
1448 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1450 /* resvdDmaChannels */
1451 /* 31 0 63 32 */
1452 {0xFFFFFFFFu, 0x0000FFFFu},
1454 /* resvdQdmaChannels */
1455 /* 31 0 */
1456 {0x00000000u},
1458 /* resvdTccs */
1459 /* 31 0 63 32 */
1460 {0xFFFFFFFFu, 0x0000FFFFu},
1461 },
1463 /* Resources owned/reserved by region 1 */
1464 {
1465 /* ownPaRAMSets */
1466 /* 31 0 63 32 95 64 127 96 */
1467 {0x00000000u, 0x000C0000u, 0x00000000u, 0xFF000000u,
1468 /* 159 128 191 160 223 192 255 224 */
1469 0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
1470 /* 287 256 319 288 351 320 383 352 */
1471 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1472 /* 415 384 447 416 479 448 511 480 */
1473 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1475 /* ownDmaChannels */
1476 /* 31 0 63 32 */
1477 {0x00000000u, 0x000C0000u},
1479 /* ownQdmaChannels */
1480 /* 31 0 */
1481 {0x00000002u},
1483 /* ownTccs */
1484 /* 31 0 63 32 */
1485 {0x00000000u, 0x000C0000u},
1487 /* resvdPaRAMSets */
1488 /* 31 0 63 32 95 64 127 96 */
1489 {0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
1490 /* 159 128 191 160 223 192 255 224 */
1491 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1492 /* 287 256 319 288 351 320 383 352 */
1493 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1494 /* 415 384 447 416 479 448 511 480 */
1495 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1497 /* resvdDmaChannels */
1498 /* 31 0 63 32 */
1499 {0xFFFFFFFFu, 0x0000FFFFu},
1501 /* resvdQdmaChannels */
1502 /* 31 0 */
1503 {0x00000000u},
1505 /* resvdTccs */
1506 /* 31 0 63 32 */
1507 {0xFFFFFFFFu, 0x0000FFFFu},
1508 },
1510 /* Resources owned/reserved by region 2 */
1511 {
1512 /* ownPaRAMSets */
1513 /* 31 0 63 32 95 64 127 96 */
1514 {0x00000000u, 0x00300000u, 0x00000000u, 0x00000000u,
1515 /* 159 128 191 160 223 192 255 224 */
1516 0x00000000u, 0xFFFF0000u, 0xFFFFFFFFu, 0x000000FFu,
1517 /* 287 256 319 288 351 320 383 352 */
1518 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1519 /* 415 384 447 416 479 448 511 480 */
1520 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1522 /* ownDmaChannels */
1523 /* 31 0 63 32 */
1524 {0x00000000u, 0x00300000u},
1526 /* ownQdmaChannels */
1527 /* 31 0 */
1528 {0x00000004u},
1530 /* ownTccs */
1531 /* 31 0 63 32 */
1532 {0x00000000u, 0x00300000u},
1534 /* resvdPaRAMSets */
1535 /* 31 0 63 32 95 64 127 96 */
1536 {0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
1537 /* 159 128 191 160 223 192 255 224 */
1538 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1539 /* 287 256 319 288 351 320 383 352 */
1540 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1541 /* 415 384 447 416 479 448 511 480 */
1542 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1544 /* resvdDmaChannels */
1545 /* 31 0 63 32 */
1546 {0xFFFFFFFFu, 0x0000FFFFu},
1548 /* resvdQdmaChannels */
1549 /* 31 0 */
1550 {0x00000000u},
1552 /* resvdTccs */
1553 /* 31 0 63 32 */
1554 {0xFFFFFFFFu, 0x0000FFFFu},
1555 },
1557 /* Resources owned/reserved by region 3 */
1558 {
1559 /* ownPaRAMSets */
1560 /* 31 0 63 32 95 64 127 96 */
1561 {0x00000000u, 0x00C00000u, 0x00000000u, 0x00000000u,
1562 /* 159 128 191 160 223 192 255 224 */
1563 0x00000000u, 0x00000000u, 0x00000000u, 0xFFFFFF00u,
1564 /* 287 256 319 288 351 320 383 352 */
1565 0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
1566 /* 415 384 447 416 479 448 511 480 */
1567 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1569 /* ownDmaChannels */
1570 /* 31 0 63 32 */
1571 {0x00000000u, 0x00C00000u},
1573 /* ownQdmaChannels */
1574 /* 31 0 */
1575 {0x00000008u},
1577 /* ownTccs */
1578 /* 31 0 63 32 */
1579 {0x00000000u, 0x00C00000u},
1581 /* resvdPaRAMSets */
1582 /* 31 0 63 32 95 64 127 96 */
1583 {0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
1584 /* 159 128 191 160 223 192 255 224 */
1585 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1586 /* 287 256 319 288 351 320 383 352 */
1587 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1588 /* 415 384 447 416 479 448 511 480 */
1589 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1591 /* resvdDmaChannels */
1592 /* 31 0 63 32 */
1593 {0xFFFFFFFFu, 0x0000FFFFu},
1595 /* resvdQdmaChannels */
1596 /* 31 0 */
1597 {0x00000000u},
1599 /* resvdTccs */
1600 /* 31 0 63 32 */
1601 {0xFFFFFFFFu, 0x0000FFFFu},
1602 },
1604 /* Resources owned/reserved by region 4 */
1605 {
1606 /* ownPaRAMSets */
1607 /* 31 0 63 32 95 64 127 96 */
1608 {0x00000000u, 0x03000000u, 0x00000000u, 0x00000000u,
1609 /* 159 128 191 160 223 192 255 224 */
1610 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1611 /* 287 256 319 288 351 320 383 352 */
1612 0x00000000u, 0xFFFFFFFFu, 0x00FFFFFFu, 0x00000000u,
1613 /* 415 384 447 416 479 448 511 480 */
1614 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1616 /* ownDmaChannels */
1617 /* 31 0 63 32 */
1618 {0x00000000u, 0x03000000u},
1620 /* ownQdmaChannels */
1621 /* 31 0 */
1622 {0x00000010u},
1624 /* ownTccs */
1625 /* 31 0 63 32 */
1626 {0x00000000u, 0x03000000u},
1628 /* resvdPaRAMSets */
1629 /* 31 0 63 32 95 64 127 96 */
1630 {0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
1631 /* 159 128 191 160 223 192 255 224 */
1632 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1633 /* 287 256 319 288 351 320 383 352 */
1634 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1635 /* 415 384 447 416 479 448 511 480 */
1636 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1638 /* resvdDmaChannels */
1639 /* 31 0 63 32 */
1640 {0xFFFFFFFFu, 0x0000FFFFu},
1642 /* resvdQdmaChannels */
1643 /* 31 0 */
1644 {0x00000000u},
1646 /* resvdTccs */
1647 /* 31 0 63 32 */
1648 {0xFFFFFFFFu, 0x0000FFFFu},
1649 },
1651 /* Resources owned/reserved by region 5 */
1652 {
1653 /* ownPaRAMSets */
1654 /* 31 0 63 32 95 64 127 96 */
1655 {0x00000000u, 0x0C000000u, 0x00000000u, 0x00000000u,
1656 /* 159 128 191 160 223 192 255 224 */
1657 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1658 /* 287 256 319 288 351 320 383 352 */
1659 0x00000000u, 0x00000000u, 0xFF000000u, 0xFFFFFFFFu,
1660 /* 415 384 447 416 479 448 511 480 */
1661 0x0000FFFFu, 0x00000000u, 0x00000000u, 0x00000000u},
1663 /* ownDmaChannels */
1664 /* 31 0 63 32 */
1665 {0x00000000u, 0x0C000000u},
1667 /* ownQdmaChannels */
1668 /* 31 0 */
1669 {0x00000020u},
1671 /* ownTccs */
1672 /* 31 0 63 32 */
1673 {0x00000000u, 0x0C000000u},
1675 /* resvdPaRAMSets */
1676 /* 31 0 63 32 95 64 127 96 */
1677 {0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
1678 /* 159 128 191 160 223 192 255 224 */
1679 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1680 /* 287 256 319 288 351 320 383 352 */
1681 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1682 /* 415 384 447 416 479 448 511 480 */
1683 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1685 /* resvdDmaChannels */
1686 /* 31 0 63 32 */
1687 {0xFFFFFFFFu, 0x0000FFFFu},
1689 /* resvdQdmaChannels */
1690 /* 31 0 */
1691 {0x00000000u},
1693 /* resvdTccs */
1694 /* 31 0 63 32 */
1695 {0xFFFFFFFFu, 0x0000FFFFu},
1696 },
1698 /* Resources owned/reserved by region 6 */
1699 {
1700 /* ownPaRAMSets */
1701 /* 31 0 63 32 95 64 127 96 */
1702 {0x00000000u, 0x30000000u, 0x00000000u, 0x00000000u,
1703 /* 159 128 191 160 223 192 255 224 */
1704 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1705 /* 287 256 319 288 351 320 383 352 */
1706 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1707 /* 415 384 447 416 479 448 511 480 */
1708 0xFFFF0000u, 0xFFFFFFFFu, 0x000000FFu, 0x00000000u},
1710 /* ownDmaChannels */
1711 /* 31 0 63 32 */
1712 {0x00000000u, 0x30000000u},
1714 /* ownQdmaChannels */
1715 /* 31 0 */
1716 {0x00000040u},
1718 /* ownTccs */
1719 /* 31 0 63 32 */
1720 {0x00000000u, 0x30000000u},
1722 /* resvdPaRAMSets */
1723 /* 31 0 63 32 95 64 127 96 */
1724 {0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
1725 /* 159 128 191 160 223 192 255 224 */
1726 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1727 /* 287 256 319 288 351 320 383 352 */
1728 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1729 /* 415 384 447 416 479 448 511 480 */
1730 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1732 /* resvdDmaChannels */
1733 /* 31 0 63 32 */
1734 {0xFFFFFFFFu, 0x0000FFFFu},
1736 /* resvdQdmaChannels */
1737 /* 31 0 */
1738 {0x00000000u},
1740 /* resvdTccs */
1741 /* 31 0 63 32 */
1742 {0xFFFFFFFFu, 0x0000FFFFu},
1743 },
1745 /* Resources owned/reserved by region 7 */
1746 {
1747 /* ownPaRAMSets */
1748 /* 31 0 63 32 95 64 127 96 */
1749 {0x00000000u, 0xC0000000u, 0x00000000u, 0x00000000u,
1750 /* 159 128 191 160 223 192 255 224 */
1751 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1752 /* 287 256 319 288 351 320 383 352 */
1753 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1754 /* 415 384 447 416 479 448 511 480 */
1755 0x00000000u, 0x00000000u, 0xFFFFFF00u, 0xFFFFFFFFu},
1757 /* ownDmaChannels */
1758 /* 31 0 63 32 */
1759 {0x00000000u, 0xC0000000u},
1761 /* ownQdmaChannels */
1762 /* 31 0 */
1763 {0x00000080u},
1765 /* ownTccs */
1766 /* 31 0 63 32 */
1767 {0x00000000u, 0xC0000000u},
1769 /* resvdPaRAMSets */
1770 /* 31 0 63 32 95 64 127 96 */
1771 {0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
1772 /* 159 128 191 160 223 192 255 224 */
1773 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1774 /* 287 256 319 288 351 320 383 352 */
1775 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1776 /* 415 384 447 416 479 448 511 480 */
1777 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1779 /* resvdDmaChannels */
1780 /* 31 0 63 32 */
1781 {0xFFFFFFFFu, 0x0000FFFFu},
1783 /* resvdQdmaChannels */
1784 /* 31 0 */
1785 {0x00000000u},
1787 /* resvdTccs */
1788 /* 31 0 63 32 */
1789 {0xFFFFFFFFu, 0x0000FFFFu},
1790 },
1791 },
1792 };
1794 /* End of File */