22cd800756a2ba76adf3923e303db30f37c1d967
[keystone-rtos/edma3_lld.git] / packages / ti / sdo / edma3 / rm / sample / src / platforms / sample_tci66ak2g02_int_reg.c
1 /*
2 * sample_tci6636k2h_int_reg.c
3 *
4 * Platform specific interrupt registration and un-registration routines.
5 *
6 * Copyright (C) 2012-2013 Texas Instruments Incorporated - http://www.ti.com/
7 *
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 *
13 * Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 *
16 * Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the
19 * distribution.
20 *
21 * Neither the name of Texas Instruments Incorporated nor the names of
22 * its contributors may be used to endorse or promote products derived
23 * from this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 */
39 #include <ti/sysbios/knl/Semaphore.h>
40 #include <ti/sysbios/family/c64p/Hwi.h>
41 #include <ti/sysbios/family/c64p/EventCombiner.h>
42 #include <ti/sysbios/family/c66/tci66xx/CpIntc.h>
44 #include <ti/sdo/edma3/rm/sample/bios6_edma3_rm_sample.h>
46 extern unsigned int ccXferCompInt[][EDMA3_MAX_REGIONS];
47 extern unsigned int ccErrorInt[];
48 extern unsigned int tcErrorInt[][EDMA3_MAX_TC];
49 extern unsigned int numEdma3Tc[];
51 void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(unsigned int arg) =
52 {
53 &lisrEdma3TC0ErrHandler0,
54 &lisrEdma3TC1ErrHandler0,
55 &lisrEdma3TC2ErrHandler0,
56 &lisrEdma3TC3ErrHandler0,
57 &lisrEdma3TC4ErrHandler0,
58 &lisrEdma3TC5ErrHandler0,
59 &lisrEdma3TC6ErrHandler0,
60 &lisrEdma3TC7ErrHandler0,
61 };
63 unsigned int hwiInterrupt = 8;
65 /* Host interrupts for transfer completion */
66 /* First 4 cores are connected from CP_INTC0 and last 4 cores are connected from CP_INTC1 */
67 //unsigned int ccXferHostInt[NUM_EDMA3_INSTANCES][NUM_DSPS] = {
68 unsigned int ccXferHostInt[2][1] = {
69 {32},
70 {33},
71 };
72 unsigned int edma3ErrHostInt[2][1] = {
73 {34},
74 {35},
75 };
77 extern unsigned int dsp_num;
79 /** To Register the ISRs with the underlying OS, if required */
80 void registerEdma3Interrupts (unsigned int edma3Id)
81 {
82 static UInt32 cookie = 0;
83 Int eventId = 0; /* GEM event id */
84 unsigned int numTc = 0;
86 /* Use CP_INTC0 for DSP core 0-3 and CP_INTC1 for DSP core 4-7 */
87 unsigned int cpIntcNum = (dsp_num > 3)? 1: 0;
89 /* Disabling the global interrupts */
90 cookie = Hwi_disable();
92 /* Transfer completion ISR */
93 CpIntc_dispatchPlug(ccXferCompInt[edma3Id][dsp_num],
94 lisrEdma3ComplHandler0,
95 edma3Id,
96 TRUE);
97 CpIntc_mapSysIntToHostInt(cpIntcNum, ccXferCompInt[edma3Id][dsp_num],
98 ccXferHostInt[edma3Id][dsp_num]);
99 CpIntc_enableHostInt(cpIntcNum, ccXferHostInt[edma3Id][dsp_num]);
100 eventId = CpIntc_getEventId(ccXferHostInt[edma3Id][dsp_num]);
101 EventCombiner_dispatchPlug (eventId, CpIntc_dispatch,
102 ccXferHostInt[edma3Id][dsp_num], TRUE);
103 EventCombiner_enableEvent(eventId);
105 /* CC Error ISR */
106 CpIntc_dispatchPlug(ccErrorInt[edma3Id], lisrEdma3CCErrHandler0,
107 edma3Id, TRUE);
108 CpIntc_mapSysIntToHostInt(cpIntcNum, ccErrorInt[edma3Id],
109 edma3ErrHostInt[edma3Id][dsp_num]);
110 /* TC Error ISR */
111 while (numTc < numEdma3Tc[edma3Id])
112 {
113 CpIntc_dispatchPlug(tcErrorInt[edma3Id][numTc],
114 (CpIntc_FuncPtr )(ptrEdma3TcIsrHandler[numTc]),
115 edma3Id, TRUE);
116 CpIntc_mapSysIntToHostInt(cpIntcNum, tcErrorInt[edma3Id][numTc],
117 edma3ErrHostInt[edma3Id][dsp_num]);
118 numTc++;
119 }
120 /* Enable the host interrupt which is common for both CC and TC error */
121 CpIntc_enableHostInt(cpIntcNum, edma3ErrHostInt[edma3Id][dsp_num]);
122 eventId = CpIntc_getEventId(edma3ErrHostInt[edma3Id][dsp_num]);
123 EventCombiner_dispatchPlug (eventId, CpIntc_dispatch,
124 edma3ErrHostInt[edma3Id][dsp_num], TRUE);
125 EventCombiner_enableEvent(eventId);
127 Hwi_enableInterrupt(hwiInterrupt);
129 /* enable the 'global' switch */
130 CpIntc_enableAllHostInts(cpIntcNum);
132 /* Restore interrupts */
133 Hwi_restore(cookie);
134 }
136 /** To Unregister the ISRs with the underlying OS, if previously registered. */
137 void unregisterEdma3Interrupts (unsigned int edma3Id)
138 {
139 static UInt32 cookie = 0;
140 Int eventId = 0; /* GEM event id */
142 /* Use CP_INTC0 for DSP core 0-3 and CP_INTC1 for DSP core 4-7 */
143 unsigned int cpIntcNum = (dsp_num > 3)? 1: 0;
145 /* Disabling the global interrupts */
146 cookie = Hwi_disable();
148 /* Transfer completion ISR */
149 CpIntc_disableHostInt(cpIntcNum, ccXferHostInt[edma3Id][dsp_num]);
150 eventId = CpIntc_getEventId(ccXferHostInt[edma3Id][dsp_num]);
151 EventCombiner_disableEvent(eventId);
153 /* CC/TC Error ISR */
154 CpIntc_disableHostInt(cpIntcNum, edma3ErrHostInt[edma3Id][dsp_num]);
155 eventId = CpIntc_getEventId(edma3ErrHostInt[edma3Id][dsp_num]);
156 EventCombiner_disableEvent(eventId);
158 /* Restore interrupts */
159 Hwi_restore(cookie);
160 }