Misra C Fixes:
[keystone-rtos/edma3_lld.git] / packages / ti / sdo / edma3 / rm / sample / src / platforms / sample_tda2xx_arm_int_reg.c
1 /*\r
2  * sample_tda2xx_int_reg.c\r
3  *\r
4  * Platform specific interrupt registration and un-registration routines.\r
5  *\r
6  * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/\r
7  *\r
8  *\r
9  *  Redistribution and use in source and binary forms, with or without\r
10  *  modification, are permitted provided that the following conditions\r
11  *  are met:\r
12  *\r
13  *    Redistributions of source code must retain the above copyright\r
14  *    notice, this list of conditions and the following disclaimer.\r
15  *\r
16  *    Redistributions in binary form must reproduce the above copyright\r
17  *    notice, this list of conditions and the following disclaimer in the\r
18  *    documentation and/or other materials provided with the\r
19  *    distribution.\r
20  *\r
21  *    Neither the name of Texas Instruments Incorporated nor the names of\r
22  *    its contributors may be used to endorse or promote products derived\r
23  *    from this software without specific prior written permission.\r
24  *\r
25  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
26  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
27  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
28  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
29  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
30  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
31  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
32  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
33  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
34  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
35  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
36  *\r
37 */\r
38 \r
39 #include <ti/sysbios/knl/Semaphore.h>\r
40 #include <ti/sysbios/hal/Hwi.h>\r
41 #include <xdc/runtime/Error.h>\r
42 #include <xdc/runtime/System.h>\r
43 \r
44 #include <ti/sdo/edma3/drv/sample/bios6_edma3_drv_sample.h>\r
45 \r
46 /**\r
47   * EDMA3 TC ISRs which need to be registered with the underlying OS by the user\r
48   * (Not all TC error ISRs need to be registered, register only for the\r
49   * available Transfer Controllers).\r
50   */\r
51 void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(uint32_t arg) =\r
52                                                 {\r
53                                                 &lisrEdma3TC0ErrHandler0,\r
54                                                 &lisrEdma3TC1ErrHandler0,\r
55                                                 &lisrEdma3TC2ErrHandler0,\r
56                                                 &lisrEdma3TC3ErrHandler0,\r
57                                                 &lisrEdma3TC4ErrHandler0,\r
58                                                 &lisrEdma3TC5ErrHandler0,\r
59                                                 &lisrEdma3TC6ErrHandler0,\r
60                                                 &lisrEdma3TC7ErrHandler0,\r
61                                                 };\r
62 \r
63 extern unsigned int ccXferCompInt[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGIONS];\r
64 extern unsigned int ccErrorInt[EDMA3_MAX_EDMA3_INSTANCES];\r
65 extern unsigned int tcErrorInt[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_TC];\r
66 extern unsigned int numEdma3Tc[EDMA3_MAX_EDMA3_INSTANCES];\r
67 \r
68 /**\r
69  * Variables which will be used internally for referring the hardware interrupt\r
70  * for various EDMA3 interrupts.\r
71  */\r
72 extern unsigned int hwIntXferComp[EDMA3_MAX_EDMA3_INSTANCES];\r
73 extern unsigned int hwIntCcErr[EDMA3_MAX_EDMA3_INSTANCES];\r
74 extern unsigned int hwIntTcErr[EDMA3_MAX_EDMA3_INSTANCES];\r
75 \r
76 extern unsigned int dsp_num;\r
77 /* This variable has to be used as an extern */\r
78 unsigned int gpp_num = 0;\r
79 \r
80 Hwi_Handle hwiCCXferCompInt;\r
81 Hwi_Handle hwiCCErrInt;\r
82 Hwi_Handle hwiTCErrInt[EDMA3_MAX_TC];\r
83 \r
84 /* External Instance Specific Configuration Structure */\r
85 extern EDMA3_DRV_GblXbarToChanConfigParams \r
86                                                                 sampleXbarChanInitConfig[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGIONS];\r
87 \r
88 typedef struct  {\r
89     volatile Uint32 TPCC_EVTMUX[32];\r
90 } CSL_IntmuxRegs;\r
91 \r
92 typedef volatile CSL_IntmuxRegs     *CSL_IntmuxRegsOvly;\r
93 \r
94 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK (0x00FF0000u)\r
95 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT (0x00000010u)\r
96 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_RESETVAL (0x00000000u)\r
97 \r
98 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK (0x000000FFu)\r
99 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_SHIFT (0x00000000u)\r
100 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_RESETVAL (0x00000000u)\r
101 \r
102 \r
103 #define EDMA3_MAX_CROSS_BAR_EVENTS_TDA2XX (127u)\r
104 #define EDMA3_NUM_TCC                     (64u)\r
105 \r
106 #define EDMA3_EVENT_MUX_REG_BASE_ADDR               (0x4a002c78)\r
107 \r
108 /*\r
109  * Forward decleration\r
110  */\r
111 EDMA3_DRV_Result sampleMapXbarEvtToChan (unsigned int eventNum,\r
112                  unsigned int *chanNum,\r
113                  const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig);\r
114 EDMA3_DRV_Result sampleConfigScr (unsigned int eventNum,\r
115                                   unsigned int chanNum);\r
116 \r
117 void Edma3MemProtectionHandler(unsigned int edma3InstanceId);\r
118 \r
119 /**  To Register the ISRs with the underlying OS, if required. */\r
120 void registerEdma3Interrupts (unsigned int edma3Id);\r
121 \r
122 /**  To Unregister the ISRs with the underlying OS, if previously registered. */\r
123 void unregisterEdma3Interrupts (unsigned int edma3Id);\r
124 \r
125 EDMA3_DRV_Result sampleInitXbarEvt(EDMA3_DRV_Handle hEdma, \r
126                                    unsigned int edma3Id);\r
127                                    \r
128 void Edma3MemProtectionHandler(unsigned int edma3InstanceId);\r
129 \r
130 /**  To Register the ISRs with the underlying OS, if required. */\r
131 void registerEdma3Interrupts (unsigned int edma3Id)\r
132     {\r
133     static UInt32 cookie = 0;\r
134     unsigned int numTc = 0;\r
135     Hwi_Params hwiParams; \r
136     Error_Block      eb;\r
137 \r
138     /* Initialize the Error Block                                             */\r
139     Error_init(&eb);\r
140         \r
141     /* Disabling the global interrupts */\r
142     cookie = Hwi_disable();\r
143 \r
144     /* Initialize the HWI parameters with user specified values */\r
145     Hwi_Params_init(&hwiParams);\r
146     \r
147     /* argument for the ISR */\r
148     hwiParams.arg = edma3Id;\r
149         /* set the priority ID     */\r
150         hwiParams.priority = hwIntXferComp[edma3Id];\r
151     \r
152     hwiCCXferCompInt = Hwi_create( ccXferCompInt[edma3Id][gpp_num],\r
153                                         ((Hwi_FuncPtr)&lisrEdma3ComplHandler0),\r
154                                         (const Hwi_Params *) (&hwiParams),\r
155                                         &eb);\r
156     if ((bool)TRUE == Error_check(&eb))\r
157     {\r
158         System_printf("HWI Create Failed\n",Error_getCode(&eb));\r
159     }\r
160 \r
161     /* Initialize the HWI parameters with user specified values */\r
162     Hwi_Params_init(&hwiParams);\r
163     /* argument for the ISR */\r
164     hwiParams.arg = edma3Id;\r
165         /* set the priority ID     */\r
166         hwiParams.priority = hwIntCcErr[edma3Id];\r
167         \r
168         hwiCCErrInt = Hwi_create( ccErrorInt[edma3Id],\r
169                 ((Hwi_FuncPtr)&lisrEdma3CCErrHandler0),\r
170                 (const Hwi_Params *) (&hwiParams),\r
171                 &eb);\r
172 \r
173     if ((bool)TRUE == Error_check(&eb))\r
174     {\r
175         System_printf("HWI Create Failed\n",Error_getCode(&eb));\r
176     }\r
177 \r
178     while (numTc < numEdma3Tc[edma3Id])\r
179             {\r
180         /* Initialize the HWI parameters with user specified values */\r
181         Hwi_Params_init(&hwiParams);\r
182         /* argument for the ISR */\r
183         hwiParams.arg = edma3Id;\r
184         /* set the priority ID     */\r
185         hwiParams.priority = hwIntTcErr[edma3Id];\r
186         \r
187         hwiTCErrInt[numTc] = Hwi_create( tcErrorInt[edma3Id][numTc],\r
188                     (ptrEdma3TcIsrHandler[numTc]),\r
189                     (const Hwi_Params *) (&hwiParams),\r
190                     &eb);\r
191         if ((bool)TRUE == Error_check(&eb))\r
192         {\r
193             System_printf("HWI Create Failed\n",Error_getCode(&eb));\r
194         }\r
195         numTc++;\r
196         }\r
197    /**\r
198     * Enabling the HWI_ID.\r
199     * EDMA3 interrupts (transfer completion, CC error etc.)\r
200     * correspond to different ECM events (SoC specific). These ECM events come\r
201     * under ECM block XXX (handling those specific ECM events). Normally, block\r
202     * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events\r
203     * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)\r
204     * is mapped to a specific HWI_INT YYY in the tcf file. So to enable this\r
205     * mapped HWI_INT YYY, one should use the corresponding bitmask in the\r
206     * API C64_enableIER(), in which the YYY bit is SET.\r
207     */\r
208     Hwi_enableInterrupt(ccErrorInt[edma3Id]);\r
209 #if 0\r
210     Hwi_enableInterrupt(13);\r
211 #endif\r
212     Hwi_enableInterrupt(ccXferCompInt[edma3Id][gpp_num]);\r
213     numTc = 0;\r
214     while (numTc < numEdma3Tc[edma3Id])\r
215             {\r
216         Hwi_enableInterrupt(tcErrorInt[edma3Id][numTc]);\r
217         numTc++;\r
218         }\r
219 \r
220     /* Restore interrupts */\r
221     Hwi_restore(cookie);\r
222     }\r
223 \r
224 /**  To Unregister the ISRs with the underlying OS, if previously registered. */\r
225 void unregisterEdma3Interrupts (unsigned int edma3Id)\r
226     {\r
227         static UInt32 cookiee = 0;\r
228     unsigned int numTc = 0;\r
229 \r
230     /* Disabling the global interrupts */\r
231     cookiee = Hwi_disable();\r
232 \r
233     Hwi_delete(&hwiCCXferCompInt);\r
234     Hwi_delete(&hwiCCErrInt);\r
235     while (numTc < numEdma3Tc[edma3Id])\r
236             {\r
237         Hwi_delete(&hwiTCErrInt[numTc]);\r
238         numTc++;\r
239         }\r
240     /* Restore interrupts */\r
241     Hwi_restore(cookiee);\r
242     }\r
243 \r
244 /**\r
245  * \brief   sampleMapXbarEvtToChan\r
246  *\r
247  * This function reads from the sample configuration structure which specifies \r
248  * cross bar events mapped to DMA channel.\r
249  *\r
250  * \return  EDMA3_DRV_SOK if success, else error code\r
251  */\r
252 EDMA3_DRV_Result sampleMapXbarEvtToChan (unsigned int eventNum,\r
253                  unsigned int *chanNum,\r
254                  const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig)\r
255         {\r
256     EDMA3_DRV_Result edma3Result = EDMA3_DRV_E_INVALID_PARAM;\r
257     unsigned int xbarEvtNum = 0;\r
258     int          edmaChanNum = 0;\r
259 \r
260         if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_TDA2XX) &&\r
261                 (chanNum != NULL) &&\r
262                 (edmaGblXbarConfig != NULL))\r
263                 {\r
264                 xbarEvtNum = eventNum - EDMA3_NUM_TCC;\r
265                 edmaChanNum = edmaGblXbarConfig->dmaMapXbarToChan[xbarEvtNum];\r
266                 if (edmaChanNum != -1)\r
267                         {\r
268                         *chanNum = edmaChanNum;\r
269                         edma3Result = EDMA3_DRV_SOK;\r
270                         }\r
271                 }\r
272         return (edma3Result);\r
273         }\r
274 \r
275 \r
276 /**\r
277  * \brief   sampleConfigScr\r
278  *\r
279  * This function configures control config registers for the cross bar events \r
280  * mapped to the EDMA channel.\r
281  *\r
282  * \return  EDMA3_DRV_SOK if success, else error code\r
283  */\r
284 EDMA3_DRV_Result sampleConfigScr (unsigned int eventNum,\r
285                                   unsigned int chanNum)\r
286         {\r
287     EDMA3_DRV_Result edma3Result = EDMA3_DRV_SOK;\r
288     unsigned int scrChanOffset = 0;\r
289     unsigned int scrRegOffset  = 0;\r
290     unsigned int xBarEvtNum    = 0;\r
291     CSL_IntmuxRegsOvly scrEvtMux = (CSL_IntmuxRegsOvly)(EDMA3_EVENT_MUX_REG_BASE_ADDR);\r
292 \r
293 \r
294         if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_TDA2XX) &&\r
295                 (chanNum < EDMA3_NUM_TCC))\r
296                 {\r
297                 scrRegOffset = chanNum / 2U;\r
298                 scrChanOffset = chanNum - (scrRegOffset * 2U);\r
299                 xBarEvtNum = eventNum + 1U;\r
300                 \r
301                 switch(scrChanOffset)\r
302                         {\r
303                         case 0:\r
304                                 scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=\r
305                                         (xBarEvtNum & CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK);\r
306                                 break;\r
307                         case 1U:\r
308                                 scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=\r
309                                         ((xBarEvtNum << CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT) & \r
310                                         (CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK));\r
311                                 break;\r
312                         default:\r
313                                 edma3Result = EDMA3_DRV_E_INVALID_PARAM;\r
314                                 break;\r
315                         }\r
316                 }\r
317         else\r
318                 {\r
319                 edma3Result = EDMA3_DRV_E_INVALID_PARAM;\r
320                 }\r
321         return edma3Result;\r
322         }\r
323 \r
324 EDMA3_DRV_Result sampleInitXbarEvt(EDMA3_DRV_Handle hEdma, \r
325                                    unsigned int edma3Id)\r
326     {\r
327     EDMA3_DRV_Result retVal = EDMA3_DRV_SOK;\r
328     const EDMA3_DRV_GblXbarToChanConfigParams *sampleXbarToChanConfig =\r
329                                 &(sampleXbarChanInitConfig[edma3Id][dsp_num]);\r
330     if (hEdma != NULL)\r
331         {\r
332         retVal = EDMA3_DRV_initXbarEventMap(hEdma, \r
333                                                                         sampleXbarToChanConfig, \r
334                                                                         (EDMA3_DRV_mapXbarEvtToChan)&sampleMapXbarEvtToChan, \r
335                                                                         (EDMA3_DRV_xbarConfigScr)&sampleConfigScr);\r
336         }\r
337     \r
338     return retVal;\r
339     }\r
340 \r
341 void Edma3MemProtectionHandler(unsigned int edma3InstanceId)\r
342     {\r
343 #ifdef EDMA3_RM_DEBUG\r
344     /*  Added to fix Misra C error */\r
345     printf("memory Protection error");\r
346 #endif\r
347     }\r