[keystone-rtos/edma3_lld.git] / packages / ti / sdo / edma3 / rm / sample / src / platforms / sample_tda2xx_arm_int_reg.c
1 /*\r
2 * sample_ti814x_int_reg.c\r
3 *\r
4 * Platform specific interrupt registration and un-registration routines.\r
5 *\r
6 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/\r
7 *\r
8 *\r
9 * Redistribution and use in source and binary forms, with or without\r
10 * modification, are permitted provided that the following conditions\r
11 * are met:\r
12 *\r
13 * Redistributions of source code must retain the above copyright\r
14 * notice, this list of conditions and the following disclaimer.\r
15 *\r
16 * Redistributions in binary form must reproduce the above copyright\r
17 * notice, this list of conditions and the following disclaimer in the\r
18 * documentation and/or other materials provided with the\r
19 * distribution.\r
20 *\r
21 * Neither the name of Texas Instruments Incorporated nor the names of\r
22 * its contributors may be used to endorse or promote products derived\r
23 * from this software without specific prior written permission.\r
24 *\r
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
36 *\r
37 */\r
38 \r
39 #include <ti/sysbios/knl/Semaphore.h>\r
40 #include <ti/sysbios/hal/Hwi.h>\r
41 #include <xdc/runtime/Error.h>\r
42 #include <xdc/runtime/System.h>\r
43 \r
44 #include <ti/sdo/edma3/drv/sample/bios6_edma3_drv_sample.h>\r
45 \r
46 /**\r
47 * EDMA3 TC ISRs which need to be registered with the underlying OS by the user\r
48 * (Not all TC error ISRs need to be registered, register only for the\r
49 * available Transfer Controllers).\r
50 */\r
51 void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(unsigned int arg) =\r
52 {\r
53 &lisrEdma3TC0ErrHandler0,\r
54 &lisrEdma3TC1ErrHandler0,\r
55 &lisrEdma3TC2ErrHandler0,\r
56 &lisrEdma3TC3ErrHandler0,\r
57 &lisrEdma3TC4ErrHandler0,\r
58 &lisrEdma3TC5ErrHandler0,\r
59 &lisrEdma3TC6ErrHandler0,\r
60 &lisrEdma3TC7ErrHandler0,\r
61 };\r
62 \r
63 extern unsigned int ccXferCompInt[][EDMA3_MAX_REGIONS];\r
64 extern unsigned int ccErrorInt[];\r
65 extern unsigned int tcErrorInt[][EDMA3_MAX_TC];\r
66 extern unsigned int numEdma3Tc[];\r
67 \r
68 /**\r
69 * Variables which will be used internally for referring the hardware interrupt\r
70 * for various EDMA3 interrupts.\r
71 */\r
72 extern unsigned int hwIntXferComp[];\r
73 extern unsigned int hwIntCcErr[];\r
74 extern unsigned int hwIntTcErr[];\r
75 \r
76 extern unsigned int dsp_num;\r
77 /* This variable has to be used as an extern */\r
78 unsigned int gpp_num = 0;\r
79 \r
80 Hwi_Handle hwiCCXferCompInt;\r
81 Hwi_Handle hwiCCErrInt;\r
82 Hwi_Handle hwiTCErrInt[EDMA3_MAX_TC];\r
83 \r
84 /* External Instance Specific Configuration Structure */\r
85 extern EDMA3_DRV_GblXbarToChanConfigParams \r
86 sampleXbarChanInitConfig[][EDMA3_MAX_REGIONS];\r
87 \r
88 typedef struct {\r
89 volatile Uint32 DSP_INTMUX[21];\r
90 volatile Uint32 DUCATI_INTMUX[15];\r
91 volatile Uint32 TPCC_EVTMUX[16];\r
92 volatile Uint32 TIMER_EVTCAPT;\r
93 volatile Uint32 GPIO_MUX;\r
94 } CSL_IntmuxRegs;\r
95 \r
96 typedef volatile CSL_IntmuxRegs *CSL_IntmuxRegsOvly;\r
97 \r
98 \r
99 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_MASK (0x3F000000u)\r
100 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_SHIFT (0x00000018u)\r
101 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_RESETVAL (0x00000000u)\r
102 \r
103 \r
104 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_MASK (0x003F0000u)\r
105 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_SHIFT (0x00000010u)\r
106 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_RESETVAL (0x00000000u)\r
107 \r
108 \r
109 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK (0x00003F00u)\r
110 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT (0x00000008u)\r
111 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_RESETVAL (0x00000000u)\r
112 \r
113 \r
114 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK (0x0000003Fu)\r
115 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_SHIFT (0x00000000u)\r
116 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_RESETVAL (0x00000000u)\r
117 \r
118 \r
119 #define EDMA3_MAX_CROSS_BAR_EVENTS_TI814X (95u)\r
120 #define EDMA3_NUM_TCC (64u)\r
121 \r
122 /*\r
123 * Forward decleration\r
124 */\r
125 EDMA3_DRV_Result sampleMapXbarEvtToChan (unsigned int eventNum,\r
126 unsigned int *chanNum,\r
127 const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig);\r
128 EDMA3_DRV_Result sampleConfigScr (unsigned int eventNum,\r
129 unsigned int chanNum);\r
130 \r
131 void Edma3MemProtectionHandler(unsigned int edma3InstanceId);\r
132 \r
133 /** To Register the ISRs with the underlying OS, if required. */\r
134 void registerEdma3Interrupts (unsigned int edma3Id)\r
135 {\r
136 static UInt32 cookie = 0;\r
137 unsigned int numTc = 0;\r
138 Hwi_Params hwiParams; \r
139 Error_Block eb;\r
140 \r
141 /* Initialize the Error Block */\r
142 Error_init(&eb);\r
143 \r
144 /* Disabling the global interrupts */\r
145 cookie = Hwi_disable();\r
146 \r
147 /* Initialize the HWI parameters with user specified values */\r
148 Hwi_Params_init(&hwiParams);\r
149 \r
150 /* argument for the ISR */\r
151 hwiParams.arg = edma3Id;\r
152 /* set the priority ID */\r
153 hwiParams.priority = hwIntXferComp[edma3Id];\r
154 \r
155 hwiCCXferCompInt = Hwi_create( ccXferCompInt[edma3Id][gpp_num],\r
156 (&lisrEdma3ComplHandler0),\r
157 (const Hwi_Params *) (&hwiParams),\r
158 &eb);\r
159 if (TRUE == Error_check(&eb))\r
160 {\r
161 System_printf("HWI Create Failed\n",Error_getCode(&eb));\r
162 }\r
163 \r
164 /* Initialize the HWI parameters with user specified values */\r
165 Hwi_Params_init(&hwiParams);\r
166 /* argument for the ISR */\r
167 hwiParams.arg = edma3Id;\r
168 /* set the priority ID */\r
169 hwiParams.priority = hwIntCcErr[edma3Id];\r
170 \r
171 hwiCCErrInt = Hwi_create( ccErrorInt[edma3Id],\r
172 (&lisrEdma3CCErrHandler0),\r
173 (const Hwi_Params *) (&hwiParams),\r
174 &eb);\r
175 \r
176 if (TRUE == Error_check(&eb))\r
177 {\r
178 System_printf("HWI Create Failed\n",Error_getCode(&eb));\r
179 }\r
180 \r
181 while (numTc < numEdma3Tc[edma3Id])\r
182 {\r
183 /* Initialize the HWI parameters with user specified values */\r
184 Hwi_Params_init(&hwiParams);\r
185 /* argument for the ISR */\r
186 hwiParams.arg = edma3Id;\r
187 /* set the priority ID */\r
188 hwiParams.priority = hwIntTcErr[edma3Id];\r
189 \r
190 hwiTCErrInt[numTc] = Hwi_create( tcErrorInt[edma3Id][numTc],\r
191 (ptrEdma3TcIsrHandler[numTc]),\r
192 (const Hwi_Params *) (&hwiParams),\r
193 &eb);\r
194 if (TRUE == Error_check(&eb))\r
195 {\r
196 System_printf("HWI Create Failed\n",Error_getCode(&eb));\r
197 }\r
198 numTc++;\r
199 }\r
200 /**\r
201 * Enabling the HWI_ID.\r
202 * EDMA3 interrupts (transfer completion, CC error etc.)\r
203 * correspond to different ECM events (SoC specific). These ECM events come\r
204 * under ECM block XXX (handling those specific ECM events). Normally, block\r
205 * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events\r
206 * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)\r
207 * is mapped to a specific HWI_INT YYY in the tcf file. So to enable this\r
208 * mapped HWI_INT YYY, one should use the corresponding bitmask in the\r
209 * API C64_enableIER(), in which the YYY bit is SET.\r
210 */\r
211 Hwi_enableInterrupt(ccErrorInt[edma3Id]);\r
212 #if 0\r
213 Hwi_enableInterrupt(13);\r
214 #endif\r
215 Hwi_enableInterrupt(ccXferCompInt[edma3Id][gpp_num]);\r
216 numTc = 0;\r
217 while (numTc < numEdma3Tc[edma3Id])\r
218 {\r
219 Hwi_enableInterrupt(tcErrorInt[edma3Id][numTc]);\r
220 numTc++;\r
221 }\r
222 \r
223 /* Restore interrupts */\r
224 Hwi_restore(cookie);\r
225 }\r
226 \r
227 /** To Unregister the ISRs with the underlying OS, if previously registered. */\r
228 void unregisterEdma3Interrupts (unsigned int edma3Id)\r
229 {\r
230 static UInt32 cookie = 0;\r
231 unsigned int numTc = 0;\r
232 \r
233 /* Disabling the global interrupts */\r
234 cookie = Hwi_disable();\r
235 \r
236 Hwi_delete(&hwiCCXferCompInt);\r
237 Hwi_delete(&hwiCCErrInt);\r
238 while (numTc < numEdma3Tc[edma3Id])\r
239 {\r
240 Hwi_delete(&hwiTCErrInt[numTc]);\r
241 numTc++;\r
242 }\r
243 /* Restore interrupts */\r
244 Hwi_restore(cookie);\r
245 }\r
246 \r
247 /**\r
248 * \brief sampleMapXbarEvtToChan\r
249 *\r
250 * This function reads from the sample configuration structure which specifies \r
251 * cross bar events mapped to DMA channel.\r
252 *\r
253 * \return EDMA3_DRV_SOK if success, else error code\r
254 */\r
255 EDMA3_DRV_Result sampleMapXbarEvtToChan (unsigned int eventNum,\r
256 unsigned int *chanNum,\r
257 const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig)\r
258 {\r
259 EDMA3_DRV_Result edma3Result = EDMA3_DRV_E_INVALID_PARAM;\r
260 unsigned int xbarEvtNum = 0;\r
261 int edmaChanNum = 0;\r
262 \r
263 if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_TI814X) &&\r
264 (chanNum != NULL) &&\r
265 (edmaGblXbarConfig != NULL))\r
266 {\r
267 xbarEvtNum = eventNum - EDMA3_NUM_TCC;\r
268 edmaChanNum = edmaGblXbarConfig->dmaMapXbarToChan[xbarEvtNum];\r
269 if (edmaChanNum != -1)\r
270 {\r
271 *chanNum = edmaChanNum;\r
272 edma3Result = EDMA3_DRV_SOK;\r
273 }\r
274 }\r
275 return (edma3Result);\r
276 }\r
277 \r
278 \r
279 /**\r
280 * \brief sampleConfigScr\r
281 *\r
282 * This function configures control config registers for the cross bar events \r
283 * mapped to the EDMA channel.\r
284 *\r
285 * \return EDMA3_DRV_SOK if success, else error code\r
286 */\r
287 EDMA3_DRV_Result sampleConfigScr (unsigned int eventNum,\r
288 unsigned int chanNum)\r
289 {\r
290 EDMA3_DRV_Result edma3Result = EDMA3_DRV_SOK;\r
291 unsigned int scrChanOffset = 0;\r
292 unsigned int scrRegOffset = 0;\r
293 unsigned int xBarEvtNum = 0;\r
294 CSL_IntmuxRegsOvly scrEvtMux = (CSL_IntmuxRegsOvly)(0x48140F00);\r
295 \r
296 \r
297 if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_TI814X) &&\r
298 (chanNum < EDMA3_NUM_TCC))\r
299 {\r
300 scrRegOffset = chanNum / 4;\r
301 scrChanOffset = chanNum - (scrRegOffset * 4);\r
302 xBarEvtNum = (eventNum - EDMA3_NUM_TCC) + 1;\r
303 \r
304 switch(scrChanOffset)\r
305 {\r
306 case 0:\r
307 scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=\r
308 (xBarEvtNum & CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK);\r
309 break;\r
310 case 1:\r
311 scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=\r
312 ((xBarEvtNum << CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT) & \r
313 (CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK));\r
314 break;\r
315 case 2:\r
316 scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=\r
317 ((xBarEvtNum << CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_SHIFT) & \r
318 (CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_MASK));\r
319 break;\r
320 case 3:\r
321 scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=\r
322 ((xBarEvtNum << CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_SHIFT) & \r
323 (CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_MASK));\r
324 break;\r
325 default:\r
326 edma3Result = EDMA3_DRV_E_INVALID_PARAM;\r
327 break;\r
328 }\r
329 }\r
330 else\r
331 {\r
332 edma3Result = EDMA3_DRV_E_INVALID_PARAM;\r
333 }\r
334 return edma3Result;\r
335 }\r
336 \r
337 EDMA3_DRV_Result sampleInitXbarEvt(EDMA3_DRV_Handle hEdma, \r
338 unsigned int edma3Id)\r
339 {\r
340 EDMA3_DRV_Result retVal = EDMA3_DRV_SOK;\r
341 const EDMA3_DRV_GblXbarToChanConfigParams *sampleXbarToChanConfig =\r
342 &(sampleXbarChanInitConfig[edma3Id][dsp_num]);\r
343 if (hEdma != NULL)\r
344 {\r
345 retVal = EDMA3_DRV_initXbarEventMap(hEdma, \r
346 sampleXbarToChanConfig, \r
347 &sampleMapXbarEvtToChan, \r
348 &sampleConfigScr);\r
349 }\r
350 \r
351 return retVal;\r
352 }\r
353 \r
354 void Edma3MemProtectionHandler(unsigned int edma3InstanceId)\r
355 {\r
356 printf("memory Protection error");\r
357 }\r