f4db950e74735d084c8fb3081c7e6929f82396db
[keystone-rtos/edma3_lld.git] / packages / ti / sdo / edma3 / rm / sample / src / platforms / sample_tda2xx_arm_int_reg.c
1 /*\r
2  * sample_tda2xx_int_reg.c\r
3  *\r
4  * Platform specific interrupt registration and un-registration routines.\r
5  *\r
6  * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/\r
7  *\r
8  *\r
9  *  Redistribution and use in source and binary forms, with or without\r
10  *  modification, are permitted provided that the following conditions\r
11  *  are met:\r
12  *\r
13  *    Redistributions of source code must retain the above copyright\r
14  *    notice, this list of conditions and the following disclaimer.\r
15  *\r
16  *    Redistributions in binary form must reproduce the above copyright\r
17  *    notice, this list of conditions and the following disclaimer in the\r
18  *    documentation and/or other materials provided with the\r
19  *    distribution.\r
20  *\r
21  *    Neither the name of Texas Instruments Incorporated nor the names of\r
22  *    its contributors may be used to endorse or promote products derived\r
23  *    from this software without specific prior written permission.\r
24  *\r
25  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
26  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
27  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
28  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
29  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
30  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
31  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
32  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
33  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
34  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
35  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
36  *\r
37 */\r
38 \r
39 #include <ti/sysbios/knl/Semaphore.h>\r
40 #include <ti/sysbios/hal/Hwi.h>\r
41 #include <xdc/runtime/Error.h>\r
42 #include <xdc/runtime/System.h>\r
43 \r
44 #include <ti/sdo/edma3/drv/sample/bios6_edma3_drv_sample.h>\r
45 \r
46 /**\r
47   * EDMA3 TC ISRs which need to be registered with the underlying OS by the user\r
48   * (Not all TC error ISRs need to be registered, register only for the\r
49   * available Transfer Controllers).\r
50   */\r
51 void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(uint32_t arg) =\r
52                                                 {\r
53                                                 (void (*)(uint32_t))&lisrEdma3TC0ErrHandler0,\r
54                                                 (void (*)(uint32_t))&lisrEdma3TC1ErrHandler0,\r
55                                                 (void (*)(uint32_t))&lisrEdma3TC2ErrHandler0,\r
56                                                 (void (*)(uint32_t))&lisrEdma3TC3ErrHandler0,\r
57                                                 (void (*)(uint32_t))&lisrEdma3TC4ErrHandler0,\r
58                                                 (void (*)(uint32_t))&lisrEdma3TC5ErrHandler0,\r
59                                                 (void (*)(uint32_t))&lisrEdma3TC6ErrHandler0,\r
60                                                 (void (*)(uint32_t))&lisrEdma3TC7ErrHandler0,\r
61                                                 };\r
62 \r
63 extern unsigned int ccXferCompInt[][EDMA3_MAX_REGIONS];\r
64 extern unsigned int ccErrorInt[];\r
65 extern unsigned int tcErrorInt[][EDMA3_MAX_TC];\r
66 extern unsigned int numEdma3Tc[];\r
67 \r
68 /**\r
69  * Variables which will be used internally for referring the hardware interrupt\r
70  * for various EDMA3 interrupts.\r
71  */\r
72 extern unsigned int hwIntXferComp[];\r
73 extern unsigned int hwIntCcErr[];\r
74 extern unsigned int hwIntTcErr[];\r
75 \r
76 extern unsigned int dsp_num;\r
77 /* This variable has to be used as an extern */\r
78 unsigned int gpp_num = 0;\r
79 \r
80 Hwi_Handle hwiCCXferCompInt;\r
81 Hwi_Handle hwiCCErrInt;\r
82 Hwi_Handle hwiTCErrInt[EDMA3_MAX_TC];\r
83 \r
84 /* External Instance Specific Configuration Structure */\r
85 extern EDMA3_DRV_GblXbarToChanConfigParams \r
86                                                                 sampleXbarChanInitConfig[][EDMA3_MAX_REGIONS];\r
87 \r
88 typedef struct  {\r
89     volatile Uint32 TPCC_EVTMUX[32];\r
90 } CSL_IntmuxRegs;\r
91 \r
92 typedef volatile CSL_IntmuxRegs     *CSL_IntmuxRegsOvly;\r
93 \r
94 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK (0x00FF0000u)\r
95 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT (0x00000010u)\r
96 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_RESETVAL (0x00000000u)\r
97 \r
98 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK (0x000000FFu)\r
99 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_SHIFT (0x00000000u)\r
100 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_RESETVAL (0x00000000u)\r
101 \r
102 \r
103 #define EDMA3_MAX_CROSS_BAR_EVENTS_TDA2XX (127u)\r
104 #define EDMA3_NUM_TCC                     (64u)\r
105 \r
106 #define EDMA3_EVENT_MUX_REG_BASE_ADDR               (0x4a002c78)\r
107 \r
108 /*\r
109  * Forward decleration\r
110  */\r
111 EDMA3_DRV_Result sampleMapXbarEvtToChan (unsigned int eventNum,\r
112                  unsigned int *chanNum,\r
113                  const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig);\r
114 EDMA3_DRV_Result sampleConfigScr (unsigned int eventNum,\r
115                                   unsigned int chanNum);\r
116 \r
117 void Edma3MemProtectionHandler(unsigned int edma3InstanceId);\r
118 \r
119 /**  To Register the ISRs with the underlying OS, if required. */\r
120 void registerEdma3Interrupts (unsigned int edma3Id)\r
121     {\r
122     static UInt32 cookie = 0;\r
123     unsigned int numTc = 0;\r
124     Hwi_Params hwiParams; \r
125     Error_Block      eb;\r
126 \r
127     /* Initialize the Error Block                                             */\r
128     Error_init(&eb);\r
129         \r
130     /* Disabling the global interrupts */\r
131     cookie = Hwi_disable();\r
132 \r
133     /* Initialize the HWI parameters with user specified values */\r
134     Hwi_Params_init(&hwiParams);\r
135     \r
136     /* argument for the ISR */\r
137     hwiParams.arg = edma3Id;\r
138         /* set the priority ID     */\r
139         hwiParams.priority = hwIntXferComp[edma3Id];\r
140     \r
141     hwiCCXferCompInt = Hwi_create( ccXferCompInt[edma3Id][gpp_num],\r
142                                         ((Hwi_FuncPtr)&lisrEdma3ComplHandler0),\r
143                                         (const Hwi_Params *) (&hwiParams),\r
144                                         &eb);\r
145     if (TRUE == Error_check(&eb))\r
146     {\r
147         System_printf("HWI Create Failed\n",Error_getCode(&eb));\r
148     }\r
149 \r
150     /* Initialize the HWI parameters with user specified values */\r
151     Hwi_Params_init(&hwiParams);\r
152     /* argument for the ISR */\r
153     hwiParams.arg = edma3Id;\r
154         /* set the priority ID     */\r
155         hwiParams.priority = hwIntCcErr[edma3Id];\r
156         \r
157         hwiCCErrInt = Hwi_create( ccErrorInt[edma3Id],\r
158                 ((Hwi_FuncPtr)&lisrEdma3CCErrHandler0),\r
159                 (const Hwi_Params *) (&hwiParams),\r
160                 &eb);\r
161 \r
162     if (TRUE == Error_check(&eb))\r
163     {\r
164         System_printf("HWI Create Failed\n",Error_getCode(&eb));\r
165     }\r
166 \r
167     while (numTc < numEdma3Tc[edma3Id])\r
168             {\r
169         /* Initialize the HWI parameters with user specified values */\r
170         Hwi_Params_init(&hwiParams);\r
171         /* argument for the ISR */\r
172         hwiParams.arg = edma3Id;\r
173         /* set the priority ID     */\r
174         hwiParams.priority = hwIntTcErr[edma3Id];\r
175         \r
176         hwiTCErrInt[numTc] = Hwi_create( tcErrorInt[edma3Id][numTc],\r
177                     (ptrEdma3TcIsrHandler[numTc]),\r
178                     (const Hwi_Params *) (&hwiParams),\r
179                     &eb);\r
180         if (TRUE == Error_check(&eb))\r
181         {\r
182             System_printf("HWI Create Failed\n",Error_getCode(&eb));\r
183         }\r
184         numTc++;\r
185         }\r
186    /**\r
187     * Enabling the HWI_ID.\r
188     * EDMA3 interrupts (transfer completion, CC error etc.)\r
189     * correspond to different ECM events (SoC specific). These ECM events come\r
190     * under ECM block XXX (handling those specific ECM events). Normally, block\r
191     * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events\r
192     * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)\r
193     * is mapped to a specific HWI_INT YYY in the tcf file. So to enable this\r
194     * mapped HWI_INT YYY, one should use the corresponding bitmask in the\r
195     * API C64_enableIER(), in which the YYY bit is SET.\r
196     */\r
197     Hwi_enableInterrupt(ccErrorInt[edma3Id]);\r
198 #if 0\r
199     Hwi_enableInterrupt(13);\r
200 #endif\r
201     Hwi_enableInterrupt(ccXferCompInt[edma3Id][gpp_num]);\r
202     numTc = 0;\r
203     while (numTc < numEdma3Tc[edma3Id])\r
204             {\r
205         Hwi_enableInterrupt(tcErrorInt[edma3Id][numTc]);\r
206         numTc++;\r
207         }\r
208 \r
209     /* Restore interrupts */\r
210     Hwi_restore(cookie);\r
211     }\r
212 \r
213 /**  To Unregister the ISRs with the underlying OS, if previously registered. */\r
214 void unregisterEdma3Interrupts (unsigned int edma3Id)\r
215     {\r
216         static UInt32 cookie = 0;\r
217     unsigned int numTc = 0;\r
218 \r
219     /* Disabling the global interrupts */\r
220     cookie = Hwi_disable();\r
221 \r
222     Hwi_delete(&hwiCCXferCompInt);\r
223     Hwi_delete(&hwiCCErrInt);\r
224     while (numTc < numEdma3Tc[edma3Id])\r
225             {\r
226         Hwi_delete(&hwiTCErrInt[numTc]);\r
227         numTc++;\r
228         }\r
229     /* Restore interrupts */\r
230     Hwi_restore(cookie);\r
231     }\r
232 \r
233 /**\r
234  * \brief   sampleMapXbarEvtToChan\r
235  *\r
236  * This function reads from the sample configuration structure which specifies \r
237  * cross bar events mapped to DMA channel.\r
238  *\r
239  * \return  EDMA3_DRV_SOK if success, else error code\r
240  */\r
241 EDMA3_DRV_Result sampleMapXbarEvtToChan (unsigned int eventNum,\r
242                  unsigned int *chanNum,\r
243                  const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig)\r
244         {\r
245     EDMA3_DRV_Result edma3Result = EDMA3_DRV_E_INVALID_PARAM;\r
246     unsigned int xbarEvtNum = 0;\r
247     int          edmaChanNum = 0;\r
248 \r
249         if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_TDA2XX) &&\r
250                 (chanNum != NULL) &&\r
251                 (edmaGblXbarConfig != NULL))\r
252                 {\r
253                 xbarEvtNum = eventNum - EDMA3_NUM_TCC;\r
254                 edmaChanNum = edmaGblXbarConfig->dmaMapXbarToChan[xbarEvtNum];\r
255                 if (edmaChanNum != -1)\r
256                         {\r
257                         *chanNum = edmaChanNum;\r
258                         edma3Result = EDMA3_DRV_SOK;\r
259                         }\r
260                 }\r
261         return (edma3Result);\r
262         }\r
263 \r
264 \r
265 /**\r
266  * \brief   sampleConfigScr\r
267  *\r
268  * This function configures control config registers for the cross bar events \r
269  * mapped to the EDMA channel.\r
270  *\r
271  * \return  EDMA3_DRV_SOK if success, else error code\r
272  */\r
273 EDMA3_DRV_Result sampleConfigScr (unsigned int eventNum,\r
274                                   unsigned int chanNum)\r
275         {\r
276     EDMA3_DRV_Result edma3Result = EDMA3_DRV_SOK;\r
277     unsigned int scrChanOffset = 0;\r
278     unsigned int scrRegOffset  = 0;\r
279     unsigned int xBarEvtNum    = 0;\r
280     CSL_IntmuxRegsOvly scrEvtMux = (CSL_IntmuxRegsOvly)(EDMA3_EVENT_MUX_REG_BASE_ADDR);\r
281 \r
282 \r
283         if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_TDA2XX) &&\r
284                 (chanNum < EDMA3_NUM_TCC))\r
285                 {\r
286                 scrRegOffset = chanNum / 2;\r
287                 scrChanOffset = chanNum - (scrRegOffset * 2);\r
288                 xBarEvtNum = eventNum + 1;\r
289                 \r
290                 switch(scrChanOffset)\r
291                         {\r
292                         case 0:\r
293                                 scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=\r
294                                         (xBarEvtNum & CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK);\r
295                                 break;\r
296                         case 1:\r
297                                 scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=\r
298                                         ((xBarEvtNum << CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT) & \r
299                                         (CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK));\r
300                                 break;\r
301                         default:\r
302                                 edma3Result = EDMA3_DRV_E_INVALID_PARAM;\r
303                                 break;\r
304                         }\r
305                 }\r
306         else\r
307                 {\r
308                 edma3Result = EDMA3_DRV_E_INVALID_PARAM;\r
309                 }\r
310         return edma3Result;\r
311         }\r
312 \r
313 EDMA3_DRV_Result sampleInitXbarEvt(EDMA3_DRV_Handle hEdma, \r
314                                    unsigned int edma3Id)\r
315     {\r
316     EDMA3_DRV_Result retVal = EDMA3_DRV_SOK;\r
317     const EDMA3_DRV_GblXbarToChanConfigParams *sampleXbarToChanConfig =\r
318                                 &(sampleXbarChanInitConfig[edma3Id][dsp_num]);\r
319     if (hEdma != NULL)\r
320         {\r
321         retVal = EDMA3_DRV_initXbarEventMap(hEdma, \r
322                                                                         sampleXbarToChanConfig, \r
323                                                                         (EDMA3_DRV_mapXbarEvtToChan)&sampleMapXbarEvtToChan, \r
324                                                                         (EDMA3_DRV_xbarConfigScr)&sampleConfigScr);\r
325         }\r
326     \r
327     return retVal;\r
328     }\r
329 \r
330 void Edma3MemProtectionHandler(unsigned int edma3InstanceId)\r
331     {\r
332     printf("memory Protection error");\r
333     }\r