PRSDK-3125: Update remainig
[keystone-rtos/edma3_lld.git] / packages / ti / sdo / edma3 / rm / sample / src / platforms / sample_tda2xx_cfg.c
1 /*\r
2  * sample_omapl138_cfg.c\r
3  *\r
4  * Platform specific EDMA3 hardware related information like number of transfer\r
5  * controllers, various interrupt ids etc. It is used while interrupts\r
6  * enabling / disabling. It needs to be ported for different SoCs.\r
7  *\r
8  * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/\r
9  *\r
10  *\r
11  *  Redistribution and use in source and binary forms, with or without\r
12  *  modification, are permitted provided that the following conditions\r
13  *  are met:\r
14  *\r
15  *    Redistributions of source code must retain the above copyright\r
16  *    notice, this list of conditions and the following disclaimer.\r
17  *\r
18  *    Redistributions in binary form must reproduce the above copyright\r
19  *    notice, this list of conditions and the following disclaimer in the\r
20  *    documentation and/or other materials provided with the\r
21  *    distribution.\r
22  *\r
23  *    Neither the name of Texas Instruments Incorporated nor the names of\r
24  *    its contributors may be used to endorse or promote products derived\r
25  *    from this software without specific prior written permission.\r
26  *\r
27  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
28  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
29  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
30  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
31  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
32  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
33  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
34  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
35  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
36  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
37  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
38  *\r
39 */\r
40 \r
41 #include <ti/sdo/edma3/rm/edma3_rm.h>\r
42 #ifdef BUILD_TDA2XX_IPU\r
43 #include <ti/sysbios/family/arm/ducati/Core.h> \r
44 \r
45 #endif\r
46 /* Number of EDMA3 controllers present in the system */\r
47 #define NUM_EDMA3_INSTANCES         3U\r
48 const uint32_t numEdma3Instances = NUM_EDMA3_INSTANCES;\r
49 \r
50 /* Number of DSPs present in the system */\r
51 #define NUM_DSPS                    1U\r
52 const uint32_t numDsps = NUM_DSPS;\r
53 \r
54 /* Determine the processor id by reading DNUM register. */\r
55 /* Statically allocate the region numbers with cores. */\r
56 volatile int32_t myCoreNum;\r
57 #define PID0_ADDRESS 0xE00FFFE0\r
58 #define CORE_ID_C0 0x0\r
59 #define CORE_ID_C1 0x1\r
60 \r
61 #ifdef BUILD_TDA2XX_MPU\r
62 static inline void readProcFeatureReg(void);\r
63 static inline void readProcFeatureReg(void)\r
64 {\r
65     asm ("    push    {r0-r2} \n\t"\r
66              "    MRC p15, 0, r0, c0, c0, 5\n\t"\r
67                  "    LDR      r1, =myCoreNum\n\t"\r
68                  "    STR      r0, [r1]\n\t"\r
69                  "    pop    {r0-r2}\n\t");\r
70 }\r
71 #endif\r
72 \r
73 int8_t*  getGlobalAddr(int8_t* addr);\r
74 \r
75 uint16_t isGblConfigRequired(uint32_t dspNum);\r
76 \r
77 uint16_t determineProcId(void);\r
78 \r
79 uint16_t determineProcId(void)\r
80 {\r
81 uint16_t regionNo = (uint16_t)numEdma3Instances;\r
82 #ifdef BUILD_TDA2XX_DSP\r
83 extern __cregister volatile uint32_t DNUM;\r
84 #endif\r
85 myCoreNum = (int32_t)numDsps;\r
86 #ifdef BUILD_TDA2XX_MPU\r
87 \r
88     readProcFeatureReg();\r
89                 regionNo = 0U;\r
90 /* myCoreNum is always 1 here, fix for klocwork error(Unreachable code) */\r
91         if(((uint32_t)myCoreNum & 0x03U) == 1U)\r
92     {\r
93                 regionNo = 1U;\r
94     }\r
95 #elif defined(BUILD_TDA2XX_IPU)\r
96 myCoreNum = (*(volatile uint32_t *)(PID0_ADDRESS));\r
97 if(Core_getIpuId() == 1){\r
98         if(myCoreNum == CORE_ID_C0)\r
99     {\r
100                 regionNo = 4U;\r
101     }\r
102         else if (myCoreNum == CORE_ID_C1)\r
103     {\r
104                 regionNo = 5U;\r
105     }\r
106     else\r
107     {\r
108         ;/* Nothing to be done */\r
109     }\r
110 }\r
111 if(Core_getIpuId() == 2){\r
112         if(myCoreNum == CORE_ID_C0)\r
113     {\r
114                 regionNo = 6U;\r
115     }\r
116         else if (myCoreNum == CORE_ID_C1)\r
117     {\r
118                 regionNo = 7U;\r
119     }\r
120     else\r
121     {\r
122         ;/* Nothing to be done */\r
123     }\r
124 }\r
125 #elif defined BUILD_TDA2XX_DSP\r
126         myCoreNum = DNUM;\r
127         if(myCoreNum == 0)\r
128     {\r
129                 regionNo = 2;\r
130     }\r
131         else\r
132     {\r
133                 regionNo = 3;\r
134     }\r
135 #endif\r
136         return regionNo;\r
137 }\r
138 \r
139 int8_t*  getGlobalAddr(int8_t* addr)\r
140 {\r
141      return (addr); /* The address is already a global address */\r
142 }\r
143 uint16_t isGblConfigRequired(uint32_t dspNum)\r
144 {\r
145     (void) dspNum;\r
146 \r
147     return 1U;\r
148 }\r
149 \r
150 /* Semaphore handles */\r
151 EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};\r
152 \r
153 /** Number of PaRAM Sets available                                            */\r
154 #define EDMA3_NUM_PARAMSET                              (512U)\r
155 \r
156 /** Number of TCCS available                                                  */\r
157 #define EDMA3_NUM_TCC                                   (64U)\r
158 \r
159 /** Number of DMA Channels available                                          */\r
160 #define EDMA3_NUM_DMA_CHANNELS                          (64U)\r
161 \r
162 /** Number of QDMA Channels available                                         */\r
163 #define EDMA3_NUM_QDMA_CHANNELS                         (8U)\r
164 \r
165 /** Number of Event Queues available                                          */\r
166 #define EDMA3_NUM_EVTQUE                                (4U)\r
167 \r
168 /** Number of Transfer Controllers available                                  */\r
169 #define EDMA3_NUM_TC                                    (2U)\r
170 \r
171 /** Number of Regions                                                         */\r
172 #define EDMA3_NUM_REGIONS                               (8U)\r
173 \r
174 /* EDMA3 configuaration for EVE */\r
175 \r
176 /** Number of PaRAM Sets available                                            */\r
177 #define EDMA3_NUM_PARAMSET_EVE                          (64U)\r
178 \r
179 /** Number of TCCS available                                                  */\r
180 #define EDMA3_NUM_TCC_EVE                               (16U)\r
181 \r
182 /** Number of DMA Channels available                                          */\r
183 #define EDMA3_NUM_DMA_CHANNELS_EVE                      (16U)\r
184 \r
185 /** Number of QDMA Channels available                                         */\r
186 #define EDMA3_NUM_QDMA_CHANNELS_EVE                     (8U)\r
187 \r
188 /** Number of Event Queues available                                          */\r
189 #define EDMA3_NUM_EVTQUE_EVE                            (2U)\r
190 \r
191 /** Number of Transfer Controllers available                                  */\r
192 #define EDMA3_NUM_TC_EVE                                (2U)\r
193 \r
194 /** Number of Regions                                                         */\r
195 #define EDMA3_NUM_REGIONS_EVE                           (8U)\r
196 \r
197 \r
198 /** Interrupt no. for Transfer Completion */\r
199 #define EDMA3_CC_XFER_COMPLETION_INT_A15                (66U)\r
200 #define EDMA3_CC_XFER_COMPLETION_INT_DSP                (38U)\r
201 #define EDMA3_CC_XFER_COMPLETION_INT_IPU_C0             (34U)\r
202 #define EDMA3_CC_XFER_COMPLETION_INT_IPU_C1             (33U)\r
203 #define EDMA3_CC_XFER_COMPLETION_INT_EVE                (8U)\r
204 \r
205 /** Based on the interrupt number to be mapped define the XBAR instance number */\r
206 #define COMPLETION_INT_A15_XBAR_INST_NO                 (29U)\r
207 #define COMPLETION_INT_DSP_XBAR_INST_NO                 (7U)\r
208 #define COMPLETION_INT_IPU_C0_XBAR_INST_NO              (12U)\r
209 #define COMPLETION_INT_IPU_C1_XBAR_INST_NO              (11U)\r
210 \r
211 /** Interrupt no. for CC Error */\r
212 #define EDMA3_CC_ERROR_INT_A15                          (67U)\r
213 #define EDMA3_CC_ERROR_INT_DSP                          (39U)\r
214 #define EDMA3_CC_ERROR_INT_IPU                          (35U)\r
215 #define EDMA3_CC_ERROR_INT_EVE                          (23U)\r
216 \r
217 /** Based on the interrupt number to be mapped define the XBAR instance number */\r
218 #define CC_ERROR_INT_A15_XBAR_INST_NO                   (30U)\r
219 #define CC_ERROR_INT_DSP_XBAR_INST_NO                   (8U)\r
220 #define CC_ERROR_INT_IPU_XBAR_INST_NO                   (13U)\r
221 \r
222 /** Interrupt no. for TCs Error */\r
223 #define EDMA3_TC0_ERROR_INT_A15                         (68U)\r
224 #define EDMA3_TC0_ERROR_INT_DSP                         (40U)\r
225 #define EDMA3_TC0_ERROR_INT_IPU                         (36U)\r
226 #define EDMA3_TC0_ERROR_INT_EVE                         (24U)\r
227 #define EDMA3_TC1_ERROR_INT_A15                         (69U)\r
228 #define EDMA3_TC1_ERROR_INT_DSP                         (41U)\r
229 #define EDMA3_TC1_ERROR_INT_IPU                         (37U)\r
230 #define EDMA3_TC1_ERROR_INT_EVE                         (25U)\r
231 \r
232 /** Based on the interrupt number to be mapped define the XBAR instance number */\r
233 #define TC0_ERROR_INT_A15_XBAR_INST_NO                  (31U)\r
234 #define TC0_ERROR_INT_DSP_XBAR_INST_NO                  (9U) \r
235 #define TC0_ERROR_INT_IPU_XBAR_INST_NO                  (14U)\r
236 #define TC1_ERROR_INT_A15_XBAR_INST_NO                  (32U)\r
237 #define TC1_ERROR_INT_DSP_XBAR_INST_NO                  (10U)\r
238 #define TC1_ERROR_INT_IPU_XBAR_INST_NO                  (15U)\r
239 \r
240 #ifdef BUILD_TDA2XX_MPU\r
241 #define EDMA3_CC_XFER_COMPLETION_INT                    (EDMA3_CC_XFER_COMPLETION_INT_A15)\r
242 #define EDMA3_CC_ERROR_INT                              (EDMA3_CC_ERROR_INT_A15)\r
243 #define CC_ERROR_INT_XBAR_INST_NO                       (CC_ERROR_INT_A15_XBAR_INST_NO)\r
244 #define EDMA3_TC0_ERROR_INT                             (EDMA3_TC0_ERROR_INT_A15)\r
245 #define EDMA3_TC1_ERROR_INT                             (EDMA3_TC1_ERROR_INT_A15)\r
246 #define TC0_ERROR_INT_XBAR_INST_NO                      (TC0_ERROR_INT_A15_XBAR_INST_NO)\r
247 #define TC1_ERROR_INT_XBAR_INST_NO                      (TC1_ERROR_INT_A15_XBAR_INST_NO)\r
248 \r
249 #elif defined BUILD_TDA2XX_DSP\r
250 #define EDMA3_CC_XFER_COMPLETION_INT                    (EDMA3_CC_XFER_COMPLETION_INT_DSP)\r
251 #define EDMA3_CC_ERROR_INT                              (EDMA3_CC_ERROR_INT_DSP)\r
252 #define CC_ERROR_INT_XBAR_INST_NO                       (CC_ERROR_INT_DSP_XBAR_INST_NO)\r
253 #define EDMA3_TC0_ERROR_INT                             (EDMA3_TC0_ERROR_INT_DSP)\r
254 #define EDMA3_TC1_ERROR_INT                             (EDMA3_TC1_ERROR_INT_DSP)\r
255 #define TC0_ERROR_INT_XBAR_INST_NO                      (TC0_ERROR_INT_DSP_XBAR_INST_NO)\r
256 #define TC1_ERROR_INT_XBAR_INST_NO                      (TC1_ERROR_INT_DSP_XBAR_INST_NO)\r
257 \r
258 #elif defined BUILD_TDA2XX_IPU\r
259 #define EDMA3_CC_XFER_COMPLETION_INT                    (EDMA3_CC_XFER_COMPLETION_INT_IPU_C0)\r
260 #define EDMA3_CC_ERROR_INT                              (EDMA3_CC_ERROR_INT_IPU)\r
261 #define CC_ERROR_INT_XBAR_INST_NO                       (CC_ERROR_INT_IPU_XBAR_INST_NO)\r
262 #define EDMA3_TC0_ERROR_INT                             (EDMA3_TC0_ERROR_INT_IPU)\r
263 #define EDMA3_TC1_ERROR_INT                             (EDMA3_TC1_ERROR_INT_IPU)\r
264 #define TC0_ERROR_INT_XBAR_INST_NO                      (TC0_ERROR_INT_IPU_XBAR_INST_NO)\r
265 #define TC1_ERROR_INT_XBAR_INST_NO                      (TC1_ERROR_INT_IPU_XBAR_INST_NO)\r
266 \r
267 #elif defined BUILD_TDA2XX_EVE\r
268 #define EDMA3_CC_XFER_COMPLETION_INT                    (EDMA3_CC_XFER_COMPLETION_INT_EVE)\r
269 #define EDMA3_CC_ERROR_INT                              (EDMA3_CC_ERROR_INT_EVE)\r
270 #define EDMA3_TC0_ERROR_INT                             (EDMA3_TC0_ERROR_INT_EVE)\r
271 #define EDMA3_TC1_ERROR_INT                             (EDMA3_TC1_ERROR_INT_EVE)\r
272 /* For accessing EVE internal edma, there is no need to configure Xbar */\r
273 #define CC_ERROR_INT_XBAR_INST_NO                       (0U)\r
274 #define TC0_ERROR_INT_XBAR_INST_NO                      (0U)\r
275 #define TC1_ERROR_INT_XBAR_INST_NO                      (0U)\r
276 \r
277 #else\r
278 #define EDMA3_CC_XFER_COMPLETION_INT                    (0U)\r
279 #define EDMA3_CC_ERROR_INT                              (0U)\r
280 #define CC_ERROR_INT_XBAR_INST_NO                       (0U)\r
281 #define EDMA3_TC0_ERROR_INT                             (0U)\r
282 #define EDMA3_TC1_ERROR_INT                             (0U)\r
283 #define TC0_ERROR_INT_XBAR_INST_NO                      (TC0_ERROR_INT_A15_XBAR_INST_NO)\r
284 #define TC1_ERROR_INT_XBAR_INST_NO                      (TC1_ERROR_INT_A15_XBAR_INST_NO)\r
285 #endif\r
286 \r
287 #define EDMA3_TC2_ERROR_INT                             (0U)\r
288 #define EDMA3_TC3_ERROR_INT                             (0U)\r
289 #define EDMA3_TC4_ERROR_INT                             (0U)\r
290 #define EDMA3_TC5_ERROR_INT                             (0U)\r
291 #define EDMA3_TC6_ERROR_INT                             (0U)\r
292 #define EDMA3_TC7_ERROR_INT                             (0U)\r
293 \r
294 #define DSP1_EDMA3_CC_XFER_COMPLETION_INT               (19U)\r
295 #define DSP2_EDMA3_CC_XFER_COMPLETION_INT               (20U)\r
296 #define DSP1_EDMA3_CC_ERROR_INT                         (27U)\r
297 #define DSP1_EDMA3_TC0_ERROR_INT                        (28U)\r
298 #define DSP1_EDMA3_TC1_ERROR_INT                        (29U)\r
299 \r
300 /** XBAR interrupt source index numbers for EDMA interrupts */\r
301 #define XBAR_EDMA_TPCC_IRQ_REGION0                      (361U)\r
302 #define XBAR_EDMA_TPCC_IRQ_REGION1                      (362U)\r
303 #define XBAR_EDMA_TPCC_IRQ_REGION2                      (363U)\r
304 #define XBAR_EDMA_TPCC_IRQ_REGION3                      (364U)\r
305 #define XBAR_EDMA_TPCC_IRQ_REGION4                      (365U)\r
306 #define XBAR_EDMA_TPCC_IRQ_REGION5                      (366U)\r
307 #define XBAR_EDMA_TPCC_IRQ_REGION6                      (367U)\r
308 #define XBAR_EDMA_TPCC_IRQ_REGION7                      (368U)\r
309 \r
310 #define XBAR_EDMA_TPCC_IRQ_ERR                          (359U)\r
311 #define XBAR_EDMA_TC0_IRQ_ERR                           (370U)\r
312 #define XBAR_EDMA_TC1_IRQ_ERR                           (371U)\r
313 \r
314 /**\r
315  * EDMA3 interrupts (transfer completion, CC error etc.) correspond to different\r
316  * ECM events (SoC specific). These ECM events come\r
317  * under ECM block XXX (handling those specific ECM events). Normally, block\r
318  * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events\r
319  * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)\r
320  * is mapped to a specific HWI_INT YYY in the tcf file.\r
321  * Define EDMA3_HWI_INT_XFER_COMP to specific HWI_INT, corresponding\r
322  * to transfer completion interrupt.\r
323  * Define EDMA3_HWI_INT_CC_ERR to specific HWI_INT, corresponding\r
324  * to CC error interrupts.\r
325  * Define EDMA3_HWI_INT_TC_ERR to specific HWI_INT, corresponding\r
326  * to TC error interrupts.\r
327  */\r
328 /* EDMA 0 */\r
329 \r
330 #define EDMA3_HWI_INT_XFER_COMP                           (7U)\r
331 #define EDMA3_HWI_INT_CC_ERR                              (7U)\r
332 #define EDMA3_HWI_INT_TC0_ERR                             (10U)\r
333 #define EDMA3_HWI_INT_TC1_ERR                             (10U)\r
334 #define EDMA3_HWI_INT_TC2_ERR                             (10U)\r
335 #define EDMA3_HWI_INT_TC3_ERR                             (10U)\r
336 \r
337 /**\r
338  * \brief Mapping of DMA channels 0-31 to Hardware Events from\r
339  * various peripherals, which use EDMA for data transfer.\r
340  * All channels need not be mapped, some can be free also.\r
341  * 1: Mapped\r
342  * 0: Not mapped (channel available)\r
343  *\r
344  * This mapping will be used to allocate DMA channels when user passes\r
345  * EDMA3_RM_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory\r
346  * copy). The same mapping is used to allocate the TCC when user passes\r
347  * EDMA3_RM_TCC_ANY as tcc id (for eg to do memory-to-memory copy).\r
348  * \r
349  * For Vayu Since the xbar can be used to map event to any EDMA channel,\r
350  * If the application is assigning events to other channel this variable \r
351  * should be modified\r
352  *\r
353  * To allocate more DMA channels or TCCs, one has to modify the event mapping.\r
354  */\r
355                                                       /* 31     0 */\r
356 #define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA       (0x3FC0C06EU)  /* TBD */\r
357 #define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_DSPEDMA        (0x000FFFFFU)  /* TBD */\r
358 #define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_EVEEDMA        (0x00000000U)  /* TBD */\r
359 \r
360 /**\r
361  * \brief Mapping of DMA channels 32-63 to Hardware Events from\r
362  * various peripherals, which use EDMA for data transfer.\r
363  * All channels need not be mapped, some can be free also.\r
364  * 1: Mapped\r
365  * 0: Not mapped (channel available)\r
366  *\r
367  * This mapping will be used to allocate DMA channels when user passes\r
368  * EDMA3_RM_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory\r
369  * copy). The same mapping is used to allocate the TCC when user passes\r
370  * EDMA3_RM_TCC_ANY as tcc id (for eg to do memory-to-memory copy).\r
371  *\r
372  * To allocate more DMA channels or TCCs, one has to modify the event mapping.\r
373  */\r
374 #define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA       (0xF3FFFFFCU) /* TBD */\r
375 #define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_DSPEDMA        (0x00000000U) /* TBD */\r
376 #define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_EVEEDMA        (0x00000000U) /* TBD */\r
377 \r
378 \r
379 /* Variable which will be used internally for referring number of Event Queues*/\r
380 uint32_t numEdma3EvtQue[NUM_EDMA3_INSTANCES] =  {\r
381                                                         EDMA3_NUM_EVTQUE,\r
382                                                         EDMA3_NUM_EVTQUE,\r
383                                                         EDMA3_NUM_EVTQUE\r
384                                                     };\r
385 \r
386 /* Variable which will be used internally for referring number of TCs.        */\r
387 uint32_t numEdma3Tc[NUM_EDMA3_INSTANCES] =  {\r
388                                                     EDMA3_NUM_TC,\r
389                                                     EDMA3_NUM_TC,\r
390                                                     EDMA3_NUM_TC\r
391                                                 };\r
392 \r
393 /**\r
394  * Variable which will be used internally for referring transfer completion\r
395  * interrupt.\r
396  */\r
397 uint32_t ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
398 {\r
399     /* EDMA3 INSTANCE# 0 */\r
400     {\r
401         EDMA3_CC_XFER_COMPLETION_INT_A15,\r
402         EDMA3_CC_XFER_COMPLETION_INT_A15,\r
403                 EDMA3_CC_XFER_COMPLETION_INT_DSP,\r
404         EDMA3_CC_XFER_COMPLETION_INT_DSP,\r
405                 EDMA3_CC_XFER_COMPLETION_INT_IPU_C0,\r
406         EDMA3_CC_XFER_COMPLETION_INT_IPU_C1,\r
407         EDMA3_CC_XFER_COMPLETION_INT_IPU_C0,\r
408         EDMA3_CC_XFER_COMPLETION_INT_IPU_C1\r
409     },\r
410     /* EDMA3 INSTANCE# 1 */\r
411     {\r
412         0U,\r
413         0U,\r
414         DSP1_EDMA3_CC_XFER_COMPLETION_INT,\r
415         DSP2_EDMA3_CC_XFER_COMPLETION_INT,\r
416         0U,\r
417         0U,\r
418         0U,\r
419         0U\r
420     },\r
421     /* EDMA3 INSTANCE# 2 */\r
422     {\r
423         0U,\r
424         /* Region 1 (Associated to EVE core)*/\r
425         EDMA3_CC_XFER_COMPLETION_INT_EVE,\r
426         0U,\r
427         0U,\r
428         0U,\r
429         0U,\r
430         0U,\r
431         0U,\r
432     }\r
433 };\r
434 /** These are the Xbar instance numbers corresponding to interrupt numbers */\r
435 uint32_t ccXferCompIntXbarInstNo[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
436 {\r
437     /* EDMA3 INSTANCE# 0 */\r
438     {\r
439         COMPLETION_INT_A15_XBAR_INST_NO,\r
440         COMPLETION_INT_A15_XBAR_INST_NO,\r
441                 COMPLETION_INT_DSP_XBAR_INST_NO,\r
442         COMPLETION_INT_DSP_XBAR_INST_NO,\r
443                 COMPLETION_INT_IPU_C0_XBAR_INST_NO,\r
444         COMPLETION_INT_IPU_C1_XBAR_INST_NO,\r
445         COMPLETION_INT_IPU_C0_XBAR_INST_NO,\r
446         COMPLETION_INT_IPU_C1_XBAR_INST_NO,\r
447     },\r
448     /* EDMA3 INSTANCE# 1 */\r
449     {\r
450         0U,\r
451         0U,\r
452         0U,\r
453         0U,\r
454         0U,\r
455         0U,\r
456         0U,\r
457         0U\r
458     },\r
459     /* EDMA3 INSTANCE# 2 */\r
460     {\r
461      /* \r
462       * For accessing EVE internal edma,\r
463       * there is no need to configure Xbar.\r
464       * So getting to zero.\r
465       */\r
466         0U,\r
467         0U,\r
468         0U,\r
469         0U,\r
470         0U,\r
471         0U,\r
472         0U,\r
473         0U\r
474     }\r
475 };\r
476 \r
477 /**\r
478  * Variable which will be used internally for referring channel controller's\r
479  * error interrupt.\r
480  */\r
481 uint32_t ccErrorInt[NUM_EDMA3_INSTANCES] = \r
482 {\r
483     EDMA3_CC_ERROR_INT,\r
484     DSP1_EDMA3_CC_ERROR_INT,\r
485     EDMA3_CC_ERROR_INT\r
486 };\r
487 \r
488 /**\r
489  * Variable which will be used internally for referring transfer controllers'\r
490  * error interrupts.\r
491  */\r
492 uint32_t tcErrorInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
493 {\r
494     /* EDMA3 INSTANCE# 0 */\r
495     {\r
496         EDMA3_TC0_ERROR_INT, EDMA3_TC1_ERROR_INT,\r
497         EDMA3_TC2_ERROR_INT, EDMA3_TC3_ERROR_INT,\r
498         EDMA3_TC4_ERROR_INT, EDMA3_TC5_ERROR_INT,\r
499         EDMA3_TC6_ERROR_INT, EDMA3_TC7_ERROR_INT,\r
500     },\r
501     /* EDMA3 INSTANCE# 1 */\r
502     {\r
503         DSP1_EDMA3_TC0_ERROR_INT, DSP1_EDMA3_TC1_ERROR_INT,\r
504         EDMA3_TC0_ERROR_INT, EDMA3_TC1_ERROR_INT,\r
505         EDMA3_TC2_ERROR_INT, EDMA3_TC3_ERROR_INT,\r
506         EDMA3_TC4_ERROR_INT, EDMA3_TC5_ERROR_INT,\r
507     },\r
508     /* EDMA3 INSTANCE# 2 */\r
509     {\r
510         EDMA3_TC0_ERROR_INT, EDMA3_TC1_ERROR_INT,\r
511         EDMA3_TC2_ERROR_INT, EDMA3_TC3_ERROR_INT,\r
512         EDMA3_TC4_ERROR_INT, EDMA3_TC5_ERROR_INT,\r
513         EDMA3_TC6_ERROR_INT, EDMA3_TC7_ERROR_INT,\r
514     }\r
515 };\r
516 \r
517 /**\r
518  * Variables which will be used internally for referring the hardware interrupt\r
519  * for various EDMA3 interrupts.\r
520  */\r
521 uint32_t hwIntXferComp[NUM_EDMA3_INSTANCES] =\r
522 {\r
523     EDMA3_HWI_INT_XFER_COMP,\r
524     EDMA3_HWI_INT_XFER_COMP,\r
525     EDMA3_CC_XFER_COMPLETION_INT\r
526 };\r
527 \r
528 uint32_t hwIntCcErr[NUM_EDMA3_INSTANCES] =\r
529 {\r
530     EDMA3_HWI_INT_CC_ERR,\r
531     EDMA3_HWI_INT_CC_ERR,\r
532     EDMA3_CC_ERROR_INT\r
533 };\r
534 \r
535 uint32_t hwIntTcErr[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
536 {\r
537     /* EDMA3 INSTANCE# 0 */\r
538     {\r
539          EDMA3_HWI_INT_TC0_ERR ,\r
540          EDMA3_HWI_INT_TC1_ERR ,\r
541          EDMA3_HWI_INT_TC2_ERR ,\r
542          EDMA3_HWI_INT_TC3_ERR ,\r
543          0U ,\r
544          0U ,\r
545          0U ,\r
546          0U \r
547     },\r
548     /* EDMA3 INSTANCE# 1 */\r
549     {\r
550          EDMA3_HWI_INT_TC0_ERR ,\r
551          EDMA3_HWI_INT_TC1_ERR ,\r
552          EDMA3_HWI_INT_TC2_ERR ,\r
553          EDMA3_HWI_INT_TC3_ERR ,\r
554          0U ,\r
555          0U ,\r
556          0U ,\r
557          0U \r
558     },\r
559     /* EDMA3 INSTANCE# 2 */\r
560     {\r
561          EDMA3_TC0_ERROR_INT ,\r
562          EDMA3_TC1_ERROR_INT ,\r
563          EDMA3_TC2_ERROR_INT ,\r
564          EDMA3_TC3_ERROR_INT ,\r
565          0U ,\r
566          0U ,\r
567          0U ,\r
568          0U \r
569     }\r
570 };\r
571 \r
572 /**\r
573  * \brief Base address as seen from the different cores may be different\r
574  * And is defined based on the core\r
575  */\r
576 #if ((defined BUILD_TDA2XX_MPU) || (defined BUILD_TDA2XX_DSP))\r
577 #define EDMA3_CC_BASE_ADDR                          ((void *)(0x43300000))\r
578 #define EDMA3_TC0_BASE_ADDR                         ((void *)(0x43400000))\r
579 #define EDMA3_TC1_BASE_ADDR                         ((void *)(0x43500000))\r
580 #elif (defined BUILD_TDA2XX_IPU)\r
581 #define EDMA3_CC_BASE_ADDR                          ((void *)(0x63300000))\r
582 #define EDMA3_TC0_BASE_ADDR                         ((void *)(0x63400000))\r
583 #define EDMA3_TC1_BASE_ADDR                         ((void *)(0x63500000))\r
584 #elif (defined BUILD_TDA2XX_EVE)\r
585 #define EDMA3_CC_BASE_ADDR                          ((void *)(0x400A0000))\r
586 #define EDMA3_TC0_BASE_ADDR                         ((void *)(0x40086000))\r
587 #define EDMA3_TC1_BASE_ADDR                         ((void *)(0x40087000))\r
588 #else\r
589 #define EDMA3_CC_BASE_ADDR                          ((void *)(0x0))\r
590 #define EDMA3_TC0_BASE_ADDR                         ((void *)(0x0))\r
591 #define EDMA3_TC1_BASE_ADDR                         ((void *)(0x0))\r
592 #endif\r
593 \r
594 #define DSP1_EDMA3_CC_BASE_ADDR                     ((void *)(0x01D10000))\r
595 #define DSP1_EDMA3_TC0_BASE_ADDR                    ((void *)(0x01D05000))\r
596 #define DSP1_EDMA3_TC1_BASE_ADDR                    ((void *)(0x01D06000))\r
597 /* Driver Object Initialization Configuration                                 */\r
598 EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =\r
599 {\r
600     {\r
601         /* EDMA3 INSTANCE# 0 */\r
602         /** Total number of DMA Channels supported by the EDMA3 Controller    */\r
603         EDMA3_NUM_DMA_CHANNELS,\r
604         /** Total number of QDMA Channels supported by the EDMA3 Controller   */\r
605         EDMA3_NUM_QDMA_CHANNELS,\r
606         /** Total number of TCCs supported by the EDMA3 Controller            */\r
607         EDMA3_NUM_TCC,\r
608         /** Total number of PaRAM Sets supported by the EDMA3 Controller      */\r
609         EDMA3_NUM_PARAMSET,\r
610         /** Total number of Event Queues in the EDMA3 Controller              */\r
611         EDMA3_NUM_EVTQUE,\r
612         /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller*/\r
613         EDMA3_NUM_TC,\r
614         /** Number of Regions on this EDMA3 controller                        */\r
615         EDMA3_NUM_REGIONS,\r
616 \r
617         /**\r
618          * \brief Channel mapping existence\r
619          * A value of 0 (No channel mapping) implies that there is fixed association\r
620          * for a channel number to a parameter entry number or, in other words,\r
621          * PaRAM entry n corresponds to channel n.\r
622          */\r
623         1U,\r
624 \r
625         /** Existence of memory protection feature */\r
626         0U,\r
627 \r
628         /** Global Register Region of CC Registers */\r
629         EDMA3_CC_BASE_ADDR,\r
630         /** Transfer Controller (TC) Registers */\r
631         {\r
632                 EDMA3_TC0_BASE_ADDR,\r
633                 EDMA3_TC1_BASE_ADDR,\r
634                 (void *)NULL,\r
635                 (void *)NULL,\r
636             (void *)NULL,\r
637             (void *)NULL,\r
638             (void *)NULL,\r
639             (void *)NULL\r
640         },\r
641         /** Interrupt no. for Transfer Completion */\r
642         EDMA3_CC_XFER_COMPLETION_INT,\r
643         /** Interrupt no. for CC Error */\r
644         EDMA3_CC_ERROR_INT,\r
645         /** Interrupt no. for TCs Error */\r
646         {\r
647             EDMA3_TC0_ERROR_INT,\r
648             EDMA3_TC1_ERROR_INT,\r
649             EDMA3_TC2_ERROR_INT,\r
650             EDMA3_TC3_ERROR_INT,\r
651             EDMA3_TC4_ERROR_INT,\r
652             EDMA3_TC5_ERROR_INT,\r
653             EDMA3_TC6_ERROR_INT,\r
654             EDMA3_TC7_ERROR_INT\r
655         },\r
656 \r
657         /**\r
658          * \brief EDMA3 TC priority setting\r
659          *\r
660          * User can program the priority of the Event Queues\r
661          * at a system-wide level.  This means that the user can set the\r
662          * priority of an IO initiated by either of the TCs (Transfer Controllers)\r
663          * relative to IO initiated by the other bus masters on the\r
664          * device (ARM, DSP, USB, etc)\r
665          */\r
666         {\r
667             0U,\r
668             1U,\r
669             0U,\r
670             0U,\r
671             0U,\r
672             0U,\r
673             0U,\r
674             0U\r
675         },\r
676         /**\r
677          * \brief To Configure the Threshold level of number of events\r
678          * that can be queued up in the Event queues. EDMA3CC error register\r
679          * (CCERR) will indicate whether or not at any instant of time the\r
680          * number of events queued up in any of the event queues exceeds\r
681          * or equals the threshold/watermark value that is set\r
682          * in the queue watermark threshold register (QWMTHRA).\r
683          */\r
684         {\r
685             16U,\r
686             16U,\r
687             0U,\r
688             0U,\r
689             0U,\r
690             0U,\r
691             0U,\r
692             0U\r
693         },\r
694 \r
695         /**\r
696          * \brief To Configure the Default Burst Size (DBS) of TCs.\r
697          * An optimally-sized command is defined by the transfer controller\r
698          * default burst size (DBS). Different TCs can have different\r
699          * DBS values. It is defined in Bytes.\r
700          */\r
701             {\r
702             16U,\r
703             16U,\r
704             0U,\r
705             0U,\r
706             0U,\r
707             0U,\r
708             0U,\r
709             0U\r
710             },\r
711 \r
712         /**\r
713          * \brief Mapping from each DMA channel to a Parameter RAM set,\r
714          * if it exists, otherwise of no use.\r
715          */\r
716             {\r
717                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
718                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
719                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
720                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
721                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
722                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
723                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
724                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
725                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
726                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
727                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
728                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
729                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
730                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
731                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
732                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
733                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
734                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
735                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
736                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
737                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
738                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
739                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
740                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
741                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
742                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
743                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
744                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
745                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
746                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
747                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
748                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP\r
749                         },\r
750 \r
751          /**\r
752           * \brief Mapping from each DMA channel to a TCC. This specific\r
753           * TCC code will be returned when the transfer is completed\r
754           * on the mapped channel.\r
755           */\r
756             {\r
757                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
758                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
759                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
760                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
761                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
762                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
763                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
764                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
765                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
766                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
767                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
768                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
769                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
770                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
771                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
772                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
773             },\r
774 \r
775         /**\r
776          * \brief Mapping of DMA channels to Hardware Events from\r
777          * various peripherals, which use EDMA for data transfer.\r
778          * All channels need not be mapped, some can be free also.\r
779          */\r
780             {\r
781             EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA,\r
782             EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA\r
783             }\r
784         },\r
785     {\r
786         /* EDMA3 INSTANCE# 1 */\r
787         /** Total number of DMA Channels supported by the EDMA3 Controller    */\r
788         EDMA3_NUM_DMA_CHANNELS,\r
789         /** Total number of QDMA Channels supported by the EDMA3 Controller   */\r
790         EDMA3_NUM_QDMA_CHANNELS,\r
791         /** Total number of TCCs supported by the EDMA3 Controller            */\r
792         EDMA3_NUM_TCC,\r
793         /** Total number of PaRAM Sets supported by the EDMA3 Controller      */\r
794         EDMA3_NUM_PARAMSET,\r
795         /** Total number of Event Queues in the EDMA3 Controller              */\r
796         EDMA3_NUM_EVTQUE,\r
797         /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller*/\r
798         EDMA3_NUM_TC,\r
799         /** Number of Regions on this EDMA3 controller                        */\r
800         EDMA3_NUM_REGIONS,\r
801 \r
802         /**\r
803          * \brief Channel mapping existence\r
804          * A value of 0 (No channel mapping) implies that there is fixed association\r
805          * for a channel number to a parameter entry number or, in other words,\r
806          * PaRAM entry n corresponds to channel n.\r
807          */\r
808         1U,\r
809 \r
810         /** Existence of memory protection feature */\r
811         0U,\r
812 \r
813         /** Global Register Region of CC Registers */\r
814         DSP1_EDMA3_CC_BASE_ADDR,\r
815         /** Transfer Controller (TC) Registers */\r
816         {\r
817                 DSP1_EDMA3_TC0_BASE_ADDR,\r
818                 DSP1_EDMA3_TC1_BASE_ADDR,\r
819                 (void *)NULL,\r
820                 (void *)NULL,\r
821             (void *)NULL,\r
822             (void *)NULL,\r
823             (void *)NULL,\r
824             (void *)NULL\r
825         },\r
826         /** Interrupt no. for Transfer Completion */\r
827         DSP1_EDMA3_CC_XFER_COMPLETION_INT,\r
828         /** Interrupt no. for CC Error */\r
829         DSP1_EDMA3_CC_ERROR_INT,\r
830         /** Interrupt no. for TCs Error */\r
831         {\r
832             DSP1_EDMA3_TC0_ERROR_INT,\r
833             DSP1_EDMA3_TC1_ERROR_INT,\r
834             EDMA3_TC2_ERROR_INT,\r
835             EDMA3_TC3_ERROR_INT,\r
836             EDMA3_TC4_ERROR_INT,\r
837             EDMA3_TC5_ERROR_INT,\r
838             EDMA3_TC6_ERROR_INT,\r
839             EDMA3_TC7_ERROR_INT\r
840         },\r
841 \r
842         /**\r
843          * \brief EDMA3 TC priority setting\r
844          *\r
845          * User can program the priority of the Event Queues\r
846          * at a system-wide level.  This means that the user can set the\r
847          * priority of an IO initiated by either of the TCs (Transfer Controllers)\r
848          * relative to IO initiated by the other bus masters on the\r
849          * device (ARM, DSP, USB, etc)\r
850          */\r
851         {\r
852             0U,\r
853             1U,\r
854             0U,\r
855             0U,\r
856             0U,\r
857             0U,\r
858             0U,\r
859             0U\r
860         },\r
861         /**\r
862          * \brief To Configure the Threshold level of number of events\r
863          * that can be queued up in the Event queues. EDMA3CC error register\r
864          * (CCERR) will indicate whether or not at any instant of time the\r
865          * number of events queued up in any of the event queues exceeds\r
866          * or equals the threshold/watermark value that is set\r
867          * in the queue watermark threshold register (QWMTHRA).\r
868          */\r
869         {\r
870             16U,\r
871             16U,\r
872             0U,\r
873             0U,\r
874             0U,\r
875             0U,\r
876             0U,\r
877             0U\r
878         },\r
879 \r
880         /**\r
881          * \brief To Configure the Default Burst Size (DBS) of TCs.\r
882          * An optimally-sized command is defined by the transfer controller\r
883          * default burst size (DBS). Different TCs can have different\r
884          * DBS values. It is defined in Bytes.\r
885          */\r
886             {\r
887             16U,\r
888             16U,\r
889             0U,\r
890             0U,\r
891             0U,\r
892             0U,\r
893             0U,\r
894             0U\r
895             },\r
896 \r
897         /**\r
898          * \brief Mapping from each DMA channel to a Parameter RAM set,\r
899          * if it exists, otherwise of no use.\r
900          */\r
901             {\r
902                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
903                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
904                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
905                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
906                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
907                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
908                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
909                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
910                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
911                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
912                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
913                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
914                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
915                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
916                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
917                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
918                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
919                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
920                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
921                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
922                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
923                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
924                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
925                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
926                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
927                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
928                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
929                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
930                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
931                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
932                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
933                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP\r
934             },\r
935 \r
936          /**\r
937           * \brief Mapping from each DMA channel to a TCC. This specific\r
938           * TCC code will be returned when the transfer is completed\r
939           * on the mapped channel.\r
940           */\r
941             {\r
942                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
943                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
944                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
945                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
946                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
947                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
948                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
949                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
950                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
951                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
952                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
953                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
954                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
955                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
956                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
957                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
958             },\r
959 \r
960         /**\r
961          * \brief Mapping of DMA channels to Hardware Events from\r
962          * various peripherals, which use EDMA for data transfer.\r
963          * All channels need not be mapped, some can be free also.\r
964          */\r
965             {\r
966             EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_DSPEDMA,\r
967             EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_DSPEDMA\r
968             }\r
969     },\r
970     {\r
971         /* EDMA3 INSTANCE# 2 */\r
972         /** Total number of DMA Channels supported by the EDMA3 Controller    */\r
973         EDMA3_NUM_DMA_CHANNELS_EVE,\r
974         /** Total number of QDMA Channels supported by the EDMA3 Controller   */\r
975         EDMA3_NUM_QDMA_CHANNELS_EVE,\r
976         /** Total number of TCCs supported by the EDMA3 Controller            */\r
977         EDMA3_NUM_TCC_EVE,\r
978         /** Total number of PaRAM Sets supported by the EDMA3 Controller      */\r
979         EDMA3_NUM_PARAMSET_EVE,\r
980         /** Total number of Event Queues in the EDMA3 Controller              */\r
981         EDMA3_NUM_EVTQUE_EVE,\r
982         /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller*/\r
983         EDMA3_NUM_TC_EVE,\r
984         /** Number of Regions on this EDMA3 controller                        */\r
985         EDMA3_NUM_REGIONS_EVE,\r
986 \r
987         /**\r
988          * \brief Channel mapping existence\r
989          * A value of 0 (No channel mapping) implies that there is fixed association\r
990          * for a channel number to a parameter entry number or, in other words,\r
991          * PaRAM entry n corresponds to channel n.\r
992          */\r
993         1U,\r
994 \r
995         /** Existence of memory protection feature */\r
996         0U,\r
997 \r
998         /** Global Register Region of CC Registers */\r
999         EDMA3_CC_BASE_ADDR,\r
1000         /** Transfer Controller (TC) Registers */\r
1001         {\r
1002                 EDMA3_TC0_BASE_ADDR,\r
1003                 EDMA3_TC1_BASE_ADDR,\r
1004                 (void *)NULL,\r
1005                 (void *)NULL,\r
1006             (void *)NULL,\r
1007             (void *)NULL,\r
1008             (void *)NULL,\r
1009             (void *)NULL\r
1010         },\r
1011         /** Interrupt no. for Transfer Completion */\r
1012         EDMA3_CC_XFER_COMPLETION_INT,\r
1013         /** Interrupt no. for CC Error */\r
1014         EDMA3_CC_ERROR_INT,\r
1015         /** Interrupt no. for TCs Error */\r
1016         {\r
1017             EDMA3_TC0_ERROR_INT,\r
1018             EDMA3_TC1_ERROR_INT,\r
1019             EDMA3_TC2_ERROR_INT,\r
1020             EDMA3_TC3_ERROR_INT,\r
1021             EDMA3_TC4_ERROR_INT,\r
1022             EDMA3_TC5_ERROR_INT,\r
1023             EDMA3_TC6_ERROR_INT,\r
1024             EDMA3_TC7_ERROR_INT\r
1025         },\r
1026 \r
1027         /**\r
1028          * \brief EDMA3 TC priority setting\r
1029          *\r
1030          * User can program the priority of the Event Queues\r
1031          * at a system-wide level.  This means that the user can set the\r
1032          * priority of an IO initiated by either of the TCs (Transfer Controllers)\r
1033          * relative to IO initiated by the other bus masters on the\r
1034          * device (ARM, DSP, USB, etc)\r
1035          */\r
1036         {\r
1037             0U,\r
1038             1U,\r
1039             0U,\r
1040             0U,\r
1041             0U,\r
1042             0U,\r
1043             0U,\r
1044             0U\r
1045         },\r
1046         /**\r
1047          * \brief To Configure the Threshold level of number of events\r
1048          * that can be queued up in the Event queues. EDMA3CC error register\r
1049          * (CCERR) will indicate whether or not at any instant of time the\r
1050          * number of events queued up in any of the event queues exceeds\r
1051          * or equals the threshold/watermark value that is set\r
1052          * in the queue watermark threshold register (QWMTHRA).\r
1053          */\r
1054         {\r
1055             16U,\r
1056             16U,\r
1057             0U,\r
1058             0U,\r
1059             0U,\r
1060             0U,\r
1061             0U,\r
1062             0U\r
1063         },\r
1064 \r
1065         /**\r
1066          * \brief To Configure the Default Burst Size (DBS) of TCs.\r
1067          * An optimally-sized command is defined by the transfer controller\r
1068          * default burst size (DBS). Different TCs can have different\r
1069          * DBS values. It is defined in Bytes.\r
1070          */\r
1071             {\r
1072             16U,\r
1073             16U,\r
1074             0U,\r
1075             0U,\r
1076             0U,\r
1077             0U,\r
1078             0U,\r
1079             0U\r
1080             },\r
1081 \r
1082         /**\r
1083          * \brief Mapping from each DMA channel to a Parameter RAM set,\r
1084          * if it exists, otherwise of no use.\r
1085          */\r
1086             {\r
1087                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1088                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1089                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1090                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1091                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1092                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1093                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1094                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1095                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1096                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1097                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1098                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1099                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1100                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1101                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1102                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1103                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1104                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1105                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1106                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1107                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1108                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1109                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1110                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1111                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1112                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1113                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1114                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1115                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1116                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1117                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
1118                         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP\r
1119             },\r
1120 \r
1121          /**\r
1122           * \brief Mapping from each DMA channel to a TCC. This specific\r
1123           * TCC code will be returned when the transfer is completed\r
1124           * on the mapped channel.\r
1125           */\r
1126             {\r
1127                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1128                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1129                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1130                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1131                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1132                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1133                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1134                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1135                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1136                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1137                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1138                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1139                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1140                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1141                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1142                         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
1143             },\r
1144 \r
1145         /**\r
1146          * \brief Mapping of DMA channels to Hardware Events from\r
1147          * various peripherals, which use EDMA for data transfer.\r
1148          * All channels need not be mapped, some can be free also.\r
1149          */\r
1150             {\r
1151             EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_EVEEDMA,\r
1152             EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_EVEEDMA\r
1153             }\r
1154     },\r
1155 \r
1156 };\r
1157 \r
1158 /**\r
1159  * \brief Resource splitting defines for Own/Reserved DMA/QDMA channels and TCCs\r
1160  * For PaRAMs explicit defines are not present but should be replaced in the structure sampleInstInitConfig\r
1161  * Default configuration has all resources owned by all cores and none reserved except for first 64 PaRAMs corrosponding to DMA channels\r
1162  * Resources to be Split properly by application and rebuild the sample library to avoid resource conflict\r
1163  *\r
1164  * Only Resources owned by a perticular core are allocated by Driver\r
1165  * Reserved resources are not allocated if requested for any available resource\r
1166  */\r
1167  \r
1168 /* Driver Instance Initialization Configuration */\r
1169 EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
1170 {\r
1171     /* EDMA3 INSTANCE# 0 */\r
1172                 {\r
1173                         /* Resources owned/reserved by region 0 (Associated to MPU core 0)*/\r
1174                         {\r
1175                                 /* ownPaRAMSets */\r
1176                                 /* 31     0     63    32     95    64     127   96 */\r
1177                                 {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1178                                 /* 159  128     191  160     223  192     255  224 */\r
1179                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1180                                 /* 287  256     319  288     351  320     383  352 */\r
1181                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1182                                 /* 415  384     447  416     479  448     511  480 */\r
1183                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},\r
1184 \r
1185                                 /* ownDmaChannels */\r
1186                                 /* 31     0     63    32 */\r
1187                                 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
1188 \r
1189                                 /* ownQdmaChannels */\r
1190                                 /* 31     0 */\r
1191                                 {0x000000FFU},\r
1192 \r
1193                                 /* ownTccs */\r
1194                                 /* 31     0     63    32 */\r
1195                                 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
1196 \r
1197                                 /* resvdPaRAMSets */\r
1198                                 /* 31     0     63    32     95    64     127   96 */\r
1199                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1200                                 /* 159  128     191  160     223  192     255  224 */\r
1201                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1202                                 /* 287  256     319  288     351  320     383  352 */\r
1203                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1204                                 /* 415  384     447  416     479  448     511  480 */\r
1205                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1206 \r
1207                                 /* resvdDmaChannels */\r
1208                                 /* 31     0     63    32 */\r
1209                                 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA},\r
1210 \r
1211                                 /* resvdQdmaChannels */\r
1212                                 /* 31     0 */\r
1213                                 {0x00U},\r
1214 \r
1215                                 /* resvdTccs */\r
1216                                 /* 31     0     63    32 */\r
1217                                 {0x00U, 0x00U},\r
1218                         },\r
1219 \r
1220                         /* Resources owned/reserved by region 1 (Associated to MPU core 1) */\r
1221                         {\r
1222                                 /* ownPaRAMSets */\r
1223                                 /* 31     0     63    32     95    64     127   96 */\r
1224                                 {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1225                                 /* 159  128     191  160     223  192     255  224 */\r
1226                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1227                                 /* 287  256     319  288     351  320     383  352 */\r
1228                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1229                                 /* 415  384     447  416     479  448     511  480 */\r
1230                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},\r
1231 /* \r
1232  * This instance 0 and region 1 is only accessible to MPU core 1.\r
1233  * So other cores should not be access.\r
1234  */\r
1235 #ifdef BUILD_TDA2XX_MPU\r
1236                                 /* ownDmaChannels */\r
1237                                 /* 31     0     63    32 */\r
1238                                 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
1239 #else\r
1240                                 /* ownDmaChannels */\r
1241                                 /* 31     0     63    32 */\r
1242                                 {0x00000000U, 0x00000000U},\r
1243 #endif\r
1244                                 /* ownQdmaChannels */\r
1245                                 /* 31     0 */\r
1246                                 {0x000000FFU},\r
1247 \r
1248                                 /* ownTccs */\r
1249                                 /* 31     0     63    32 */\r
1250                                 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
1251 \r
1252                                 /* resvdPaRAMSets */\r
1253                                 /* 31     0     63    32     95    64     127   96 */\r
1254                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1255                                 /* 159  128     191  160     223  192     255  224 */\r
1256                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1257                                 /* 287  256     319  288     351  320     383  352 */\r
1258                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1259                                 /* 415  384     447  416     479  448     511  480 */\r
1260                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1261 \r
1262                                 /* resvdDmaChannels */\r
1263                                 /* 31     0     63    32 */\r
1264                                 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA},\r
1265 \r
1266                                 /* resvdQdmaChannels */\r
1267                                 /* 31     0 */\r
1268                                 {0x00U},\r
1269 \r
1270                                 /* resvdTccs */\r
1271                                 /* 31     0     63    32 */\r
1272                                 {0x00U, 0x00U},\r
1273                         },\r
1274 \r
1275                 /* Resources owned/reserved by region 2 (Associated to any DSP1)*/\r
1276                         {\r
1277                                 /* ownPaRAMSets */\r
1278                                 /* 31     0     63    32     95    64     127   96 */\r
1279                                 {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1280                                 /* 159  128     191  160     223  192     255  224 */\r
1281                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1282                                 /* 287  256     319  288     351  320     383  352 */\r
1283                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1284                                 /* 415  384     447  416     479  448     511  480 */\r
1285                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},\r
1286 \r
1287                                 /* ownDmaChannels */\r
1288                                 /* 31     0     63    32 */\r
1289                                 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
1290 \r
1291                                 /* ownQdmaChannels */\r
1292                                 /* 31     0 */\r
1293                                 {0x000000FFU},\r
1294 \r
1295                                 /* ownTccs */\r
1296                                 /* 31     0     63    32 */\r
1297                                 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
1298 \r
1299                                 /* resvdPaRAMSets */\r
1300                                 /* 31     0     63    32     95    64     127   96 */\r
1301                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1302                                 /* 159  128     191  160     223  192     255  224 */\r
1303                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1304                                 /* 287  256     319  288     351  320     383  352 */\r
1305                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1306                                 /* 415  384     447  416     479  448     511  480 */\r
1307                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1308 \r
1309                                 /* resvdDmaChannels */\r
1310                                 /* 31     0     63    32 */\r
1311                                 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA},\r
1312 \r
1313                                 /* resvdQdmaChannels */\r
1314                                 /* 31     0 */\r
1315                                 {0x00U},\r
1316 \r
1317                                 /* resvdTccs */\r
1318                                 /* 31     0     63    32 */\r
1319                                 {0x00U, 0x00U},\r
1320                         },\r
1321 \r
1322                 /* Resources owned/reserved by region 3 (Associated to any DSP2)*/\r
1323                         {\r
1324                                 /* ownPaRAMSets */\r
1325                                 /* 31     0     63    32     95    64     127   96 */\r
1326                                 {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1327                                 /* 159  128     191  160     223  192     255  224 */\r
1328                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1329                                 /* 287  256     319  288     351  320     383  352 */\r
1330                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1331                                 /* 415  384     447  416     479  448     511  480 */\r
1332                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},\r
1333 \r
1334                                 /* ownDmaChannels */\r
1335                                 /* 31     0     63    32 */\r
1336                                 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
1337 \r
1338                                 /* ownQdmaChannels */\r
1339                                 /* 31     0 */\r
1340                                 {0x000000FFU},\r
1341 \r
1342                                 /* ownTccs */\r
1343                                 /* 31     0     63    32 */\r
1344                                 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
1345 \r
1346                                 /* resvdPaRAMSets */\r
1347                                 /* 31     0     63    32     95    64     127   96 */\r
1348                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1349                                 /* 159  128     191  160     223  192     255  224 */\r
1350                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1351                                 /* 287  256     319  288     351  320     383  352 */\r
1352                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1353                                 /* 415  384     447  416     479  448     511  480 */\r
1354                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1355 \r
1356                                 /* resvdDmaChannels */\r
1357                                 /* 31     0     63    32 */\r
1358                                 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA},\r
1359 \r
1360                                 /* resvdQdmaChannels */\r
1361                                 /* 31     0 */\r
1362                                 {0x00U},\r
1363 \r
1364                                 /* resvdTccs */\r
1365                                 /* 31     0     63    32 */\r
1366                                 {0x00U, 0x00U},\r
1367                         },\r
1368 \r
1369                 /* Resources owned/reserved by region 4 (Associated to any IPU1 core 0)*/\r
1370                         {\r
1371                                 /* ownPaRAMSets */\r
1372                                 /* 31     0     63    32     95    64     127   96 */\r
1373                                 {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1374                                 /* 159  128     191  160     223  192     255  224 */\r
1375                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1376                                 /* 287  256     319  288     351  320     383  352 */\r
1377                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1378                                 /* 415  384     447  416     479  448     511  480 */\r
1379                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},\r
1380 \r
1381                                 /* ownDmaChannels */\r
1382                                 /* 31     0     63    32 */\r
1383                                 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
1384 \r
1385                                 /* ownQdmaChannels */\r
1386                                 /* 31     0 */\r
1387                                 {0x000000FFU},\r
1388 \r
1389                                 /* ownTccs */\r
1390                                 /* 31     0     63    32 */\r
1391                                 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
1392 \r
1393                                 /* resvdPaRAMSets */\r
1394                                 /* 31     0     63    32     95    64     127   96 */\r
1395                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1396                                 /* 159  128     191  160     223  192     255  224 */\r
1397                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1398                                 /* 287  256     319  288     351  320     383  352 */\r
1399                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1400                                 /* 415  384     447  416     479  448     511  480 */\r
1401                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1402 \r
1403                                 /* resvdDmaChannels */\r
1404                                 /* 31     0     63    32 */\r
1405                                 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA},\r
1406 \r
1407                                 /* resvdQdmaChannels */\r
1408                                 /* 31     0 */\r
1409                                 {0x00U},\r
1410 \r
1411                                 /* resvdTccs */\r
1412                                 /* 31     0     63    32 */\r
1413                                 {0x00U, 0x00U},\r
1414                         },\r
1415 \r
1416                 /* Resources owned/reserved by region 5 (Associated to any IPU1 core 1)*/\r
1417                         {\r
1418                                 /* ownPaRAMSets */\r
1419                                 /* 31     0     63    32     95    64     127   96 */\r
1420                                 {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1421                                 /* 159  128     191  160     223  192     255  224 */\r
1422                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1423                                 /* 287  256     319  288     351  320     383  352 */\r
1424                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1425                                 /* 415  384     447  416     479  448     511  480 */\r
1426                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},\r
1427 \r
1428                                 /* ownDmaChannels */\r
1429                                 /* 31     0     63    32 */\r
1430                                 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
1431 \r
1432                                 /* ownQdmaChannels */\r
1433                                 /* 31     0 */\r
1434                                 {0x000000FFU},\r
1435 \r
1436                                 /* ownTccs */\r
1437                                 /* 31     0     63    32 */\r
1438                                 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
1439 \r
1440                                 /* resvdPaRAMSets */\r
1441                                 /* 31     0     63    32     95    64     127   96 */\r
1442                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1443                                 /* 159  128     191  160     223  192     255  224 */\r
1444                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1445                                 /* 287  256     319  288     351  320     383  352 */\r
1446                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1447                                 /* 415  384     447  416     479  448     511  480 */\r
1448                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1449 \r
1450                                 /* resvdDmaChannels */\r
1451                                 /* 31     0     63    32 */\r
1452                                 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA},\r
1453 \r
1454                                 /* resvdQdmaChannels */\r
1455                                 /* 31     0 */\r
1456                                 {0x00U},\r
1457 \r
1458                                 /* resvdTccs */\r
1459                                 /* 31     0     63    32 */\r
1460                                 {0x00U, 0x00U},\r
1461                         },\r
1462 \r
1463                 /* Resources owned/reserved by region 6 (Associated to any IPU2 core 0)*/\r
1464                         {\r
1465                                 /* ownPaRAMSets */\r
1466                                 /* 31     0     63    32     95    64     127   96 */\r
1467                                 {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1468                                 /* 159  128     191  160     223  192     255  224 */\r
1469                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1470                                 /* 287  256     319  288     351  320     383  352 */\r
1471                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1472                                 /* 415  384     447  416     479  448     511  480 */\r
1473                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},\r
1474 \r
1475                                 /* ownDmaChannels */\r
1476                                 /* 31     0     63    32 */\r
1477                                 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
1478 \r
1479                                 /* ownQdmaChannels */\r
1480                                 /* 31     0 */\r
1481                                 {0x000000FFU},\r
1482 \r
1483                                 /* ownTccs */\r
1484                                 /* 31     0     63    32 */\r
1485                                 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
1486 \r
1487                                 /* resvdPaRAMSets */\r
1488                                 /* 31     0     63    32     95    64     127   96 */\r
1489                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1490                                 /* 159  128     191  160     223  192     255  224 */\r
1491                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1492                                 /* 287  256     319  288     351  320     383  352 */\r
1493                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1494                                 /* 415  384     447  416     479  448     511  480 */\r
1495                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1496 \r
1497                                 /* resvdDmaChannels */\r
1498                                 /* 31     0     63    32 */\r
1499                                 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA},\r
1500 \r
1501                                 /* resvdQdmaChannels */\r
1502                                 /* 31     0 */\r
1503                                 {0x00U},\r
1504 \r
1505                                 /* resvdTccs */\r
1506                                 /* 31     0     63    32 */\r
1507                                 {0x00U, 0x00U},\r
1508                         },\r
1509 \r
1510                 /* Resources owned/reserved by region 7 (Associated to any IPU2 core 1)*/\r
1511                         {\r
1512                                 /* ownPaRAMSets */\r
1513                                 /* 31     0     63    32     95    64     127   96 */\r
1514                                 {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1515                                 /* 159  128     191  160     223  192     255  224 */\r
1516                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1517                                 /* 287  256     319  288     351  320     383  352 */\r
1518                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1519                                 /* 415  384     447  416     479  448     511  480 */\r
1520                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},\r
1521 \r
1522                                 /* ownDmaChannels */\r
1523                                 /* 31     0     63    32 */\r
1524                                 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
1525 \r
1526                                 /* ownQdmaChannels */\r
1527                                 /* 31     0 */\r
1528                                 {0x000000FFU},\r
1529 \r
1530                                 /* ownTccs */\r
1531                                 /* 31     0     63    32 */\r
1532                                 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
1533 \r
1534                                 /* resvdPaRAMSets */\r
1535                                 /* 31     0     63    32     95    64     127   96 */\r
1536                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1537                                 /* 159  128     191  160     223  192     255  224 */\r
1538                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1539                                 /* 287  256     319  288     351  320     383  352 */\r
1540                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1541                                 /* 415  384     447  416     479  448     511  480 */\r
1542                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1543 \r
1544                                 /* resvdDmaChannels */\r
1545                                 /* 31     0     63    32 */\r
1546                                 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA},\r
1547 \r
1548                                 /* resvdQdmaChannels */\r
1549                                 /* 31     0 */\r
1550                                 {0x00U},\r
1551 \r
1552                                 /* resvdTccs */\r
1553                                 /* 31     0     63    32 */\r
1554                                 {0x00U, 0x00U},\r
1555                         },\r
1556             },\r
1557                 /* EDMA3 INSTANCE# 1 DSP1 EDMA*/\r
1558                 {\r
1559                 /* Resources owned/reserved by region 0 (Not Associated to any core supported)*/\r
1560                         {\r
1561                                 /* ownPaRAMSets */\r
1562                                 /* 31     0     63    32     95    64     127   96 */\r
1563                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1564                                 /* 159  128     191  160     223  192     255  224 */\r
1565                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1566                                 /* 287  256     319  288     351  320     383  352 */\r
1567                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1568                                 /* 415  384     447  416     479  448     511  480 */\r
1569                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1570 \r
1571                                 /* ownDmaChannels */\r
1572                                 /* 31     0     63    32 */\r
1573                                 {0x00000000U, 0x00000000U},\r
1574 \r
1575                                 /* ownQdmaChannels */\r
1576                                 /* 31     0 */\r
1577                                 {0x00000000U},\r
1578 \r
1579                                 /* ownTccs */\r
1580                                 /* 31     0     63    32 */\r
1581                                 {0x00000000U, 0x00000000U},\r
1582 \r
1583                                 /* resvdPaRAMSets */\r
1584                                 /* 31     0     63    32     95    64     127   96 */\r
1585                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1586                                 /* 159  128     191  160     223  192     255  224 */\r
1587                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1588                                 /* 287  256     319  288     351  320     383  352 */\r
1589                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1590                                 /* 415  384     447  416     479  448     511  480 */\r
1591                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1592 \r
1593                                 /* resvdDmaChannels */\r
1594                                 /* 31     0     63    32 */\r
1595                                 {0x00000000U, 0x00000000U},\r
1596 \r
1597                                 /* resvdQdmaChannels */\r
1598                                 /* 31     0 */\r
1599                                 {0x00000000U},\r
1600 \r
1601                                 /* resvdTccs */\r
1602                                 /* 31     0     63    32 */\r
1603                                 {0x00000000U, 0x00000000U},\r
1604                         },\r
1605 \r
1606                         /* Resources owned/reserved by region 1 (Not Associated to any core supported) */\r
1607                         {\r
1608                                 /* ownPaRAMSets */\r
1609                                 /* 31     0     63    32     95    64     127   96 */\r
1610                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1611                                 /* 159  128     191  160     223  192     255  224 */\r
1612                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1613                                 /* 287  256     319  288     351  320     383  352 */\r
1614                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1615                                 /* 415  384     447  416     479  448     511  480 */\r
1616                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1617 \r
1618                                 /* ownDmaChannels */\r
1619                                 /* 31     0     63    32 */\r
1620                                 {0x00000000U, 0x00000000U},\r
1621 \r
1622                                 /* ownQdmaChannels */\r
1623                                 /* 31     0 */\r
1624                                 {0x00000000U},\r
1625 \r
1626                                 /* ownTccs */\r
1627                                 /* 31     0     63    32 */\r
1628                                 {0x00000000U, 0x00000000U},\r
1629 \r
1630                                 /* resvdPaRAMSets */\r
1631                                 /* 31     0     63    32     95    64     127   96 */\r
1632                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1633                                 /* 159  128     191  160     223  192     255  224 */\r
1634                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1635                                 /* 287  256     319  288     351  320     383  352 */\r
1636                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1637                                 /* 415  384     447  416     479  448     511  480 */\r
1638                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1639 \r
1640                                 /* resvdDmaChannels */\r
1641                                 /* 31     0     63    32 */\r
1642                                 {0x00000000U, 0x00000000U},\r
1643 \r
1644                                 /* resvdQdmaChannels */\r
1645                                 /* 31     0 */\r
1646                                 {0x00000000U},\r
1647 \r
1648                                 /* resvdTccs */\r
1649                                 /* 31     0     63    32 */\r
1650                                 {0x00000000U, 0x00000000U},\r
1651                         },\r
1652 \r
1653                 /* Resources owned/reserved by region 2 (Associated to any DSP core 0)*/\r
1654                         {\r
1655                                 /* ownPaRAMSets */\r
1656                                 /* 31     0     63    32     95    64     127   96 */\r
1657                                 {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1658                                 /* 159  128     191  160     223  192     255  224 */\r
1659                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1660                                 /* 287  256     319  288     351  320     383  352 */\r
1661                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1662                                 /* 415  384     447  416     479  448     511  480 */\r
1663                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},\r
1664 \r
1665                                 /* ownDmaChannels */\r
1666                                 /* 31     0     63    32 */\r
1667                                 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
1668 \r
1669                                 /* ownQdmaChannels */\r
1670                                 /* 31     0 */\r
1671                                 {0x000000FFU},\r
1672 \r
1673                                 /* ownTccs */\r
1674                                 /* 31     0     63    32 */\r
1675                                 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
1676 \r
1677                                 /* resvdPaRAMSets */\r
1678                                 /* 31     0     63    32     95    64     127   96 */\r
1679                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1680                                 /* 159  128     191  160     223  192     255  224 */\r
1681                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1682                                 /* 287  256     319  288     351  320     383  352 */\r
1683                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1684                                 /* 415  384     447  416     479  448     511  480 */\r
1685                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1686 \r
1687                                 /* resvdDmaChannels */\r
1688                                 /* 31     0     63    32 */\r
1689                                 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_DSPEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_DSPEDMA},\r
1690 \r
1691                                 /* resvdQdmaChannels */\r
1692                                 /* 31     0 */\r
1693                                 {0x00U},\r
1694 \r
1695                                 /* resvdTccs */\r
1696                                 /* 31     0     63    32 */\r
1697                                 {0x00U, 0x00U},\r
1698                         },\r
1699 \r
1700                 /* Resources owned/reserved by region 3 (Associated to any DSP core 1)*/\r
1701                         {\r
1702                                 /* ownPaRAMSets */\r
1703                                 /* 31     0     63    32     95    64     127   96 */\r
1704                                 {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1705                                 /* 159  128     191  160     223  192     255  224 */\r
1706                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1707                                 /* 287  256     319  288     351  320     383  352 */\r
1708                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1709                                 /* 415  384     447  416     479  448     511  480 */\r
1710                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},\r
1711 \r
1712                                 /* ownDmaChannels */\r
1713                                 /* 31     0     63    32 */\r
1714                                 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
1715 \r
1716                                 /* ownQdmaChannels */\r
1717                                 /* 31     0 */\r
1718                                 {0x000000FFU},\r
1719 \r
1720                                 /* ownTccs */\r
1721                                 /* 31     0     63    32 */\r
1722                                 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
1723 \r
1724                                 /* resvdPaRAMSets */\r
1725                                 /* 31     0     63    32     95    64     127   96 */\r
1726                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1727                                 /* 159  128     191  160     223  192     255  224 */\r
1728                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1729                                 /* 287  256     319  288     351  320     383  352 */\r
1730                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1731                                 /* 415  384     447  416     479  448     511  480 */\r
1732                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1733 \r
1734                                 /* resvdDmaChannels */\r
1735                                 /* 31     0     63    32 */\r
1736                                 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_DSPEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_DSPEDMA},\r
1737 \r
1738                                 /* resvdQdmaChannels */\r
1739                                 /* 31     0 */\r
1740                                 {0x00U},\r
1741 \r
1742                                 /* resvdTccs */\r
1743                                 /* 31     0     63    32 */\r
1744                                 {0x00U, 0x00U},\r
1745                         },\r
1746 \r
1747                 /* Resources owned/reserved by region 4 (Not Associated to any core supported)*/\r
1748                         {\r
1749                                 /* ownPaRAMSets */\r
1750                                 /* 31     0     63    32     95    64     127   96 */\r
1751                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1752                                 /* 159  128     191  160     223  192     255  224 */\r
1753                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1754                                 /* 287  256     319  288     351  320     383  352 */\r
1755                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1756                                 /* 415  384     447  416     479  448     511  480 */\r
1757                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1758 \r
1759                                 /* ownDmaChannels */\r
1760                                 /* 31     0     63    32 */\r
1761                                 {0x00000000U, 0x00000000U},\r
1762 \r
1763                                 /* ownQdmaChannels */\r
1764                                 /* 31     0 */\r
1765                                 {0x00000000U},\r
1766 \r
1767                                 /* ownTccs */\r
1768                                 /* 31     0     63    32 */\r
1769                                 {0x00000000U, 0x00000000U},\r
1770 \r
1771                                 /* resvdPaRAMSets */\r
1772                                 /* 31     0     63    32     95    64     127   96 */\r
1773                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1774                                 /* 159  128     191  160     223  192     255  224 */\r
1775                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1776                                 /* 287  256     319  288     351  320     383  352 */\r
1777                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1778                                 /* 415  384     447  416     479  448     511  480 */\r
1779                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1780 \r
1781                                 /* resvdDmaChannels */\r
1782                                 /* 31     0     63    32 */\r
1783                                 {0x00000000U, 0x00000000U},\r
1784 \r
1785                                 /* resvdQdmaChannels */\r
1786                                 /* 31     0 */\r
1787                                 {0x00000000U},\r
1788 \r
1789                                 /* resvdTccs */\r
1790                                 /* 31     0     63    32 */\r
1791                                 {0x00000000U, 0x00000000U},\r
1792                         },\r
1793 \r
1794                 /* Resources owned/reserved by region 5 (Not Associated to any core supported)*/\r
1795                         {\r
1796                                 /* ownPaRAMSets */\r
1797                                 /* 31     0     63    32     95    64     127   96 */\r
1798                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1799                                 /* 159  128     191  160     223  192     255  224 */\r
1800                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1801                                 /* 287  256     319  288     351  320     383  352 */\r
1802                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1803                                 /* 415  384     447  416     479  448     511  480 */\r
1804                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1805 \r
1806                                 /* ownDmaChannels */\r
1807                                 /* 31     0     63    32 */\r
1808                                 {0x00000000U, 0x00000000U},\r
1809 \r
1810                                 /* ownQdmaChannels */\r
1811                                 /* 31     0 */\r
1812                                 {0x00000000U},\r
1813 \r
1814                                 /* ownTccs */\r
1815                                 /* 31     0     63    32 */\r
1816                                 {0x00000000U, 0x00000000U},\r
1817 \r
1818                                 /* resvdPaRAMSets */\r
1819                                 /* 31     0     63    32     95    64     127   96 */\r
1820                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1821                                 /* 159  128     191  160     223  192     255  224 */\r
1822                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1823                                 /* 287  256     319  288     351  320     383  352 */\r
1824                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1825                                 /* 415  384     447  416     479  448     511  480 */\r
1826                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1827 \r
1828                                 /* resvdDmaChannels */\r
1829                                 /* 31     0     63    32 */\r
1830                                 {0x00000000U, 0x00000000U},\r
1831 \r
1832                                 /* resvdQdmaChannels */\r
1833                                 /* 31     0 */\r
1834                                 {0x00000000U},\r
1835 \r
1836                                 /* resvdTccs */\r
1837                                 /* 31     0     63    32 */\r
1838                                 {0x00000000U, 0x00000000U},\r
1839                         },\r
1840 \r
1841                 /* Resources owned/reserved by region 6 (Not Associated to any core supported)*/\r
1842                         {\r
1843                                 /* ownPaRAMSets */\r
1844                                 /* 31     0     63    32     95    64     127   96 */\r
1845                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1846                                 /* 159  128     191  160     223  192     255  224 */\r
1847                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1848                                 /* 287  256     319  288     351  320     383  352 */\r
1849                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1850                                 /* 415  384     447  416     479  448     511  480 */\r
1851                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1852 \r
1853                                 /* ownDmaChannels */\r
1854                                 /* 31     0     63    32 */\r
1855                                 {0x00000000U, 0x00000000U},\r
1856 \r
1857                                 /* ownQdmaChannels */\r
1858                                 /* 31     0 */\r
1859                                 {0x00000000U},\r
1860 \r
1861                                 /* ownTccs */\r
1862                                 /* 31     0     63    32 */\r
1863                                 {0x00000000U, 0x00000000U},\r
1864 \r
1865                                 /* resvdPaRAMSets */\r
1866                                 /* 31     0     63    32     95    64     127   96 */\r
1867                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1868                                 /* 159  128     191  160     223  192     255  224 */\r
1869                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1870                                 /* 287  256     319  288     351  320     383  352 */\r
1871                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1872                                 /* 415  384     447  416     479  448     511  480 */\r
1873                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1874 \r
1875                                 /* resvdDmaChannels */\r
1876                                 /* 31     0     63    32 */\r
1877                                 {0x00000000U, 0x00000000U},\r
1878 \r
1879                                 /* resvdQdmaChannels */\r
1880                                 /* 31     0 */\r
1881                                 {0x00000000U},\r
1882 \r
1883                                 /* resvdTccs */\r
1884                                 /* 31     0     63    32 */\r
1885                                 {0x00000000U, 0x00000000U},\r
1886                         },\r
1887 \r
1888                 /* Resources owned/reserved by region 7 (Not Associated to any core supported)*/\r
1889                         {\r
1890                                 /* ownPaRAMSets */\r
1891                                 /* 31     0     63    32     95    64     127   96 */\r
1892                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1893                                 /* 159  128     191  160     223  192     255  224 */\r
1894                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1895                                 /* 287  256     319  288     351  320     383  352 */\r
1896                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1897                                 /* 415  384     447  416     479  448     511  480 */\r
1898                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1899 \r
1900                                 /* ownDmaChannels */\r
1901                                 /* 31     0     63    32 */\r
1902                                 {0x00000000U, 0x00000000U},\r
1903 \r
1904                                 /* ownQdmaChannels */\r
1905                                 /* 31     0 */\r
1906                                 {0x00000000U},\r
1907 \r
1908                                 /* ownTccs */\r
1909                                 /* 31     0     63    32 */\r
1910                                 {0x00000000U, 0x00000000U},\r
1911 \r
1912                                 /* resvdPaRAMSets */\r
1913                                 /* 31     0     63    32     95    64     127   96 */\r
1914                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1915                                 /* 159  128     191  160     223  192     255  224 */\r
1916                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1917                                 /* 287  256     319  288     351  320     383  352 */\r
1918                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1919                                 /* 415  384     447  416     479  448     511  480 */\r
1920                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1921 \r
1922                                 /* resvdDmaChannels */\r
1923                                 /* 31     0     63    32 */\r
1924                                 {0x00000000U, 0x00000000U},\r
1925 \r
1926                                 /* resvdQdmaChannels */\r
1927                                 /* 31     0 */\r
1928                                 {0x00000000U},\r
1929 \r
1930                                 /* resvdTccs */\r
1931                                 /* 31     0     63    32 */\r
1932                                 {0x00000000U, 0x00000000U},\r
1933                         },\r
1934             },\r
1935                 /* EDMA3 INSTANCE# 2 EVE EDMA*/\r
1936                 {\r
1937                 /* Resources owned/reserved by region 0 (Not Associated to any core supported)*/\r
1938                         {\r
1939                                 /* ownPaRAMSets */\r
1940                                 /* 31     0     63    32     95    64     127   96 */\r
1941                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1942                                 /* 159  128     191  160     223  192     255  224 */\r
1943                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1944                                 /* 287  256     319  288     351  320     383  352 */\r
1945                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1946                                 /* 415  384     447  416     479  448     511  480 */\r
1947                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1948 \r
1949                                 /* ownDmaChannels */\r
1950                                 /* 31     0     63    32 */\r
1951                                 {0x00000000U, 0x00000000U},\r
1952 \r
1953                                 /* ownQdmaChannels */\r
1954                                 /* 31     0 */\r
1955                                 {0x00000000U},\r
1956 \r
1957                                 /* ownTccs */\r
1958                                 /* 31     0     63    32 */\r
1959                                 {0x00000000U, 0x00000000U},\r
1960 \r
1961                                 /* resvdPaRAMSets */\r
1962                                 /* 31     0     63    32     95    64     127   96 */\r
1963                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1964                                 /* 159  128     191  160     223  192     255  224 */\r
1965                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1966                                 /* 287  256     319  288     351  320     383  352 */\r
1967                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1968                                 /* 415  384     447  416     479  448     511  480 */\r
1969                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1970 \r
1971                                 /* resvdDmaChannels */\r
1972                                 /* 31     0     63    32 */\r
1973                                 {0x00000000U, 0x00000000U},\r
1974 \r
1975                                 /* resvdQdmaChannels */\r
1976                                 /* 31     0 */\r
1977                                 {0x00000000U},\r
1978 \r
1979                                 /* resvdTccs */\r
1980                                 /* 31     0     63    32 */\r
1981                                 {0x00000000U, 0x00000000U},\r
1982                         },\r
1983 \r
1984                 /* Resources owned/reserved by region 1 (Associated to any EVE core)*/\r
1985                         {\r
1986                                 /* ownPaRAMSets */\r
1987                                 /* 31     0     63    32     95    64     127   96 */\r
1988                                 {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1989                                 /* 159  128     191  160     223  192     255  224 */\r
1990                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1991                                 /* 287  256     319  288     351  320     383  352 */\r
1992                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1993                                 /* 415  384     447  416     479  448     511  480 */\r
1994                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,},\r
1995 \r
1996                                 /* ownDmaChannels */\r
1997                                 /* 31     0     63    32 */\r
1998                                 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
1999 \r
2000                                 /* ownQdmaChannels */\r
2001                                 /* 31     0 */\r
2002                                 {0x000000FFU},\r
2003 \r
2004                                 /* ownTccs */\r
2005                                 /* 31     0     63    32 */\r
2006                                 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
2007 \r
2008                                 /* resvdPaRAMSets */\r
2009                                 /* 31     0     63    32     95    64     127   96 */\r
2010                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2011                                 /* 159  128     191  160     223  192     255  224 */\r
2012                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2013                                 /* 287  256     319  288     351  320     383  352 */\r
2014                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2015                                 /* 415  384     447  416     479  448     511  480 */\r
2016                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
2017 \r
2018                                 /* resvdDmaChannels */\r
2019                                 /* 31     0     63    32 */\r
2020                                 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_EVEEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_EVEEDMA},\r
2021 \r
2022                                 /* resvdQdmaChannels */\r
2023                                 /* 31     0 */\r
2024                                 {0x00U},\r
2025 \r
2026                                 /* resvdTccs */\r
2027                                 /* 31     0     63    32 */\r
2028                                 {0x00U, 0x00U},\r
2029                         },\r
2030 \r
2031                 /* Resources owned/reserved by region 2 (Not Associated to any core supported)*/\r
2032                         {\r
2033                                 /* ownPaRAMSets */\r
2034                                 /* 31     0     63    32     95    64     127   96 */\r
2035                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2036                                 /* 159  128     191  160     223  192     255  224 */\r
2037                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2038                                 /* 287  256     319  288     351  320     383  352 */\r
2039                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2040                                 /* 415  384     447  416     479  448     511  480 */\r
2041                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
2042 \r
2043                                 /* ownDmaChannels */\r
2044                                 /* 31     0     63    32 */\r
2045                                 {0x00000000U, 0x00000000U},\r
2046 \r
2047                                 /* ownQdmaChannels */\r
2048                                 /* 31     0 */\r
2049                                 {0x00000000U},\r
2050 \r
2051                                 /* ownTccs */\r
2052                                 /* 31     0     63    32 */\r
2053                                 {0x00000000U, 0x00000000U},\r
2054 \r
2055                                 /* resvdPaRAMSets */\r
2056                                 /* 31     0     63    32     95    64     127   96 */\r
2057                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2058                                 /* 159  128     191  160     223  192     255  224 */\r
2059                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2060                                 /* 287  256     319  288     351  320     383  352 */\r
2061                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2062                                 /* 415  384     447  416     479  448     511  480 */\r
2063                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
2064 \r
2065                                 /* resvdDmaChannels */\r
2066                                 /* 31     0     63    32 */\r
2067                                 {0x00000000U, 0x00000000U},\r
2068 \r
2069                                 /* resvdQdmaChannels */\r
2070                                 /* 31     0 */\r
2071                                 {0x00000000U},\r
2072 \r
2073                                 /* resvdTccs */\r
2074                                 /* 31     0     63    32 */\r
2075                                 {0x00000000U, 0x00000000U},\r
2076                         },\r
2077 \r
2078                 /* Resources owned/reserved by region 3 (Not Associated to any core supported)*/\r
2079                         {\r
2080                                 /* ownPaRAMSets */\r
2081                                 /* 31     0     63    32     95    64     127   96 */\r
2082                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2083                                 /* 159  128     191  160     223  192     255  224 */\r
2084                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2085                                 /* 287  256     319  288     351  320     383  352 */\r
2086                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2087                                 /* 415  384     447  416     479  448     511  480 */\r
2088                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
2089 \r
2090                                 /* ownDmaChannels */\r
2091                                 /* 31     0     63    32 */\r
2092                                 {0x00000000U, 0x00000000U},\r
2093 \r
2094                                 /* ownQdmaChannels */\r
2095                                 /* 31     0 */\r
2096                                 {0x00000000U},\r
2097 \r
2098                                 /* ownTccs */\r
2099                                 /* 31     0     63    32 */\r
2100                                 {0x00000000U, 0x00000000U},\r
2101 \r
2102                                 /* resvdPaRAMSets */\r
2103                                 /* 31     0     63    32     95    64     127   96 */\r
2104                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2105                                 /* 159  128     191  160     223  192     255  224 */\r
2106                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2107                                 /* 287  256     319  288     351  320     383  352 */\r
2108                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2109                                 /* 415  384     447  416     479  448     511  480 */\r
2110                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
2111 \r
2112                                 /* resvdDmaChannels */\r
2113                                 /* 31     0     63    32 */\r
2114                                 {0x00000000U, 0x00000000U},\r
2115 \r
2116                                 /* resvdQdmaChannels */\r
2117                                 /* 31     0 */\r
2118                                 {0x00000000U},\r
2119 \r
2120                                 /* resvdTccs */\r
2121                                 /* 31     0     63    32 */\r
2122                                 {0x00000000U, 0x00000000U},\r
2123                         },\r
2124 \r
2125                 /* Resources owned/reserved by region 4 (Not Associated to any core supported)*/\r
2126                         {\r
2127                                 /* ownPaRAMSets */\r
2128                                 /* 31     0     63    32     95    64     127   96 */\r
2129                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2130                                 /* 159  128     191  160     223  192     255  224 */\r
2131                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2132                                 /* 287  256     319  288     351  320     383  352 */\r
2133                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2134                                 /* 415  384     447  416     479  448     511  480 */\r
2135                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
2136 \r
2137                                 /* ownDmaChannels */\r
2138                                 /* 31     0     63    32 */\r
2139                                 {0x00000000U, 0x00000000U},\r
2140 \r
2141                                 /* ownQdmaChannels */\r
2142                                 /* 31     0 */\r
2143                                 {0x00000000U},\r
2144 \r
2145                                 /* ownTccs */\r
2146                                 /* 31     0     63    32 */\r
2147                                 {0x00000000U, 0x00000000U},\r
2148 \r
2149                                 /* resvdPaRAMSets */\r
2150                                 /* 31     0     63    32     95    64     127   96 */\r
2151                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2152                                 /* 159  128     191  160     223  192     255  224 */\r
2153                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2154                                 /* 287  256     319  288     351  320     383  352 */\r
2155                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2156                                 /* 415  384     447  416     479  448     511  480 */\r
2157                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
2158 \r
2159                                 /* resvdDmaChannels */\r
2160                                 /* 31     0     63    32 */\r
2161                                 {0x00000000U, 0x00000000U},\r
2162 \r
2163                                 /* resvdQdmaChannels */\r
2164                                 /* 31     0 */\r
2165                                 {0x00000000U},\r
2166 \r
2167                                 /* resvdTccs */\r
2168                                 /* 31     0     63    32 */\r
2169                                 {0x00000000U, 0x00000000U},\r
2170                         },\r
2171 \r
2172                 /* Resources owned/reserved by region 5 (Not Associated to any core supported)*/\r
2173                         {\r
2174                                 /* ownPaRAMSets */\r
2175                                 /* 31     0     63    32     95    64     127   96 */\r
2176                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2177                                 /* 159  128     191  160     223  192     255  224 */\r
2178                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2179                                 /* 287  256     319  288     351  320     383  352 */\r
2180                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2181                                 /* 415  384     447  416     479  448     511  480 */\r
2182                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
2183 \r
2184                                 /* ownDmaChannels */\r
2185                                 /* 31     0     63    32 */\r
2186                                 {0x00000000U, 0x00000000U},\r
2187 \r
2188                                 /* ownQdmaChannels */\r
2189                                 /* 31     0 */\r
2190                                 {0x00000000U},\r
2191 \r
2192                                 /* ownTccs */\r
2193                                 /* 31     0     63    32 */\r
2194                                 {0x00000000U, 0x00000000U},\r
2195 \r
2196                                 /* resvdPaRAMSets */\r
2197                                 /* 31     0     63    32     95    64     127   96 */\r
2198                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2199                                 /* 159  128     191  160     223  192     255  224 */\r
2200                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2201                                 /* 287  256     319  288     351  320     383  352 */\r
2202                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2203                                 /* 415  384     447  416     479  448     511  480 */\r
2204                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
2205 \r
2206                                 /* resvdDmaChannels */\r
2207                                 /* 31     0     63    32 */\r
2208                                 {0x00000000U, 0x00000000U},\r
2209 \r
2210                                 /* resvdQdmaChannels */\r
2211                                 /* 31     0 */\r
2212                                 {0x00000000U},\r
2213 \r
2214                                 /* resvdTccs */\r
2215                                 /* 31     0     63    32 */\r
2216                                 {0x00000000U, 0x00000000U},\r
2217                         },\r
2218 \r
2219                 /* Resources owned/reserved by region 6 (Not Associated to any core supported)*/\r
2220                         {\r
2221                                 /* ownPaRAMSets */\r
2222                                 /* 31     0     63    32     95    64     127   96 */\r
2223                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2224                                 /* 159  128     191  160     223  192     255  224 */\r
2225                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2226                                 /* 287  256     319  288     351  320     383  352 */\r
2227                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
2228                                 /* 415  384     447  416     479  448     511  480 */\r
2229                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
2230 \r
2231                                 /* ownDmaChannels */\r
2232                                 /* 31     0     63    32 */\r
2233                                 {0x00000000U, 0x00000000U},\r