Misra C fixes:
[keystone-rtos/edma3_lld.git] / packages / ti / sdo / edma3 / rm / sample / src / platforms / sample_tda2xx_cfg.c
1 /*\r
2  * sample_omapl138_cfg.c\r
3  *\r
4  * Platform specific EDMA3 hardware related information like number of transfer\r
5  * controllers, various interrupt ids etc. It is used while interrupts\r
6  * enabling / disabling. It needs to be ported for different SoCs.\r
7  *\r
8  * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/\r
9  *\r
10  *\r
11  *  Redistribution and use in source and binary forms, with or without\r
12  *  modification, are permitted provided that the following conditions\r
13  *  are met:\r
14  *\r
15  *    Redistributions of source code must retain the above copyright\r
16  *    notice, this list of conditions and the following disclaimer.\r
17  *\r
18  *    Redistributions in binary form must reproduce the above copyright\r
19  *    notice, this list of conditions and the following disclaimer in the\r
20  *    documentation and/or other materials provided with the\r
21  *    distribution.\r
22  *\r
23  *    Neither the name of Texas Instruments Incorporated nor the names of\r
24  *    its contributors may be used to endorse or promote products derived\r
25  *    from this software without specific prior written permission.\r
26  *\r
27  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
28  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
29  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
30  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
31  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
32  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
33  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
34  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
35  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
36  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
37  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
38  *\r
39 */\r
40 \r
41 #include <ti/sdo/edma3/rm/edma3_rm.h>\r
42 \r
43 /* Number of EDMA3 controllers present in the system */\r
44 #define NUM_EDMA3_INSTANCES         1U\r
45 const uint32_t numEdma3Instances = NUM_EDMA3_INSTANCES;\r
46 \r
47 /* Number of DSPs present in the system */\r
48 #define NUM_DSPS                    1U\r
49 const uint32_t numDsps = NUM_DSPS;\r
50 \r
51 /* Determine the processor id by reading DNUM register. */\r
52 /* Statically allocate the region numbers with cores. */\r
53 int32_t myCoreNum;\r
54 #define PID0_ADDRESS 0xE00FFFE0\r
55 #define CORE_ID_C0 0x0\r
56 #define CORE_ID_C1 0x1\r
57 \r
58 #ifdef BUILD_TDA2XX_MPU\r
59 void __inline readProcFeatureReg(void);\r
60 void __inline readProcFeatureReg(void)\r
61 {\r
62     asm ("    push    {r0-r2} \n\t"\r
63              "    MRC p15, 0, r0, c0, c0, 5\n\t"\r
64                  "    LDR      r1, =myCoreNum\n\t"\r
65                  "    STR      r0, [r1]\n\t"\r
66                  "    pop    {r0-r2}\n\t");\r
67 }\r
68 #endif\r
69 \r
70 int8_t*  getGlobalAddr(int8_t* addr);\r
71 \r
72 uint16_t isGblConfigRequired(uint32_t dspNum);\r
73 \r
74 uint16_t determineProcId(void);\r
75 \r
76 uint16_t determineProcId(void)\r
77 {\r
78 uint16_t regionNo = (uint16_t)numEdma3Instances;\r
79 #ifdef BUILD_TDA2XX_DSP\r
80 extern __cregister volatile uint32_t DNUM;\r
81 #endif\r
82 myCoreNum = (int32_t)numDsps;\r
83 #ifdef BUILD_TDA2XX_MPU\r
84 \r
85     readProcFeatureReg();\r
86                 regionNo = 0U;\r
87 /* myCoreNum is always 1 here, fix for klocwork error(Unreachable code) */\r
88         if(((uint32_t)myCoreNum & 0x03U) == 1U)\r
89     {\r
90                 regionNo = 1U;\r
91     }\r
92 #elif defined(BUILD_TDA2XX_IPU)\r
93 myCoreNum = (*(uint32_t *)(PID0_ADDRESS));\r
94 if(Core_getIpuId() == 1){\r
95         if(myCoreNum == CORE_ID_C0)\r
96     {\r
97                 regionNo = 4U;\r
98     }\r
99         else if (myCoreNum == CORE_ID_C1)\r
100     {\r
101                 regionNo = 5U;\r
102     }\r
103     else\r
104     {\r
105         ;/* Nothing to be done */\r
106     }\r
107 }\r
108 if(Core_getIpuId() == 2){\r
109         if(myCoreNum == CORE_ID_C0)\r
110     {\r
111                 regionNo = 6U;\r
112     }\r
113         else if (myCoreNum == CORE_ID_C1)\r
114     {\r
115                 regionNo = 7U;\r
116     }\r
117     else\r
118     {\r
119         ;/* Nothing to be done */\r
120     }\r
121 }\r
122 #elif defined BUILD_TDA2XX_DSP\r
123         myCoreNum = DNUM;\r
124         if(myCoreNum == 0)\r
125     {\r
126                 regionNo = 2;\r
127     }\r
128         else\r
129     {\r
130                 regionNo = 3;\r
131     }\r
132 #endif\r
133         return regionNo;\r
134 }\r
135 \r
136 int8_t*  getGlobalAddr(int8_t* addr)\r
137 {\r
138      return (addr); /* The address is already a global address */\r
139 }\r
140 uint16_t isGblConfigRequired(uint32_t dspNum)\r
141 {\r
142     (void) dspNum;\r
143 \r
144     return 1U;\r
145 }\r
146 \r
147 /* Semaphore handles */\r
148 EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};\r
149 \r
150 /** Number of PaRAM Sets available                                            */\r
151 #define EDMA3_NUM_PARAMSET                              (512U)\r
152 \r
153 /** Number of TCCS available                                                  */\r
154 #define EDMA3_NUM_TCC                                   (64U)\r
155 \r
156 /** Number of DMA Channels available                                          */\r
157 #define EDMA3_NUM_DMA_CHANNELS                          (64U)\r
158 \r
159 /** Number of QDMA Channels available                                         */\r
160 #define EDMA3_NUM_QDMA_CHANNELS                         (8U)\r
161 \r
162 /** Number of Event Queues available                                          */\r
163 #define EDMA3_0_NUM_EVTQUE                              (4U)\r
164 \r
165 /** Number of Transfer Controllers available                                  */\r
166 #define EDMA3_0_NUM_TC                                  (4U)\r
167 \r
168 /** Number of Regions                                                         */\r
169 #define EDMA3_0_NUM_REGIONS                             (2U)\r
170 \r
171 \r
172 /** Interrupt no. for Transfer Completion                                     */\r
173 #define EDMA3_0_CC_XFER_COMPLETION_INT                  (34U)\r
174 /** Interrupt no. for CC Error                                                */\r
175 #define EDMA3_0_CC_ERROR_INT                            (35U)\r
176 /** Interrupt no. for TCs Error                                               */\r
177 #define EDMA3_0_TC0_ERROR_INT                           (36U)\r
178 #define EDMA3_0_TC1_ERROR_INT                           (37U)\r
179 #define EDMA3_0_TC2_ERROR_INT                           (0U)\r
180 #define EDMA3_0_TC3_ERROR_INT                           (0U)\r
181 #define EDMA3_0_TC4_ERROR_INT                           (0U)\r
182 #define EDMA3_0_TC5_ERROR_INT                           (0U)\r
183 #define EDMA3_0_TC6_ERROR_INT                           (0U)\r
184 #define EDMA3_0_TC7_ERROR_INT                           (0U)\r
185 \r
186 /**\r
187  * EDMA3 interrupts (transfer completion, CC error etc.) correspond to different\r
188  * ECM events (SoC specific). These ECM events come\r
189  * under ECM block XXX (handling those specific ECM events). Normally, block\r
190  * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events\r
191  * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)\r
192  * is mapped to a specific HWI_INT YYY in the tcf file.\r
193  * Define EDMA3_HWI_INT_XFER_COMP to specific HWI_INT, corresponding\r
194  * to transfer completion interrupt.\r
195  * Define EDMA3_HWI_INT_CC_ERR to specific HWI_INT, corresponding\r
196  * to CC error interrupts.\r
197  * Define EDMA3_HWI_INT_TC_ERR to specific HWI_INT, corresponding\r
198  * to TC error interrupts.\r
199  */\r
200 /* EDMA 0 */\r
201 \r
202 #define EDMA3_0_HWI_INT_XFER_COMP                           (7U)\r
203 #define EDMA3_0_HWI_INT_CC_ERR                              (7U)\r
204 #define EDMA3_0_HWI_INT_TC0_ERR                             (7U)\r
205 #define EDMA3_0_HWI_INT_TC1_ERR                             (7U)\r
206 #define EDMA3_0_HWI_INT_TC2_ERR                             (7U)\r
207 #define EDMA3_0_HWI_INT_TC3_ERR                             (7U)\r
208 \r
209 \r
210 /**\r
211  * \brief Mapping of DMA channels 0-31 to Hardware Events from\r
212  * various peripherals, which use EDMA for data transfer.\r
213  * All channels need not be mapped, some can be free also.\r
214  * 1: Mapped\r
215  * 0: Not mapped\r
216  *\r
217  * This mapping will be used to allocate DMA channels when user passes\r
218  * EDMA3_RM_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory\r
219  * copy). The same mapping is used to allocate the TCC when user passes\r
220  * EDMA3_RM_TCC_ANY as tcc id (for eg to do memory-to-memory copy).\r
221  *\r
222  * To allocate more DMA channels or TCCs, one has to modify the event mapping.\r
223  */\r
224                                                       /* 31     0 */\r
225 #define EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0       (0x3FC0C06EU)  /* TBD */\r
226 \r
227 \r
228 /**\r
229  * \brief Mapping of DMA channels 32-63 to Hardware Events from\r
230  * various peripherals, which use EDMA for data transfer.\r
231  * All channels need not be mapped, some can be free also.\r
232  * 1: Mapped\r
233  * 0: Not mapped\r
234  *\r
235  * This mapping will be used to allocate DMA channels when user passes\r
236  * EDMA3_RM_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory\r
237  * copy). The same mapping is used to allocate the TCC when user passes\r
238  * EDMA3_RM_TCC_ANY as tcc id (for eg to do memory-to-memory copy).\r
239  *\r
240  * To allocate more DMA channels or TCCs, one has to modify the event mapping.\r
241  */\r
242 #define EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1       (0xF3FFFFFCU) /* TBD */\r
243 \r
244 \r
245 /* Variable which will be used internally for referring number of Event Queues*/\r
246 uint32_t numEdma3EvtQue[NUM_EDMA3_INSTANCES] =  {\r
247                                                         EDMA3_0_NUM_EVTQUE,\r
248                                                     };\r
249 \r
250 /* Variable which will be used internally for referring number of TCs.        */\r
251 uint32_t numEdma3Tc[NUM_EDMA3_INSTANCES] =  {\r
252                                                     EDMA3_0_NUM_TC,\r
253                                                 };\r
254 \r
255 /**\r
256  * Variable which will be used internally for referring transfer completion\r
257  * interrupt.\r
258  */\r
259 uint32_t ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
260 {\r
261     {\r
262         0U, EDMA3_0_CC_XFER_COMPLETION_INT, 0U, 0U, 0U, 0U, 0U, 0U,\r
263     },\r
264 };\r
265 \r
266 /**\r
267  * Variable which will be used internally for referring channel controller's\r
268  * error interrupt.\r
269  */\r
270 uint32_t ccErrorInt[NUM_EDMA3_INSTANCES] = {\r
271                                                     EDMA3_0_CC_ERROR_INT,\r
272                                                };\r
273 \r
274 /**\r
275  * Variable which will be used internally for referring transfer controllers'\r
276  * error interrupts.\r
277  */\r
278 uint32_t tcErrorInt[NUM_EDMA3_INSTANCES][8] =\r
279 {\r
280    {\r
281        EDMA3_0_TC0_ERROR_INT, EDMA3_0_TC1_ERROR_INT,\r
282        EDMA3_0_TC2_ERROR_INT, EDMA3_0_TC3_ERROR_INT,\r
283        EDMA3_0_TC4_ERROR_INT, EDMA3_0_TC5_ERROR_INT,\r
284        EDMA3_0_TC6_ERROR_INT, EDMA3_0_TC7_ERROR_INT,\r
285    }\r
286 };\r
287 \r
288 /**\r
289  * Variables which will be used internally for referring the hardware interrupt\r
290  * for various EDMA3 interrupts.\r
291  */\r
292 uint32_t hwIntXferComp[NUM_EDMA3_INSTANCES] = {\r
293                                                     EDMA3_0_HWI_INT_XFER_COMP\r
294                                                   };\r
295 \r
296 uint32_t hwIntCcErr[NUM_EDMA3_INSTANCES] = {\r
297                                                    EDMA3_0_HWI_INT_CC_ERR\r
298                                                };\r
299 \r
300 uint32_t hwIntTcErr[NUM_EDMA3_INSTANCES][8] = {\r
301                                                      {\r
302                                                         EDMA3_0_HWI_INT_TC0_ERR,\r
303                                                         EDMA3_0_HWI_INT_TC1_ERR,\r
304                                                         EDMA3_0_HWI_INT_TC2_ERR,\r
305                                                         EDMA3_0_HWI_INT_TC3_ERR,\r
306                                                         0U,\r
307                                                         0U,\r
308                                                         0U,\r
309                                                         0U\r
310                                                      }\r
311                                                };\r
312 \r
313 #define EDMA3_CC_BASE_ADDR                          ((void *)(0x43300000))\r
314 #define EDMA3_TC0_BASE_ADDR                         ((void *)(0x43400000))\r
315 #define EDMA3_TC1_BASE_ADDR                         ((void *)(0x43500000))\r
316 /* Driver Object Initialization Configuration                                 */\r
317 EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =\r
318 {\r
319     {\r
320         /* EDMA3 INSTANCE# 0 */\r
321         /** Total number of DMA Channels supported by the EDMA3 Controller    */\r
322         EDMA3_NUM_DMA_CHANNELS,\r
323         /** Total number of QDMA Channels supported by the EDMA3 Controller   */\r
324         EDMA3_NUM_QDMA_CHANNELS,\r
325         /** Total number of TCCs supported by the EDMA3 Controller            */\r
326         EDMA3_NUM_TCC,\r
327         /** Total number of PaRAM Sets supported by the EDMA3 Controller      */\r
328         EDMA3_NUM_PARAMSET,\r
329         /** Total number of Event Queues in the EDMA3 Controller              */\r
330         EDMA3_0_NUM_EVTQUE,\r
331         /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller*/\r
332         EDMA3_0_NUM_TC,\r
333         /** Number of Regions on this EDMA3 controller                        */\r
334         EDMA3_0_NUM_REGIONS,\r
335 \r
336         /**\r
337          * \brief Channel mapping existence\r
338          * A value of 0 (No channel mapping) implies that there is fixed association\r
339          * for a channel number to a parameter entry number or, in other words,\r
340          * PaRAM entry n corresponds to channel n.\r
341          */\r
342         1U,\r
343 \r
344         /** Existence of memory protection feature */\r
345         0U,\r
346 \r
347         /** Global Register Region of CC Registers */\r
348         EDMA3_CC_BASE_ADDR,\r
349         /** Transfer Controller (TC) Registers */\r
350         {\r
351                 EDMA3_TC0_BASE_ADDR,\r
352                 EDMA3_TC1_BASE_ADDR,\r
353                 (void *)NULL,\r
354                 (void *)NULL,\r
355             (void *)NULL,\r
356             (void *)NULL,\r
357             (void *)NULL,\r
358             (void *)NULL\r
359         },\r
360         /** Interrupt no. for Transfer Completion */\r
361         EDMA3_0_CC_XFER_COMPLETION_INT,\r
362         /** Interrupt no. for CC Error */\r
363         EDMA3_0_CC_ERROR_INT,\r
364         /** Interrupt no. for TCs Error */\r
365         {\r
366             EDMA3_0_TC0_ERROR_INT,\r
367             EDMA3_0_TC1_ERROR_INT,\r
368             EDMA3_0_TC2_ERROR_INT,\r
369             EDMA3_0_TC3_ERROR_INT,\r
370             EDMA3_0_TC4_ERROR_INT,\r
371             EDMA3_0_TC5_ERROR_INT,\r
372             EDMA3_0_TC6_ERROR_INT,\r
373             EDMA3_0_TC7_ERROR_INT\r
374         },\r
375 \r
376         /**\r
377          * \brief EDMA3 TC priority setting\r
378          *\r
379          * User can program the priority of the Event Queues\r
380          * at a system-wide level.  This means that the user can set the\r
381          * priority of an IO initiated by either of the TCs (Transfer Controllers)\r
382          * relative to IO initiated by the other bus masters on the\r
383          * device (ARM, DSP, USB, etc)\r
384          */\r
385         {\r
386             0U,\r
387             1U,\r
388             2U,\r
389             3U,\r
390             0U,\r
391             0U,\r
392             0U,\r
393             0U\r
394         },\r
395         /**\r
396          * \brief To Configure the Threshold level of number of events\r
397          * that can be queued up in the Event queues. EDMA3CC error register\r
398          * (CCERR) will indicate whether or not at any instant of time the\r
399          * number of events queued up in any of the event queues exceeds\r
400          * or equals the threshold/watermark value that is set\r
401          * in the queue watermark threshold register (QWMTHRA).\r
402          */\r
403         {\r
404             16U,\r
405             16U,\r
406             16U,\r
407             16U,\r
408             0U,\r
409             0U,\r
410             0U,\r
411             0U\r
412         },\r
413 \r
414         /**\r
415          * \brief To Configure the Default Burst Size (DBS) of TCs.\r
416          * An optimally-sized command is defined by the transfer controller\r
417          * default burst size (DBS). Different TCs can have different\r
418          * DBS values. It is defined in Bytes.\r
419          */\r
420             {\r
421             16U,\r
422             16U,\r
423             0U,\r
424             0U,\r
425             0U,\r
426             0U,\r
427             0U,\r
428             0U\r
429             },\r
430 \r
431         /**\r
432          * \brief Mapping from each DMA channel to a Parameter RAM set,\r
433          * if it exists, otherwise of no use.\r
434          */\r
435             {\r
436             0U, 1U, 2U, 3U, 4U, 5U, 6U, 7U,\r
437             8U, 9U, 10U, 11U, 12U, 13U, 14U, 15U,\r
438             16U, 17U, 18U, 19U, 20U, 21U, 22U, 23U,\r
439             24U, 25U, 26U, 27U, 28U, 29U, 30U, 31U,\r
440             32U, 33U, 34U, 35U, 36U, 37U, 38U, 39U, \r
441             40U, 41U, 42U, 43U, 44U, 45U, 46U, 47U,\r
442             48U, 49U, 50U, 51U, 52U, 53U, 54U, 55U,\r
443             56U, 57U, 58U, 59U, 60U, 61U, 62U, 63U\r
444             },\r
445 \r
446          /**\r
447           * \brief Mapping from each DMA channel to a TCC. This specific\r
448           * TCC code will be returned when the transfer is completed\r
449           * on the mapped channel.\r
450           */\r
451             {\r
452             0U, 1U, 2U, 3U,\r
453             4U, 5U, 6U, 7U,\r
454             8U, 9U, 10U, 11U,\r
455             12U, 13U, 14U, 15U,\r
456             16U, 17U, 18U, 19U,\r
457             20U, 21U, 22U, 23U,\r
458             24U, 25U, 26U, 27U,\r
459             28U, 29U, 30U, 31U,\r
460             32U, 33U, 34U, 35U,\r
461             36U, 37U, 38U, 39U,\r
462             40U, 41U, 42U, 43U,\r
463             44U, 45U, 46U, 47U,\r
464             48U, 49U, 50U, 51U,\r
465             52U, 53U, 54U, 55U,\r
466             56U, 57U, 58U, 59U,\r
467             60U, 61U, 62U, 63U\r
468             },\r
469 \r
470         /**\r
471          * \brief Mapping of DMA channels to Hardware Events from\r
472          * various peripherals, which use EDMA for data transfer.\r
473          * All channels need not be mapped, some can be free also.\r
474          */\r
475             {\r
476             EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0,\r
477             EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1\r
478             }\r
479         },\r
480 \r
481 };\r
482 \r
483 \r
484 /* Driver Instance Initialization Configuration */\r
485 EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
486 {\r
487     /* EDMA3 INSTANCE# 0 */\r
488                 {\r
489                         /* Resources owned/reserved by region 0 (Associated to any MPU core)*/\r
490                         {\r
491                                 /* ownPaRAMSets */\r
492                                 /* 31     0     63    32     95    64     127   96 */\r
493                                 {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
494                                 /* 159  128     191  160     223  192     255  224 */\r
495                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
496                                 /* 287  256     319  288     351  320     383  352 */\r
497                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
498                                 /* 415  384     447  416     479  448     511  480 */\r
499                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},\r
500 \r
501                                 /* ownDmaChannels */\r
502                                 /* 31     0     63    32 */\r
503                                 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
504 \r
505                                 /* ownQdmaChannels */\r
506                                 /* 31     0 */\r
507                                 {0x000000FFU},\r
508 \r
509                                 /* ownTccs */\r
510                                 /* 31     0     63    32 */\r
511                                 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
512 \r
513                                 /* resvdPaRAMSets */\r
514                                 /* 31     0     63    32     95    64     127   96 */\r
515                                 {0xFFFFFFFFU, 0xFFFFFFFFU, 0x00000000U, 0x00000000U,\r
516                                 /* 159  128     191  160     223  192     255  224 */\r
517                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
518                                 /* 287  256     319  288     351  320     383  352 */\r
519                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
520                                 /* 415  384     447  416     479  448     511  480 */\r
521                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
522 \r
523                                 /* resvdDmaChannels */\r
524                                 /* 31     0     63    32 */\r
525                                 {0x00U, 0x00U},\r
526 \r
527                                 /* resvdQdmaChannels */\r
528                                 /* 31     0 */\r
529                                 {0x00U},\r
530 \r
531                                 /* resvdTccs */\r
532                                 /* 31     0     63    32 */\r
533                                 {0x00U, 0x00U},\r
534                         },\r
535 \r
536                         /* Resources owned/reserved by region 1 (Associated to any DSP core) */\r
537                         {\r
538                                 /* ownPaRAMSets */\r
539                                 /* 31     0     63    32     95    64     127   96 */\r
540                                 {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
541                                 /* 159  128     191  160     223  192     255  224 */\r
542                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
543                                 /* 287  256     319  288     351  320     383  352 */\r
544                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
545                                 /* 415  384     447  416     479  448     511  480 */\r
546                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},\r
547 \r
548                                 /* ownDmaChannels */\r
549                                 /* 31     0     63    32 */\r
550                                 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
551 \r
552                                 /* ownQdmaChannels */\r
553                                 /* 31     0 */\r
554                                 {0x000000FFU},\r
555 \r
556                                 /* ownTccs */\r
557                                 /* 31     0     63    32 */\r
558                                 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
559 \r
560                                 /* resvdPaRAMSets */\r
561                                 /* 31     0     63    32     95    64     127   96 */\r
562                                 {0xFFFFFFFFU, 0xFFFFFFFFU, 0x00000000U, 0x00000000U,\r
563                                 /* 159  128     191  160     223  192     255  224 */\r
564                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
565                                 /* 287  256     319  288     351  320     383  352 */\r
566                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
567                                 /* 415  384     447  416     479  448     511  480 */\r
568                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
569 \r
570                                 /* resvdDmaChannels */\r
571                                 /* 31     0     63    32 */\r
572                                 {0x00U, 0x00U},\r
573 \r
574                                 /* resvdQdmaChannels */\r
575                                 /* 31     0 */\r
576                                 {0x00U},\r
577 \r
578                                 /* resvdTccs */\r
579                                 /* 31     0     63    32 */\r
580                                 {0x00U, 0x00U},\r
581                         },\r
582 \r
583                 /* Resources owned/reserved by region 2 (Associated to any IPU0 core)*/\r
584                         {\r
585                                 /* ownPaRAMSets */\r
586                                 /* 31     0     63    32     95    64     127   96 */\r
587                                 {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
588                                 /* 159  128     191  160     223  192     255  224 */\r
589                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
590                                 /* 287  256     319  288     351  320     383  352 */\r
591                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
592                                 /* 415  384     447  416     479  448     511  480 */\r
593                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},\r
594 \r
595                                 /* ownDmaChannels */\r
596                                 /* 31     0     63    32 */\r
597                                 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
598 \r
599                                 /* ownQdmaChannels */\r
600                                 /* 31     0 */\r
601                                 {0x000000FFU},\r
602 \r
603                                 /* ownTccs */\r
604                                 /* 31     0     63    32 */\r
605                                 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
606 \r
607                                 /* resvdPaRAMSets */\r
608                                 /* 31     0     63    32     95    64     127   96 */\r
609                                 {0xFFFFFFFFU, 0xFFFFFFFFU, 0x00000000U, 0x00000000U,\r
610                                 /* 159  128     191  160     223  192     255  224 */\r
611                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
612                                 /* 287  256     319  288     351  320     383  352 */\r
613                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
614                                 /* 415  384     447  416     479  448     511  480 */\r
615                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
616 \r
617                                 /* resvdDmaChannels */\r
618                                 /* 31     0     63    32 */\r
619                                 {0x00U, 0x00U},\r
620 \r
621                                 /* resvdQdmaChannels */\r
622                                 /* 31     0 */\r
623                                 {0x00U},\r
624 \r
625                                 /* resvdTccs */\r
626                                 /* 31     0     63    32 */\r
627                                 {0x00U, 0x00U},\r
628                         },\r
629 \r
630                 /* Resources owned/reserved by region 3 (Associated to any IPU1 core)*/\r
631                         {\r
632                                 /* ownPaRAMSets */\r
633                                 /* 31     0     63    32     95    64     127   96 */\r
634                                 {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
635                                 /* 159  128     191  160     223  192     255  224 */\r
636                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
637                                 /* 287  256     319  288     351  320     383  352 */\r
638                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
639                                 /* 415  384     447  416     479  448     511  480 */\r
640                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},\r
641 \r
642                                 /* ownDmaChannels */\r
643                                 /* 31     0     63    32 */\r
644                                 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
645 \r
646                                 /* ownQdmaChannels */\r
647                                 /* 31     0 */\r
648                                 {0x000000FFU},\r
649 \r
650                                 /* ownTccs */\r
651                                 /* 31     0     63    32 */\r
652                                 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
653 \r
654                                 /* resvdPaRAMSets */\r
655                                 /* 31     0     63    32     95    64     127   96 */\r
656                                 {0xFFFFFFFFU, 0xFFFFFFFFU, 0x00000000U, 0x00000000U,\r
657                                 /* 159  128     191  160     223  192     255  224 */\r
658                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
659                                 /* 287  256     319  288     351  320     383  352 */\r
660                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
661                                 /* 415  384     447  416     479  448     511  480 */\r
662                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
663 \r
664                                 /* resvdDmaChannels */\r
665                                 /* 31     0     63    32 */\r
666                                 {0x00U, 0x00U},\r
667 \r
668                                 /* resvdQdmaChannels */\r
669                                 /* 31     0 */\r
670                                 {0x00U},\r
671 \r
672                                 /* resvdTccs */\r
673                                 /* 31     0     63    32 */\r
674                                 {0x00U, 0x00U},\r
675                         },\r
676 \r
677                 /* Resources owned/reserved by region 4 (Not Associated to any core supported)*/\r
678                         {\r
679                                 /* ownPaRAMSets */\r
680                                 /* 31     0     63    32     95    64     127   96 */\r
681                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
682                                 /* 159  128     191  160     223  192     255  224 */\r
683                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
684                                 /* 287  256     319  288     351  320     383  352 */\r
685                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
686                                 /* 415  384     447  416     479  448     511  480 */\r
687                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
688 \r
689                                 /* ownDmaChannels */\r
690                                 /* 31     0     63    32 */\r
691                                 {0x00000000U, 0x00000000U},\r
692 \r
693                                 /* ownQdmaChannels */\r
694                                 /* 31     0 */\r
695                                 {0x00000000U},\r
696 \r
697                                 /* ownTccs */\r
698                                 /* 31     0     63    32 */\r
699                                 {0x00000000U, 0x00000000U},\r
700 \r
701                                 /* resvdPaRAMSets */\r
702                                 /* 31     0     63    32     95    64     127   96 */\r
703                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
704                                 /* 159  128     191  160     223  192     255  224 */\r
705                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
706                                 /* 287  256     319  288     351  320     383  352 */\r
707                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
708                                 /* 415  384     447  416     479  448     511  480 */\r
709                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
710 \r
711                                 /* resvdDmaChannels */\r
712                                 /* 31     0     63    32 */\r
713                                 {0x00000000U, 0x00000000U},\r
714 \r
715                                 /* resvdQdmaChannels */\r
716                                 /* 31     0 */\r
717                                 {0x00000000U},\r
718 \r
719                                 /* resvdTccs */\r
720                                 /* 31     0     63    32 */\r
721                                 {0x00000000U, 0x00000000U},\r
722                         },\r
723 \r
724                 /* Resources owned/reserved by region 5 (Not Associated to any core supported)*/\r
725                         {\r
726                                 /* ownPaRAMSets */\r
727                                 /* 31     0     63    32     95    64     127   96 */\r
728                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
729                                 /* 159  128     191  160     223  192     255  224 */\r
730                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
731                                 /* 287  256     319  288     351  320     383  352 */\r
732                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
733                                 /* 415  384     447  416     479  448     511  480 */\r
734                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
735 \r
736                                 /* ownDmaChannels */\r
737                                 /* 31     0     63    32 */\r
738                                 {0x00000000U, 0x00000000U},\r
739 \r
740                                 /* ownQdmaChannels */\r
741                                 /* 31     0 */\r
742                                 {0x00000000U},\r
743 \r
744                                 /* ownTccs */\r
745                                 /* 31     0     63    32 */\r
746                                 {0x00000000U, 0x00000000U},\r
747 \r
748                                 /* resvdPaRAMSets */\r
749                                 /* 31     0     63    32     95    64     127   96 */\r
750                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
751                                 /* 159  128     191  160     223  192     255  224 */\r
752                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
753                                 /* 287  256     319  288     351  320     383  352 */\r
754                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
755                                 /* 415  384     447  416     479  448     511  480 */\r
756                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
757 \r
758                                 /* resvdDmaChannels */\r
759                                 /* 31     0     63    32 */\r
760                                 {0x00000000U, 0x00000000U},\r
761 \r
762                                 /* resvdQdmaChannels */\r
763                                 /* 31     0 */\r
764                                 {0x00000000U},\r
765 \r
766                                 /* resvdTccs */\r
767                                 /* 31     0     63    32 */\r
768                                 {0x00000000U, 0x00000000U},\r
769                         },\r
770 \r
771                 /* Resources owned/reserved by region 6 (Not Associated to any core supported)*/\r
772                         {\r
773                                 /* ownPaRAMSets */\r
774                                 /* 31     0     63    32     95    64     127   96 */\r
775                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
776                                 /* 159  128     191  160     223  192     255  224 */\r
777                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
778                                 /* 287  256     319  288     351  320     383  352 */\r
779                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
780                                 /* 415  384     447  416     479  448     511  480 */\r
781                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
782 \r
783                                 /* ownDmaChannels */\r
784                                 /* 31     0     63    32 */\r
785                                 {0x00000000U, 0x00000000U},\r
786 \r
787                                 /* ownQdmaChannels */\r
788                                 /* 31     0 */\r
789                                 {0x00000000U},\r
790 \r
791                                 /* ownTccs */\r
792                                 /* 31     0     63    32 */\r
793                                 {0x00000000U, 0x00000000U},\r
794 \r
795                                 /* resvdPaRAMSets */\r
796                                 /* 31     0     63    32     95    64     127   96 */\r
797                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
798                                 /* 159  128     191  160     223  192     255  224 */\r
799                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
800                                 /* 287  256     319  288     351  320     383  352 */\r
801                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
802                                 /* 415  384     447  416     479  448     511  480 */\r
803                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
804 \r
805                                 /* resvdDmaChannels */\r
806                                 /* 31     0     63    32 */\r
807                                 {0x00000000U, 0x00000000U},\r
808 \r
809                                 /* resvdQdmaChannels */\r
810                                 /* 31     0 */\r
811                                 {0x00000000U},\r
812 \r
813                                 /* resvdTccs */\r
814                                 /* 31     0     63    32 */\r
815                                 {0x00000000U, 0x00000000U},\r
816                         },\r
817 \r
818                 /* Resources owned/reserved by region 7 (Not Associated to any core supported)*/\r
819                         {\r
820                                 /* ownPaRAMSets */\r
821                                 /* 31     0     63    32     95    64     127   96 */\r
822                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
823                                 /* 159  128     191  160     223  192     255  224 */\r
824                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
825                                 /* 287  256     319  288     351  320     383  352 */\r
826                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
827                                 /* 415  384     447  416     479  448     511  480 */\r
828                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
829 \r
830                                 /* ownDmaChannels */\r
831                                 /* 31     0     63    32 */\r
832                                 {0x00000000U, 0x00000000U},\r
833 \r
834                                 /* ownQdmaChannels */\r
835                                 /* 31     0 */\r
836                                 {0x00000000U},\r
837 \r
838                                 /* ownTccs */\r
839                                 /* 31     0     63    32 */\r
840                                 {0x00000000U, 0x00000000U},\r
841 \r
842                                 /* resvdPaRAMSets */\r
843                                 /* 31     0     63    32     95    64     127   96 */\r
844                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
845                                 /* 159  128     191  160     223  192     255  224 */\r
846                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
847                                 /* 287  256     319  288     351  320     383  352 */\r
848                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
849                                 /* 415  384     447  416     479  448     511  480 */\r
850                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
851 \r
852                                 /* resvdDmaChannels */\r
853                                 /* 31     0     63    32 */\r
854                                 {0x00000000U, 0x00000000U},\r
855 \r
856                                 /* resvdQdmaChannels */\r
857                                 /* 31     0 */\r
858                                 {0x00000000U},\r
859 \r
860                                 /* resvdTccs */\r
861                                 /* 31     0     63    32 */\r
862                                 {0x00000000U, 0x00000000U},\r
863         },\r
864     },\r
865 };\r
866 \r
867 /* Driver Instance Cross bar event to channel map Initialization Configuration */\r
868 EDMA3_RM_GblXbarToChanConfigParams sampleXbarChanInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
869 {\r
870     /* EDMA3 INSTANCE# 0 */\r
871     {\r
872         /* Event to channel map for region 0 */\r
873         {\r
874             {-1, -1, -1, -1, -1, -1, -1, -1,\r
875             -1, -1, -1, -1, -1, -1, -1, -1,\r
876             -1, -1, -1, -1, -1, -1, -1, -1,\r
877             -1, -1, -1, -1, -1, -1, -1}\r
878         },\r
879         /* Event to channel map for region 1 */\r
880         {\r
881             {-1, -1, -1, -1, -1, -1, -1, -1,\r
882             -1, -1, -1, -1, -1, -1, -1, -1,\r
883             -1, -1, -1, -1, -1, -1, -1, -1,\r
884             -1, 26, 27, -1, -1, -1, -1}\r
885         },\r
886         /* Event to channel map for region 2 */\r
887         {\r
888             {-1, -1, -1, -1, -1, -1, -1, -1,\r
889             -1, -1, -1, -1, -1, -1, -1, -1,\r
890             -1, -1, -1, -1, -1, -1, -1, -1,\r
891             -1, -1, -1, -1, -1, -1, -1}\r
892         },\r
893         /* Event to channel map for region 3 */\r
894         {\r
895             {-1, -1, -1, -1, -1, -1, -1, -1,\r
896             -1, -1, -1, -1, -1, -1, -1, -1,\r
897             -1, -1, -1, -1, -1, -1, -1, -1,\r
898             -1, -1, -1, -1, -1, -1, -1}\r
899         },\r
900         /* Event to channel map for region 4 */\r
901         {\r
902             {-1, -1, -1, -1, -1, -1, -1, -1,\r
903             -1, -1, -1, -1, -1, -1, -1, -1,\r
904             -1, -1, -1, -1, -1, -1, -1, -1,\r
905             -1, -1, -1, -1, -1, -1, -1}\r
906         },\r
907         /* Event to channel map for region 5 */\r
908         {\r
909             {-1, -1, -1, -1, -1, -1, -1, -1,\r
910             -1, -1, -1, -1, -1, -1, -1, -1,\r
911             -1, -1, -1, -1, -1, -1, -1, -1,\r
912             -1, -1, -1, -1, -1, -1, -1}\r
913         },\r
914         /* Event to channel map for region 6 */\r
915         {\r
916             {-1, -1, -1, -1, -1, -1, -1, -1,\r
917             -1, -1, -1, -1, -1, -1, -1, -1,\r
918             -1, -1, -1, -1, -1, -1, -1, -1,\r
919             -1, -1, -1, -1, -1, -1, -1}\r
920         },\r
921         /* Event to channel map for region 7 */\r
922         {\r
923             {-1, -1, -1, -1, -1, -1, -1, -1,\r
924             -1, -1, -1, -1, -1, -1, -1, -1,\r
925             -1, -1, -1, -1, -1, -1, -1, -1,\r
926             -1, -1, -1, -1, -1, -1, -1}\r
927         },\r
928     }\r
929 };\r
930 \r
931 /* End of File */\r
932 \r