7bbfc10bf6a28fd13bb662183f8d74b0f99a2237
[keystone-rtos/edma3_lld.git] / packages / ti / sdo / edma3 / rm / sample / src / platforms / sample_tda2xx_cfg.c
1 /*\r
2  * sample_omapl138_cfg.c\r
3  *\r
4  * Platform specific EDMA3 hardware related information like number of transfer\r
5  * controllers, various interrupt ids etc. It is used while interrupts\r
6  * enabling / disabling. It needs to be ported for different SoCs.\r
7  *\r
8  * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/\r
9  *\r
10  *\r
11  *  Redistribution and use in source and binary forms, with or without\r
12  *  modification, are permitted provided that the following conditions\r
13  *  are met:\r
14  *\r
15  *    Redistributions of source code must retain the above copyright\r
16  *    notice, this list of conditions and the following disclaimer.\r
17  *\r
18  *    Redistributions in binary form must reproduce the above copyright\r
19  *    notice, this list of conditions and the following disclaimer in the\r
20  *    documentation and/or other materials provided with the\r
21  *    distribution.\r
22  *\r
23  *    Neither the name of Texas Instruments Incorporated nor the names of\r
24  *    its contributors may be used to endorse or promote products derived\r
25  *    from this software without specific prior written permission.\r
26  *\r
27  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
28  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
29  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
30  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
31  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
32  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
33  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
34  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
35  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
36  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
37  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
38  *\r
39 */\r
40 \r
41 #include <ti/sdo/edma3/rm/edma3_rm.h>\r
42 \r
43 /* Number of EDMA3 controllers present in the system */\r
44 #define NUM_EDMA3_INSTANCES         1u\r
45 const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;\r
46 \r
47 /* Number of DSPs present in the system */\r
48 #define NUM_DSPS                    1u\r
49 const unsigned int numDsps = NUM_DSPS;\r
50 \r
51 /* Determine the processor id by reading DNUM register. */\r
52 /* Statically allocate the region numbers with cores. */\r
53 int myCoreNum;\r
54 #define PID0_ADDRESS 0xE00FFFE0\r
55 #define CORE_ID_C0 0x0\r
56 #define CORE_ID_C1 0x1\r
57 unsigned short determineProcId()\r
58 {\r
59 unsigned short regionNo = numEdma3Instances;\r
60 #ifdef BUILD_TDA2XX_DSP\r
61 extern __cregister volatile unsigned int DNUM;\r
62 #endif\r
63 myCoreNum = numDsps;\r
64 #ifdef BUILD_TDA2XX_MPU\r
65 \r
66     asm ("    push    {r0-r2} \n\t"\r
67              "    MRC p15, 0, r0, c0, c0, 5\n\t"\r
68                  "    LDR      r1, =myCoreNum\n\t"\r
69                  "    STR      r0, [r1]\n\t"\r
70                  "    pop    {r0-r2}\n\t");\r
71         if((myCoreNum & 0x03) == 1)\r
72                 regionNo = 1;\r
73         else\r
74                 regionNo = 0;\r
75 #elif defined(BUILD_TDA2XX_IPU)\r
76 myCoreNum = (*(unsigned int *)(PID0_ADDRESS));\r
77 if(Core_getIpuId() == 1){\r
78         if(myCoreNum == CORE_ID_C0)\r
79                 regionNo = 4;\r
80         else if (myCoreNum == CORE_ID_C1)\r
81                 regionNo = 5;\r
82 }\r
83 if(Core_getIpuId() == 2){\r
84         if(myCoreNum == CORE_ID_C0)\r
85                 regionNo = 6;\r
86         else if (myCoreNum == CORE_ID_C1)\r
87                 regionNo = 7;\r
88 }\r
89 #elif defined BUILD_TDA2XX_DSP\r
90         myCoreNum = DNUM;\r
91         if(myCoreNum == 0)\r
92                 regionNo = 2;\r
93         else\r
94                 regionNo = 3;\r
95 #endif\r
96         return regionNo;\r
97 }\r
98 \r
99 signed char*  getGlobalAddr(signed char* addr)\r
100 {\r
101      return (addr); /* The address is already a global address */\r
102 }\r
103 unsigned short isGblConfigRequired(unsigned int dspNum)\r
104 {\r
105     (void) dspNum;\r
106 \r
107     return 1;\r
108 }\r
109 \r
110 /* Semaphore handles */\r
111 EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};\r
112 \r
113 /** Number of PaRAM Sets available                                            */\r
114 #define EDMA3_NUM_PARAMSET                              (512u)\r
115 \r
116 /** Number of TCCS available                                                  */\r
117 #define EDMA3_NUM_TCC                                   (64u)\r
118 \r
119 /** Number of DMA Channels available                                          */\r
120 #define EDMA3_NUM_DMA_CHANNELS                          (64u)\r
121 \r
122 /** Number of QDMA Channels available                                         */\r
123 #define EDMA3_NUM_QDMA_CHANNELS                         (8u)\r
124 \r
125 /** Number of Event Queues available                                          */\r
126 #define EDMA3_0_NUM_EVTQUE                              (4u)\r
127 \r
128 /** Number of Transfer Controllers available                                  */\r
129 #define EDMA3_0_NUM_TC                                  (4u)\r
130 \r
131 /** Number of Regions                                                         */\r
132 #define EDMA3_0_NUM_REGIONS                             (2u)\r
133 \r
134 \r
135 /** Interrupt no. for Transfer Completion                                     */\r
136 #define EDMA3_0_CC_XFER_COMPLETION_INT                  (34u)\r
137 /** Interrupt no. for CC Error                                                */\r
138 #define EDMA3_0_CC_ERROR_INT                            (35u)\r
139 /** Interrupt no. for TCs Error                                               */\r
140 #define EDMA3_0_TC0_ERROR_INT                           (36u)\r
141 #define EDMA3_0_TC1_ERROR_INT                           (37u)\r
142 #define EDMA3_0_TC2_ERROR_INT                           (0u)\r
143 #define EDMA3_0_TC3_ERROR_INT                           (0u)\r
144 #define EDMA3_0_TC4_ERROR_INT                           (0u)\r
145 #define EDMA3_0_TC5_ERROR_INT                           (0u)\r
146 #define EDMA3_0_TC6_ERROR_INT                           (0u)\r
147 #define EDMA3_0_TC7_ERROR_INT                           (0u)\r
148 \r
149 /**\r
150  * EDMA3 interrupts (transfer completion, CC error etc.) correspond to different\r
151  * ECM events (SoC specific). These ECM events come\r
152  * under ECM block XXX (handling those specific ECM events). Normally, block\r
153  * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events\r
154  * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)\r
155  * is mapped to a specific HWI_INT YYY in the tcf file.\r
156  * Define EDMA3_HWI_INT_XFER_COMP to specific HWI_INT, corresponding\r
157  * to transfer completion interrupt.\r
158  * Define EDMA3_HWI_INT_CC_ERR to specific HWI_INT, corresponding\r
159  * to CC error interrupts.\r
160  * Define EDMA3_HWI_INT_TC_ERR to specific HWI_INT, corresponding\r
161  * to TC error interrupts.\r
162  */\r
163 /* EDMA 0 */\r
164 \r
165 #define EDMA3_0_HWI_INT_XFER_COMP                           (7u)\r
166 #define EDMA3_0_HWI_INT_CC_ERR                              (7u)\r
167 #define EDMA3_0_HWI_INT_TC0_ERR                             (7u)\r
168 #define EDMA3_0_HWI_INT_TC1_ERR                             (7u)\r
169 #define EDMA3_0_HWI_INT_TC2_ERR                             (7u)\r
170 #define EDMA3_0_HWI_INT_TC3_ERR                             (7u)\r
171 \r
172 \r
173 /**\r
174  * \brief Mapping of DMA channels 0-31 to Hardware Events from\r
175  * various peripherals, which use EDMA for data transfer.\r
176  * All channels need not be mapped, some can be free also.\r
177  * 1: Mapped\r
178  * 0: Not mapped\r
179  *\r
180  * This mapping will be used to allocate DMA channels when user passes\r
181  * EDMA3_RM_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory\r
182  * copy). The same mapping is used to allocate the TCC when user passes\r
183  * EDMA3_RM_TCC_ANY as tcc id (for eg to do memory-to-memory copy).\r
184  *\r
185  * To allocate more DMA channels or TCCs, one has to modify the event mapping.\r
186  */\r
187                                                       /* 31     0 */\r
188 #define EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0       (0x3FC0C06Eu)  /* TBD */\r
189 \r
190 \r
191 /**\r
192  * \brief Mapping of DMA channels 32-63 to Hardware Events from\r
193  * various peripherals, which use EDMA for data transfer.\r
194  * All channels need not be mapped, some can be free also.\r
195  * 1: Mapped\r
196  * 0: Not mapped\r
197  *\r
198  * This mapping will be used to allocate DMA channels when user passes\r
199  * EDMA3_RM_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory\r
200  * copy). The same mapping is used to allocate the TCC when user passes\r
201  * EDMA3_RM_TCC_ANY as tcc id (for eg to do memory-to-memory copy).\r
202  *\r
203  * To allocate more DMA channels or TCCs, one has to modify the event mapping.\r
204  */\r
205 #define EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1       (0xF3FFFFFCu) /* TBD */\r
206 \r
207 \r
208 /* Variable which will be used internally for referring number of Event Queues*/\r
209 unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] =  {\r
210                                                         EDMA3_0_NUM_EVTQUE,\r
211                                                     };\r
212 \r
213 /* Variable which will be used internally for referring number of TCs.        */\r
214 unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] =  {\r
215                                                     EDMA3_0_NUM_TC,\r
216                                                 };\r
217 \r
218 /**\r
219  * Variable which will be used internally for referring transfer completion\r
220  * interrupt.\r
221  */\r
222 unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
223 {\r
224     {\r
225         0u, EDMA3_0_CC_XFER_COMPLETION_INT, 0u, 0u, 0u, 0u, 0u, 0u,\r
226     },\r
227 };\r
228 \r
229 /**\r
230  * Variable which will be used internally for referring channel controller's\r
231  * error interrupt.\r
232  */\r
233 unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {\r
234                                                     EDMA3_0_CC_ERROR_INT,\r
235                                                };\r
236 \r
237 /**\r
238  * Variable which will be used internally for referring transfer controllers'\r
239  * error interrupts.\r
240  */\r
241 unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][8] =\r
242 {\r
243    {\r
244        EDMA3_0_TC0_ERROR_INT, EDMA3_0_TC1_ERROR_INT,\r
245        EDMA3_0_TC2_ERROR_INT, EDMA3_0_TC3_ERROR_INT,\r
246        EDMA3_0_TC4_ERROR_INT, EDMA3_0_TC5_ERROR_INT,\r
247        EDMA3_0_TC6_ERROR_INT, EDMA3_0_TC7_ERROR_INT,\r
248    }\r
249 };\r
250 \r
251 /**\r
252  * Variables which will be used internally for referring the hardware interrupt\r
253  * for various EDMA3 interrupts.\r
254  */\r
255 unsigned int hwIntXferComp[NUM_EDMA3_INSTANCES] = {\r
256                                                     EDMA3_0_HWI_INT_XFER_COMP\r
257                                                   };\r
258 \r
259 unsigned int hwIntCcErr[NUM_EDMA3_INSTANCES] = {\r
260                                                    EDMA3_0_HWI_INT_CC_ERR\r
261                                                };\r
262 \r
263 unsigned int hwIntTcErr[NUM_EDMA3_INSTANCES][8] = {\r
264                                                      {\r
265                                                         EDMA3_0_HWI_INT_TC0_ERR,\r
266                                                         EDMA3_0_HWI_INT_TC1_ERR,\r
267                                                         EDMA3_0_HWI_INT_TC2_ERR,\r
268                                                         EDMA3_0_HWI_INT_TC3_ERR\r
269                                                      }\r
270                                                };\r
271 \r
272 #define EDMA3_CC_BASE_ADDR                          ((void *)(0x43300000))\r
273 #define EDMA3_TC0_BASE_ADDR                         ((void *)(0x43400000))\r
274 #define EDMA3_TC1_BASE_ADDR                         ((void *)(0x43500000))\r
275 /* Driver Object Initialization Configuration                                 */\r
276 EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =\r
277 {\r
278     {\r
279         /* EDMA3 INSTANCE# 0 */\r
280         /** Total number of DMA Channels supported by the EDMA3 Controller    */\r
281         EDMA3_NUM_DMA_CHANNELS,\r
282         /** Total number of QDMA Channels supported by the EDMA3 Controller   */\r
283         EDMA3_NUM_QDMA_CHANNELS,\r
284         /** Total number of TCCs supported by the EDMA3 Controller            */\r
285         EDMA3_NUM_TCC,\r
286         /** Total number of PaRAM Sets supported by the EDMA3 Controller      */\r
287         EDMA3_NUM_PARAMSET,\r
288         /** Total number of Event Queues in the EDMA3 Controller              */\r
289         EDMA3_0_NUM_EVTQUE,\r
290         /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller*/\r
291         EDMA3_0_NUM_TC,\r
292         /** Number of Regions on this EDMA3 controller                        */\r
293         EDMA3_0_NUM_REGIONS,\r
294 \r
295         /**\r
296          * \brief Channel mapping existence\r
297          * A value of 0 (No channel mapping) implies that there is fixed association\r
298          * for a channel number to a parameter entry number or, in other words,\r
299          * PaRAM entry n corresponds to channel n.\r
300          */\r
301         1u,\r
302 \r
303         /** Existence of memory protection feature */\r
304         0u,\r
305 \r
306         /** Global Register Region of CC Registers */\r
307         EDMA3_CC_BASE_ADDR,\r
308         /** Transfer Controller (TC) Registers */\r
309         {\r
310                 EDMA3_TC0_BASE_ADDR,\r
311                 EDMA3_TC1_BASE_ADDR,\r
312                 (void *)NULL,\r
313                 (void *)NULL,\r
314             (void *)NULL,\r
315             (void *)NULL,\r
316             (void *)NULL,\r
317             (void *)NULL\r
318         },\r
319         /** Interrupt no. for Transfer Completion */\r
320         EDMA3_0_CC_XFER_COMPLETION_INT,\r
321         /** Interrupt no. for CC Error */\r
322         EDMA3_0_CC_ERROR_INT,\r
323         /** Interrupt no. for TCs Error */\r
324         {\r
325             EDMA3_0_TC0_ERROR_INT,\r
326             EDMA3_0_TC1_ERROR_INT,\r
327             EDMA3_0_TC2_ERROR_INT,\r
328             EDMA3_0_TC3_ERROR_INT,\r
329             EDMA3_0_TC4_ERROR_INT,\r
330             EDMA3_0_TC5_ERROR_INT,\r
331             EDMA3_0_TC6_ERROR_INT,\r
332             EDMA3_0_TC7_ERROR_INT\r
333         },\r
334 \r
335         /**\r
336          * \brief EDMA3 TC priority setting\r
337          *\r
338          * User can program the priority of the Event Queues\r
339          * at a system-wide level.  This means that the user can set the\r
340          * priority of an IO initiated by either of the TCs (Transfer Controllers)\r
341          * relative to IO initiated by the other bus masters on the\r
342          * device (ARM, DSP, USB, etc)\r
343          */\r
344         {\r
345             0u,\r
346             1u,\r
347             2u,\r
348             3u,\r
349             0u,\r
350             0u,\r
351             0u,\r
352             0u\r
353         },\r
354         /**\r
355          * \brief To Configure the Threshold level of number of events\r
356          * that can be queued up in the Event queues. EDMA3CC error register\r
357          * (CCERR) will indicate whether or not at any instant of time the\r
358          * number of events queued up in any of the event queues exceeds\r
359          * or equals the threshold/watermark value that is set\r
360          * in the queue watermark threshold register (QWMTHRA).\r
361          */\r
362         {\r
363             16u,\r
364             16u,\r
365             16u,\r
366             16u,\r
367             0u,\r
368             0u,\r
369             0u,\r
370             0u\r
371         },\r
372 \r
373         /**\r
374          * \brief To Configure the Default Burst Size (DBS) of TCs.\r
375          * An optimally-sized command is defined by the transfer controller\r
376          * default burst size (DBS). Different TCs can have different\r
377          * DBS values. It is defined in Bytes.\r
378          */\r
379             {\r
380             16u,\r
381             16u,\r
382             0u,\r
383             0u,\r
384             0u,\r
385             0u,\r
386             0u,\r
387             0u\r
388             },\r
389 \r
390         /**\r
391          * \brief Mapping from each DMA channel to a Parameter RAM set,\r
392          * if it exists, otherwise of no use.\r
393          */\r
394             {\r
395             0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,\r
396             8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,\r
397             16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,\r
398             24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,\r
399             32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u, \r
400             40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,\r
401             48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,\r
402             56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u\r
403             },\r
404 \r
405          /**\r
406           * \brief Mapping from each DMA channel to a TCC. This specific\r
407           * TCC code will be returned when the transfer is completed\r
408           * on the mapped channel.\r
409           */\r
410             {\r
411             0u, 1u, 2u, 3u,\r
412             4u, 5u, 6u, 7u,\r
413             8u, 9u, 10u, 11u,\r
414             12u, 13u, 14u, 15u,\r
415             16u, 17u, 18u, 19u,\r
416             20u, 21u, 22u, 23u,\r
417             24u, 25u, 26u, 27u,\r
418             28u, 29u, 30u, 31u,\r
419             32u, 33u, 34u, 35u,\r
420             36u, 37u, 38u, 39u,\r
421             40u, 41u, 42u, 43u,\r
422             44u, 45u, 46u, 47u,\r
423             48u, 49u, 50u, 51u,\r
424             52u, 53u, 54u, 55u,\r
425             56u, 57u, 58u, 59u,\r
426             60u, 61u, 62u, 63u\r
427             },\r
428 \r
429         /**\r
430          * \brief Mapping of DMA channels to Hardware Events from\r
431          * various peripherals, which use EDMA for data transfer.\r
432          * All channels need not be mapped, some can be free also.\r
433          */\r
434             {\r
435             EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0,\r
436             EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1\r
437             }\r
438         },\r
439 \r
440 };\r
441 \r
442 \r
443 /* Driver Instance Initialization Configuration */\r
444 EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
445 {\r
446     /* EDMA3 INSTANCE# 0 */\r
447                 {\r
448                         /* Resources owned/reserved by region 0 (Associated to any MPU core)*/\r
449                         {\r
450                                 /* ownPaRAMSets */\r
451                                 /* 31     0     63    32     95    64     127   96 */\r
452                                 {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
453                                 /* 159  128     191  160     223  192     255  224 */\r
454                                  0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
455                                 /* 287  256     319  288     351  320     383  352 */\r
456                                  0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
457                                 /* 415  384     447  416     479  448     511  480 */\r
458                                  0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
459 \r
460                                 /* ownDmaChannels */\r
461                                 /* 31     0     63    32 */\r
462                                 {0xFFFFFFFFu, 0xFFFFFFFFu},\r
463 \r
464                                 /* ownQdmaChannels */\r
465                                 /* 31     0 */\r
466                                 {0x000000FFu},\r
467 \r
468                                 /* ownTccs */\r
469                                 /* 31     0     63    32 */\r
470                                 {0xFFFFFFFFu, 0xFFFFFFFFu},\r
471 \r
472                                 /* resvdPaRAMSets */\r
473                                 /* 31     0     63    32     95    64     127   96 */\r
474                                 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
475                                 /* 159  128     191  160     223  192     255  224 */\r
476                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
477                                 /* 287  256     319  288     351  320     383  352 */\r
478                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
479                                 /* 415  384     447  416     479  448     511  480 */\r
480                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
481 \r
482                                 /* resvdDmaChannels */\r
483                                 /* 31     0     63    32 */\r
484                                 {0x00u, 0x00u},\r
485 \r
486                                 /* resvdQdmaChannels */\r
487                                 /* 31     0 */\r
488                                 {0x00u},\r
489 \r
490                                 /* resvdTccs */\r
491                                 /* 31     0     63    32 */\r
492                                 {0x00u, 0x00u},\r
493                         },\r
494 \r
495                         /* Resources owned/reserved by region 1 (Associated to any DSP core) */\r
496                         {\r
497                                 /* ownPaRAMSets */\r
498                                 /* 31     0     63    32     95    64     127   96 */\r
499                                 {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
500                                 /* 159  128     191  160     223  192     255  224 */\r
501                                  0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
502                                 /* 287  256     319  288     351  320     383  352 */\r
503                                  0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
504                                 /* 415  384     447  416     479  448     511  480 */\r
505                                  0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
506 \r
507                                 /* ownDmaChannels */\r
508                                 /* 31     0     63    32 */\r
509                                 {0xFFFFFFFFu, 0xFFFFFFFFu},\r
510 \r
511                                 /* ownQdmaChannels */\r
512                                 /* 31     0 */\r
513                                 {0x000000FFu},\r
514 \r
515                                 /* ownTccs */\r
516                                 /* 31     0     63    32 */\r
517                                 {0xFFFFFFFFu, 0xFFFFFFFFu},\r
518 \r
519                                 /* resvdPaRAMSets */\r
520                                 /* 31     0     63    32     95    64     127   96 */\r
521                                 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
522                                 /* 159  128     191  160     223  192     255  224 */\r
523                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
524                                 /* 287  256     319  288     351  320     383  352 */\r
525                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
526                                 /* 415  384     447  416     479  448     511  480 */\r
527                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
528 \r
529                                 /* resvdDmaChannels */\r
530                                 /* 31     0     63    32 */\r
531                                 {0x00u, 0x00u},\r
532 \r
533                                 /* resvdQdmaChannels */\r
534                                 /* 31     0 */\r
535                                 {0x00u},\r
536 \r
537                                 /* resvdTccs */\r
538                                 /* 31     0     63    32 */\r
539                                 {0x00u, 0x00u},\r
540                         },\r
541 \r
542                 /* Resources owned/reserved by region 2 (Associated to any IPU0 core)*/\r
543                         {\r
544                                 /* ownPaRAMSets */\r
545                                 /* 31     0     63    32     95    64     127   96 */\r
546                                 {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
547                                 /* 159  128     191  160     223  192     255  224 */\r
548                                  0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
549                                 /* 287  256     319  288     351  320     383  352 */\r
550                                  0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
551                                 /* 415  384     447  416     479  448     511  480 */\r
552                                  0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
553 \r
554                                 /* ownDmaChannels */\r
555                                 /* 31     0     63    32 */\r
556                                 {0xFFFFFFFFu, 0xFFFFFFFFu},\r
557 \r
558                                 /* ownQdmaChannels */\r
559                                 /* 31     0 */\r
560                                 {0x000000FFu},\r
561 \r
562                                 /* ownTccs */\r
563                                 /* 31     0     63    32 */\r
564                                 {0xFFFFFFFFu, 0xFFFFFFFFu},\r
565 \r
566                                 /* resvdPaRAMSets */\r
567                                 /* 31     0     63    32     95    64     127   96 */\r
568                                 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
569                                 /* 159  128     191  160     223  192     255  224 */\r
570                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
571                                 /* 287  256     319  288     351  320     383  352 */\r
572                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
573                                 /* 415  384     447  416     479  448     511  480 */\r
574                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
575 \r
576                                 /* resvdDmaChannels */\r
577                                 /* 31     0     63    32 */\r
578                                 {0x00u, 0x00u},\r
579 \r
580                                 /* resvdQdmaChannels */\r
581                                 /* 31     0 */\r
582                                 {0x00u},\r
583 \r
584                                 /* resvdTccs */\r
585                                 /* 31     0     63    32 */\r
586                                 {0x00u, 0x00u},\r
587                         },\r
588 \r
589                 /* Resources owned/reserved by region 3 (Associated to any IPU1 core)*/\r
590                         {\r
591                                 /* ownPaRAMSets */\r
592                                 /* 31     0     63    32     95    64     127   96 */\r
593                                 {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
594                                 /* 159  128     191  160     223  192     255  224 */\r
595                                  0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
596                                 /* 287  256     319  288     351  320     383  352 */\r
597                                  0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
598                                 /* 415  384     447  416     479  448     511  480 */\r
599                                  0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
600 \r
601                                 /* ownDmaChannels */\r
602                                 /* 31     0     63    32 */\r
603                                 {0xFFFFFFFFu, 0xFFFFFFFFu},\r
604 \r
605                                 /* ownQdmaChannels */\r
606                                 /* 31     0 */\r
607                                 {0x000000FFu},\r
608 \r
609                                 /* ownTccs */\r
610                                 /* 31     0     63    32 */\r
611                                 {0xFFFFFFFFu, 0xFFFFFFFFu},\r
612 \r
613                                 /* resvdPaRAMSets */\r
614                                 /* 31     0     63    32     95    64     127   96 */\r
615                                 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
616                                 /* 159  128     191  160     223  192     255  224 */\r
617                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
618                                 /* 287  256     319  288     351  320     383  352 */\r
619                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
620                                 /* 415  384     447  416     479  448     511  480 */\r
621                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
622 \r
623                                 /* resvdDmaChannels */\r
624                                 /* 31     0     63    32 */\r
625                                 {0x00u, 0x00u},\r
626 \r
627                                 /* resvdQdmaChannels */\r
628                                 /* 31     0 */\r
629                                 {0x00u},\r
630 \r
631                                 /* resvdTccs */\r
632                                 /* 31     0     63    32 */\r
633                                 {0x00u, 0x00u},\r
634                         },\r
635 \r
636                 /* Resources owned/reserved by region 4 (Not Associated to any core supported)*/\r
637                         {\r
638                                 /* ownPaRAMSets */\r
639                                 /* 31     0     63    32     95    64     127   96 */\r
640                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
641                                 /* 159  128     191  160     223  192     255  224 */\r
642                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
643                                 /* 287  256     319  288     351  320     383  352 */\r
644                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
645                                 /* 415  384     447  416     479  448     511  480 */\r
646                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
647 \r
648                                 /* ownDmaChannels */\r
649                                 /* 31     0     63    32 */\r
650                                 {0x00000000u, 0x00000000u},\r
651 \r
652                                 /* ownQdmaChannels */\r
653                                 /* 31     0 */\r
654                                 {0x00000000u},\r
655 \r
656                                 /* ownTccs */\r
657                                 /* 31     0     63    32 */\r
658                                 {0x00000000u, 0x00000000u},\r
659 \r
660                                 /* resvdPaRAMSets */\r
661                                 /* 31     0     63    32     95    64     127   96 */\r
662                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
663                                 /* 159  128     191  160     223  192     255  224 */\r
664                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
665                                 /* 287  256     319  288     351  320     383  352 */\r
666                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
667                                 /* 415  384     447  416     479  448     511  480 */\r
668                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
669 \r
670                                 /* resvdDmaChannels */\r
671                                 /* 31     0     63    32 */\r
672                                 {0x00000000u, 0x00000000u},\r
673 \r
674                                 /* resvdQdmaChannels */\r
675                                 /* 31     0 */\r
676                                 {0x00000000u},\r
677 \r
678                                 /* resvdTccs */\r
679                                 /* 31     0     63    32 */\r
680                                 {0x00000000u, 0x00000000u},\r
681                         },\r
682 \r
683                 /* Resources owned/reserved by region 5 (Not Associated to any core supported)*/\r
684                         {\r
685                                 /* ownPaRAMSets */\r
686                                 /* 31     0     63    32     95    64     127   96 */\r
687                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
688                                 /* 159  128     191  160     223  192     255  224 */\r
689                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
690                                 /* 287  256     319  288     351  320     383  352 */\r
691                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
692                                 /* 415  384     447  416     479  448     511  480 */\r
693                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
694 \r
695                                 /* ownDmaChannels */\r
696                                 /* 31     0     63    32 */\r
697                                 {0x00000000u, 0x00000000u},\r
698 \r
699                                 /* ownQdmaChannels */\r
700                                 /* 31     0 */\r
701                                 {0x00000000u},\r
702 \r
703                                 /* ownTccs */\r
704                                 /* 31     0     63    32 */\r
705                                 {0x00000000u, 0x00000000u},\r
706 \r
707                                 /* resvdPaRAMSets */\r
708                                 /* 31     0     63    32     95    64     127   96 */\r
709                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
710                                 /* 159  128     191  160     223  192     255  224 */\r
711                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
712                                 /* 287  256     319  288     351  320     383  352 */\r
713                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
714                                 /* 415  384     447  416     479  448     511  480 */\r
715                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
716 \r
717                                 /* resvdDmaChannels */\r
718                                 /* 31     0     63    32 */\r
719                                 {0x00000000u, 0x00000000u},\r
720 \r
721                                 /* resvdQdmaChannels */\r
722                                 /* 31     0 */\r
723                                 {0x00000000u},\r
724 \r
725                                 /* resvdTccs */\r
726                                 /* 31     0     63    32 */\r
727                                 {0x00000000u, 0x00000000u},\r
728                         },\r
729 \r
730                 /* Resources owned/reserved by region 6 (Not Associated to any core supported)*/\r
731                         {\r
732                                 /* ownPaRAMSets */\r
733                                 /* 31     0     63    32     95    64     127   96 */\r
734                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
735                                 /* 159  128     191  160     223  192     255  224 */\r
736                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
737                                 /* 287  256     319  288     351  320     383  352 */\r
738                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
739                                 /* 415  384     447  416     479  448     511  480 */\r
740                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
741 \r
742                                 /* ownDmaChannels */\r
743                                 /* 31     0     63    32 */\r
744                                 {0x00000000u, 0x00000000u},\r
745 \r
746                                 /* ownQdmaChannels */\r
747                                 /* 31     0 */\r
748                                 {0x00000000u},\r
749 \r
750                                 /* ownTccs */\r
751                                 /* 31     0     63    32 */\r
752                                 {0x00000000u, 0x00000000u},\r
753 \r
754                                 /* resvdPaRAMSets */\r
755                                 /* 31     0     63    32     95    64     127   96 */\r
756                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
757                                 /* 159  128     191  160     223  192     255  224 */\r
758                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
759                                 /* 287  256     319  288     351  320     383  352 */\r
760                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
761                                 /* 415  384     447  416     479  448     511  480 */\r
762                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
763 \r
764                                 /* resvdDmaChannels */\r
765                                 /* 31     0     63    32 */\r
766                                 {0x00000000u, 0x00000000u},\r
767 \r
768                                 /* resvdQdmaChannels */\r
769                                 /* 31     0 */\r
770                                 {0x00000000u},\r
771 \r
772                                 /* resvdTccs */\r
773                                 /* 31     0     63    32 */\r
774                                 {0x00000000u, 0x00000000u},\r
775                         },\r
776 \r
777                 /* Resources owned/reserved by region 7 (Not Associated to any core supported)*/\r
778                         {\r
779                                 /* ownPaRAMSets */\r
780                                 /* 31     0     63    32     95    64     127   96 */\r
781                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
782                                 /* 159  128     191  160     223  192     255  224 */\r
783                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
784                                 /* 287  256     319  288     351  320     383  352 */\r
785                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
786                                 /* 415  384     447  416     479  448     511  480 */\r
787                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
788 \r
789                                 /* ownDmaChannels */\r
790                                 /* 31     0     63    32 */\r
791                                 {0x00000000u, 0x00000000u},\r
792 \r
793                                 /* ownQdmaChannels */\r
794                                 /* 31     0 */\r
795                                 {0x00000000u},\r
796 \r
797                                 /* ownTccs */\r
798                                 /* 31     0     63    32 */\r
799                                 {0x00000000u, 0x00000000u},\r
800 \r
801                                 /* resvdPaRAMSets */\r
802                                 /* 31     0     63    32     95    64     127   96 */\r
803                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
804                                 /* 159  128     191  160     223  192     255  224 */\r
805                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
806                                 /* 287  256     319  288     351  320     383  352 */\r
807                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
808                                 /* 415  384     447  416     479  448     511  480 */\r
809                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
810 \r
811                                 /* resvdDmaChannels */\r
812                                 /* 31     0     63    32 */\r
813                                 {0x00000000u, 0x00000000u},\r
814 \r
815                                 /* resvdQdmaChannels */\r
816                                 /* 31     0 */\r
817                                 {0x00000000u},\r
818 \r
819                                 /* resvdTccs */\r
820                                 /* 31     0     63    32 */\r
821                                 {0x00000000u, 0x00000000u},\r
822         },\r
823     },\r
824 };\r
825 \r
826 /* Driver Instance Cross bar event to channel map Initialization Configuration */\r
827 EDMA3_RM_GblXbarToChanConfigParams sampleXbarChanInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
828 {\r
829     /* EDMA3 INSTANCE# 0 */\r
830     {\r
831         /* Event to channel map for region 0 */\r
832         {\r
833             {-1, -1, -1, -1, -1, -1, -1, -1,\r
834             -1, -1, -1, -1, -1, -1, -1, -1,\r
835             -1, -1, -1, -1, -1, -1, -1, -1,\r
836             -1, -1, -1, -1, -1, -1, -1}\r
837         },\r
838         /* Event to channel map for region 1 */\r
839         {\r
840             {-1, -1, -1, -1, -1, -1, -1, -1,\r
841             -1, -1, -1, -1, -1, -1, -1, -1,\r
842             -1, -1, -1, -1, -1, -1, -1, -1,\r
843             -1, 26, 27, -1, -1, -1, -1}\r
844         },\r
845         /* Event to channel map for region 2 */\r
846         {\r
847             {-1, -1, -1, -1, -1, -1, -1, -1,\r
848             -1, -1, -1, -1, -1, -1, -1, -1,\r
849             -1, -1, -1, -1, -1, -1, -1, -1,\r
850             -1, -1, -1, -1, -1, -1, -1}\r
851         },\r
852         /* Event to channel map for region 3 */\r
853         {\r
854             {-1, -1, -1, -1, -1, -1, -1, -1,\r
855             -1, -1, -1, -1, -1, -1, -1, -1,\r
856             -1, -1, -1, -1, -1, -1, -1, -1,\r
857             -1, -1, -1, -1, -1, -1, -1}\r
858         },\r
859         /* Event to channel map for region 4 */\r
860         {\r
861             {-1, -1, -1, -1, -1, -1, -1, -1,\r
862             -1, -1, -1, -1, -1, -1, -1, -1,\r
863             -1, -1, -1, -1, -1, -1, -1, -1,\r
864             -1, -1, -1, -1, -1, -1, -1}\r
865         },\r
866         /* Event to channel map for region 5 */\r
867         {\r
868             {-1, -1, -1, -1, -1, -1, -1, -1,\r
869             -1, -1, -1, -1, -1, -1, -1, -1,\r
870             -1, -1, -1, -1, -1, -1, -1, -1,\r
871             -1, -1, -1, -1, -1, -1, -1}\r
872         },\r
873         /* Event to channel map for region 6 */\r
874         {\r
875             {-1, -1, -1, -1, -1, -1, -1, -1,\r
876             -1, -1, -1, -1, -1, -1, -1, -1,\r
877             -1, -1, -1, -1, -1, -1, -1, -1,\r
878             -1, -1, -1, -1, -1, -1, -1}\r
879         },\r
880         /* Event to channel map for region 7 */\r
881         {\r
882             {-1, -1, -1, -1, -1, -1, -1, -1,\r
883             -1, -1, -1, -1, -1, -1, -1, -1,\r
884             -1, -1, -1, -1, -1, -1, -1, -1,\r
885             -1, -1, -1, -1, -1, -1, -1}\r
886         },\r
887     }\r
888 };\r
889 \r
890 /* End of File */\r
891 \r