a5551d3109c9d4efe3a256c4bcc3ad1f075a8ef7
[keystone-rtos/edma3_lld.git] / packages / ti / sdo / edma3 / rm / sample / src / platforms / sample_tda2xx_cfg.c
1 /*\r
2  * sample_omapl138_cfg.c\r
3  *\r
4  * Platform specific EDMA3 hardware related information like number of transfer\r
5  * controllers, various interrupt ids etc. It is used while interrupts\r
6  * enabling / disabling. It needs to be ported for different SoCs.\r
7  *\r
8  * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/\r
9  *\r
10  *\r
11  *  Redistribution and use in source and binary forms, with or without\r
12  *  modification, are permitted provided that the following conditions\r
13  *  are met:\r
14  *\r
15  *    Redistributions of source code must retain the above copyright\r
16  *    notice, this list of conditions and the following disclaimer.\r
17  *\r
18  *    Redistributions in binary form must reproduce the above copyright\r
19  *    notice, this list of conditions and the following disclaimer in the\r
20  *    documentation and/or other materials provided with the\r
21  *    distribution.\r
22  *\r
23  *    Neither the name of Texas Instruments Incorporated nor the names of\r
24  *    its contributors may be used to endorse or promote products derived\r
25  *    from this software without specific prior written permission.\r
26  *\r
27  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
28  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
29  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
30  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
31  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
32  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
33  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
34  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
35  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
36  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
37  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
38  *\r
39 */\r
40 \r
41 #include <ti/sdo/edma3/rm/edma3_rm.h>\r
42 \r
43 /* Number of EDMA3 controllers present in the system */\r
44 #define NUM_EDMA3_INSTANCES         1u\r
45 const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;\r
46 \r
47 /* Number of DSPs present in the system */\r
48 #define NUM_DSPS                    1u\r
49 const unsigned int numDsps = NUM_DSPS;\r
50 \r
51 /* Determine the processor id by reading DNUM register. */\r
52 /* Statically allocate the region numbers with cores. */\r
53 int myCoreNum;\r
54 #define PID0_ADDRESS 0xE00FFFE0\r
55 #define CORE_ID_C0 0x0\r
56 #define CORE_ID_C1 0x1\r
57 \r
58 #ifdef BUILD_TDA2XX_MPU\r
59 void __inline readProcFeatureReg(void);\r
60 void __inline readProcFeatureReg(void)\r
61 {\r
62     asm ("    push    {r0-r2} \n\t"\r
63              "    MRC p15, 0, r0, c0, c0, 5\n\t"\r
64                  "    LDR      r1, =myCoreNum\n\t"\r
65                  "    STR      r0, [r1]\n\t"\r
66                  "    pop    {r0-r2}\n\t");\r
67 }\r
68 #endif\r
69 \r
70 signed char*  getGlobalAddr(signed char* addr);\r
71 \r
72 unsigned short isGblConfigRequired(unsigned int dspNum);\r
73 \r
74 unsigned short determineProcId(void);\r
75 \r
76 unsigned short determineProcId(void)\r
77 {\r
78 unsigned short regionNo = (unsigned short)numEdma3Instances;\r
79 #ifdef BUILD_TDA2XX_DSP\r
80 extern __cregister volatile unsigned int DNUM;\r
81 #endif\r
82 myCoreNum = (int)numDsps;\r
83 #ifdef BUILD_TDA2XX_MPU\r
84 \r
85     readProcFeatureReg();\r
86                 regionNo = 0U;\r
87 /* myCoreNum is always 1 here, fix for klocwork error(Unreachable code) */\r
88         if(((unsigned int)myCoreNum & 0x03U) == 1U)\r
89     {\r
90                 regionNo = 1U;\r
91     }\r
92 #elif defined(BUILD_TDA2XX_IPU)\r
93 myCoreNum = (*(unsigned int *)(PID0_ADDRESS));\r
94 if(Core_getIpuId() == 1){\r
95         if(myCoreNum == CORE_ID_C0)\r
96                 regionNo = 4;\r
97         else if (myCoreNum == CORE_ID_C1)\r
98                 regionNo = 5;\r
99 }\r
100 if(Core_getIpuId() == 2){\r
101         if(myCoreNum == CORE_ID_C0)\r
102                 regionNo = 6;\r
103         else if (myCoreNum == CORE_ID_C1)\r
104                 regionNo = 7;\r
105 }\r
106 #elif defined BUILD_TDA2XX_DSP\r
107         myCoreNum = DNUM;\r
108         if(myCoreNum == 0)\r
109                 regionNo = 2;\r
110         else\r
111                 regionNo = 3;\r
112 #endif\r
113         return regionNo;\r
114 }\r
115 \r
116 signed char*  getGlobalAddr(signed char* addr)\r
117 {\r
118      return (addr); /* The address is already a global address */\r
119 }\r
120 unsigned short isGblConfigRequired(unsigned int dspNum)\r
121 {\r
122     (void) dspNum;\r
123 \r
124     return 1U;\r
125 }\r
126 \r
127 /* Semaphore handles */\r
128 EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};\r
129 \r
130 /** Number of PaRAM Sets available                                            */\r
131 #define EDMA3_NUM_PARAMSET                              (512u)\r
132 \r
133 /** Number of TCCS available                                                  */\r
134 #define EDMA3_NUM_TCC                                   (64u)\r
135 \r
136 /** Number of DMA Channels available                                          */\r
137 #define EDMA3_NUM_DMA_CHANNELS                          (64u)\r
138 \r
139 /** Number of QDMA Channels available                                         */\r
140 #define EDMA3_NUM_QDMA_CHANNELS                         (8u)\r
141 \r
142 /** Number of Event Queues available                                          */\r
143 #define EDMA3_0_NUM_EVTQUE                              (4u)\r
144 \r
145 /** Number of Transfer Controllers available                                  */\r
146 #define EDMA3_0_NUM_TC                                  (4u)\r
147 \r
148 /** Number of Regions                                                         */\r
149 #define EDMA3_0_NUM_REGIONS                             (2u)\r
150 \r
151 \r
152 /** Interrupt no. for Transfer Completion                                     */\r
153 #define EDMA3_0_CC_XFER_COMPLETION_INT                  (34u)\r
154 /** Interrupt no. for CC Error                                                */\r
155 #define EDMA3_0_CC_ERROR_INT                            (35u)\r
156 /** Interrupt no. for TCs Error                                               */\r
157 #define EDMA3_0_TC0_ERROR_INT                           (36u)\r
158 #define EDMA3_0_TC1_ERROR_INT                           (37u)\r
159 #define EDMA3_0_TC2_ERROR_INT                           (0u)\r
160 #define EDMA3_0_TC3_ERROR_INT                           (0u)\r
161 #define EDMA3_0_TC4_ERROR_INT                           (0u)\r
162 #define EDMA3_0_TC5_ERROR_INT                           (0u)\r
163 #define EDMA3_0_TC6_ERROR_INT                           (0u)\r
164 #define EDMA3_0_TC7_ERROR_INT                           (0u)\r
165 \r
166 /**\r
167  * EDMA3 interrupts (transfer completion, CC error etc.) correspond to different\r
168  * ECM events (SoC specific). These ECM events come\r
169  * under ECM block XXX (handling those specific ECM events). Normally, block\r
170  * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events\r
171  * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)\r
172  * is mapped to a specific HWI_INT YYY in the tcf file.\r
173  * Define EDMA3_HWI_INT_XFER_COMP to specific HWI_INT, corresponding\r
174  * to transfer completion interrupt.\r
175  * Define EDMA3_HWI_INT_CC_ERR to specific HWI_INT, corresponding\r
176  * to CC error interrupts.\r
177  * Define EDMA3_HWI_INT_TC_ERR to specific HWI_INT, corresponding\r
178  * to TC error interrupts.\r
179  */\r
180 /* EDMA 0 */\r
181 \r
182 #define EDMA3_0_HWI_INT_XFER_COMP                           (7u)\r
183 #define EDMA3_0_HWI_INT_CC_ERR                              (7u)\r
184 #define EDMA3_0_HWI_INT_TC0_ERR                             (7u)\r
185 #define EDMA3_0_HWI_INT_TC1_ERR                             (7u)\r
186 #define EDMA3_0_HWI_INT_TC2_ERR                             (7u)\r
187 #define EDMA3_0_HWI_INT_TC3_ERR                             (7u)\r
188 \r
189 \r
190 /**\r
191  * \brief Mapping of DMA channels 0-31 to Hardware Events from\r
192  * various peripherals, which use EDMA for data transfer.\r
193  * All channels need not be mapped, some can be free also.\r
194  * 1: Mapped\r
195  * 0: Not mapped\r
196  *\r
197  * This mapping will be used to allocate DMA channels when user passes\r
198  * EDMA3_RM_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory\r
199  * copy). The same mapping is used to allocate the TCC when user passes\r
200  * EDMA3_RM_TCC_ANY as tcc id (for eg to do memory-to-memory copy).\r
201  *\r
202  * To allocate more DMA channels or TCCs, one has to modify the event mapping.\r
203  */\r
204                                                       /* 31     0 */\r
205 #define EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0       (0x3FC0C06Eu)  /* TBD */\r
206 \r
207 \r
208 /**\r
209  * \brief Mapping of DMA channels 32-63 to Hardware Events from\r
210  * various peripherals, which use EDMA for data transfer.\r
211  * All channels need not be mapped, some can be free also.\r
212  * 1: Mapped\r
213  * 0: Not mapped\r
214  *\r
215  * This mapping will be used to allocate DMA channels when user passes\r
216  * EDMA3_RM_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory\r
217  * copy). The same mapping is used to allocate the TCC when user passes\r
218  * EDMA3_RM_TCC_ANY as tcc id (for eg to do memory-to-memory copy).\r
219  *\r
220  * To allocate more DMA channels or TCCs, one has to modify the event mapping.\r
221  */\r
222 #define EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1       (0xF3FFFFFCu) /* TBD */\r
223 \r
224 \r
225 /* Variable which will be used internally for referring number of Event Queues*/\r
226 unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] =  {\r
227                                                         EDMA3_0_NUM_EVTQUE,\r
228                                                     };\r
229 \r
230 /* Variable which will be used internally for referring number of TCs.        */\r
231 unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] =  {\r
232                                                     EDMA3_0_NUM_TC,\r
233                                                 };\r
234 \r
235 /**\r
236  * Variable which will be used internally for referring transfer completion\r
237  * interrupt.\r
238  */\r
239 unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
240 {\r
241     {\r
242         0u, EDMA3_0_CC_XFER_COMPLETION_INT, 0u, 0u, 0u, 0u, 0u, 0u,\r
243     },\r
244 };\r
245 \r
246 /**\r
247  * Variable which will be used internally for referring channel controller's\r
248  * error interrupt.\r
249  */\r
250 unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {\r
251                                                     EDMA3_0_CC_ERROR_INT,\r
252                                                };\r
253 \r
254 /**\r
255  * Variable which will be used internally for referring transfer controllers'\r
256  * error interrupts.\r
257  */\r
258 unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][8] =\r
259 {\r
260    {\r
261        EDMA3_0_TC0_ERROR_INT, EDMA3_0_TC1_ERROR_INT,\r
262        EDMA3_0_TC2_ERROR_INT, EDMA3_0_TC3_ERROR_INT,\r
263        EDMA3_0_TC4_ERROR_INT, EDMA3_0_TC5_ERROR_INT,\r
264        EDMA3_0_TC6_ERROR_INT, EDMA3_0_TC7_ERROR_INT,\r
265    }\r
266 };\r
267 \r
268 /**\r
269  * Variables which will be used internally for referring the hardware interrupt\r
270  * for various EDMA3 interrupts.\r
271  */\r
272 unsigned int hwIntXferComp[NUM_EDMA3_INSTANCES] = {\r
273                                                     EDMA3_0_HWI_INT_XFER_COMP\r
274                                                   };\r
275 \r
276 unsigned int hwIntCcErr[NUM_EDMA3_INSTANCES] = {\r
277                                                    EDMA3_0_HWI_INT_CC_ERR\r
278                                                };\r
279 \r
280 unsigned int hwIntTcErr[NUM_EDMA3_INSTANCES][8] = {\r
281                                                      {\r
282                                                         EDMA3_0_HWI_INT_TC0_ERR,\r
283                                                         EDMA3_0_HWI_INT_TC1_ERR,\r
284                                                         EDMA3_0_HWI_INT_TC2_ERR,\r
285                                                         EDMA3_0_HWI_INT_TC3_ERR,\r
286                                                         0U,\r
287                                                         0U,\r
288                                                         0U,\r
289                                                         0U\r
290                                                      }\r
291                                                };\r
292 \r
293 #define EDMA3_CC_BASE_ADDR                          ((void *)(0x43300000))\r
294 #define EDMA3_TC0_BASE_ADDR                         ((void *)(0x43400000))\r
295 #define EDMA3_TC1_BASE_ADDR                         ((void *)(0x43500000))\r
296 /* Driver Object Initialization Configuration                                 */\r
297 EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =\r
298 {\r
299     {\r
300         /* EDMA3 INSTANCE# 0 */\r
301         /** Total number of DMA Channels supported by the EDMA3 Controller    */\r
302         EDMA3_NUM_DMA_CHANNELS,\r
303         /** Total number of QDMA Channels supported by the EDMA3 Controller   */\r
304         EDMA3_NUM_QDMA_CHANNELS,\r
305         /** Total number of TCCs supported by the EDMA3 Controller            */\r
306         EDMA3_NUM_TCC,\r
307         /** Total number of PaRAM Sets supported by the EDMA3 Controller      */\r
308         EDMA3_NUM_PARAMSET,\r
309         /** Total number of Event Queues in the EDMA3 Controller              */\r
310         EDMA3_0_NUM_EVTQUE,\r
311         /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller*/\r
312         EDMA3_0_NUM_TC,\r
313         /** Number of Regions on this EDMA3 controller                        */\r
314         EDMA3_0_NUM_REGIONS,\r
315 \r
316         /**\r
317          * \brief Channel mapping existence\r
318          * A value of 0 (No channel mapping) implies that there is fixed association\r
319          * for a channel number to a parameter entry number or, in other words,\r
320          * PaRAM entry n corresponds to channel n.\r
321          */\r
322         1u,\r
323 \r
324         /** Existence of memory protection feature */\r
325         0u,\r
326 \r
327         /** Global Register Region of CC Registers */\r
328         EDMA3_CC_BASE_ADDR,\r
329         /** Transfer Controller (TC) Registers */\r
330         {\r
331                 EDMA3_TC0_BASE_ADDR,\r
332                 EDMA3_TC1_BASE_ADDR,\r
333                 (void *)NULL,\r
334                 (void *)NULL,\r
335             (void *)NULL,\r
336             (void *)NULL,\r
337             (void *)NULL,\r
338             (void *)NULL\r
339         },\r
340         /** Interrupt no. for Transfer Completion */\r
341         EDMA3_0_CC_XFER_COMPLETION_INT,\r
342         /** Interrupt no. for CC Error */\r
343         EDMA3_0_CC_ERROR_INT,\r
344         /** Interrupt no. for TCs Error */\r
345         {\r
346             EDMA3_0_TC0_ERROR_INT,\r
347             EDMA3_0_TC1_ERROR_INT,\r
348             EDMA3_0_TC2_ERROR_INT,\r
349             EDMA3_0_TC3_ERROR_INT,\r
350             EDMA3_0_TC4_ERROR_INT,\r
351             EDMA3_0_TC5_ERROR_INT,\r
352             EDMA3_0_TC6_ERROR_INT,\r
353             EDMA3_0_TC7_ERROR_INT\r
354         },\r
355 \r
356         /**\r
357          * \brief EDMA3 TC priority setting\r
358          *\r
359          * User can program the priority of the Event Queues\r
360          * at a system-wide level.  This means that the user can set the\r
361          * priority of an IO initiated by either of the TCs (Transfer Controllers)\r
362          * relative to IO initiated by the other bus masters on the\r
363          * device (ARM, DSP, USB, etc)\r
364          */\r
365         {\r
366             0u,\r
367             1u,\r
368             2u,\r
369             3u,\r
370             0u,\r
371             0u,\r
372             0u,\r
373             0u\r
374         },\r
375         /**\r
376          * \brief To Configure the Threshold level of number of events\r
377          * that can be queued up in the Event queues. EDMA3CC error register\r
378          * (CCERR) will indicate whether or not at any instant of time the\r
379          * number of events queued up in any of the event queues exceeds\r
380          * or equals the threshold/watermark value that is set\r
381          * in the queue watermark threshold register (QWMTHRA).\r
382          */\r
383         {\r
384             16u,\r
385             16u,\r
386             16u,\r
387             16u,\r
388             0u,\r
389             0u,\r
390             0u,\r
391             0u\r
392         },\r
393 \r
394         /**\r
395          * \brief To Configure the Default Burst Size (DBS) of TCs.\r
396          * An optimally-sized command is defined by the transfer controller\r
397          * default burst size (DBS). Different TCs can have different\r
398          * DBS values. It is defined in Bytes.\r
399          */\r
400             {\r
401             16u,\r
402             16u,\r
403             0u,\r
404             0u,\r
405             0u,\r
406             0u,\r
407             0u,\r
408             0u\r
409             },\r
410 \r
411         /**\r
412          * \brief Mapping from each DMA channel to a Parameter RAM set,\r
413          * if it exists, otherwise of no use.\r
414          */\r
415             {\r
416             0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,\r
417             8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,\r
418             16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,\r
419             24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,\r
420             32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u, \r
421             40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,\r
422             48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,\r
423             56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u\r
424             },\r
425 \r
426          /**\r
427           * \brief Mapping from each DMA channel to a TCC. This specific\r
428           * TCC code will be returned when the transfer is completed\r
429           * on the mapped channel.\r
430           */\r
431             {\r
432             0u, 1u, 2u, 3u,\r
433             4u, 5u, 6u, 7u,\r
434             8u, 9u, 10u, 11u,\r
435             12u, 13u, 14u, 15u,\r
436             16u, 17u, 18u, 19u,\r
437             20u, 21u, 22u, 23u,\r
438             24u, 25u, 26u, 27u,\r
439             28u, 29u, 30u, 31u,\r
440             32u, 33u, 34u, 35u,\r
441             36u, 37u, 38u, 39u,\r
442             40u, 41u, 42u, 43u,\r
443             44u, 45u, 46u, 47u,\r
444             48u, 49u, 50u, 51u,\r
445             52u, 53u, 54u, 55u,\r
446             56u, 57u, 58u, 59u,\r
447             60u, 61u, 62u, 63u\r
448             },\r
449 \r
450         /**\r
451          * \brief Mapping of DMA channels to Hardware Events from\r
452          * various peripherals, which use EDMA for data transfer.\r
453          * All channels need not be mapped, some can be free also.\r
454          */\r
455             {\r
456             EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0,\r
457             EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1\r
458             }\r
459         },\r
460 \r
461 };\r
462 \r
463 \r
464 /* Driver Instance Initialization Configuration */\r
465 EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
466 {\r
467     /* EDMA3 INSTANCE# 0 */\r
468                 {\r
469                         /* Resources owned/reserved by region 0 (Associated to any MPU core)*/\r
470                         {\r
471                                 /* ownPaRAMSets */\r
472                                 /* 31     0     63    32     95    64     127   96 */\r
473                                 {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
474                                 /* 159  128     191  160     223  192     255  224 */\r
475                                  0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
476                                 /* 287  256     319  288     351  320     383  352 */\r
477                                  0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
478                                 /* 415  384     447  416     479  448     511  480 */\r
479                                  0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
480 \r
481                                 /* ownDmaChannels */\r
482                                 /* 31     0     63    32 */\r
483                                 {0xFFFFFFFFu, 0xFFFFFFFFu},\r
484 \r
485                                 /* ownQdmaChannels */\r
486                                 /* 31     0 */\r
487                                 {0x000000FFu},\r
488 \r
489                                 /* ownTccs */\r
490                                 /* 31     0     63    32 */\r
491                                 {0xFFFFFFFFu, 0xFFFFFFFFu},\r
492 \r
493                                 /* resvdPaRAMSets */\r
494                                 /* 31     0     63    32     95    64     127   96 */\r
495                                 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
496                                 /* 159  128     191  160     223  192     255  224 */\r
497                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
498                                 /* 287  256     319  288     351  320     383  352 */\r
499                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
500                                 /* 415  384     447  416     479  448     511  480 */\r
501                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
502 \r
503                                 /* resvdDmaChannels */\r
504                                 /* 31     0     63    32 */\r
505                                 {0x00u, 0x00u},\r
506 \r
507                                 /* resvdQdmaChannels */\r
508                                 /* 31     0 */\r
509                                 {0x00u},\r
510 \r
511                                 /* resvdTccs */\r
512                                 /* 31     0     63    32 */\r
513                                 {0x00u, 0x00u},\r
514                         },\r
515 \r
516                         /* Resources owned/reserved by region 1 (Associated to any DSP core) */\r
517                         {\r
518                                 /* ownPaRAMSets */\r
519                                 /* 31     0     63    32     95    64     127   96 */\r
520                                 {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
521                                 /* 159  128     191  160     223  192     255  224 */\r
522                                  0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
523                                 /* 287  256     319  288     351  320     383  352 */\r
524                                  0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
525                                 /* 415  384     447  416     479  448     511  480 */\r
526                                  0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
527 \r
528                                 /* ownDmaChannels */\r
529                                 /* 31     0     63    32 */\r
530                                 {0xFFFFFFFFu, 0xFFFFFFFFu},\r
531 \r
532                                 /* ownQdmaChannels */\r
533                                 /* 31     0 */\r
534                                 {0x000000FFu},\r
535 \r
536                                 /* ownTccs */\r
537                                 /* 31     0     63    32 */\r
538                                 {0xFFFFFFFFu, 0xFFFFFFFFu},\r
539 \r
540                                 /* resvdPaRAMSets */\r
541                                 /* 31     0     63    32     95    64     127   96 */\r
542                                 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
543                                 /* 159  128     191  160     223  192     255  224 */\r
544                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
545                                 /* 287  256     319  288     351  320     383  352 */\r
546                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
547                                 /* 415  384     447  416     479  448     511  480 */\r
548                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
549 \r
550                                 /* resvdDmaChannels */\r
551                                 /* 31     0     63    32 */\r
552                                 {0x00u, 0x00u},\r
553 \r
554                                 /* resvdQdmaChannels */\r
555                                 /* 31     0 */\r
556                                 {0x00u},\r
557 \r
558                                 /* resvdTccs */\r
559                                 /* 31     0     63    32 */\r
560                                 {0x00u, 0x00u},\r
561                         },\r
562 \r
563                 /* Resources owned/reserved by region 2 (Associated to any IPU0 core)*/\r
564                         {\r
565                                 /* ownPaRAMSets */\r
566                                 /* 31     0     63    32     95    64     127   96 */\r
567                                 {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
568                                 /* 159  128     191  160     223  192     255  224 */\r
569                                  0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
570                                 /* 287  256     319  288     351  320     383  352 */\r
571                                  0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
572                                 /* 415  384     447  416     479  448     511  480 */\r
573                                  0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
574 \r
575                                 /* ownDmaChannels */\r
576                                 /* 31     0     63    32 */\r
577                                 {0xFFFFFFFFu, 0xFFFFFFFFu},\r
578 \r
579                                 /* ownQdmaChannels */\r
580                                 /* 31     0 */\r
581                                 {0x000000FFu},\r
582 \r
583                                 /* ownTccs */\r
584                                 /* 31     0     63    32 */\r
585                                 {0xFFFFFFFFu, 0xFFFFFFFFu},\r
586 \r
587                                 /* resvdPaRAMSets */\r
588                                 /* 31     0     63    32     95    64     127   96 */\r
589                                 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
590                                 /* 159  128     191  160     223  192     255  224 */\r
591                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
592                                 /* 287  256     319  288     351  320     383  352 */\r
593                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
594                                 /* 415  384     447  416     479  448     511  480 */\r
595                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
596 \r
597                                 /* resvdDmaChannels */\r
598                                 /* 31     0     63    32 */\r
599                                 {0x00u, 0x00u},\r
600 \r
601                                 /* resvdQdmaChannels */\r
602                                 /* 31     0 */\r
603                                 {0x00u},\r
604 \r
605                                 /* resvdTccs */\r
606                                 /* 31     0     63    32 */\r
607                                 {0x00u, 0x00u},\r
608                         },\r
609 \r
610                 /* Resources owned/reserved by region 3 (Associated to any IPU1 core)*/\r
611                         {\r
612                                 /* ownPaRAMSets */\r
613                                 /* 31     0     63    32     95    64     127   96 */\r
614                                 {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
615                                 /* 159  128     191  160     223  192     255  224 */\r
616                                  0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
617                                 /* 287  256     319  288     351  320     383  352 */\r
618                                  0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
619                                 /* 415  384     447  416     479  448     511  480 */\r
620                                  0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
621 \r
622                                 /* ownDmaChannels */\r
623                                 /* 31     0     63    32 */\r
624                                 {0xFFFFFFFFu, 0xFFFFFFFFu},\r
625 \r
626                                 /* ownQdmaChannels */\r
627                                 /* 31     0 */\r
628                                 {0x000000FFu},\r
629 \r
630                                 /* ownTccs */\r
631                                 /* 31     0     63    32 */\r
632                                 {0xFFFFFFFFu, 0xFFFFFFFFu},\r
633 \r
634                                 /* resvdPaRAMSets */\r
635                                 /* 31     0     63    32     95    64     127   96 */\r
636                                 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
637                                 /* 159  128     191  160     223  192     255  224 */\r
638                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
639                                 /* 287  256     319  288     351  320     383  352 */\r
640                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
641                                 /* 415  384     447  416     479  448     511  480 */\r
642                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
643 \r
644                                 /* resvdDmaChannels */\r
645                                 /* 31     0     63    32 */\r
646                                 {0x00u, 0x00u},\r
647 \r
648                                 /* resvdQdmaChannels */\r
649                                 /* 31     0 */\r
650                                 {0x00u},\r
651 \r
652                                 /* resvdTccs */\r
653                                 /* 31     0     63    32 */\r
654                                 {0x00u, 0x00u},\r
655                         },\r
656 \r
657                 /* Resources owned/reserved by region 4 (Not Associated to any core supported)*/\r
658                         {\r
659                                 /* ownPaRAMSets */\r
660                                 /* 31     0     63    32     95    64     127   96 */\r
661                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
662                                 /* 159  128     191  160     223  192     255  224 */\r
663                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
664                                 /* 287  256     319  288     351  320     383  352 */\r
665                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
666                                 /* 415  384     447  416     479  448     511  480 */\r
667                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
668 \r
669                                 /* ownDmaChannels */\r
670                                 /* 31     0     63    32 */\r
671                                 {0x00000000u, 0x00000000u},\r
672 \r
673                                 /* ownQdmaChannels */\r
674                                 /* 31     0 */\r
675                                 {0x00000000u},\r
676 \r
677                                 /* ownTccs */\r
678                                 /* 31     0     63    32 */\r
679                                 {0x00000000u, 0x00000000u},\r
680 \r
681                                 /* resvdPaRAMSets */\r
682                                 /* 31     0     63    32     95    64     127   96 */\r
683                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
684                                 /* 159  128     191  160     223  192     255  224 */\r
685                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
686                                 /* 287  256     319  288     351  320     383  352 */\r
687                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
688                                 /* 415  384     447  416     479  448     511  480 */\r
689                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
690 \r
691                                 /* resvdDmaChannels */\r
692                                 /* 31     0     63    32 */\r
693                                 {0x00000000u, 0x00000000u},\r
694 \r
695                                 /* resvdQdmaChannels */\r
696                                 /* 31     0 */\r
697                                 {0x00000000u},\r
698 \r
699                                 /* resvdTccs */\r
700                                 /* 31     0     63    32 */\r
701                                 {0x00000000u, 0x00000000u},\r
702                         },\r
703 \r
704                 /* Resources owned/reserved by region 5 (Not Associated to any core supported)*/\r
705                         {\r
706                                 /* ownPaRAMSets */\r
707                                 /* 31     0     63    32     95    64     127   96 */\r
708                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
709                                 /* 159  128     191  160     223  192     255  224 */\r
710                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
711                                 /* 287  256     319  288     351  320     383  352 */\r
712                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
713                                 /* 415  384     447  416     479  448     511  480 */\r
714                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
715 \r
716                                 /* ownDmaChannels */\r
717                                 /* 31     0     63    32 */\r
718                                 {0x00000000u, 0x00000000u},\r
719 \r
720                                 /* ownQdmaChannels */\r
721                                 /* 31     0 */\r
722                                 {0x00000000u},\r
723 \r
724                                 /* ownTccs */\r
725                                 /* 31     0     63    32 */\r
726                                 {0x00000000u, 0x00000000u},\r
727 \r
728                                 /* resvdPaRAMSets */\r
729                                 /* 31     0     63    32     95    64     127   96 */\r
730                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
731                                 /* 159  128     191  160     223  192     255  224 */\r
732                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
733                                 /* 287  256     319  288     351  320     383  352 */\r
734                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
735                                 /* 415  384     447  416     479  448     511  480 */\r
736                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
737 \r
738                                 /* resvdDmaChannels */\r
739                                 /* 31     0     63    32 */\r
740                                 {0x00000000u, 0x00000000u},\r
741 \r
742                                 /* resvdQdmaChannels */\r
743                                 /* 31     0 */\r
744                                 {0x00000000u},\r
745 \r
746                                 /* resvdTccs */\r
747                                 /* 31     0     63    32 */\r
748                                 {0x00000000u, 0x00000000u},\r
749                         },\r
750 \r
751                 /* Resources owned/reserved by region 6 (Not Associated to any core supported)*/\r
752                         {\r
753                                 /* ownPaRAMSets */\r
754                                 /* 31     0     63    32     95    64     127   96 */\r
755                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
756                                 /* 159  128     191  160     223  192     255  224 */\r
757                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
758                                 /* 287  256     319  288     351  320     383  352 */\r
759                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
760                                 /* 415  384     447  416     479  448     511  480 */\r
761                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
762 \r
763                                 /* ownDmaChannels */\r
764                                 /* 31     0     63    32 */\r
765                                 {0x00000000u, 0x00000000u},\r
766 \r
767                                 /* ownQdmaChannels */\r
768                                 /* 31     0 */\r
769                                 {0x00000000u},\r
770 \r
771                                 /* ownTccs */\r
772                                 /* 31     0     63    32 */\r
773                                 {0x00000000u, 0x00000000u},\r
774 \r
775                                 /* resvdPaRAMSets */\r
776                                 /* 31     0     63    32     95    64     127   96 */\r
777                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
778                                 /* 159  128     191  160     223  192     255  224 */\r
779                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
780                                 /* 287  256     319  288     351  320     383  352 */\r
781                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
782                                 /* 415  384     447  416     479  448     511  480 */\r
783                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
784 \r
785                                 /* resvdDmaChannels */\r
786                                 /* 31     0     63    32 */\r
787                                 {0x00000000u, 0x00000000u},\r
788 \r
789                                 /* resvdQdmaChannels */\r
790                                 /* 31     0 */\r
791                                 {0x00000000u},\r
792 \r
793                                 /* resvdTccs */\r
794                                 /* 31     0     63    32 */\r
795                                 {0x00000000u, 0x00000000u},\r
796                         },\r
797 \r
798                 /* Resources owned/reserved by region 7 (Not Associated to any core supported)*/\r
799                         {\r
800                                 /* ownPaRAMSets */\r
801                                 /* 31     0     63    32     95    64     127   96 */\r
802                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
803                                 /* 159  128     191  160     223  192     255  224 */\r
804                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
805                                 /* 287  256     319  288     351  320     383  352 */\r
806                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
807                                 /* 415  384     447  416     479  448     511  480 */\r
808                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
809 \r
810                                 /* ownDmaChannels */\r
811                                 /* 31     0     63    32 */\r
812                                 {0x00000000u, 0x00000000u},\r
813 \r
814                                 /* ownQdmaChannels */\r
815                                 /* 31     0 */\r
816                                 {0x00000000u},\r
817 \r
818                                 /* ownTccs */\r
819                                 /* 31     0     63    32 */\r
820                                 {0x00000000u, 0x00000000u},\r
821 \r
822                                 /* resvdPaRAMSets */\r
823                                 /* 31     0     63    32     95    64     127   96 */\r
824                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
825                                 /* 159  128     191  160     223  192     255  224 */\r
826                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
827                                 /* 287  256     319  288     351  320     383  352 */\r
828                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
829                                 /* 415  384     447  416     479  448     511  480 */\r
830                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
831 \r
832                                 /* resvdDmaChannels */\r
833                                 /* 31     0     63    32 */\r
834                                 {0x00000000u, 0x00000000u},\r
835 \r
836                                 /* resvdQdmaChannels */\r
837                                 /* 31     0 */\r
838                                 {0x00000000u},\r
839 \r
840                                 /* resvdTccs */\r
841                                 /* 31     0     63    32 */\r
842                                 {0x00000000u, 0x00000000u},\r
843         },\r
844     },\r
845 };\r
846 \r
847 /* Driver Instance Cross bar event to channel map Initialization Configuration */\r
848 EDMA3_RM_GblXbarToChanConfigParams sampleXbarChanInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
849 {\r
850     /* EDMA3 INSTANCE# 0 */\r
851     {\r
852         /* Event to channel map for region 0 */\r
853         {\r
854             {-1, -1, -1, -1, -1, -1, -1, -1,\r
855             -1, -1, -1, -1, -1, -1, -1, -1,\r
856             -1, -1, -1, -1, -1, -1, -1, -1,\r
857             -1, -1, -1, -1, -1, -1, -1}\r
858         },\r
859         /* Event to channel map for region 1 */\r
860         {\r
861             {-1, -1, -1, -1, -1, -1, -1, -1,\r
862             -1, -1, -1, -1, -1, -1, -1, -1,\r
863             -1, -1, -1, -1, -1, -1, -1, -1,\r
864             -1, 26, 27, -1, -1, -1, -1}\r
865         },\r
866         /* Event to channel map for region 2 */\r
867         {\r
868             {-1, -1, -1, -1, -1, -1, -1, -1,\r
869             -1, -1, -1, -1, -1, -1, -1, -1,\r
870             -1, -1, -1, -1, -1, -1, -1, -1,\r
871             -1, -1, -1, -1, -1, -1, -1}\r
872         },\r
873         /* Event to channel map for region 3 */\r
874         {\r
875             {-1, -1, -1, -1, -1, -1, -1, -1,\r
876             -1, -1, -1, -1, -1, -1, -1, -1,\r
877             -1, -1, -1, -1, -1, -1, -1, -1,\r
878             -1, -1, -1, -1, -1, -1, -1}\r
879         },\r
880         /* Event to channel map for region 4 */\r
881         {\r
882             {-1, -1, -1, -1, -1, -1, -1, -1,\r
883             -1, -1, -1, -1, -1, -1, -1, -1,\r
884             -1, -1, -1, -1, -1, -1, -1, -1,\r
885             -1, -1, -1, -1, -1, -1, -1}\r
886         },\r
887         /* Event to channel map for region 5 */\r
888         {\r
889             {-1, -1, -1, -1, -1, -1, -1, -1,\r
890             -1, -1, -1, -1, -1, -1, -1, -1,\r
891             -1, -1, -1, -1, -1, -1, -1, -1,\r
892             -1, -1, -1, -1, -1, -1, -1}\r
893         },\r
894         /* Event to channel map for region 6 */\r
895         {\r
896             {-1, -1, -1, -1, -1, -1, -1, -1,\r
897             -1, -1, -1, -1, -1, -1, -1, -1,\r
898             -1, -1, -1, -1, -1, -1, -1, -1,\r
899             -1, -1, -1, -1, -1, -1, -1}\r
900         },\r
901         /* Event to channel map for region 7 */\r
902         {\r
903             {-1, -1, -1, -1, -1, -1, -1, -1,\r
904             -1, -1, -1, -1, -1, -1, -1, -1,\r
905             -1, -1, -1, -1, -1, -1, -1, -1,\r
906             -1, -1, -1, -1, -1, -1, -1}\r
907         },\r
908     }\r
909 };\r
910 \r
911 /* End of File */\r
912 \r