[keystone-rtos/edma3_lld.git] / packages / ti / sdo / edma3 / rm / sample / src / platforms / sample_tda3xx_cfg.c
1 /*
2 * sample_tda3xx_cfg.c
3 *
4 * Platform specific EDMA3 hardware related information like number of transfer
5 * controllers, various interrupt ids etc. It is used while interrupts
6 * enabling / disabling. It needs to be ported for different SoCs.
7 *
8 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
9 *
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 *
18 * Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the
21 * distribution.
22 *
23 * Neither the name of Texas Instruments Incorporated nor the names of
24 * its contributors may be used to endorse or promote products derived
25 * from this software without specific prior written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 *
39 */
41 #include <ti/sdo/edma3/rm/edma3_rm.h>
42 #ifdef BUILD_TDA3XX_IPU
43 #include <ti/sysbios/family/arm/ducati/Core.h>
45 #endif
46 /* Number of EDMA3 controllers present in the system */
47 #define NUM_EDMA3_INSTANCES 3U
48 const uint32_t numEdma3Instances = NUM_EDMA3_INSTANCES;
50 /* Number of DSPs present in the system */
51 #define NUM_DSPS 1U
52 const uint32_t numDsps = NUM_DSPS;
54 /* Determine the processor id by reading DNUM register. */
55 /* Statically allocate the region numbers with cores. */
56 int32_t myCoreNum;
57 #define PID0_ADDRESS 0xE00FFFE0U
58 #define CORE_ID_C0 0x0
59 #define CORE_ID_C1 0x1
61 int8_t* getGlobalAddr(int8_t* addr);
63 uint16_t isGblConfigRequired(uint32_t dspNum);
65 uint16_t determineProcId(void);
67 uint16_t determineProcId(void)
68 {
69 uint16_t regionNo = (uint16_t)numEdma3Instances;
70 #ifdef BUILD_TDA3XX_DSP
71 extern __cregister volatile uint32_t DNUM;
72 #endif
73 myCoreNum = (int32_t)numDsps;
75 #ifdef BUILD_TDA3XX_IPU
76 myCoreNum = (*(volatile uint32_t *)(PID0_ADDRESS));
77 if(Core_getIpuId() == 1){
78 if(myCoreNum == CORE_ID_C0)
79 {
80 regionNo = 4U;
81 }
82 else if (myCoreNum == CORE_ID_C1)
83 {
84 regionNo = 5U;
85 }
86 else
87 {
88 /* Nothing to be done here */
89 }
90 }
91 if(Core_getIpuId() == 2){
92 if(myCoreNum == CORE_ID_C0)
93 {
94 regionNo = 6U;
95 }
96 else if (myCoreNum == CORE_ID_C1)
97 {
98 regionNo = 7U;
99 }
100 else
101 {
102 /* Nothing to be done here */
103 }
104 }
105 #elif defined(BUILD_TDA3XX_DSP)
106 myCoreNum = (int32_t)DNUM;
107 if(myCoreNum == 0)
108 {
109 regionNo = 2U;
110 }
111 else
112 {
113 regionNo = 3U;
114 }
115 #elif defined(BUILD_TDA3XX_EVE)
116 regionNo = 1U;
117 #endif
118 return regionNo;
119 }
121 int8_t* getGlobalAddr(int8_t* addr)
122 {
123 return (addr); /* The address is already a global address */
124 }
125 uint16_t isGblConfigRequired(uint32_t dspNum)
126 {
127 (void) dspNum;
129 return 1U;
130 }
132 /* Semaphore handles */
133 EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
135 /** Number of PaRAM Sets available */
136 #define EDMA3_NUM_PARAMSET (512U)
138 /** Number of TCCS available */
139 #define EDMA3_NUM_TCC (64U)
141 /** Number of DMA Channels available */
142 #define EDMA3_NUM_DMA_CHANNELS (64U)
144 /** Number of QDMA Channels available */
145 #define EDMA3_NUM_QDMA_CHANNELS (8U)
147 /** Number of Event Queues available */
148 #define EDMA3_NUM_EVTQUE (4U)
150 /** Number of Transfer Controllers available */
151 #define EDMA3_NUM_TC (2U)
153 /** Number of Regions */
154 #define EDMA3_NUM_REGIONS (8U)
156 /* EDMA3 configuaration for EVE */
158 /** Number of PaRAM Sets available */
159 #define EDMA3_NUM_PARAMSET_EVE (64U)
161 /** Number of TCCS available */
162 #define EDMA3_NUM_TCC_EVE (16U)
164 /** Number of DMA Channels available */
165 #define EDMA3_NUM_DMA_CHANNELS_EVE (16U)
167 /** Number of QDMA Channels available */
168 #define EDMA3_NUM_QDMA_CHANNELS_EVE (8U)
170 /** Number of Event Queues available */
171 #define EDMA3_NUM_EVTQUE_EVE (2U)
173 /** Number of Transfer Controllers available */
174 #define EDMA3_NUM_TC_EVE (2U)
176 /** Number of Regions */
177 #define EDMA3_NUM_REGIONS_EVE (8U)
180 /** Interrupt no. for Transfer Completion */
181 #define EDMA3_CC_XFER_COMPLETION_INT_DSP (38U)
182 #define EDMA3_CC_XFER_COMPLETION_INT_IPU_C0 (34U)
183 #define EDMA3_CC_XFER_COMPLETION_INT_IPU_C1 (33U)
184 #define EDMA3_CC_XFER_COMPLETION_INT_EVE (8U)
186 /** Based on the interrupt number to be mapped define the XBAR instance number */
187 #define COMPLETION_INT_DSP_XBAR_INST_NO (7U)
188 #define COMPLETION_INT_IPU_C0_XBAR_INST_NO (12U)
189 #define COMPLETION_INT_IPU_C1_XBAR_INST_NO (11U)
191 /** Interrupt no. for CC Error */
192 #define EDMA3_CC_ERROR_INT_DSP (39U)
193 #define EDMA3_CC_ERROR_INT_IPU (35U)
194 #define EDMA3_CC_ERROR_INT_EVE (23U)
196 /** Based on the interrupt number to be mapped define the XBAR instance number */
197 #define CC_ERROR_INT_DSP_XBAR_INST_NO (8U)
198 #define CC_ERROR_INT_IPU_XBAR_INST_NO (13U)
200 /** Interrupt no. for TCs Error */
201 #define EDMA3_TC0_ERROR_INT_DSP (40U)
202 #define EDMA3_TC0_ERROR_INT_IPU (36U)
203 #define EDMA3_TC0_ERROR_INT_EVE (24U)
204 #define EDMA3_TC1_ERROR_INT_DSP (41U)
205 #define EDMA3_TC1_ERROR_INT_IPU (37U)
206 #define EDMA3_TC1_ERROR_INT_EVE (25U)
208 /** Based on the interrupt number to be mapped define the XBAR instance number */
209 #define TC0_ERROR_INT_DSP_XBAR_INST_NO (9U)
210 #define TC0_ERROR_INT_IPU_XBAR_INST_NO (14U)
211 #define TC1_ERROR_INT_DSP_XBAR_INST_NO (10U)
212 #define TC1_ERROR_INT_IPU_XBAR_INST_NO (15U)
214 #ifdef BUILD_TDA3XX_DSP
215 #define EDMA3_CC_XFER_COMPLETION_INT (EDMA3_CC_XFER_COMPLETION_INT_DSP)
216 #define EDMA3_CC_ERROR_INT (EDMA3_CC_ERROR_INT_DSP)
217 #define CC_ERROR_INT_XBAR_INST_NO (CC_ERROR_INT_DSP_XBAR_INST_NO)
218 #define EDMA3_TC0_ERROR_INT (EDMA3_TC0_ERROR_INT_DSP)
219 #define EDMA3_TC1_ERROR_INT (EDMA3_TC1_ERROR_INT_DSP)
220 #define TC0_ERROR_INT_XBAR_INST_NO (TC0_ERROR_INT_DSP_XBAR_INST_NO)
221 #define TC1_ERROR_INT_XBAR_INST_NO (TC1_ERROR_INT_DSP_XBAR_INST_NO)
223 #elif defined BUILD_TDA3XX_IPU
224 #define EDMA3_CC_XFER_COMPLETION_INT (EDMA3_CC_XFER_COMPLETION_INT_IPU_C0)
225 #define EDMA3_CC_ERROR_INT (EDMA3_CC_ERROR_INT_IPU)
226 #define CC_ERROR_INT_XBAR_INST_NO (CC_ERROR_INT_IPU_XBAR_INST_NO)
227 #define EDMA3_TC0_ERROR_INT (EDMA3_TC0_ERROR_INT_IPU)
228 #define EDMA3_TC1_ERROR_INT (EDMA3_TC1_ERROR_INT_IPU)
229 #define TC0_ERROR_INT_XBAR_INST_NO (TC0_ERROR_INT_IPU_XBAR_INST_NO)
230 #define TC1_ERROR_INT_XBAR_INST_NO (TC1_ERROR_INT_IPU_XBAR_INST_NO)
232 #elif defined BUILD_TDA3XX_EVE
233 #define EDMA3_CC_XFER_COMPLETION_INT (EDMA3_CC_XFER_COMPLETION_INT_EVE)
234 #define EDMA3_CC_ERROR_INT (EDMA3_CC_ERROR_INT_EVE)
235 #define EDMA3_TC0_ERROR_INT (EDMA3_TC0_ERROR_INT_EVE)
236 #define EDMA3_TC1_ERROR_INT (EDMA3_TC1_ERROR_INT_EVE)
237 /* For accessing EVE internal edma, there is no need to configure Xbar */
238 #define CC_ERROR_INT_XBAR_INST_NO 0U
239 #define TC0_ERROR_INT_XBAR_INST_NO 0U
240 #define TC1_ERROR_INT_XBAR_INST_NO 0U
242 #else
243 #define EDMA3_CC_XFER_COMPLETION_INT (0U)
244 #define EDMA3_CC_ERROR_INT (0U)
245 #define CC_ERROR_INT_XBAR_INST_NO (0U)
246 #define EDMA3_TC0_ERROR_INT (0U)
247 #define EDMA3_TC1_ERROR_INT (0U)
248 #define TC0_ERROR_INT_XBAR_INST_NO (TC0_ERROR_INT_A15_XBAR_INST_NO)
249 #define TC1_ERROR_INT_XBAR_INST_NO (TC1_ERROR_INT_A15_XBAR_INST_NO)
250 #endif
252 #define EDMA3_TC2_ERROR_INT (0U)
253 #define EDMA3_TC3_ERROR_INT (0U)
254 #define EDMA3_TC4_ERROR_INT (0U)
255 #define EDMA3_TC5_ERROR_INT (0U)
256 #define EDMA3_TC6_ERROR_INT (0U)
257 #define EDMA3_TC7_ERROR_INT (0U)
259 #define DSP1_EDMA3_CC_XFER_COMPLETION_INT (19U)
260 #define DSP2_EDMA3_CC_XFER_COMPLETION_INT (20U)
261 #define DSP1_EDMA3_CC_ERROR_INT (27U)
262 #define DSP1_EDMA3_TC0_ERROR_INT (28U)
263 #define DSP1_EDMA3_TC1_ERROR_INT (29U)
265 /** XBAR interrupt source index numbers for EDMA interrupts */
266 #define XBAR_EDMA_TPCC_IRQ_REGION0 (361U)
267 #define XBAR_EDMA_TPCC_IRQ_REGION1 (362U)
268 #define XBAR_EDMA_TPCC_IRQ_REGION2 (363U)
269 #define XBAR_EDMA_TPCC_IRQ_REGION3 (364U)
270 #define XBAR_EDMA_TPCC_IRQ_REGION4 (365U)
271 #define XBAR_EDMA_TPCC_IRQ_REGION5 (366U)
272 #define XBAR_EDMA_TPCC_IRQ_REGION6 (367U)
273 #define XBAR_EDMA_TPCC_IRQ_REGION7 (368U)
275 #define XBAR_EDMA_TPCC_IRQ_ERR (359U)
276 #define XBAR_EDMA_TC0_IRQ_ERR (370U)
277 #define XBAR_EDMA_TC1_IRQ_ERR (371U)
279 /**
280 * EDMA3 interrupts (transfer completion, CC error etc.) correspond to different
281 * ECM events (SoC specific). These ECM events come
282 * under ECM block XXX (handling those specific ECM events). Normally, block
283 * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events
284 * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)
285 * is mapped to a specific HWI_INT YYY in the tcf file.
286 * Define EDMA3_HWI_INT_XFER_COMP to specific HWI_INT, corresponding
287 * to transfer completion interrupt.
288 * Define EDMA3_HWI_INT_CC_ERR to specific HWI_INT, corresponding
289 * to CC error interrupts.
290 * Define EDMA3_HWI_INT_TC_ERR to specific HWI_INT, corresponding
291 * to TC error interrupts.
292 */
293 /* EDMA 0 */
295 #define EDMA3_HWI_INT_XFER_COMP (7U)
296 #define EDMA3_HWI_INT_CC_ERR (7U)
297 #define EDMA3_HWI_INT_TC0_ERR (10U)
298 #define EDMA3_HWI_INT_TC1_ERR (10U)
299 #define EDMA3_HWI_INT_TC2_ERR (10U)
300 #define EDMA3_HWI_INT_TC3_ERR (10U)
303 /**
304 * \brief Mapping of DMA channels 0-31 to Hardware Events from
305 * various peripherals, which use EDMA for data transfer.
306 * All channels need not be mapped, some can be free also.
307 * 1: Mapped
308 * 0: Not mapped (channel available)
309 *
310 * This mapping will be used to allocate DMA channels when user passes
311 * EDMA3_RM_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
312 * copy). The same mapping is used to allocate the TCC when user passes
313 * EDMA3_RM_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
314 *
315 * For ADAS low Since the xbar can be used to map event to any EDMA channel,
316 * If the application is assigning events to other channel this variable
317 * should be modified
318 *
319 * To allocate more DMA channels or TCCs, one has to modify the event mapping.
320 */
321 /* 31 0 */
322 #define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA (0x3CC0DB6EU) /* TBD */
323 #define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_DSPEDMA (0x00000003U) /* TBD */
324 #define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_EVEEDMA (0x00000000U) /* TBD */
326 /**
327 * \brief Mapping of DMA channels 32-63 to Hardware Events from
328 * various peripherals, which use EDMA for data transfer.
329 * All channels need not be mapped, some can be free also.
330 * 1: Mapped
331 * 0: Not mapped (channel available)
332 *
333 * This mapping will be used to allocate DMA channels when user passes
334 * EDMA3_RM_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
335 * copy). The same mapping is used to allocate the TCC when user passes
336 * EDMA3_RM_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
337 *
338 * To allocate more DMA channels or TCCs, one has to modify the event mapping.
339 */
340 #define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA (0x303F3FFCU) /* TBD */
341 #define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_DSPEDMA (0x00000000U) /* TBD */
342 #define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_EVEEDMA (0x00000000U) /* TBD */
345 /* Variable which will be used internally for referring number of Event Queues*/
346 uint32_t numEdma3EvtQue[NUM_EDMA3_INSTANCES] = {
347 EDMA3_NUM_EVTQUE,
348 EDMA3_NUM_EVTQUE,
349 EDMA3_NUM_EVTQUE
350 };
352 /* Variable which will be used internally for referring number of TCs. */
353 uint32_t numEdma3Tc[NUM_EDMA3_INSTANCES] = {
354 EDMA3_NUM_TC,
355 EDMA3_NUM_TC,
356 EDMA3_NUM_TC
357 };
359 /**
360 * Variable which will be used internally for referring transfer completion
361 * interrupt.
362 */
363 uint32_t ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
364 {
365 /* EDMA3 INSTANCE# 0 */
366 {
367 0U,
368 0U,
369 EDMA3_CC_XFER_COMPLETION_INT_DSP,
370 EDMA3_CC_XFER_COMPLETION_INT_DSP,
371 EDMA3_CC_XFER_COMPLETION_INT_IPU_C0,
372 EDMA3_CC_XFER_COMPLETION_INT_IPU_C1,
373 0U,
374 0U
375 },
376 /* EDMA3 INSTANCE# 1 */
377 {
378 0U,
379 0U,
380 DSP1_EDMA3_CC_XFER_COMPLETION_INT,
381 DSP2_EDMA3_CC_XFER_COMPLETION_INT,
382 0U,
383 0U,
384 0U,
385 0U
386 },
387 /* EDMA3 INSTANCE# 2 */
388 {
389 0U,
390 /* Region 1 (Associated to EVE core)*/
391 EDMA3_CC_XFER_COMPLETION_INT_EVE,
392 0U,
393 0U,
394 0U,
395 0U,
396 0U,
397 0U,
398 }
399 };
401 /**
402 * Variable which will be used internally for referring channel controller's
403 * error interrupt.
404 */
405 uint32_t ccErrorInt[NUM_EDMA3_INSTANCES] =
406 {
407 EDMA3_CC_ERROR_INT,
408 DSP1_EDMA3_CC_ERROR_INT,
409 EDMA3_CC_ERROR_INT
410 };
411 uint32_t ccErrorIntXbarInstNo[NUM_EDMA3_INSTANCES] =
412 {
413 CC_ERROR_INT_XBAR_INST_NO,
414 CC_ERROR_INT_XBAR_INST_NO,
415 CC_ERROR_INT_XBAR_INST_NO
416 };
417 uint32_t ccErrEdmaXbarIndex[NUM_EDMA3_INSTANCES] =
418 {
419 XBAR_EDMA_TPCC_IRQ_ERR,
420 XBAR_EDMA_TPCC_IRQ_ERR,
421 XBAR_EDMA_TPCC_IRQ_ERR
422 };
424 /**
425 * Variable which will be used internally for referring transfer controllers'
426 * error interrupts.
427 */
428 uint32_t tcErrorInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
429 {
430 /* EDMA3 INSTANCE# 0 */
431 {
432 EDMA3_TC0_ERROR_INT, EDMA3_TC1_ERROR_INT,
433 EDMA3_TC2_ERROR_INT, EDMA3_TC3_ERROR_INT,
434 EDMA3_TC4_ERROR_INT, EDMA3_TC5_ERROR_INT,
435 EDMA3_TC6_ERROR_INT, EDMA3_TC7_ERROR_INT,
436 },
437 /* EDMA3 INSTANCE# 1 */
438 {
439 DSP1_EDMA3_TC0_ERROR_INT, DSP1_EDMA3_TC1_ERROR_INT,
440 EDMA3_TC0_ERROR_INT, EDMA3_TC1_ERROR_INT,
441 EDMA3_TC2_ERROR_INT, EDMA3_TC3_ERROR_INT,
442 EDMA3_TC4_ERROR_INT, EDMA3_TC5_ERROR_INT,
443 },
444 /* EDMA3 INSTANCE# 2 */
445 {
446 EDMA3_TC0_ERROR_INT, EDMA3_TC1_ERROR_INT,
447 EDMA3_TC2_ERROR_INT, EDMA3_TC3_ERROR_INT,
448 EDMA3_TC4_ERROR_INT, EDMA3_TC5_ERROR_INT,
449 EDMA3_TC6_ERROR_INT, EDMA3_TC7_ERROR_INT,
450 }
451 };
453 /**
454 * Variables which will be used internally for referring the hardware interrupt
455 * for various EDMA3 interrupts.
456 */
457 uint32_t hwIntXferComp[NUM_EDMA3_INSTANCES] =
458 {
459 EDMA3_HWI_INT_XFER_COMP,
460 EDMA3_HWI_INT_XFER_COMP,
461 EDMA3_CC_XFER_COMPLETION_INT
462 };
464 uint32_t hwIntCcErr[NUM_EDMA3_INSTANCES] =
465 {
466 EDMA3_HWI_INT_CC_ERR,
467 EDMA3_HWI_INT_CC_ERR,
468 EDMA3_CC_ERROR_INT
469 };
471 uint32_t hwIntTcErr[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
472 {
473 /* EDMA3 INSTANCE# 0 */
474 {
475 EDMA3_HWI_INT_TC0_ERR,
476 EDMA3_HWI_INT_TC1_ERR,
477 EDMA3_HWI_INT_TC2_ERR,
478 EDMA3_HWI_INT_TC3_ERR,
479 0,
480 0,
481 0,
482 0
483 },
484 /* EDMA3 INSTANCE# 1 */
485 {
486 EDMA3_HWI_INT_TC0_ERR,
487 EDMA3_HWI_INT_TC1_ERR,
488 EDMA3_HWI_INT_TC2_ERR,
489 EDMA3_HWI_INT_TC3_ERR,
490 0,
491 0,
492 0,
493 0
494 },
495 /* EDMA3 INSTANCE# 2 */
496 {
497 EDMA3_TC0_ERROR_INT,
498 EDMA3_TC1_ERROR_INT,
499 EDMA3_TC2_ERROR_INT,
500 EDMA3_TC3_ERROR_INT,
501 0,
502 0,
503 0,
504 0
505 }
506 };
508 /**
509 * \brief Base address as seen from the different cores may be different
510 * And is defined based on the core
511 */
512 #ifdef BUILD_TDA3XX_DSP
513 #define EDMA3_CC_BASE_ADDR ((void *)(0x43300000))
514 #define EDMA3_TC0_BASE_ADDR ((void *)(0x43400000))
515 #define EDMA3_TC1_BASE_ADDR ((void *)(0x43500000))
516 #elif (defined BUILD_TDA3XX_IPU)
517 #define EDMA3_CC_BASE_ADDR ((void *)(0x63300000))
518 #define EDMA3_TC0_BASE_ADDR ((void *)(0x63400000))
519 #define EDMA3_TC1_BASE_ADDR ((void *)(0x63500000))
520 #elif (defined BUILD_TDA3XX_EVE)
521 #define EDMA3_CC_BASE_ADDR ((void *)(0x400A0000))
522 #define EDMA3_TC0_BASE_ADDR ((void *)(0x40086000))
523 #define EDMA3_TC1_BASE_ADDR ((void *)(0x40087000))
524 #else
525 #define EDMA3_CC_BASE_ADDR ((void *)(0x0))
526 #define EDMA3_TC0_BASE_ADDR ((void *)(0x0))
527 #define EDMA3_TC1_BASE_ADDR ((void *)(0x0))
528 #endif
530 #define DSP1_EDMA3_CC_BASE_ADDR ((void *)(0x01D10000))
531 #define DSP1_EDMA3_TC0_BASE_ADDR ((void *)(0x01D05000))
532 #define DSP1_EDMA3_TC1_BASE_ADDR ((void *)(0x01D06000))
534 /* Driver Object Initialization Configuration */
535 EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
536 {
537 {
538 /* EDMA3 INSTANCE# 0 */
539 /** Total number of DMA Channels supported by the EDMA3 Controller */
540 EDMA3_NUM_DMA_CHANNELS,
541 /** Total number of QDMA Channels supported by the EDMA3 Controller */
542 EDMA3_NUM_QDMA_CHANNELS,
543 /** Total number of TCCs supported by the EDMA3 Controller */
544 EDMA3_NUM_TCC,
545 /** Total number of PaRAM Sets supported by the EDMA3 Controller */
546 EDMA3_NUM_PARAMSET,
547 /** Total number of Event Queues in the EDMA3 Controller */
548 EDMA3_NUM_EVTQUE,
549 /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller*/
550 EDMA3_NUM_TC,
551 /** Number of Regions on this EDMA3 controller */
552 EDMA3_NUM_REGIONS,
554 /**
555 * \brief Channel mapping existence
556 * A value of 0 (No channel mapping) implies that there is fixed association
557 * for a channel number to a parameter entry number or, in other words,
558 * PaRAM entry n corresponds to channel n.
559 */
560 1U,
562 /** Existence of memory protection feature */
563 0U,
565 /** Global Register Region of CC Registers */
566 EDMA3_CC_BASE_ADDR,
567 /** Transfer Controller (TC) Registers */
568 {
569 EDMA3_TC0_BASE_ADDR,
570 EDMA3_TC1_BASE_ADDR,
571 (void *)NULL,
572 (void *)NULL,
573 (void *)NULL,
574 (void *)NULL,
575 (void *)NULL,
576 (void *)NULL
577 },
578 /** Interrupt no. for Transfer Completion */
579 EDMA3_CC_XFER_COMPLETION_INT,
580 /** Interrupt no. for CC Error */
581 EDMA3_CC_ERROR_INT,
582 /** Interrupt no. for TCs Error */
583 {
584 EDMA3_TC0_ERROR_INT,
585 EDMA3_TC1_ERROR_INT,
586 EDMA3_TC2_ERROR_INT,
587 EDMA3_TC3_ERROR_INT,
588 EDMA3_TC4_ERROR_INT,
589 EDMA3_TC5_ERROR_INT,
590 EDMA3_TC6_ERROR_INT,
591 EDMA3_TC7_ERROR_INT
592 },
594 /**
595 * \brief EDMA3 TC priority setting
596 *
597 * User can program the priority of the Event Queues
598 * at a system-wide level. This means that the user can set the
599 * priority of an IO initiated by either of the TCs (Transfer Controllers)
600 * relative to IO initiated by the other bus masters on the
601 * device (ARM, DSP, USB, etc)
602 */
603 {
604 0U,
605 1U,
606 0U,
607 0U,
608 0U,
609 0U,
610 0U,
611 0U
612 },
613 /**
614 * \brief To Configure the Threshold level of number of events
615 * that can be queued up in the Event queues. EDMA3CC error register
616 * (CCERR) will indicate whether or not at any instant of time the
617 * number of events queued up in any of the event queues exceeds
618 * or equals the threshold/watermark value that is set
619 * in the queue watermark threshold register (QWMTHRA).
620 */
621 {
622 16U,
623 16U,
624 0U,
625 0U,
626 0U,
627 0U,
628 0U,
629 0U
630 },
632 /**
633 * \brief To Configure the Default Burst Size (DBS) of TCs.
634 * An optimally-sized command is defined by the transfer controller
635 * default burst size (DBS). Different TCs can have different
636 * DBS values. It is defined in Bytes.
637 */
638 {
639 16U,
640 16U,
641 0U,
642 0U,
643 0U,
644 0U,
645 0U,
646 0U
647 },
649 /**
650 * \brief Mapping from each DMA channel to a Parameter RAM set,
651 * if it exists, otherwise of no use.
652 */
653 {
654 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
655 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
656 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
657 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
658 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
659 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
660 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
661 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
662 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
663 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
664 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
665 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
666 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
667 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
668 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
669 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
670 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
671 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
672 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
673 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
674 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
675 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
676 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
677 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
678 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
679 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
680 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
681 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
682 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
683 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
684 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
685 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP
686 },
688 /**
689 * \brief Mapping from each DMA channel to a TCC. This specific
690 * TCC code will be returned when the transfer is completed
691 * on the mapped channel.
692 */
693 {
694 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
695 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
696 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
697 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
698 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
699 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
700 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
701 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
702 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
703 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
704 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
705 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
706 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
707 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
708 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
709 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
710 },
712 /**
713 * \brief Mapping of DMA channels to Hardware Events from
714 * various peripherals, which use EDMA for data transfer.
715 * All channels need not be mapped, some can be free also.
716 */
717 {
718 EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA,
719 EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA
720 }
721 },
722 {
723 /* EDMA3 INSTANCE# 1 */
724 /** Total number of DMA Channels supported by the EDMA3 Controller */
725 EDMA3_NUM_DMA_CHANNELS,
726 /** Total number of QDMA Channels supported by the EDMA3 Controller */
727 EDMA3_NUM_QDMA_CHANNELS,
728 /** Total number of TCCs supported by the EDMA3 Controller */
729 EDMA3_NUM_TCC,
730 /** Total number of PaRAM Sets supported by the EDMA3 Controller */
731 EDMA3_NUM_PARAMSET,
732 /** Total number of Event Queues in the EDMA3 Controller */
733 EDMA3_NUM_EVTQUE,
734 /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller*/
735 EDMA3_NUM_TC,
736 /** Number of Regions on this EDMA3 controller */
737 EDMA3_NUM_REGIONS,
739 /**
740 * \brief Channel mapping existence
741 * A value of 0 (No channel mapping) implies that there is fixed association
742 * for a channel number to a parameter entry number or, in other words,
743 * PaRAM entry n corresponds to channel n.
744 */
745 1U,
747 /** Existence of memory protection feature */
748 0U,
750 /** Global Register Region of CC Registers */
751 DSP1_EDMA3_CC_BASE_ADDR,
752 /** Transfer Controller (TC) Registers */
753 {
754 DSP1_EDMA3_TC0_BASE_ADDR,
755 DSP1_EDMA3_TC1_BASE_ADDR,
756 (void *)NULL,
757 (void *)NULL,
758 (void *)NULL,
759 (void *)NULL,
760 (void *)NULL,
761 (void *)NULL
762 },
763 /** Interrupt no. for Transfer Completion */
764 DSP1_EDMA3_CC_XFER_COMPLETION_INT,
765 /** Interrupt no. for CC Error */
766 DSP1_EDMA3_CC_ERROR_INT,
767 /** Interrupt no. for TCs Error */
768 {
769 DSP1_EDMA3_TC0_ERROR_INT,
770 DSP1_EDMA3_TC1_ERROR_INT,
771 EDMA3_TC2_ERROR_INT,
772 EDMA3_TC3_ERROR_INT,
773 EDMA3_TC4_ERROR_INT,
774 EDMA3_TC5_ERROR_INT,
775 EDMA3_TC6_ERROR_INT,
776 EDMA3_TC7_ERROR_INT
777 },
779 /**
780 * \brief EDMA3 TC priority setting
781 *
782 * User can program the priority of the Event Queues
783 * at a system-wide level. This means that the user can set the
784 * priority of an IO initiated by either of the TCs (Transfer Controllers)
785 * relative to IO initiated by the other bus masters on the
786 * device (ARM, DSP, USB, etc)
787 */
788 {
789 0U,
790 1U,
791 0U,
792 0U,
793 0U,
794 0U,
795 0U,
796 0U
797 },
798 /**
799 * \brief To Configure the Threshold level of number of events
800 * that can be queued up in the Event queues. EDMA3CC error register
801 * (CCERR) will indicate whether or not at any instant of time the
802 * number of events queued up in any of the event queues exceeds
803 * or equals the threshold/watermark value that is set
804 * in the queue watermark threshold register (QWMTHRA).
805 */
806 {
807 16U,
808 16U,
809 0U,
810 0U,
811 0U,
812 0U,
813 0U,
814 0U
815 },
817 /**
818 * \brief To Configure the Default Burst Size (DBS) of TCs.
819 * An optimally-sized command is defined by the transfer controller
820 * default burst size (DBS). Different TCs can have different
821 * DBS values. It is defined in Bytes.
822 */
823 {
824 16U,
825 16U,
826 0U,
827 0U,
828 0U,
829 0U,
830 0U,
831 0U
832 },
834 /**
835 * \brief Mapping from each DMA channel to a Parameter RAM set,
836 * if it exists, otherwise of no use.
837 */
838 {
839 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
840 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
841 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
842 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
843 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
844 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
845 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
846 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
847 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
848 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
849 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
850 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
851 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
852 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
853 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
854 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
855 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
856 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
857 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
858 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
859 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
860 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
861 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
862 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
863 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
864 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
865 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
866 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
867 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
868 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
869 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
870 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP
871 },
873 /**
874 * \brief Mapping from each DMA channel to a TCC. This specific
875 * TCC code will be returned when the transfer is completed
876 * on the mapped channel.
877 */
878 {
879 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
880 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
881 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
882 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
883 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
884 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
885 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
886 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
887 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
888 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
889 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
890 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
891 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
892 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
893 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
894 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
895 },
897 /**
898 * \brief Mapping of DMA channels to Hardware Events from
899 * various peripherals, which use EDMA for data transfer.
900 * All channels need not be mapped, some can be free also.
901 */
902 {
903 EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_DSPEDMA,
904 EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_DSPEDMA
905 }
906 },
907 {
908 /* EDMA3 INSTANCE# 2 */
909 /** Total number of DMA Channels supported by the EDMA3 Controller */
910 EDMA3_NUM_DMA_CHANNELS_EVE,
911 /** Total number of QDMA Channels supported by the EDMA3 Controller */
912 EDMA3_NUM_QDMA_CHANNELS_EVE,
913 /** Total number of TCCs supported by the EDMA3 Controller */
914 EDMA3_NUM_TCC_EVE,
915 /** Total number of PaRAM Sets supported by the EDMA3 Controller */
916 EDMA3_NUM_PARAMSET_EVE,
917 /** Total number of Event Queues in the EDMA3 Controller */
918 EDMA3_NUM_EVTQUE_EVE,
919 /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller*/
920 EDMA3_NUM_TC_EVE,
921 /** Number of Regions on this EDMA3 controller */
922 EDMA3_NUM_REGIONS_EVE,
924 /**
925 * \brief Channel mapping existence
926 * A value of 0 (No channel mapping) implies that there is fixed association
927 * for a channel number to a parameter entry number or, in other words,
928 * PaRAM entry n corresponds to channel n.
929 */
930 1U,
932 /** Existence of memory protection feature */
933 0U,
935 /** Global Register Region of CC Registers */
936 EDMA3_CC_BASE_ADDR,
937 /** Transfer Controller (TC) Registers */
938 {
939 EDMA3_TC0_BASE_ADDR,
940 EDMA3_TC1_BASE_ADDR,
941 (void *)NULL,
942 (void *)NULL,
943 (void *)NULL,
944 (void *)NULL,
945 (void *)NULL,
946 (void *)NULL
947 },
948 /** Interrupt no. for Transfer Completion */
949 EDMA3_CC_XFER_COMPLETION_INT,
950 /** Interrupt no. for CC Error */
951 EDMA3_CC_ERROR_INT,
952 /** Interrupt no. for TCs Error */
953 {
954 EDMA3_TC0_ERROR_INT,
955 EDMA3_TC1_ERROR_INT,
956 EDMA3_TC2_ERROR_INT,
957 EDMA3_TC3_ERROR_INT,
958 EDMA3_TC4_ERROR_INT,
959 EDMA3_TC5_ERROR_INT,
960 EDMA3_TC6_ERROR_INT,
961 EDMA3_TC7_ERROR_INT
962 },
964 /**
965 * \brief EDMA3 TC priority setting
966 *
967 * User can program the priority of the Event Queues
968 * at a system-wide level. This means that the user can set the
969 * priority of an IO initiated by either of the TCs (Transfer Controllers)
970 * relative to IO initiated by the other bus masters on the
971 * device (ARM, DSP, USB, etc)
972 */
973 {
974 0U,
975 1U,
976 0U,
977 0U,
978 0U,
979 0U,
980 0U,
981 0U
982 },
983 /**
984 * \brief To Configure the Threshold level of number of events
985 * that can be queued up in the Event queues. EDMA3CC error register
986 * (CCERR) will indicate whether or not at any instant of time the
987 * number of events queued up in any of the event queues exceeds
988 * or equals the threshold/watermark value that is set
989 * in the queue watermark threshold register (QWMTHRA).
990 */
991 {
992 16U,
993 16U,
994 0U,
995 0U,
996 0U,
997 0U,
998 0U,
999 0U
1000 },
1002 /**
1003 * \brief To Configure the Default Burst Size (DBS) of TCs.
1004 * An optimally-sized command is defined by the transfer controller
1005 * default burst size (DBS). Different TCs can have different
1006 * DBS values. It is defined in Bytes.
1007 */
1008 {
1009 16U,
1010 16U,
1011 0U,
1012 0U,
1013 0U,
1014 0U,
1015 0U,
1016 0U
1017 },
1019 /**
1020 * \brief Mapping from each DMA channel to a Parameter RAM set,
1021 * if it exists, otherwise of no use.
1022 */
1023 {
1024 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1025 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1026 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1027 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1028 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1029 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1030 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1031 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1032 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1033 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1034 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1035 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1036 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1037 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1038 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1039 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1040 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1041 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1042 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1043 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1044 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1045 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1046 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1047 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1048 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1049 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1050 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1051 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1052 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1053 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1054 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
1055 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP
1056 },
1058 /**
1059 * \brief Mapping from each DMA channel to a TCC. This specific
1060 * TCC code will be returned when the transfer is completed
1061 * on the mapped channel.
1062 */
1063 {
1064 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
1065 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
1066 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
1067 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
1068 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
1069 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
1070 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
1071 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
1072 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
1073 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
1074 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
1075 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
1076 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
1077 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
1078 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
1079 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
1080 },
1082 /**
1083 * \brief Mapping of DMA channels to Hardware Events from
1084 * various peripherals, which use EDMA for data transfer.
1085 * All channels need not be mapped, some can be free also.
1086 */
1087 {
1088 EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_EVEEDMA,
1089 EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_EVEEDMA
1090 }
1091 },
1093 };
1095 /**
1096 * \brief Resource splitting defines for Own/Reserved DMA/QDMA channels and TCCs
1097 * For PaRAMs explicit defines are not present but should be replaced in the structure sampleInstInitConfig
1098 * Default configuration has all resources owned by all cores and none reserved except for first 64 PaRAMs corrosponding to DMA channels
1099 * Resources to be Split properly by application and rebuild the sample library to avoid resource conflict
1100 *
1101 * Only Resources owned by a perticular core are allocated by Driver
1102 * Reserved resources are not allocated if requested for any available resource
1103 */
1105 /* Driver Instance Initialization Configuration */
1106 EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
1107 {
1108 /* EDMA3 INSTANCE# 0 */
1109 {
1110 /* Resources owned/reserved by region 0 (Not Associated to any core supported)*/
1111 {
1112 /* ownPaRAMSets */
1113 /* 31 0 63 32 95 64 127 96 */
1114 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1115 /* 159 128 191 160 223 192 255 224 */
1116 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1117 /* 287 256 319 288 351 320 383 352 */
1118 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1119 /* 415 384 447 416 479 448 511 480 */
1120 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
1122 /* ownDmaChannels */
1123 /* 31 0 63 32 */
1124 {0x00000000U, 0x00000000U},
1126 /* ownQdmaChannels */
1127 /* 31 0 */
1128 {0x00000000U},
1130 /* ownTccs */
1131 /* 31 0 63 32 */
1132 {0x00000000U, 0x00000000U},
1134 /* resvdPaRAMSets */
1135 /* 31 0 63 32 95 64 127 96 */
1136 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1137 /* 159 128 191 160 223 192 255 224 */
1138 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1139 /* 287 256 319 288 351 320 383 352 */
1140 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1141 /* 415 384 447 416 479 448 511 480 */
1142 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
1144 /* resvdDmaChannels */
1145 /* 31 0 63 32 */
1146 {0x00000000U, 0x00000000U},
1148 /* resvdQdmaChannels */
1149 /* 31 0 */
1150 {0x00000000U},
1152 /* resvdTccs */
1153 /* 31 0 63 32 */
1154 {0x00000000U, 0x00000000U},
1155 },
1157 /* Resources owned/reserved by region 1 (Not Associated to any core supported)*/
1158 {
1159 /* ownPaRAMSets */
1160 /* 31 0 63 32 95 64 127 96 */
1161 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1162 /* 159 128 191 160 223 192 255 224 */
1163 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1164 /* 287 256 319 288 351 320 383 352 */
1165 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1166 /* 415 384 447 416 479 448 511 480 */
1167 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
1169 /* ownDmaChannels */
1170 /* 31 0 63 32 */
1171 {0x00000000U, 0x00000000U},
1173 /* ownQdmaChannels */
1174 /* 31 0 */
1175 {0x00000000U},
1177 /* ownTccs */
1178 /* 31 0 63 32 */
1179 {0x00000000U, 0x00000000U},
1181 /* resvdPaRAMSets */
1182 /* 31 0 63 32 95 64 127 96 */
1183 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1184 /* 159 128 191 160 223 192 255 224 */
1185 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1186 /* 287 256 319 288 351 320 383 352 */
1187 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1188 /* 415 384 447 416 479 448 511 480 */
1189 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
1191 /* resvdDmaChannels */
1192 /* 31 0 63 32 */
1193 {0x00000000U, 0x00000000U},
1195 /* resvdQdmaChannels */
1196 /* 31 0 */
1197 {0x00000000U},
1199 /* resvdTccs */
1200 /* 31 0 63 32 */
1201 {0x00000000U, 0x00000000U},
1202 },
1204 /* Resources owned/reserved by region 2 (Associated to any DSP1)*/
1205 {
1206 /* ownPaRAMSets */
1207 /* 31 0 63 32 95 64 127 96 */
1208 {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
1209 /* 159 128 191 160 223 192 255 224 */
1210 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
1211 /* 287 256 319 288 351 320 383 352 */
1212 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
1213 /* 415 384 447 416 479 448 511 480 */
1214 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},
1216 /* ownDmaChannels */
1217 /* 31 0 63 32 */
1218 {0xFFFFFFFFU, 0xFFFFFFFFU},
1220 /* ownQdmaChannels */
1221 /* 31 0 */
1222 {0x000000FFU},
1224 /* ownTccs */
1225 /* 31 0 63 32 */
1226 {0xFFFFFFFFU, 0xFFFFFFFFU},
1228 /* resvdPaRAMSets */
1229 /* 31 0 63 32 95 64 127 96 */
1230 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1231 /* 159 128 191 160 223 192 255 224 */
1232 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1233 /* 287 256 319 288 351 320 383 352 */
1234 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1235 /* 415 384 447 416 479 448 511 480 */
1236 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
1238 /* resvdDmaChannels */
1239 /* 31 0 63 32 */
1240 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA},
1242 /* resvdQdmaChannels */
1243 /* 31 0 */
1244 {0x00U},
1246 /* resvdTccs */
1247 /* 31 0 63 32 */
1248 {0x00U, 0x00U},
1249 },
1251 /* Resources owned/reserved by region 3 (Associated to any DSP2)*/
1252 {
1253 /* ownPaRAMSets */
1254 /* 31 0 63 32 95 64 127 96 */
1255 {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
1256 /* 159 128 191 160 223 192 255 224 */
1257 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
1258 /* 287 256 319 288 351 320 383 352 */
1259 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
1260 /* 415 384 447 416 479 448 511 480 */
1261 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},
1263 /* ownDmaChannels */
1264 /* 31 0 63 32 */
1265 {0xFFFFFFFFU, 0xFFFFFFFFU},
1267 /* ownQdmaChannels */
1268 /* 31 0 */
1269 {0x000000FFU},
1271 /* ownTccs */
1272 /* 31 0 63 32 */
1273 {0xFFFFFFFFU, 0xFFFFFFFFU},
1275 /* resvdPaRAMSets */
1276 /* 31 0 63 32 95 64 127 96 */
1277 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1278 /* 159 128 191 160 223 192 255 224 */
1279 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1280 /* 287 256 319 288 351 320 383 352 */
1281 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1282 /* 415 384 447 416 479 448 511 480 */
1283 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
1285 /* resvdDmaChannels */
1286 /* 31 0 63 32 */
1287 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA},
1289 /* resvdQdmaChannels */
1290 /* 31 0 */
1291 {0x00U},
1293 /* resvdTccs */
1294 /* 31 0 63 32 */
1295 {0x00U, 0x00U},
1296 },
1298 /* Resources owned/reserved by region 4 (Associated to any IPU core 0)*/
1299 {
1300 /* ownPaRAMSets */
1301 /* 31 0 63 32 95 64 127 96 */
1302 {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
1303 /* 159 128 191 160 223 192 255 224 */
1304 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
1305 /* 287 256 319 288 351 320 383 352 */
1306 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
1307 /* 415 384 447 416 479 448 511 480 */
1308 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},
1310 /* ownDmaChannels */
1311 /* 31 0 63 32 */
1312 {0xFFFFFFFFU, 0xFFFFFFFFU},
1314 /* ownQdmaChannels */
1315 /* 31 0 */
1316 {0x000000FFU},
1318 /* ownTccs */
1319 /* 31 0 63 32 */
1320 {0xFFFFFFFFU, 0xFFFFFFFFU},
1322 /* resvdPaRAMSets */
1323 /* 31 0 63 32 95 64 127 96 */
1324 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1325 /* 159 128 191 160 223 192 255 224 */
1326 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1327 /* 287 256 319 288 351 320 383 352 */
1328 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1329 /* 415 384 447 416 479 448 511 480 */
1330 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
1332 /* resvdDmaChannels */
1333 /* 31 0 63 32 */
1334 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA},
1336 /* resvdQdmaChannels */
1337 /* 31 0 */
1338 {0x00U},
1340 /* resvdTccs */
1341 /* 31 0 63 32 */
1342 {0x00U, 0x00U},
1343 },
1345 /* Resources owned/reserved by region 5 (Associated to any IPU core 1)*/
1346 {
1347 /* ownPaRAMSets */
1348 /* 31 0 63 32 95 64 127 96 */
1349 {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
1350 /* 159 128 191 160 223 192 255 224 */
1351 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
1352 /* 287 256 319 288 351 320 383 352 */
1353 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
1354 /* 415 384 447 416 479 448 511 480 */
1355 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},
1357 /* ownDmaChannels */
1358 /* 31 0 63 32 */
1359 {0xFFFFFFFFU, 0xFFFFFFFFU},
1361 /* ownQdmaChannels */
1362 /* 31 0 */
1363 {0x000000FFU},
1365 /* ownTccs */
1366 /* 31 0 63 32 */
1367 {0xFFFFFFFFU, 0xFFFFFFFFU},
1369 /* resvdPaRAMSets */
1370 /* 31 0 63 32 95 64 127 96 */
1371 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1372 /* 159 128 191 160 223 192 255 224 */
1373 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1374 /* 287 256 319 288 351 320 383 352 */
1375 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1376 /* 415 384 447 416 479 448 511 480 */
1377 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
1379 /* resvdDmaChannels */
1380 /* 31 0 63 32 */
1381 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA},
1383 /* resvdQdmaChannels */
1384 /* 31 0 */
1385 {0x00U},
1387 /* resvdTccs */
1388 /* 31 0 63 32 */
1389 {0x00U, 0x00U},
1390 },
1392 /* Resources owned/reserved by region 6 (Not Associated to any core supported)*/
1393 {
1394 /* ownPaRAMSets */
1395 /* 31 0 63 32 95 64 127 96 */
1396 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1397 /* 159 128 191 160 223 192 255 224 */
1398 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1399 /* 287 256 319 288 351 320 383 352 */
1400 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1401 /* 415 384 447 416 479 448 511 480 */
1402 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
1404 /* ownDmaChannels */
1405 /* 31 0 63 32 */
1406 {0x00000000U, 0x00000000U},
1408 /* ownQdmaChannels */
1409 /* 31 0 */
1410 {0x00000000U},
1412 /* ownTccs */
1413 /* 31 0 63 32 */
1414 {0x00000000U, 0x00000000U},
1416 /* resvdPaRAMSets */
1417 /* 31 0 63 32 95 64 127 96 */
1418 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1419 /* 159 128 191 160 223 192 255 224 */
1420 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1421 /* 287 256 319 288 351 320 383 352 */
1422 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1423 /* 415 384 447 416 479 448 511 480 */
1424 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
1426 /* resvdDmaChannels */
1427 /* 31 0 63 32 */
1428 {0x00000000U, 0x00000000U},
1430 /* resvdQdmaChannels */
1431 /* 31 0 */
1432 {0x00000000U},
1434 /* resvdTccs */
1435 /* 31 0 63 32 */
1436 {0x00000000U, 0x00000000U},
1437 },
1439 /* Resources owned/reserved by region 7 (Not Associated to any core supported)*/
1440 {
1441 /* ownPaRAMSets */
1442 /* 31 0 63 32 95 64 127 96 */
1443 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1444 /* 159 128 191 160 223 192 255 224 */
1445 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1446 /* 287 256 319 288 351 320 383 352 */
1447 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1448 /* 415 384 447 416 479 448 511 480 */
1449 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
1451 /* ownDmaChannels */
1452 /* 31 0 63 32 */
1453 {0x00000000U, 0x00000000U},
1455 /* ownQdmaChannels */
1456 /* 31 0 */
1457 {0x00000000U},
1459 /* ownTccs */
1460 /* 31 0 63 32 */
1461 {0x00000000U, 0x00000000U},
1463 /* resvdPaRAMSets */
1464 /* 31 0 63 32 95 64 127 96 */
1465 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1466 /* 159 128 191 160 223 192 255 224 */
1467 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1468 /* 287 256 319 288 351 320 383 352 */
1469 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1470 /* 415 384 447 416 479 448 511 480 */
1471 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
1473 /* resvdDmaChannels */
1474 /* 31 0 63 32 */
1475 {0x00000000U, 0x00000000U},
1477 /* resvdQdmaChannels */
1478 /* 31 0 */
1479 {0x00000000U},
1481 /* resvdTccs */
1482 /* 31 0 63 32 */
1483 {0x00000000U, 0x00000000U},
1484 },
1485 },
1486 /* EDMA3 INSTANCE# 1 DSP1 EDMA*/
1487 {
1488 /* Resources owned/reserved by region 0 (Not Associated to any core supported)*/
1489 {
1490 /* ownPaRAMSets */
1491 /* 31 0 63 32 95 64 127 96 */
1492 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1493 /* 159 128 191 160 223 192 255 224 */
1494 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1495 /* 287 256 319 288 351 320 383 352 */
1496 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1497 /* 415 384 447 416 479 448 511 480 */
1498 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
1500 /* ownDmaChannels */
1501 /* 31 0 63 32 */
1502 {0x00000000U, 0x00000000U},
1504 /* ownQdmaChannels */
1505 /* 31 0 */
1506 {0x00000000U},
1508 /* ownTccs */
1509 /* 31 0 63 32 */
1510 {0x00000000U, 0x00000000U},
1512 /* resvdPaRAMSets */
1513 /* 31 0 63 32 95 64 127 96 */
1514 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1515 /* 159 128 191 160 223 192 255 224 */
1516 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1517 /* 287 256 319 288 351 320 383 352 */
1518 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1519 /* 415 384 447 416 479 448 511 480 */
1520 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
1522 /* resvdDmaChannels */
1523 /* 31 0 63 32 */
1524 {0x00000000U, 0x00000000U},
1526 /* resvdQdmaChannels */
1527 /* 31 0 */
1528 {0x00000000U},
1530 /* resvdTccs */
1531 /* 31 0 63 32 */
1532 {0x00000000U, 0x00000000U},
1533 },
1535 /* Resources owned/reserved by region 1 (Not Associated to any core supported) */
1536 {
1537 /* ownPaRAMSets */
1538 /* 31 0 63 32 95 64 127 96 */
1539 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1540 /* 159 128 191 160 223 192 255 224 */
1541 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1542 /* 287 256 319 288 351 320 383 352 */
1543 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1544 /* 415 384 447 416 479 448 511 480 */
1545 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
1547 /* ownDmaChannels */
1548 /* 31 0 63 32 */
1549 {0x00000000U, 0x00000000U},
1551 /* ownQdmaChannels */
1552 /* 31 0 */
1553 {0x00000000U},
1555 /* ownTccs */
1556 /* 31 0 63 32 */
1557 {0x00000000U, 0x00000000U},
1559 /* resvdPaRAMSets */
1560 /* 31 0 63 32 95 64 127 96 */
1561 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1562 /* 159 128 191 160 223 192 255 224 */
1563 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1564 /* 287 256 319 288 351 320 383 352 */
1565 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1566 /* 415 384 447 416 479 448 511 480 */
1567 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
1569 /* resvdDmaChannels */
1570 /* 31 0 63 32 */
1571 {0x00000000U, 0x00000000U},
1573 /* resvdQdmaChannels */
1574 /* 31 0 */
1575 {0x00000000U},
1577 /* resvdTccs */
1578 /* 31 0 63 32 */
1579 {0x00000000U, 0x00000000U},
1580 },
1582 /* Resources owned/reserved by region 2 (Associated to any DSP core 0)*/
1583 {
1584 /* ownPaRAMSets */
1585 /* 31 0 63 32 95 64 127 96 */
1586 {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
1587 /* 159 128 191 160 223 192 255 224 */
1588 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
1589 /* 287 256 319 288 351 320 383 352 */
1590 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
1591 /* 415 384 447 416 479 448 511 480 */
1592 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},
1594 /* ownDmaChannels */
1595 /* 31 0 63 32 */
1596 {0xFFFFFFFFU, 0xFFFFFFFFU},
1598 /* ownQdmaChannels */
1599 /* 31 0 */
1600 {0x000000FFU},
1602 /* ownTccs */
1603 /* 31 0 63 32 */
1604 {0xFFFFFFFFU, 0xFFFFFFFFU},
1606 /* resvdPaRAMSets */
1607 /* 31 0 63 32 95 64 127 96 */
1608 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1609 /* 159 128 191 160 223 192 255 224 */
1610 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1611 /* 287 256 319 288 351 320 383 352 */
1612 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1613 /* 415 384 447 416 479 448 511 480 */
1614 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
1616 /* resvdDmaChannels */
1617 /* 31 0 63 32 */
1618 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_DSPEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_DSPEDMA},
1620 /* resvdQdmaChannels */
1621 /* 31 0 */
1622 {0x00U},
1624 /* resvdTccs */
1625 /* 31 0 63 32 */
1626 {0x00U, 0x00U},
1627 },
1629 /* Resources owned/reserved by region 3 (Associated to any DSP core 1)*/
1630 {
1631 /* ownPaRAMSets */
1632 /* 31 0 63 32 95 64 127 96 */
1633 {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
1634 /* 159 128 191 160 223 192 255 224 */
1635 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
1636 /* 287 256 319 288 351 320 383 352 */
1637 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
1638 /* 415 384 447 416 479 448 511 480 */
1639 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},
1641 /* ownDmaChannels */
1642 /* 31 0 63 32 */
1643 {0xFFFFFFFFU, 0xFFFFFFFFU},
1645 /* ownQdmaChannels */
1646 /* 31 0 */
1647 {0x000000FFU},
1649 /* ownTccs */
1650 /* 31 0 63 32 */
1651 {0xFFFFFFFFU, 0xFFFFFFFFU},
1653 /* resvdPaRAMSets */
1654 /* 31 0 63 32 95 64 127 96 */
1655 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1656 /* 159 128 191 160 223 192 255 224 */
1657 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1658 /* 287 256 319 288 351 320 383 352 */
1659 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1660 /* 415 384 447 416 479 448 511 480 */
1661 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
1663 /* resvdDmaChannels */
1664 /* 31 0 63 32 */
1665 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_DSPEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_DSPEDMA},
1667 /* resvdQdmaChannels */
1668 /* 31 0 */
1669 {0x00U},
1671 /* resvdTccs */
1672 /* 31 0 63 32 */
1673 {0x00U, 0x00U},
1674 },
1676 /* Resources owned/reserved by region 4 (Not Associated to any core supported)*/
1677 {
1678 /* ownPaRAMSets */
1679 /* 31 0 63 32 95 64 127 96 */
1680 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1681 /* 159 128 191 160 223 192 255 224 */
1682 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1683 /* 287 256 319 288 351 320 383 352 */
1684 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1685 /* 415 384 447 416 479 448 511 480 */
1686 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
1688 /* ownDmaChannels */
1689 /* 31 0 63 32 */
1690 {0x00000000U, 0x00000000U},
1692 /* ownQdmaChannels */
1693 /* 31 0 */
1694 {0x00000000U},
1696 /* ownTccs */
1697 /* 31 0 63 32 */
1698 {0x00000000U, 0x00000000U},
1700 /* resvdPaRAMSets */
1701 /* 31 0 63 32 95 64 127 96 */
1702 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1703 /* 159 128 191 160 223 192 255 224 */
1704 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1705 /* 287 256 319 288 351 320 383 352 */
1706 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1707 /* 415 384 447 416 479 448 511 480 */
1708 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
1710 /* resvdDmaChannels */
1711 /* 31 0 63 32 */
1712 {0x00000000U, 0x00000000U},
1714 /* resvdQdmaChannels */
1715 /* 31 0 */
1716 {0x00000000U},
1718 /* resvdTccs */
1719 /* 31 0 63 32 */
1720 {0x00000000U, 0x00000000U},
1721 },
1723 /* Resources owned/reserved by region 5 (Not Associated to any core supported)*/
1724 {
1725 /* ownPaRAMSets */
1726 /* 31 0 63 32 95 64 127 96 */
1727 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1728 /* 159 128 191 160 223 192 255 224 */
1729 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1730 /* 287 256 319 288 351 320 383 352 */
1731 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1732 /* 415 384 447 416 479 448 511 480 */
1733 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
1735 /* ownDmaChannels */
1736 /* 31 0 63 32 */
1737 {0x00000000U, 0x00000000U},
1739 /* ownQdmaChannels */
1740 /* 31 0 */
1741 {0x00000000U},
1743 /* ownTccs */
1744 /* 31 0 63 32 */
1745 {0x00000000U, 0x00000000U},
1747 /* resvdPaRAMSets */
1748 /* 31 0 63 32 95 64 127 96 */
1749 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1750 /* 159 128 191 160 223 192 255 224 */
1751 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1752 /* 287 256 319 288 351 320 383 352 */
1753 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1754 /* 415 384 447 416 479 448 511 480 */
1755 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
1757 /* resvdDmaChannels */
1758 /* 31 0 63 32 */
1759 {0x00000000U, 0x00000000U},
1761 /* resvdQdmaChannels */
1762 /* 31 0 */
1763 {0x00000000U},
1765 /* resvdTccs */
1766 /* 31 0 63 32 */
1767 {0x00000000U, 0x00000000U},
1768 },
1770 /* Resources owned/reserved by region 6 (Not Associated to any core supported)*/
1771 {
1772 /* ownPaRAMSets */
1773 /* 31 0 63 32 95 64 127 96 */
1774 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1775 /* 159 128 191 160 223 192 255 224 */
1776 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1777 /* 287 256 319 288 351 320 383 352 */
1778 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1779 /* 415 384 447 416 479 448 511 480 */
1780 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
1782 /* ownDmaChannels */
1783 /* 31 0 63 32 */
1784 {0x00000000U, 0x00000000U},
1786 /* ownQdmaChannels */
1787 /* 31 0 */
1788 {0x00000000U},
1790 /* ownTccs */
1791 /* 31 0 63 32 */
1792 {0x00000000U, 0x00000000U},
1794 /* resvdPaRAMSets */
1795 /* 31 0 63 32 95 64 127 96 */
1796 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1797 /* 159 128 191 160 223 192 255 224 */
1798 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1799 /* 287 256 319 288 351 320 383 352 */
1800 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1801 /* 415 384 447 416 479 448 511 480 */
1802 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
1804 /* resvdDmaChannels */
1805 /* 31 0 63 32 */
1806 {0x00000000U, 0x00000000U},
1808 /* resvdQdmaChannels */
1809 /* 31 0 */
1810 {0x00000000U},
1812 /* resvdTccs */
1813 /* 31 0 63 32 */
1814 {0x00000000U, 0x00000000U},
1815 },
1817 /* Resources owned/reserved by region 7 (Not Associated to any core supported)*/
1818 {
1819 /* ownPaRAMSets */
1820 /* 31 0 63 32 95 64 127 96 */
1821 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1822 /* 159 128 191 160 223 192 255 224 */
1823 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1824 /* 287 256 319 288 351 320 383 352 */
1825 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1826 /* 415 384 447 416 479 448 511 480 */
1827 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
1829 /* ownDmaChannels */
1830 /* 31 0 63 32 */
1831 {0x00000000U, 0x00000000U},
1833 /* ownQdmaChannels */
1834 /* 31 0 */
1835 {0x00000000U},
1837 /* ownTccs */
1838 /* 31 0 63 32 */
1839 {0x00000000U, 0x00000000U},
1841 /* resvdPaRAMSets */
1842 /* 31 0 63 32 95 64 127 96 */
1843 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1844 /* 159 128 191 160 223 192 255 224 */
1845 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1846 /* 287 256 319 288 351 320 383 352 */
1847 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1848 /* 415 384 447 416 479 448 511 480 */
1849 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
1851 /* resvdDmaChannels */
1852 /* 31 0 63 32 */
1853 {0x00000000U, 0x00000000U},
1855 /* resvdQdmaChannels */
1856 /* 31 0 */
1857 {0x00000000U},
1859 /* resvdTccs */
1860 /* 31 0 63 32 */
1861 {0x00000000U, 0x00000000U},
1862 },
1863 },
1864 /* EDMA3 INSTANCE# 2 EVE EDMA*/
1865 {
1866 /* Resources owned/reserved by region 0 (Not Associated to any core supported)*/
1867 {
1868 /* ownPaRAMSets */
1869 /* 31 0 63 32 95 64 127 96 */
1870 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1871 /* 159 128 191 160 223 192 255 224 */
1872 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1873 /* 287 256 319 288 351 320 383 352 */
1874 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1875 /* 415 384 447 416 479 448 511 480 */
1876 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
1878 /* ownDmaChannels */
1879 /* 31 0 63 32 */
1880 {0x00000000U, 0x00000000U},
1882 /* ownQdmaChannels */
1883 /* 31 0 */
1884 {0x00000000U},
1886 /* ownTccs */
1887 /* 31 0 63 32 */
1888 {0x00000000U, 0x00000000U},
1890 /* resvdPaRAMSets */
1891 /* 31 0 63 32 95 64 127 96 */
1892 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1893 /* 159 128 191 160 223 192 255 224 */
1894 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1895 /* 287 256 319 288 351 320 383 352 */
1896 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1897 /* 415 384 447 416 479 448 511 480 */
1898 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
1900 /* resvdDmaChannels */
1901 /* 31 0 63 32 */
1902 {0x00000000U, 0x00000000U},
1904 /* resvdQdmaChannels */
1905 /* 31 0 */
1906 {0x00000000U},
1908 /* resvdTccs */
1909 /* 31 0 63 32 */
1910 {0x00000000U, 0x00000000U},
1911 },
1913 /* Resources owned/reserved by region 1 (Associated to any EVE core)*/
1914 {
1915 /* ownPaRAMSets */
1916 /* 31 0 63 32 95 64 127 96 */
1917 {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
1918 /* 159 128 191 160 223 192 255 224 */
1919 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1920 /* 287 256 319 288 351 320 383 352 */
1921 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1922 /* 415 384 447 416 479 448 511 480 */
1923 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,},
1925 /* ownDmaChannels */
1926 /* 31 0 63 32 */
1927 {0xFFFFFFFFU, 0xFFFFFFFFU},
1929 /* ownQdmaChannels */
1930 /* 31 0 */
1931 {0x000000FFU},
1933 /* ownTccs */
1934 /* 31 0 63 32 */
1935 {0xFFFFFFFFU, 0xFFFFFFFFU},
1937 /* resvdPaRAMSets */
1938 /* 31 0 63 32 95 64 127 96 */
1939 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1940 /* 159 128 191 160 223 192 255 224 */
1941 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1942 /* 287 256 319 288 351 320 383 352 */
1943 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1944 /* 415 384 447 416 479 448 511 480 */
1945 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
1947 /* resvdDmaChannels */
1948 /* 31 0 63 32 */
1949 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_EVEEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_EVEEDMA},
1951 /* resvdQdmaChannels */
1952 /* 31 0 */
1953 {0x00U},
1955 /* resvdTccs */
1956 /* 31 0 63 32 */
1957 {0x00U, 0x00U},
1958 },
1960 /* Resources owned/reserved by region 2 (Not Associated to any core supported)*/
1961 {
1962 /* ownPaRAMSets */
1963 /* 31 0 63 32 95 64 127 96 */
1964 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1965 /* 159 128 191 160 223 192 255 224 */
1966 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1967 /* 287 256 319 288 351 320 383 352 */
1968 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1969 /* 415 384 447 416 479 448 511 480 */
1970 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
1972 /* ownDmaChannels */
1973 /* 31 0 63 32 */
1974 {0x00000000U, 0x00000000U},
1976 /* ownQdmaChannels */
1977 /* 31 0 */
1978 {0x00000000U},
1980 /* ownTccs */
1981 /* 31 0 63 32 */
1982 {0x00000000U, 0x00000000U},
1984 /* resvdPaRAMSets */
1985 /* 31 0 63 32 95 64 127 96 */
1986 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1987 /* 159 128 191 160 223 192 255 224 */
1988 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1989 /* 287 256 319 288 351 320 383 352 */
1990 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
1991 /* 415 384 447 416 479 448 511 480 */
1992 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
1994 /* resvdDmaChannels */
1995 /* 31 0 63 32 */
1996 {0x00000000U, 0x00000000U},
1998 /* resvdQdmaChannels */
1999 /* 31 0 */
2000 {0x00000000U},
2002 /* resvdTccs */
2003 /* 31 0 63 32 */
2004 {0x00000000U, 0x00000000U},
2005 },
2007 /* Resources owned/reserved by region 3 (Not Associated to any core supported)*/
2008 {
2009 /* ownPaRAMSets */
2010 /* 31 0 63 32 95 64 127 96 */
2011 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
2012 /* 159 128 191 160 223 192 255 224 */
2013 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
2014 /* 287 256 319 288 351 320 383 352 */
2015 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
2016 /* 415 384 447 416 479 448 511 480 */
2017 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
2019 /* ownDmaChannels */
2020 /* 31 0 63 32 */
2021 {0x00000000U, 0x00000000U},
2023 /* ownQdmaChannels */
2024 /* 31 0 */
2025 {0x00000000U},
2027 /* ownTccs */
2028 /* 31 0 63 32 */
2029 {0x00000000U, 0x00000000U},
2031 /* resvdPaRAMSets */
2032 /* 31 0 63 32 95 64 127 96 */
2033 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
2034 /* 159 128 191 160 223 192 255 224 */
2035 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
2036 /* 287 256 319 288 351 320 383 352 */
2037 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
2038 /* 415 384 447 416 479 448 511 480 */
2039 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
2041 /* resvdDmaChannels */
2042 /* 31 0 63 32 */
2043 {0x00000000U, 0x00000000U},
2045 /* resvdQdmaChannels */
2046 /* 31 0 */
2047 {0x00000000U},
2049 /* resvdTccs */
2050 /* 31 0 63 32 */
2051 {0x00000000U, 0x00000000U},
2052 },
2054 /* Resources owned/reserved by region 4 (Not Associated to any core supported)*/
2055 {
2056 /* ownPaRAMSets */
2057 /* 31 0 63 32 95 64 127 96 */
2058 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
2059 /* 159 128 191 160 223 192 255 224 */
2060 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
2061 /* 287 256 319 288 351 320 383 352 */
2062 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
2063 /* 415 384 447 416 479 448 511 480 */
2064 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
2066 /* ownDmaChannels */
2067 /* 31 0 63 32 */
2068 {0x00000000U, 0x00000000U},
2070 /* ownQdmaChannels */
2071 /* 31 0 */
2072 {0x00000000U},
2074 /* ownTccs */
2075 /* 31 0 63 32 */
2076 {0x00000000U, 0x00000000U},
2078 /* resvdPaRAMSets */
2079 /* 31 0 63 32 95 64 127 96 */
2080 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
2081 /* 159 128 191 160 223 192 255 224 */
2082 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
2083 /* 287 256 319 288 351 320 383 352 */
2084 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
2085 /* 415 384 447 416 479 448 511 480 */
2086 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
2088 /* resvdDmaChannels */
2089 /* 31 0 63 32 */
2090 {0x00000000U, 0x00000000U},
2092 /* resvdQdmaChannels */
2093 /* 31 0 */
2094 {0x00000000U},
2096 /* resvdTccs */
2097 /* 31 0 63 32 */
2098 {0x00000000U, 0x00000000U},
2099 },
2101 /* Resources owned/reserved by region 5 (Not Associated to any core supported)*/
2102 {
2103 /* ownPaRAMSets */
2104 /* 31 0 63 32 95 64 127 96 */
2105 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
2106 /* 159 128 191 160 223 192 255 224 */
2107 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
2108 /* 287 256 319 288 351 320 383 352 */
2109 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
2110 /* 415 384 447 416 479 448 511 480 */
2111 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
2113 /* ownDmaChannels */
2114 /* 31 0 63 32 */
2115 {0x00000000U, 0x00000000U},
2117 /* ownQdmaChannels */
2118 /* 31 0 */
2119 {0x00000000U},
2121 /* ownTccs */
2122 /* 31 0 63 32 */
2123 {0x00000000U, 0x00000000U},
2125 /* resvdPaRAMSets */
2126 /* 31 0 63 32 95 64 127 96 */
2127 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
2128 /* 159 128 191 160 223 192 255 224 */
2129 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
2130 /* 287 256 319 288 351 320 383 352 */
2131 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
2132 /* 415 384 447 416 479 448 511 480 */
2133 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
2135 /* resvdDmaChannels */
2136 /* 31 0 63 32 */
2137 {0x00000000U, 0x00000000U},
2139 /* resvdQdmaChannels */
2140 /* 31 0 */
2141 {0x00000000U},
2143 /* resvdTccs */
2144 /* 31 0 63 32 */
2145 {0x00000000U, 0x00000000U},
2146 },
2148 /* Resources owned/reserved by region 6 (Not Associated to any core supported)*/
2149 {
2150 /* ownPaRAMSets */
2151 /* 31 0 63 32 95 64 127 96 */
2152 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
2153 /* 159 128 191 160 223 192 255 224 */
2154 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
2155 /* 287 256 319 288 351 320 383 352 */
2156 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
2157 /* 415 384 447 416 479 448 511 480 */
2158 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
2160 /* ownDmaChannels */
2161 /* 31 0 63 32 */
2162 {0x00000000U, 0x00000000U},
2164 /* ownQdmaChannels */
2165 /* 31 0 */
2166 {0x00000000U},
2168 /* ownTccs */
2169 /* 31 0 63 32 */
2170 {0x00000000U, 0x00000000U},
2172 /* resvdPaRAMSets */
2173 /* 31 0 63 32 95 64 127 96 */
2174 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
2175 /* 159 128 191 160 223 192 255 224 */
2176 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
2177 /* 287 256 319 288 351 320 383 352 */
2178 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
2179 /* 415 384 447 416 479 448 511 480 */
2180 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
2182 /* resvdDmaChannels */
2183 /* 31 0 63 32 */
2184 {0x00000000U, 0x00000000U},
2186 /* resvdQdmaChannels */
2187 /* 31 0 */
2188 {0x00000000U},
2190 /* resvdTccs */
2191 /* 31 0 63 32 */
2192 {0x00000000U, 0x00000000U},
2193 },
2195 /* Resources owned/reserved by region 7 (Not Associated to any core supported)*/
2196 {
2197 /* ownPaRAMSets */
2198 /* 31 0 63 32 95 64 127 96 */
2199 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
2200 /* 159 128 191 160 223 192 255 224 */
2201 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
2202 /* 287 256 319 288 351 320 383 352 */
2203 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
2204 /* 415 384 447 416 479 448 511 480 */
2205 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
2207 /* ownDmaChannels */
2208 /* 31 0 63 32 */
2209 {0x00000000U, 0x00000000U},
2211 /* ownQdmaChannels */
2212 /* 31 0 */
2213 {0x00000000U},
2215 /* ownTccs */
2216 /* 31 0 63 32 */
2217 {0x00000000U, 0x00000000U},
2219 /* resvdPaRAMSets */
2220 /* 31 0 63 32 95 64 127 96 */
2221 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
2222 /* 159 128 191 160 223 192 255 224 */
2223 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
2224 /* 287 256 319 288 351 320 383 352 */
2225 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
2226 /* 415 384 447 416 479 448 511 480 */
2227 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
2229 /* resvdDmaChannels */
2230 /* 31 0 63 32 */
2231 {0x00000000U, 0x00000000U},
2233 /* resvdQdmaChannels */
2234 /* 31 0 */
2235 {0x00000000U},
2237 /* resvdTccs */
2238 /* 31 0 63 32 */
2239 {0x00000000U, 0x00000000U},
2240 },
2241 },
2242 };
2244 /* Driver Instance Cross bar event to channel map Initialization Configuration */
2245 EDMA3_RM_GblXbarToChanConfigParams sampleXbarChanInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
2246 {
2247 /* EDMA3 INSTANCE# 0 */
2248 {
2249 /* Event to channel map for region 0 */
2250 {
2251 {-1, -1, -1, -1, -1, -1, -1, -1,
2252 -1, -1, -1, -1, -1, -1, -1, -1,
2253 -1, -1, -1, -1, -1, -1, -1, -1,
2254 -1, -1, -1, -1, -1, -1, -1, -1,
2255 -1, -1, -1, -1, -1, -1, -1, -1,
2256 -1, -1, -1, -1, -1, -1, -1, -1,
2257 -1, -1, -1, -1, -1, -1, -1, -1,
2258 -1, -1, -1, -1, -1, -1, -1}
2259 },
2260 /* Event to channel map for region 1 */
2261 {
2262 {-1, -1, -1, -1, -1, -1, -1, -1,
2263 -1, -1, -1, -1, -1, -1, -1, -1,
2264 -1, -1, -1, -1, -1, -1, -1, -1,
2265 -1, -1, -1, -1, -1, -1, -1, -1,
2266 -1, -1, -1, -1, -1, -1, -1, -1,
2267 -1, -1, -1, -1, -1, -1, -1, -1,
2268 -1, -1, -1, -1, -1, -1, -1, -1,
2269 -1, -1, -1, -1, -1, -1, -1}
2270 },
2271 /* Event to channel map for region 2 */
2272 {
2273 {-1, -1, -1, -1, -1, -1, -1, -1,
2274 -1, -1, -1, -1, -1, -1, -1, -1,
2275 -1, -1, -1, -1, -1, -1, -1, -1,
2276 -1, -1, -1, -1, -1, -1, -1, -1,
2277 -1, -1, -1, -1, -1, -1, -1, -1,
2278 -1, -1, -1, -1, -1, -1, -1, -1,
2279 -1, -1, -1, -1, -1, -1, -1, -1,
2280 -1, -1, -1, -1, -1, -1, -1}
2281 },
2282 /* Event to channel map for region 3 */
2283 {
2284 {-1, -1, -1, -1, -1, -1, -1, -1,
2285 -1, -1, -1, -1, -1, -1, -1, -1,
2286 -1, -1, -1, -1, -1, -1, -1, -1,
2287 -1, -1, -1, -1, -1, -1, -1, -1,
2288 -1, -1, -1, -1, -1, -1, -1, -1,
2289 -1, -1, -1, -1, -1, -1, -1, -1,
2290 -1, -1, -1, -1, -1, -1, -1, -1,
2291 -1, -1, -1, -1, -1, -1, -1}
2292 },
2293 /* Event to channel map for region 4 */
2294 {
2295 {-1, -1, -1, -1, -1, -1, -1, -1,
2296 -1, -1, -1, -1, -1, -1, -1, -1,
2297 -1, -1, -1, -1, -1, -1, -1, -1,
2298 -1, -1, -1, -1, -1, -1, -1, -1,
2299 -1, -1, -1, -1, -1, -1, -1, -1,
2300 -1, -1, -1, -1, -1, -1, -1, -1,
2301 -1, -1, -1, -1, -1, -1, -1, -1,
2302 -1, -1, -1, -1, -1, -1, -1}
2303 },
2304 /* Event to channel map for region 5 */
2305 {
2306 {-1, -1, -1, -1, -1, -1, -1, -1,
2307 -1, -1, -1, -1, -1, -1, -1, -1,
2308 -1, -1, -1, -1, -1, -1, -1, -1,
2309 -1, -1, -1, -1, -1, -1, -1, -1,
2310 -1, -1, -1, -1, -1, -1, -1, -1,
2311 -1, -1, -1, -1, -1, -1, -1, -1,
2312 -1, -1, -1, -1, -1, -1, -1, -1,
2313 -1, -1, -1, -1, -1, -1, -1}
2314 },
2315 /* Event to channel map for region 6 */
2316 {
2317 {-1, -1, -1, -1, -1, -1, -1, -1,
2318 -1, -1, -1, -1, -1, -1, -1, -1,
2319 -1, -1, -1, -1, -1, -1, -1, -1,
2320 -1, -1, -1, -1, -1, -1, -1, -1,
2321 -1, -1, -1, -1, -1, -1, -1, -1,
2322 -1, -1, -1, -1, -1, -1, -1, -1,
2323 -1, -1, -1, -1, -1, -1, -1, -1,
2324 -1, -1, -1, -1, -1, -1, -1}
2325 },
2326 /* Event to channel map for region 7 */
2327 {
2328 {-1, -1, -1, -1, -1, -1, -1, -1,
2329 -1, -1, -1, -1, -1, -1, -1, -1,
2330 -1, -1, -1, -1, -1, -1, -1, -1,
2331 -1, -1, -1, -1, -1, -1, -1, -1,
2332 -1, -1, -1, -1, -1, -1, -1, -1,
2333 -1, -1, -1, -1, -1, -1, -1, -1,
2334 -1, -1, -1, -1, -1, -1, -1, -1,
2335 -1, -1, -1, -1, -1, -1, -1}
2336 },
2337 },
2338 /* EDMA3 INSTANCE# 1 */
2339 {
2340 /* Event to channel map for region 0 */
2341 {
2342 {-1, -1, -1, -1, -1, -1, -1, -1,
2343 -1, -1, -1, -1, -1, -1, -1, -1,
2344 -1, -1, -1, -1, -1, -1, -1, -1,
2345 -1, -1, -1, -1, -1, -1, -1, -1,
2346 -1, -1, -1, -1, -1, -1, -1, -1,
2347 -1, -1, -1, -1, -1, -1, -1, -1,
2348 -1, -1, -1, -1, -1, -1, -1, -1,
2349 -1, -1, -1, -1, -1, -1, -1}
2350 },
2351 /* Event to channel map for region 1 */
2352 {
2353 {-1, -1, -1, -1, -1, -1, -1, -1,
2354 -1, -1, -1, -1, -1, -1, -1, -1,
2355 -1, -1, -1, -1, -1, -1, -1, -1,
2356 -1, -1, -1, -1, -1, -1, -1, -1,
2357 -1, -1, -1, -1, -1, -1, -1, -1,
2358 -1, -1, -1, -1, -1, -1, -1, -1,
2359 -1, -1, -1, -1, -1, -1, -1, -1,
2360 -1, -1, -1, -1, -1, -1, -1}
2361 },
2362 /* Event to channel map for region 2 */
2363 {
2364 {-1, -1, -1, -1, -1, -1, -1, -1,
2365 -1, -1, -1, -1, -1, -1, -1, -1,
2366 -1, -1, -1, -1, -1, -1, -1, -1,
2367 -1, -1, -1, -1, -1, -1, -1, -1,
2368 -1, -1, -1, -1, -1, -1, -1, -1,
2369 -1, -1, -1, -1, -1, -1, -1, -1,
2370 -1, -1, -1, -1, -1, -1, -1, -1,
2371 -1, -1, -1, -1, -1, -1, -1}
2372 },
2373 /* Event to channel map for region 3 */
2374 {
2375 {-1, -1, -1, -1, -1, -1, -1, -1,
2376 -1, -1, -1, -1, -1, -1, -1, -1,
2377 -1, -1, -1, -1, -1, -1, -1, -1,
2378 -1, -1, -1, -1, -1, -1, -1, -1,
2379 -1, -1, -1, -1, -1, -1, -1, -1,
2380 -1, -1, -1, -1, -1, -1, -1, -1,
2381 -1, -1, -1, -1, -1, -1, -1, -1,
2382 -1, -1, -1, -1, -1, -1, -1}
2383 },
2384 /* Event to channel map for region 4 */
2385 {
2386 {-1, -1, -1, -1, -1, -1, -1, -1,
2387 -1, -1, -1, -1, -1, -1, -1, -1,
2388 -1, -1, -1, -1, -1, -1, -1, -1,
2389 -1, -1, -1, -1, -1, -1, -1, -1,
2390 -1, -1, -1, -1, -1, -1, -1, -1,
2391 -1, -1, -1, -1, -1, -1, -1, -1,
2392 -1, -1, -1, -1, -1, -1, -1, -1,
2393 -1, -1, -1, -1, -1, -1, -1}
2394 },
2395 /* Event to channel map for region 5 */
2396 {
2397 {-1, -1, -1, -1, -1, -1, -1, -1,
2398 -1, -1, -1, -1, -1, -1, -1, -1,
2399 -1, -1, -1, -1, -1, -1, -1, -1,
2400 -1, -1, -1, -1, -1, -1, -1, -1,
2401 -1, -1, -1, -1, -1, -1, -1, -1,
2402 -1, -1, -1, -1, -1, -1, -1, -1,
2403 -1, -1, -1, -1, -1, -1, -1, -1,
2404 -1, -1, -1, -1, -1, -1, -1}
2405 },
2406 /* Event to channel map for region 6 */
2407 {
2408 {-1, -1, -1, -1, -1, -1, -1, -1,
2409 -1, -1, -1, -1, -1, -1, -1, -1,
2410 -1, -1, -1, -1, -1, -1, -1, -1,
2411 -1, -1, -1, -1, -1, -1, -1, -1,
2412 -1, -1, -1, -1, -1, -1, -1, -1,
2413 -1, -1, -1, -1, -1, -1, -1, -1,
2414 -1, -1, -1, -1, -1, -1, -1, -1,
2415 -1, -1, -1, -1, -1, -1, -1}
2416 },
2417 /* Event to channel map for region 7 */
2418 {
2419 {-1, -1, -1, -1, -1, -1, -1, -1,
2420 -1, -1, -1, -1, -1, -1, -1, -1,
2421 -1, -1, -1, -1, -1, -1, -1, -1,
2422 -1, -1, -1, -1, -1, -1, -1, -1,
2423 -1, -1, -1, -1, -1, -1, -1, -1,
2424 -1, -1, -1, -1, -1, -1, -1, -1,
2425 -1, -1, -1, -1, -1, -1, -1, -1,
2426 -1, -1, -1, -1, -1, -1, -1}
2427 },
2428 },
2429 /* EDMA3 INSTANCE# 2 */
2430 {
2431 /* Event to channel map for region 0 */
2432 {
2433 {-1, -1, -1, -1, -1, -1, -1, -1,
2434 -1, -1, -1, -1, -1, -1, -1, -1,
2435 -1, -1, -1, -1, -1, -1, -1, -1,
2436 -1, -1, -1, -1, -1, -1, -1, -1,
2437 -1, -1, -1, -1, -1, -1, -1, -1,
2438 -1, -1, -1, -1, -1, -1, -1, -1,
2439 -1, -1, -1, -1, -1, -1, -1, -1,
2440 -1, -1, -1, -1, -1, -1, -1}
2441 },
2442 /* Event to channel map for region 1 */
2443 {
2444 {-1, -1, -1, -1, -1, -1, -1, -1,
2445 -1, -1, -1, -1, -1, -1, -1, -1,
2446 -1, -1, -1, -1, -1, -1, -1, -1,
2447 -1, -1, -1, -1, -1, -1, -1, -1,
2448 -1, -1, -1, -1, -1, -1, -1, -1,
2449 -1, -1, -1, -1, -1, -1, -1, -1,
2450 -1, -1, -1, -1, -1, -1, -1, -1,
2451 -1, -1, -1, -1, -1, -1, -1}
2452 },
2453 /* Event to channel map for region 2 */
2454 {
2455 {-1, -1, -1, -1, -1, -1, -1, -1,
2456 -1, -1, -1, -1, -1, -1, -1, -1,
2457 -1, -1, -1, -1, -1, -1, -1, -1,
2458 -1, -1, -1, -1, -1, -1, -1, -1,
2459 -1, -1, -1, -1, -1, -1, -1, -1,
2460 -1, -1, -1, -1, -1, -1, -1, -1,
2461 -1, -1, -1, -1, -1, -1, -1, -1,
2462 -1, -1, -1, -1, -1, -1, -1}
2463 },
2464 /* Event to channel map for region 3 */
2465 {
2466 {-1, -1, -1, -1, -1, -1, -1, -1,
2467 -1, -1, -1, -1, -1, -1, -1, -1,
2468 -1, -1, -1, -1, -1, -1, -1, -1,
2469 -1, -1, -1, -1, -1, -1, -1, -1,
2470 -1, -1, -1, -1, -1, -1, -1, -1,
2471 -1, -1, -1, -1, -1, -1, -1, -1,
2472 -1, -1, -1, -1, -1, -1, -1, -1,
2473 -1, -1, -1, -1, -1, -1, -1}
2474 },
2475 /* Event to channel map for region 4 */
2476 {
2477 {-1, -1, -1, -1, -1, -1, -1, -1,
2478 -1, -1, -1, -1, -1, -1, -1, -1,
2479 -1, -1, -1, -1, -1, -1, -1, -1,
2480 -1, -1, -1, -1, -1, -1, -1, -1,
2481 -1, -1, -1, -1, -1, -1, -1, -1,
2482 -1, -1, -1, -1, -1, -1, -1, -1,
2483 -1, -1, -1, -1, -1, -1, -1, -1,
2484 -1, -1, -1, -1, -1, -1, -1}
2485 },
2486 /* Event to channel map for region 5 */
2487 {
2488 {-1, -1, -1, -1, -1, -1, -1, -1,
2489 -1, -1, -1, -1, -1, -1, -1, -1,
2490 -1, -1, -1, -1, -1, -1, -1, -1,
2491 -1, -1, -1, -1, -1, -1, -1, -1,
2492 -1, -1, -1, -1, -1, -1, -1, -1,
2493 -1, -1, -1, -1, -1, -1, -1, -1,
2494 -1, -1, -1, -1, -1, -1, -1, -1,
2495 -1, -1, -1, -1, -1, -1, -1}
2496 },
2497 /* Event to channel map for region 6 */
2498 {
2499 {-1, -1, -1, -1, -1, -1, -1, -1,
2500 -1, -1, -1, -1, -1, -1, -1, -1,
2501 -1, -1, -1, -1, -1, -1, -1, -1,
2502 -1, -1, -1, -1, -1, -1, -1, -1,
2503 -1, -1, -1, -1, -1, -1, -1, -1,
2504 -1, -1, -1, -1, -1, -1, -1, -1,
2505 -1, -1, -1, -1, -1, -1, -1, -1,
2506 -1, -1, -1, -1, -1, -1, -1}
2507 },
2508 /* Event to channel map for region 7 */
2509 {
2510 {-1, -1, -1, -1, -1, -1, -1, -1,
2511 -1, -1, -1, -1, -1, -1, -1, -1,
2512 -1, -1, -1, -1, -1, -1, -1, -1,
2513 -1, -1, -1, -1, -1, -1, -1, -1,
2514 -1, -1, -1, -1, -1, -1, -1, -1,
2515 -1, -1, -1, -1, -1, -1, -1, -1,
2516 -1, -1, -1, -1, -1, -1, -1, -1,
2517 -1, -1, -1, -1, -1, -1, -1}
2518 },
2519 }
2520 };
2522 /* End of File */