packages/ti/sdo/edma3/rm/sample/src/platforms/sample_ti814x_int_reg.c

   1 /*
   2  * sample_ti814x_int_reg.c
   3  *
   4  * Platform specific interrupt registration and un-registration routines.
   5  *
   6  * Copyright (C) 2009-2017 Texas Instruments Incorporated - http://www.ti.com/
   7  *
   8  *
   9  *  Redistribution and use in source and binary forms, with or without
  10  *  modification, are permitted provided that the following conditions
  11  *  are met:
  12  *
  13  *    Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  *
  16  *    Redistributions in binary form must reproduce the above copyright
  17  *    notice, this list of conditions and the following disclaimer in the
  18  *    documentation and/or other materials provided with the
  19  *    distribution.
  20  *
  21  *    Neither the name of Texas Instruments Incorporated nor the names of
  22  *    its contributors may be used to endorse or promote products derived
  23  *    from this software without specific prior written permission.
  24  *
  25  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  26  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  27  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  28  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  29  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  30  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  31  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  32  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  33  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  34  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  35  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36  *
  37 */
  38
  39 #include <ti/sysbios/knl/Semaphore.h>
  40 #include <ti/sysbios/family/c64p/EventCombiner.h>
  41 #include <ti/sysbios/family/c64p/Hwi.h>
  42
  43 #include <ti/sdo/edma3/rm/sample/bios6_edma3_rm_sample.h>
  44
  45 /**
  46   * EDMA3 TC ISRs which need to be registered with the underlying OS by the user
  47   * (Not all TC error ISRs need to be registered, register only for the
  48   * available Transfer Controllers).
  49   */
  50 void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(uint32_t arg) =
  51                                                 {
  52                                                 &lisrEdma3TC0ErrHandler0,
  53                                                 &lisrEdma3TC1ErrHandler0,
  54                                                 &lisrEdma3TC2ErrHandler0,
  55                                                 &lisrEdma3TC3ErrHandler0,
  56                                                 &lisrEdma3TC4ErrHandler0,
  57                                                 &lisrEdma3TC5ErrHandler0,
  58                                                 &lisrEdma3TC6ErrHandler0,
  59                                                 &lisrEdma3TC7ErrHandler0,
  60                                                 };
  61
  62 extern uint32_t ccXferCompInt[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGIONS];
  63 extern uint32_t ccErrorInt[EDMA3_MAX_EDMA3_INSTANCES];
  64 extern uint32_t tcErrorInt[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_TC];
  65 extern uint32_t numEdma3Tc[EDMA3_MAX_EDMA3_INSTANCES];
  66
  67 /**
  68  * Variables which will be used internally for referring the hardware interrupt
  69  * for various EDMA3 interrupts.
  70  */
  71 extern uint32_t hwIntXferComp[EDMA3_MAX_EDMA3_INSTANCES];
  72 extern uint32_t hwIntCcErr[EDMA3_MAX_EDMA3_INSTANCES];
  73 extern uint32_t hwIntTcErr[EDMA3_MAX_EDMA3_INSTANCES];
  74
  75 extern uint32_t dsp_num;
  76
  77 /* External Instance Specific Configuration Structure */
  78 extern EDMA3_RM_GblXbarToChanConfigParams
  79                                                                 sampleXbarChanInitConfig[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGIONS];
  80
  81 typedef struct  {
  82     volatile Uint32 DSP_INTMUX[21];
  83     volatile Uint32 DUCATI_INTMUX[15];
  84     volatile Uint32 TPCC_EVTMUX[16];
  85     volatile Uint32 TIMER_EVTCAPT;
  86     volatile Uint32 GPIO_MUX;
  87 } CSL_IntmuxRegs;
  88
  89 typedef volatile CSL_IntmuxRegs     *CSL_IntmuxRegsOvly;
  90
  91
  92 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_MASK (0x3F000000U)
  93 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_SHIFT (0x00000018U)
  94 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_RESETVAL (0x00000000U)
  95
  96
  97 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_MASK (0x003F0000U)
  98 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_SHIFT (0x00000010U)
  99 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_RESETVAL (0x00000000U)
 100
 101
 102 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK (0x00003F00U)
 103 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT (0x00000008U)
 104 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_RESETVAL (0x00000000U)
 105
 106
 107 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK (0x0000003FU)
 108 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_SHIFT (0x00000000U)
 109 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_RESETVAL (0x00000000U)
 110
 111
 112 #define EDMA3_MAX_CROSS_BAR_EVENTS_TI814X (95U)
 113 #define EDMA3_NUM_TCC                     (64U)
 114
 115 /*
 116  * Forward decleration
 117  */
 118 EDMA3_RM_Result sampleMapXbarEvtToChan (uint32_t eventNum,
 119                  uint32_t *chanNum,
 120                  const EDMA3_RM_GblXbarToChanConfigParams * edmaGblXbarConfig);
 121 EDMA3_RM_Result sampleConfigScr (uint32_t eventNum,
 122                                   uint32_t chanNum);
 123
 124 /**  To Unregister the ISRs with the underlying OS, if previously registered. */
 125 void unregisterEdma3Interrupts (uint32_t edma3Id);
 126
 127 EDMA3_RM_Result sampleInitXbarEvt(EDMA3_RM_Handle hEdma,
 128                                    uint32_t edma3Id);
 129
 130 /**  To Register the ISRs with the underlying OS, if required. */
 131 void registerEdma3Interrupts (uint32_t edma3Id);
 132
 133 /**  To Register the ISRs with the underlying OS, if required. */
 134 void registerEdma3Interrupts (uint32_t edma3Id)
 135     {
 136     static UInt32 cookie = 0;
 137     uint32_t numTc = 0;
 138
 139     /* Disabling the global interrupts */
 140     cookie = Hwi_disable();
 141
 142     /* Enable the Xfer Completion Event Interrupt */
 143     EventCombiner_dispatchPlug(ccXferCompInt[edma3Id][dsp_num],
 144                                                 (EventCombiner_FuncPtr)(&lisrEdma3ComplHandler0),
 145                                 edma3Id, (Bool)1);
 146     EventCombiner_enableEvent(ccXferCompInt[edma3Id][dsp_num]);
 147
 148     /* Enable the CC Error Event Interrupt */
 149     EventCombiner_dispatchPlug(ccErrorInt[edma3Id],
 150                                                 (EventCombiner_FuncPtr)(&lisrEdma3CCErrHandler0),
 151                                                 edma3Id, (Bool)1);
 152     EventCombiner_enableEvent(ccErrorInt[edma3Id]);
 153
 154     /* Enable the TC Error Event Interrupt, according to the number of TCs. */
 155     while (numTc < numEdma3Tc[edma3Id])
 156             {
 157         EventCombiner_dispatchPlug(tcErrorInt[edma3Id][numTc],
 158                             (EventCombiner_FuncPtr)(ptrEdma3TcIsrHandler[numTc]),
 159                             edma3Id, (Bool)1);
 160         EventCombiner_enableEvent(tcErrorInt[edma3Id][numTc]);
 161         numTc++;
 162         }
 163
 164    /**
 165     * Enabling the HWI_ID.
 166     * EDMA3 interrupts (transfer completion, CC error etc.)
 167     * correspond to different ECM events (SoC specific). These ECM events come
 168     * under ECM block XXX (handling those specific ECM events). Normally, block
 169     * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events
 170     * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)
 171     * is mapped to a specific HWI_INT YYY in the tcf file. So to enable this
 172     * mapped HWI_INT YYY, one should use the corresponding bitmask in the
 173     * API C64_enableIER(), in which the YYY bit is SET.
 174     */
 175     Hwi_enableInterrupt(hwIntXferComp[edma3Id]);
 176     Hwi_enableInterrupt(hwIntCcErr[edma3Id]);
 177     Hwi_enableInterrupt(hwIntTcErr[edma3Id]);
 178
 179     /* Restore interrupts */
 180     Hwi_restore(cookie);
 181     }
 182
 183 /**  To Unregister the ISRs with the underlying OS, if previously registered. */
 184 void unregisterEdma3Interrupts (uint32_t edma3Id)
 185     {
 186         static UInt32 cookiee = 0;
 187     uint32_t numTc = 0;
 188
 189     /* Disabling the global interrupts */
 190     cookiee = Hwi_disable();
 191
 192     /* Disable the Xfer Completion Event Interrupt */
 193         EventCombiner_disableEvent(ccXferCompInt[edma3Id][dsp_num]);
 194
 195     /* Disable the CC Error Event Interrupt */
 196         EventCombiner_disableEvent(ccErrorInt[edma3Id]);
 197
 198     /* Enable the TC Error Event Interrupt, according to the number of TCs. */
 199     while (numTc < numEdma3Tc[edma3Id])
 200         {
 201         EventCombiner_disableEvent(tcErrorInt[edma3Id][numTc]);
 202         numTc++;
 203         }
 204
 205     /* Restore interrupts */
 206     Hwi_restore(cookiee);
 207     }
 208
 209 /**
 210  * \brief   sampleMapXbarEvtToChan
 211  *
 212  * This function reads from the sample configuration structure which specifies
 213  * cross bar events mapped to DMA channel.
 214  *
 215  * \return  EDMA3_DRV_SOK if success, else error code
 216  */
 217 EDMA3_RM_Result sampleMapXbarEvtToChan (uint32_t eventNum,
 218                  uint32_t *chanNum,
 219                  const EDMA3_RM_GblXbarToChanConfigParams * edmaGblXbarConfig)
 220         {
 221     EDMA3_RM_Result edma3Result = EDMA3_RM_E_INVALID_PARAM;
 222     uint32_t xbarEvtNum = 0;
 223     int32_t          edmaChanNum = 0;
 224
 225         if ((eventNum >= EDMA3_NUM_TCC) && (eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_TI814X) &&
 226                 (chanNum != NULL) &&
 227                 (edmaGblXbarConfig != NULL))
 228                 {
 229                 xbarEvtNum = eventNum - EDMA3_NUM_TCC;
 230                 edmaChanNum = edmaGblXbarConfig->dmaMapXbarToChan[xbarEvtNum];
 231                 if (edmaChanNum != -1)
 232                         {
 233                         *chanNum = edmaChanNum;
 234                         edma3Result = EDMA3_RM_SOK;
 235                         }
 236                 }
 237         return (edma3Result);
 238         }
 239
 240
 241 /**
 242  * \brief   sampleConfigScr
 243  *
 244  * This function configures control config registers for the cross bar events
 245  * mapped to the EDMA channel.
 246  *
 247  * \return  EDMA3_DRV_SOK if success, else error code
 248  */
 249 EDMA3_RM_Result sampleConfigScr (uint32_t eventNum,
 250                                   uint32_t chanNum)
 251         {
 252     EDMA3_RM_Result edma3Result = EDMA3_RM_SOK;
 253     uint32_t scrChanOffset = 0;
 254     uint32_t scrRegOffset  = 0;
 255     uint32_t xBarEvtNum    = 0;
 256     CSL_IntmuxRegsOvly scrEvtMux = (CSL_IntmuxRegsOvly)(0x08140F00);
 257
 258
 259         if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_TI814X) &&
 260                 (chanNum < EDMA3_NUM_TCC))
 261                 {
 262                 scrRegOffset = chanNum / 4U;
 263                 scrChanOffset = chanNum - (scrRegOffset * 4U);
 264                 xBarEvtNum = (eventNum - EDMA3_NUM_TCC) + 1U;
 265
 266                 switch(scrChanOffset)
 267                         {
 268                         case 0:
 269                                 scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
 270                                         (xBarEvtNum & CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK);
 271                                 break;
 272                         case 1U:
 273                                 scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
 274                                         ((xBarEvtNum << CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT) &
 275                                         (CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK));
 276                                 break;
 277                         case 2U:
 278                                 scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
 279                                         ((xBarEvtNum << CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_SHIFT) &
 280                                         (CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_MASK));
 281                                 break;
 282                         case 3U:
 283                                 scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
 284                                         ((xBarEvtNum << CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_SHIFT) &
 285                                         (CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_MASK));
 286                                 break;
 287                         default:
 288                                 edma3Result = EDMA3_RM_E_INVALID_PARAM;
 289                                 break;
 290                         }
 291                 }
 292         else
 293                 {
 294                 edma3Result = EDMA3_RM_E_INVALID_PARAM;
 295                 }
 296         return edma3Result;
 297         }
 298
 299 EDMA3_RM_Result sampleInitXbarEvt(EDMA3_RM_Handle hEdma,
 300                                    uint32_t edma3Id)
 301     {
 302     EDMA3_DRV_Result retVal = EDMA3_RM_E_INVALID_PARAM;
 303     const EDMA3_RM_GblXbarToChanConfigParams *sampleXbarToChanConfig =
 304                                 &(sampleXbarChanInitConfig[edma3Id][dsp_num]);
 305     if (hEdma != NULL)
 306         {
 307         retVal = EDMA3_RM_initXbarEventMap(hEdma,
 308                                                                         sampleXbarToChanConfig,
 309                                                                         &sampleMapXbarEvtToChan,
 310                                                                         &sampleConfigScr);
 311         }
 312
 313     return retVal;
 314     }
 315
 316 /**
 317  * \brief   enableXferCompInterrupt
 318  *
 319  * This function enables the tranfer completion interrupt of EDMA3.
 320  *
 321  * \return  nil
 322  */
 323 void enableXferCompInterrupt(uint32_t edma3Id)
 324 {
 325     EventCombiner_enableEvent(ccXferCompInt[edma3Id][dsp_num]);
 326 }
 327
 328 /**
 329  * \brief   disableXferCompInterrupt
 330  *
 331  * This function disables the tranfer completion interrupt of EDMA3.
 332  *
 333  * \return  nil
 334  */
 335 void disableXferCompInterrupt(uint32_t edma3Id)
 336 {
 337     EventCombiner_disableEvent(ccXferCompInt[edma3Id][dsp_num]);
 338 }
 339
 340 /**
 341  * \brief   enableErrorInterrupt
 342  *
 343  * This function enables the error interrupt of EDMA3.
 344  *
 345  * \return  nil
 346  */
 347 void enableErrorInterrupt(uint32_t edma3Id)
 348 {
 349     EventCombiner_enableEvent(ccErrorInt[edma3Id]);
 350 }
 351
 352 /**
 353  * \brief   disableErrorInterrupt
 354  *
 355  * This function disables the error interrupt of EDMA3.
 356  *
 357  * \return  nil
 358  */
 359 void disableErrorInterrupt(uint32_t edma3Id)
 360 {
 361     EventCombiner_disableEvent(ccErrorInt[edma3Id]);
 362 }