packages/ti/sdo/edma3/rm/sample/src/platforms/sample_ti814x_m3video_cfg.c

   1 /*
   2  * sample_dm740_cfg.c
   3  *
   4  * Platform specific EDMA3 hardware related information like number of transfer
   5  * controllers, various interrupt ids etc. It is used while interrupts
   6  * enabling / disabling. It needs to be ported for different SoCs.
   7  *
   8  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
   9  *
  10  *
  11  *  Redistribution and use in source and binary forms, with or without
  12  *  modification, are permitted provided that the following conditions
  13  *  are met:
  14  *
  15  *    Redistributions of source code must retain the above copyright
  16  *    notice, this list of conditions and the following disclaimer.
  17  *
  18  *    Redistributions in binary form must reproduce the above copyright
  19  *    notice, this list of conditions and the following disclaimer in the
  20  *    documentation and/or other materials provided with the
  21  *    distribution.
  22  *
  23  *    Neither the name of Texas Instruments Incorporated nor the names of
  24  *    its contributors may be used to endorse or promote products derived
  25  *    from this software without specific prior written permission.
  26  *
  27  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  28  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  29  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  30  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  31  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  32  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  33  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  34  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  35  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  36  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  37  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  38  *
  39 */
  40
  41 #include <ti/sdo/edma3/rm/edma3_rm.h>
  42
  43 /* Number of EDMA3 controllers present in the system */
  44 #define NUM_EDMA3_INSTANCES                     1U
  45 const uint32_t numEdma3Instances = NUM_EDMA3_INSTANCES;
  46
  47 /* Number of DSPs present in the system */
  48 #define NUM_DSPS                                        1U
  49 const uint32_t numDsps = NUM_DSPS;
  50
  51 /* Determine the processor id by reading DNUM register. */
  52 uint16_t determineProcId()
  53         {
  54 #if 0
  55         volatile uint32_t *addr;
  56         uint32_t core_no;
  57
  58     /* Identify the core number */
  59     addr = (uint32_t *)(CGEM_REG_START+0x40000);
  60     core_no = ((*addr) & 0x000F0000)>>16;
  61
  62         return core_no;
  63 #endif
  64         return 4;
  65         }
  66
  67 int8_t*  getGlobalAddr(int8_t* addr)
  68 {
  69      return (addr); /* The address is already a global address */
  70 }
  71
  72 uint16_t isGblConfigRequired(uint32_t dspNum)
  73         {
  74         (void) dspNum;
  75
  76         return 0;
  77         }
  78
  79 /* Semaphore handles */
  80 EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
  81
  82 /** Number of PaRAM Sets available */
  83 #define EDMA3_NUM_PARAMSET                              (512U)
  84 /** Number of TCCS available */
  85 #define EDMA3_NUM_TCC                                   (64U)
  86 /** Number of Event Queues available */
  87 #define EDMA3_NUM_EVTQUE                                (4U)
  88 /** Number of Transfer Controllers available */
  89 #define EDMA3_NUM_TC                                    (4U)
  90 /** Interrupt no. for Transfer Completion */
  91 #define EDMA3_CC_XFER_COMPLETION_INT                    (62)
  92 /** Interrupt no. for CC Error */
  93 #define EDMA3_CC_ERROR_INT                              (46U)
  94 /** Interrupt no. for TCs Error */
  95 #define EDMA3_TC0_ERROR_INT                             (0U)
  96 #define EDMA3_TC1_ERROR_INT                             (0U)
  97 #define EDMA3_TC2_ERROR_INT                             (0U)
  98 #define EDMA3_TC3_ERROR_INT                             (0U)
  99 #define EDMA3_TC4_ERROR_INT                             (0U)
 100 #define EDMA3_TC5_ERROR_INT                             (0U)
 101 #define EDMA3_TC6_ERROR_INT                             (0U)
 102 #define EDMA3_TC7_ERROR_INT                             (0U)
 103
 104 /**
 105 * EDMA3 interrupts (transfer completion, CC error etc.) correspond to different
 106 * ECM events (SoC specific). These ECM events come
 107 * under ECM block XXX (handling those specific ECM events). Normally, block
 108 * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events
 109 * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)
 110 * is mapped to a specific HWI_INT YYY in the tcf file.
 111 * Define EDMA3_HWI_INT_XFER_COMP to specific HWI_INT, corresponding
 112 * to transfer completion interrupt.
 113 * Define EDMA3_HWI_INT_CC_ERR to specific HWI_INT, corresponding
 114 * to CC error interrupts.
 115 * Define EDMA3_HWI_INT_TC_ERR to specific HWI_INT, corresponding
 116 * to TC error interrupts.
 117 */
 118 #define EDMA3_HWI_INT_XFER_COMP                                                 (7U)
 119 #define EDMA3_HWI_INT_CC_ERR                                                    (11U)
 120 #define EDMA3_HWI_INT_TC_ERR                                                    (11U)
 121
 122
 123 /**
 124  * \brief Mapping of DMA channels 0-31 to Hardware Events from
 125  * various peripherals, which use EDMA for data transfer.
 126  * All channels need not be mapped, some can be free also.
 127  * 1: Mapped
 128  * 0: Not mapped
 129  *
 130  * This mapping will be used to allocate DMA channels when user passes
 131  * EDMA3_rm_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
 132  * copy). The same mapping is used to allocate the TCC when user passes
 133  * EDMA3_rm_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
 134  *
 135  * To allocate more DMA channels or TCCs, one has to modify the event mapping.
 136  */
 137                                                                                                           /* 31     0 */
 138 #define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0          (0xFFFFFFF0U)
 139
 140 /**
 141  * \brief Mapping of DMA channels 32-63 to Hardware Events from
 142  * various peripherals, which use EDMA for data transfer.
 143  * All channels need not be mapped, some can be free also.
 144  * 1: Mapped
 145  * 0: Not mapped
 146  *
 147  * This mapping will be used to allocate DMA channels when user passes
 148  * EDMA3_rm_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
 149  * copy). The same mapping is used to allocate the TCC when user passes
 150  * EDMA3_rm_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
 151  *
 152  * To allocate more DMA channels or TCCs, one has to modify the event mapping.
 153  */
 154                                                                                                           /* 63     32 */
 155 #define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1          (0x3C7FFFFFU)
 156
 157 /* Variable which will be used internally for referring number of Event Queues. */
 158 uint32_t numEdma3EvtQue[NUM_EDMA3_INSTANCES] = {EDMA3_NUM_EVTQUE};
 159
 160 /* Variable which will be used internally for referring number of TCs. */
 161 uint32_t numEdma3Tc[NUM_EDMA3_INSTANCES] = {EDMA3_NUM_TC};
 162
 163 /**
 164  * Variable which will be used internally for referring transfer completion
 165  * interrupt.
 166  */
 167 uint32_t ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = {
 168                                                         {
 169                                                         EDMA3_CC_XFER_COMPLETION_INT, EDMA3_CC_XFER_COMPLETION_INT, EDMA3_CC_XFER_COMPLETION_INT, EDMA3_CC_XFER_COMPLETION_INT,
 170                                                         EDMA3_CC_XFER_COMPLETION_INT, EDMA3_CC_XFER_COMPLETION_INT, EDMA3_CC_XFER_COMPLETION_INT, EDMA3_CC_XFER_COMPLETION_INT,
 171                                                         },
 172                         };
 173
 174 /**
 175  * Variable which will be used internally for referring channel controller's
 176  * error interrupt.
 177  */
 178 uint32_t ccErrorInt[NUM_EDMA3_INSTANCES] = {EDMA3_CC_ERROR_INT};
 179
 180 /**
 181  * Variable which will be used internally for referring transfer controllers'
 182  * error interrupts.
 183  */
 184 uint32_t tcErrorInt[NUM_EDMA3_INSTANCES][8] =    {
 185                                 {
 186                                 EDMA3_TC0_ERROR_INT, EDMA3_TC1_ERROR_INT,
 187                                 EDMA3_TC2_ERROR_INT, EDMA3_TC3_ERROR_INT,
 188                                 EDMA3_TC4_ERROR_INT, EDMA3_TC5_ERROR_INT,
 189                                 EDMA3_TC6_ERROR_INT, EDMA3_TC7_ERROR_INT,
 190                                 }
 191                             };
 192
 193 /**
 194  * Variables which will be used internally for referring the hardware interrupt
 195  * for various EDMA3 interrupts.
 196  */
 197 uint32_t hwIntXferComp = EDMA3_HWI_INT_XFER_COMP;
 198 uint32_t hwIntCcErr = EDMA3_HWI_INT_CC_ERR;
 199 uint32_t hwIntTcErr = EDMA3_HWI_INT_TC_ERR;
 200
 201
 202 /* Driver Object Initialization Configuration */
 203 EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
 204         {
 205             {
 206             /** Total number of DMA Channels supported by the EDMA3 Controller */
 207             64U,
 208             /** Total number of QDMA Channels supported by the EDMA3 Controller */
 209             8U,
 210             /** Total number of TCCs supported by the EDMA3 Controller */
 211             64U,
 212             /** Total number of PaRAM Sets supported by the EDMA3 Controller */
 213             512U,
 214             /** Total number of Event Queues in the EDMA3 Controller */
 215             4U,
 216             /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
 217             4U,
 218             /** Number of Regions on this EDMA3 controller */
 219             5U,
 220
 221             /**
 222              * \brief Channel mapping existence
 223              * A value of 0 (No channel mapping) implies that there is fixed association
 224              * for a channel number to a parameter entry number or, in other words,
 225              * PaRAM entry n corresponds to channel n.
 226              */
 227             1U,
 228
 229             /** Existence of memory protection feature */
 230             1U,
 231
 232             /** Global Register Region of CC Registers */
 233             (void *)0x49000000U,
 234             /** Transfer Controller (TC) Registers */
 235                 {
 236                 (void *)0x49800000U,
 237                 (void *)0x49900000U,
 238                 (void *)0x49A00000U,
 239                 (void *)0x49B00000U,
 240                 (void *)NULL,
 241                 (void *)NULL,
 242                 (void *)NULL,
 243                 (void *)NULL
 244                 },
 245             /** Interrupt no. for Transfer Completion */
 246             EDMA3_CC_XFER_COMPLETION_INT,
 247             /** Interrupt no. for CC Error */
 248             EDMA3_CC_ERROR_INT,
 249             /** Interrupt no. for TCs Error */
 250                 {
 251                 EDMA3_TC0_ERROR_INT,
 252                 EDMA3_TC1_ERROR_INT,
 253                 EDMA3_TC2_ERROR_INT,
 254                 EDMA3_TC3_ERROR_INT,
 255                 EDMA3_TC4_ERROR_INT,
 256                 EDMA3_TC5_ERROR_INT,
 257                 EDMA3_TC6_ERROR_INT,
 258                 EDMA3_TC7_ERROR_INT
 259                 },
 260
 261             /**
 262              * \brief EDMA3 TC priority setting
 263              *
 264              * User can program the priority of the Event Queues
 265              * at a system-wide level.  This means that the user can set the
 266              * priority of an IO initiated by either of the TCs (Transfer Controllers)
 267              * relative to IO initiated by the other bus masters on the
 268              * device (ARM, DSP, USB, etc)
 269              */
 270                 {
 271                 0U,
 272                 1U,
 273                 2U,
 274                 3U,
 275                 0U,
 276                 0U,
 277                 0U,
 278                 0U
 279                 },
 280             /**
 281              * \brief To Configure the Threshold level of number of events
 282              * that can be queued up in the Event queues. EDMA3CC error register
 283              * (CCERR) will indicate whether or not at any instant of time the
 284              * number of events queued up in any of the event queues exceeds
 285              * or equals the threshold/watermark value that is set
 286              * in the queue watermark threshold register (QWMTHRA).
 287              */
 288                 {
 289                 16U,
 290                 16U,
 291                 16U,
 292                 16U,
 293                 0U,
 294                 0U,
 295                 0U,
 296                 0U
 297                 },
 298
 299             /**
 300              * \brief To Configure the Default Burst Size (DBS) of TCs.
 301              * An optimally-sized command is defined by the transfer controller
 302              * default burst size (DBS). Different TCs can have different
 303              * DBS values. It is defined in Bytes.
 304              */
 305                 {
 306                 16U,
 307                 16U,
 308                 16U,
 309                 16U,
 310                 0U,
 311                 0U,
 312                 0U,
 313                 0U
 314                 },
 315
 316             /**
 317              * \brief Mapping from each DMA channel to a Parameter RAM set,
 318              * if it exists, otherwise of no use.
 319              */
 320             {
 321             0U, 1U, 2U, 3U, 4U, 5U, 6U, 7U,
 322             8U, 9U, 10U, 11U, 12U, 13U, 14U, 15U,
 323             16U, 17U, 18U, 19U, 20U, 21U, 22U, 23U,
 324             24U, 25U, 26U, 27U, 28U, 29U, 30U, 31U,
 325             32U, 33U, 34U, 35U, 36U, 37U, 38U, 39U,
 326             40U, 41U, 42U, 43U, 44U, 45U, 46U, 47U,
 327             48U, 49U, 50U, 51U, 52U, 53U, 54U, 55U,
 328             56U, 57U, 58U, 59U, 60U, 61U, 62U, 63U
 329             },
 330
 331              /**
 332               * \brief Mapping from each DMA channel to a TCC. This specific
 333               * TCC code will be returned when the transfer is completed
 334               * on the mapped channel.
 335               */
 336             {
 337             0U, 1U, 2U, 3U,
 338             4U, 5U, 6U, 7U,
 339             8U, 9U, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
 340             12U, 13U, 14U, 15U,
 341             16U, 17U, 18U, 19U,
 342             20U, 21U, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
 343             24U, 25U, 26U, 27U,
 344             28U, 29U, 30U, 31U,
 345             32U, 33U, 34U, 35U,
 346             36U, 37U, 38U, 39U,
 347             40U, 41U, 42U, 43U,
 348             44U, 45U, 46U, 47U,
 349             48U, 49U, 50U, 51U,
 350             52U, 53U, 54U, 55U,
 351             56U, 57U, 58U, 59U,
 352             60U, 61U, 62U, 63U
 353             },
 354
 355
 356             /**
 357              * \brief Mapping of DMA channels to Hardware Events from
 358              * various peripherals, which use EDMA for data transfer.
 359              * All channels need not be mapped, some can be free also.
 360              */
 361                 {
 362                 0x00000000U,
 363                 0x00000000U
 364                 },
 365                 },
 366         };
 367
 368
 369 /* Driver Instance Initialization Configuration */
 370 EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
 371         {
 372                 /* EDMA3 INSTANCE# 0 */
 373                 {
 374                         /* Resources owned/reserved by region 0 */
 375                         {
 376                 /* 31     0     63    32     95    64     127   96 */
 377                 {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
 378                 /* 159  128     191  160     223  192     255  224 */
 379                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
 380                 /* 287  256     319  288     351  320     383  352 */
 381                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
 382                 /* 415  384     447  416     479  448     511  480 */
 383                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,},
 384
 385                 /* ownDmaChannels */
 386                 /* 31     0     63    32 */
 387                 {0xFFFFFFFFU, 0xFFFFFFFFU},
 388
 389                 /* ownQdmaChannels */
 390                 /* 31     0 */
 391                 {0x00000001U},
 392
 393                 /* ownTccs */
 394                 /* 31     0     63    32 */
 395                 {0xFFFFFFFFU, 0xFFFFFFFFU},
 396
 397
 398                 /* Resources reserved by Region 0 */
 399                 /* resvdPaRAMSets */
 400                 /* 31     0     63    32     95    64     127   96 */
 401                 {0xFFFFFFFFU, 0xFFFFFFFFU, 0x00000000U, 0x00000000U,
 402                 /* 159  128     191  160     223  192     255  224 */
 403                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
 404                 /* 287  256     319  288     351  320     383  352 */
 405                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
 406                 /* 415  384     447  416     479  448     511  480 */
 407                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,},
 408
 409                 /* resvdDmaChannels */
 410         /* 31     0    63     32 */
 411         {0x00000000U, 0x00000000U},
 412
 413                 /* resvdQdmaChannels */
 414                 /* 31     0 */
 415                 {0x00000000U},
 416
 417                 /* resvdTccs */
 418         /* 31     0    63     32 */
 419         {0x00000000U, 0x00000000U},
 420                         },
 421
 422                 /* Resources owned/reserved by region 1 */
 423                     {
 424                         /* ownPaRAMSets */
 425                         /* 31     0     63    32     95    64     127   96 */
 426                 {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
 427                 /* 159  128     191  160     223  192     255  224 */
 428                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
 429                 /* 287  256     319  288     351  320     383  352 */
 430                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
 431                 /* 415  384     447  416     479  448     511  480 */
 432                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,},
 433
 434                 /* ownDmaChannels */
 435                 /* 31     0     63    32 */
 436                 {0xFFFFFFFFU, 0xFFFFFFFFU},
 437
 438                 /* ownQdmaChannels */
 439                 /* 31     0 */
 440                 {0x00000002U},
 441
 442                 /* ownTccs */
 443                 /* 31     0     63    32 */
 444                 {0xFFFFFFFFU, 0xFFFFFFFFU},
 445
 446                 /* Resources reserved by Region 1 */
 447                 /* resvdPaRAMSets */
 448                 /* 31     0     63    32     95    64     127   96 */
 449                 {0xFFFFFFFFU, 0xFFFFFFFFU, 0x00000000U, 0x00000000U,
 450                 /* 159  128     191  160     223  192     255  224 */
 451                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
 452                 /* 287  256     319  288     351  320     383  352 */
 453                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
 454                 /* 415  384     447  416     479  448     511  480 */
 455                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,},
 456
 457                 /* resvdDmaChannels */
 458         /* 31     0    63     32 */
 459         {0x00000000U, 0x00000000U},
 460
 461                 /* resvdQdmaChannels */
 462                 /* 31     0 */
 463                 {0x00000000U},
 464
 465                 /* resvdTccs */
 466         /* 31     0    63     32 */
 467         {0x00000000U, 0x00000000U},
 468                     },
 469
 470                 /* Resources owned/reserved by region 2 */
 471                         {
 472                                 /* ownPaRAMSets */
 473                                 /* 31     0     63    32     95    64     127   96 */
 474                 {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
 475                 /* 159  128     191  160     223  192     255  224 */
 476                  0xFFFFFFFFU, 0x00000000U, 0x00000000U, 0x00000000U,
 477                 /* 287  256     319  288     351  320     383  352 */
 478                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
 479                 /* 415  384     447  416     479  448     511  480 */
 480                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,},
 481
 482                 /* ownDmaChannels */
 483                 /* 31     0     63    32 */
 484                 {0xFFFFFFFFU, 0xFFFFFFFFU},
 485
 486                 /* ownQdmaChannels */
 487                 /* 31     0 */
 488                 {0x00000004U},
 489
 490                 /* ownTccs */
 491                 /* 31     0     63    32 */
 492                 {0xFFFFFFFFU, 0xFFFFFFFFU},
 493
 494                 /* Resources reserved by Region 2 */
 495                 /* resvdPaRAMSets */
 496                 /* 31     0     63    32     95    64     127   96 */
 497                 {0xFFFFFFFFU, 0xFFFFFFFFU, 0x00000000U, 0x00000000U,
 498                 /* 159  128     191  160     223  192     255  224 */
 499                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
 500                 /* 287  256     319  288     351  320     383  352 */
 501                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
 502                 /* 415  384     447  416     479  448     511  480 */
 503                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,},
 504
 505                 /* resvdDmaChannels */
 506         /* 31     0    63     32 */
 507         {0x00000000U, 0x00000000U},
 508
 509                 /* resvdQdmaChannels */
 510                 /* 31     0 */
 511                 {0x00000000U},
 512
 513                 /* resvdTccs */
 514         /* 31     0    63     32 */
 515         {0x00000000U, 0x00000000U},
 516                         },
 517
 518                 /* Resources owned/reserved by region 3 */
 519                         {
 520                                 /* ownPaRAMSets */
 521                                 /* 31     0     63    32     95    64     127   96 */
 522                 {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
 523                 /* 159  128     191  160     223  192     255  224 */
 524                  0x00000000U, 0xFFFFFFFFU, 0x00000000U, 0x00000000U,
 525                 /* 287  256     319  288     351  320     383  352 */
 526                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
 527                 /* 415  384     447  416     479  448     511  480 */
 528                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,},
 529
 530                 /* ownDmaChannels */
 531                 /* 31     0     63    32 */
 532                 {0xFFFFFFFFU, 0xFFFFFFFFU},
 533
 534                 /* ownQdmaChannels */
 535                 /* 31     0 */
 536                 {0x00000008U},
 537
 538                 /* ownTccs */
 539                 /* 31     0     63    32 */
 540                 {0xFFFFFFFFU, 0xFFFFFFFFU},
 541
 542                 /* Resources reserved by Region 3 */
 543                 /* resvdPaRAMSets */
 544                 /* 31     0     63    32     95    64     127   96 */
 545                 {0xFFFFFFFFU, 0xFFFFFFFFU, 0x00000000U, 0x00000000U,
 546                 /* 159  128     191  160     223  192     255  224 */
 547                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
 548                 /* 287  256     319  288     351  320     383  352 */
 549                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
 550                 /* 415  384     447  416     479  448     511  480 */
 551                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,},
 552
 553                 /* resvdDmaChannels */
 554                 /* 31     0     63    32 */
 555                 {0x00000000U, 0x00000000U},
 556
 557                 /* resvdQdmaChannels */
 558                 /* 31     0 */
 559                 {0x00000000U},
 560
 561                 /* resvdTccs */
 562                 /* 31     0     63    32 */
 563                 {0x00000000U, 0x00000000U},
 564                         },
 565
 566                 /* Resources owned/reserved by region 4 */
 567                         {
 568                                 /* ownPaRAMSets */
 569                                 /* 31     0     63    32     95    64     127   96 */
 570                 {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
 571                 /* 159  128     191  160     223  192     255  224 */
 572                  0x00000000U, 0x00000000U, 0xFFFFFFFFU, 0x00000000U,
 573                 /* 287  256     319  288     351  320     383  352 */
 574                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
 575                 /* 415  384     447  416     479  448     511  480 */
 576                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,},
 577
 578                 /* ownDmaChannels */
 579                 /* 31     0     63    32 */
 580                 {0xFFFFFFFFU, 0xFFFFFFFFU},
 581
 582                 /* ownQdmaChannels */
 583                 /* 31     0 */
 584                 {0x00000008U},
 585
 586                 /* ownTccs */
 587                 /* 31     0     63    32 */
 588                 {0xFFFFFFFFU, 0xFFFFFFFFU},
 589
 590                 /* Resources reserved by Region 4 */
 591                 /* resvdPaRAMSets */
 592                 /* 31     0     63    32     95    64     127   96 */
 593                 {0xFFFFFFFFU, 0xFFFFFFFFU, 0x00000000U, 0x00000000U,
 594                 /* 159  128     191  160     223  192     255  224 */
 595                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
 596                 /* 287  256     319  288     351  320     383  352 */
 597                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
 598                 /* 415  384     447  416     479  448     511  480 */
 599                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,},
 600
 601                 /* resvdDmaChannels */
 602                 /* 31     0     63    32 */
 603                 {0x00000000U, 0x00000000U},
 604
 605                 /* resvdQdmaChannels */
 606                 /* 31     0 */
 607                 {0x00000000U},
 608
 609                 /* resvdTccs */
 610                 /* 31     0     63    32 */
 611                 {0x00000000U, 0x00000000U},
 612                         },
 613
 614                 /* Resources owned/reserved by region 5 */
 615                         {
 616                                 /* ownPaRAMSets */
 617                                 /* 31     0     63    32     95    64     127   96 */
 618                 {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
 619                 /* 159  128     191  160     223  192     255  224 */
 620                  0x00000000U, 0x00000000U, 0x00000000U, 0xFFFFFFFFU,
 621                 /* 287  256     319  288     351  320     383  352 */
 622                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
 623                 /* 415  384     447  416     479  448     511  480 */
 624                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,},
 625
 626                 /* ownDmaChannels */
 627                 /* 31     0     63    32 */
 628                 {0xFFFFFFFFU, 0xFFFFFFFFU},
 629
 630                 /* ownQdmaChannels */
 631                 /* 31     0 */
 632                 {0x00000008U},
 633
 634                 /* ownTccs */
 635                 /* 31     0     63    32 */
 636                 {0xFFFFFFFFU, 0xFFFFFFFFU},
 637
 638                 /* Resources reserved by Region 5 */
 639                 /* resvdPaRAMSets */
 640                 /* 31     0     63    32     95    64     127   96 */
 641                 {0xFFFFFFFFU, 0xFFFFFFFFU, 0x00000000U, 0x00000000U,
 642                 /* 159  128     191  160     223  192     255  224 */
 643                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
 644                 /* 287  256     319  288     351  320     383  352 */
 645                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
 646                 /* 415  384     447  416     479  448     511  480 */
 647                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,},
 648
 649                 /* resvdDmaChannels */
 650                 /* 31     0     63    32 */
 651                 {0x00000000U, 0x00000000U},
 652
 653                 /* resvdQdmaChannels */
 654                 /* 31     0 */
 655                 {0x00000000U},
 656
 657                 /* resvdTccs */
 658                 /* 31     0     63    32 */
 659                 {0x00000000U, 0x00000000U},
 660                         },
 661
 662                 /* Resources owned/reserved by region 6 */
 663                         {
 664                                 /* ownPaRAMSets */
 665                                 /* 31     0     63    32     95    64     127   96 */
 666                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
 667                                 /* 159  128     191  160     223  192     255  224 */
 668                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
 669                                 /* 287  256     319  288     351  320     383  352 */
 670                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
 671                                 /* 415  384     447  416     479  448     511  480 */
 672                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 673
 674                                 /* ownDmaChannels */
 675                                 /* 31     0     63    32 */
 676                                 {0x00000000U, 0x00000000U},
 677
 678                                 /* ownQdmaChannels */
 679                                 /* 31     0 */
 680                                 {0x00000000U},
 681
 682                                 /* ownTccs */
 683                                 /* 31     0     63    32 */
 684                                 {0x00000000U, 0x00000000U},
 685
 686                                 /* resvdPaRAMSets */
 687                                 /* 31     0     63    32     95    64     127   96 */
 688                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
 689                                 /* 159  128     191  160     223  192     255  224 */
 690                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
 691                                 /* 287  256     319  288     351  320     383  352 */
 692                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
 693                                 /* 415  384     447  416     479  448     511  480 */
 694                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 695
 696                                 /* resvdDmaChannels */
 697                                 /* 31     0     63    32 */
 698                                 {0x00000000U, 0x00000000U},
 699
 700                                 /* resvdQdmaChannels */
 701                                 /* 31     0 */
 702                                 {0x00000000U},
 703
 704                                 /* resvdTccs */
 705                                 /* 31     0     63    32 */
 706                                 {0x00000000U, 0x00000000U},
 707                         },
 708
 709                 /* Resources owned/reserved by region 7 */
 710                         {
 711                                 /* ownPaRAMSets */
 712                                 /* 31     0     63    32     95    64     127   96 */
 713                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
 714                                 /* 159  128     191  160     223  192     255  224 */
 715                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
 716                                 /* 287  256     319  288     351  320     383  352 */
 717                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
 718                                 /* 415  384     447  416     479  448     511  480 */
 719                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 720
 721                                 /* ownDmaChannels */
 722                                 /* 31     0     63    32 */
 723                                 {0x00000000U, 0x00000000U},
 724
 725                                 /* ownQdmaChannels */
 726                                 /* 31     0 */
 727                                 {0x00000000U},
 728
 729                                 /* ownTccs */
 730                                 /* 31     0     63    32 */
 731                                 {0x00000000U, 0x00000000U},
 732
 733                                 /* resvdPaRAMSets */
 734                                 /* 31     0     63    32     95    64     127   96 */
 735                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
 736                                 /* 159  128     191  160     223  192     255  224 */
 737                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
 738                                 /* 287  256     319  288     351  320     383  352 */
 739                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
 740                                 /* 415  384     447  416     479  448     511  480 */
 741                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 742
 743                                 /* resvdDmaChannels */
 744                                 /* 31     0     63    32 */
 745                                 {0x00000000U, 0x00000000U},
 746
 747                                 /* resvdQdmaChannels */
 748                                 /* 31     0 */
 749                                 {0x00000000U},
 750
 751                                 /* resvdTccs */
 752                                 /* 31     0     63    32 */
 753                                 {0x00000000U, 0x00000000U},
 754                         },
 755             },
 756         };
 757
 758
 759
 760 /* End of File */
 761
 762