packages/ti/sdo/edma3/rm/sample/src/platforms/sample_ti816x_cfg.c

   1 /*
   2  * sample_dm740_cfg.c
   3  *
   4  * Platform specific EDMA3 hardware related information like number of transfer
   5  * controllers, various interrupt ids etc. It is used while interrupts
   6  * enabling / disabling. It needs to be ported for different SoCs.
   7  *
   8  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
   9  *
  10  *
  11  *  Redistribution and use in source and binary forms, with or without
  12  *  modification, are permitted provided that the following conditions
  13  *  are met:
  14  *
  15  *    Redistributions of source code must retain the above copyright
  16  *    notice, this list of conditions and the following disclaimer.
  17  *
  18  *    Redistributions in binary form must reproduce the above copyright
  19  *    notice, this list of conditions and the following disclaimer in the
  20  *    documentation and/or other materials provided with the
  21  *    distribution.
  22  *
  23  *    Neither the name of Texas Instruments Incorporated nor the names of
  24  *    its contributors may be used to endorse or promote products derived
  25  *    from this software without specific prior written permission.
  26  *
  27  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  28  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  29  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  30  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  31  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  32  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  33  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  34  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  35  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  36  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  37  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  38  *
  39 */
  40
  41 #include <ti/sdo/edma3/rm/edma3_rm.h>
  42
  43 /* Number of EDMA3 controllers present in the system */
  44 #define NUM_EDMA3_INSTANCES                     1u
  45 const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;
  46
  47 /* Number of DSPs present in the system */
  48 #define NUM_DSPS                                        1u
  49 const unsigned int numDsps = NUM_DSPS;
  50
  51 /* Determine the processor id by reading DNUM register. */
  52 unsigned short determineProcId()
  53         {
  54 #if 0
  55         volatile unsigned int *addr;
  56         unsigned int core_no;
  57
  58     /* Identify the core number */
  59     addr = (unsigned int *)(CGEM_REG_START+0x40000);
  60     core_no = ((*addr) & 0x000F0000)>>16;
  61
  62         return core_no;
  63 #endif
  64         return 1;
  65         }
  66
  67 signed char*  getGlobalAddr(signed char* addr)
  68 {
  69      return (addr); /* The address is already a global address */
  70 }
  71
  72 unsigned short isGblConfigRequired(unsigned int dspNum)
  73         {
  74         (void) dspNum;
  75
  76         return 1;
  77         }
  78
  79 /* Semaphore handles */
  80 EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
  81
  82 /** Number of PaRAM Sets available */
  83 #define EDMA3_NUM_PARAMSET                              (512u)
  84 /** Number of TCCS available */
  85 #define EDMA3_NUM_TCC                                   (64u)
  86 /** Number of Event Queues available */
  87 #define EDMA3_NUM_EVTQUE                                (4u)
  88 /** Number of Transfer Controllers available */
  89 #define EDMA3_NUM_TC                                    (4u)
  90 /** Interrupt no. for Transfer Completion */
  91 #define EDMA3_CC_XFER_COMPLETION_INT                    (20u)
  92 /** Interrupt no. for CC Error */
  93 #define EDMA3_CC_ERROR_INT                              (21u)
  94 /** Interrupt no. for TCs Error */
  95 #define EDMA3_TC0_ERROR_INT                             (22u)
  96 #define EDMA3_TC1_ERROR_INT                             (0u)
  97 #define EDMA3_TC2_ERROR_INT                             (0u)
  98 #define EDMA3_TC3_ERROR_INT                             (0u)
  99 #define EDMA3_TC4_ERROR_INT                             (0u)
 100 #define EDMA3_TC5_ERROR_INT                             (0u)
 101 #define EDMA3_TC6_ERROR_INT                             (0u)
 102 #define EDMA3_TC7_ERROR_INT                             (0u)
 103
 104 /**
 105 * EDMA3 interrupts (transfer completion, CC error etc.) correspond to different
 106 * ECM events (SoC specific). These ECM events come
 107 * under ECM block XXX (handling those specific ECM events). Normally, block
 108 * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events
 109 * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)
 110 * is mapped to a specific HWI_INT YYY in the tcf file.
 111 * Define EDMA3_HWI_INT_XFER_COMP to specific HWI_INT, corresponding
 112 * to transfer completion interrupt.
 113 * Define EDMA3_HWI_INT_CC_ERR to specific HWI_INT, corresponding
 114 * to CC error interrupts.
 115 * Define EDMA3_HWI_INT_TC_ERR to specific HWI_INT, corresponding
 116 * to TC error interrupts.
 117 */
 118 #define EDMA3_HWI_INT_XFER_COMP                                                 (7u)
 119 #define EDMA3_HWI_INT_CC_ERR                                                    (7u)
 120 #define EDMA3_HWI_INT_TC_ERR                                                    (7u)
 121
 122
 123 /**
 124  * \brief Mapping of DMA channels 0-31 to Hardware Events from
 125  * various peripherals, which use EDMA for data transfer.
 126  * All channels need not be mapped, some can be free also.
 127  * 1: Mapped
 128  * 0: Not mapped
 129  *
 130  * This mapping will be used to allocate DMA channels when user passes
 131  * EDMA3_RM_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
 132  * copy). The same mapping is used to allocate the TCC when user passes
 133  * EDMA3_RM_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
 134  *
 135  * To allocate more DMA channels or TCCs, one has to modify the event mapping.
 136  */
 137                                                                                                           /* 31     0 */
 138 #define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0          (0xFFFFFFF0u)
 139
 140 /**
 141  * \brief Mapping of DMA channels 32-63 to Hardware Events from
 142  * various peripherals, which use EDMA for data transfer.
 143  * All channels need not be mapped, some can be free also.
 144  * 1: Mapped
 145  * 0: Not mapped
 146  *
 147  * This mapping will be used to allocate DMA channels when user passes
 148  * EDMA3_RM_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
 149  * copy). The same mapping is used to allocate the TCC when user passes
 150  * EDMA3_RM_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
 151  *
 152  * To allocate more DMA channels or TCCs, one has to modify the event mapping.
 153  */
 154                                                                                                           /* 63     32 */
 155 #define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1          (0x3C7FFFFFu)
 156
 157 /* Variable which will be used internally for referring number of Event Queues. */
 158 unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] = {EDMA3_NUM_EVTQUE};
 159
 160 /* Variable which will be used internally for referring number of TCs. */
 161 unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] = {EDMA3_NUM_TC};
 162
 163 /**
 164  * Variable which will be used internally for referring transfer completion
 165  * interrupt.
 166  */
 167 unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = {
 168                                                         {
 169                                                         0u, EDMA3_CC_XFER_COMPLETION_INT, 0u, 0u,
 170                                                         0u, 0u, 0u, 0u,
 171                                                         },
 172                         };
 173
 174 /**
 175  * Variable which will be used internally for referring channel controller's
 176  * error interrupt.
 177  */
 178 unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {EDMA3_CC_ERROR_INT};
 179
 180 /**
 181  * Variable which will be used internally for referring transfer controllers'
 182  * error interrupts.
 183  */
 184 unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][8] =    {
 185                                 {
 186                                 EDMA3_TC0_ERROR_INT, EDMA3_TC1_ERROR_INT,
 187                                 EDMA3_TC2_ERROR_INT, EDMA3_TC3_ERROR_INT,
 188                                 EDMA3_TC4_ERROR_INT, EDMA3_TC5_ERROR_INT,
 189                                 EDMA3_TC6_ERROR_INT, EDMA3_TC7_ERROR_INT,
 190                                 }
 191                             };
 192
 193 /**
 194  * Variables which will be used internally for referring the hardware interrupt
 195  * for various EDMA3 interrupts.
 196  */
 197 unsigned int hwIntXferComp = EDMA3_HWI_INT_XFER_COMP;
 198 unsigned int hwIntCcErr = EDMA3_HWI_INT_CC_ERR;
 199 unsigned int hwIntTcErr = EDMA3_HWI_INT_TC_ERR;
 200
 201
 202 /* Driver Object Initialization Configuration */
 203 EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
 204         {
 205             {
 206             /** Total number of DMA Channels supported by the EDMA3 Controller */
 207             64u,
 208             /** Total number of QDMA Channels supported by the EDMA3 Controller */
 209             8u,
 210             /** Total number of TCCs supported by the EDMA3 Controller */
 211             64u,
 212             /** Total number of PaRAM Sets supported by the EDMA3 Controller */
 213             512u,
 214             /** Total number of Event Queues in the EDMA3 Controller */
 215             4u,
 216             /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
 217             4u,
 218             /** Number of Regions on this EDMA3 controller */
 219             5u,
 220
 221             /**
 222              * \brief Channel mapping existence
 223              * A value of 0 (No channel mapping) implies that there is fixed association
 224              * for a channel number to a parameter entry number or, in other words,
 225              * PaRAM entry n corresponds to channel n.
 226              */
 227             1u,
 228
 229             /** Existence of memory protection feature */
 230             1u,
 231
 232             /** Global Register Region of CC Registers */
 233             (void *)0x49000000u,
 234             /** Transfer Controller (TC) Registers */
 235                 {
 236                 (void *)0x49800000u,
 237                 (void *)0x49900000u,
 238                 (void *)0x49A00000u,
 239                 (void *)0x49B00000u,
 240                 (void *)NULL,
 241                 (void *)NULL,
 242                 (void *)NULL,
 243                 (void *)NULL
 244                 },
 245             /** Interrupt no. for Transfer Completion */
 246             EDMA3_CC_XFER_COMPLETION_INT,
 247             /** Interrupt no. for CC Error */
 248             EDMA3_CC_ERROR_INT,
 249             /** Interrupt no. for TCs Error */
 250                 {
 251                 EDMA3_TC0_ERROR_INT,
 252                 EDMA3_TC1_ERROR_INT,
 253                 EDMA3_TC2_ERROR_INT,
 254                 EDMA3_TC3_ERROR_INT,
 255                 EDMA3_TC4_ERROR_INT,
 256                 EDMA3_TC5_ERROR_INT,
 257                 EDMA3_TC6_ERROR_INT,
 258                 EDMA3_TC7_ERROR_INT
 259                 },
 260
 261             /**
 262              * \brief EDMA3 TC priority setting
 263              *
 264              * User can program the priority of the Event Queues
 265              * at a system-wide level.  This means that the user can set the
 266              * priority of an IO initiated by either of the TCs (Transfer Controllers)
 267              * relative to IO initiated by the other bus masters on the
 268              * device (ARM, DSP, USB, etc)
 269              */
 270                 {
 271                 0u,
 272                 1u,
 273                 2u,
 274                 3u,
 275                 0u,
 276                 0u,
 277                 0u,
 278                 0u
 279                 },
 280             /**
 281              * \brief To Configure the Threshold level of number of events
 282              * that can be queued up in the Event queues. EDMA3CC error register
 283              * (CCERR) will indicate whether or not at any instant of time the
 284              * number of events queued up in any of the event queues exceeds
 285              * or equals the threshold/watermark value that is set
 286              * in the queue watermark threshold register (QWMTHRA).
 287              */
 288                 {
 289                 16u,
 290                 16u,
 291                 16u,
 292                 16u,
 293                 0u,
 294                 0u,
 295                 0u,
 296                 0u
 297                 },
 298
 299             /**
 300              * \brief To Configure the Default Burst Size (DBS) of TCs.
 301              * An optimally-sized command is defined by the transfer controller
 302              * default burst size (DBS). Different TCs can have different
 303              * DBS values. It is defined in Bytes.
 304              */
 305                 {
 306                 16u,
 307                 16u,
 308                 16u,
 309                 16u,
 310                 0u,
 311                 0u,
 312                 0u,
 313                 0u
 314                 },
 315
 316             /**
 317              * \brief Mapping from each DMA channel to a Parameter RAM set,
 318              * if it exists, otherwise of no use.
 319              */
 320                 {
 321                 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 322                 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 323                 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 324                 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 325                 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 326                 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 327                 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 328                 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 329                 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 330                 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 331                 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 332                 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 333                 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 334                 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 335                 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 336                 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 337                 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 338                 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 339                 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 340                 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 341                 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 342                 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 343                 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 344                 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 345                 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 346                 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 347                 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 348                 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 349                 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 350                 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 351                 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 352                 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP
 353                 },
 354
 355              /**
 356               * \brief Mapping from each DMA channel to a TCC. This specific
 357               * TCC code will be returned when the transfer is completed
 358               * on the mapped channel.
 359               */
 360                 {
 361                 0u, 1u, 2u, 3u,
 362                 4u, 5u, 6u, 7u,
 363                 8u, 9u, 10u, 11u,
 364                 12u, 13u, 14u, 15u,
 365                 16u, 17u, 18u, 19u,
 366                 20u, 21u, 22u, 23u,
 367                 24u, 25u, 26u, 27u,
 368                 28u, 29u, 30u, 31u,
 369                 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
 370                 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
 371                 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
 372                 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
 373                 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
 374                 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
 375                 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
 376                 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP
 377                 },
 378
 379             /**
 380              * \brief Mapping of DMA channels to Hardware Events from
 381              * various peripherals, which use EDMA for data transfer.
 382              * All channels need not be mapped, some can be free also.
 383              */
 384                 {
 385                 EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0,
 386                 EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1
 387                 },
 388                 },
 389         };
 390
 391
 392 /* Driver Instance Initialization Configuration */
 393 EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
 394         {
 395                 /* EDMA3 INSTANCE# 0 */
 396                 {
 397                         /* Resources owned/reserved by region 0 */
 398                         {
 399                                 /* ownPaRAMSets */
 400                                 /* 31     0     63    32     95    64     127   96 */
 401                                 {0x03FFFFF0u, 0x03E0FFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
 402                                 /* 159  128     191  160     223  192     255  224 */
 403                                  0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
 404                                 /* 287  256     319  288     351  320     383  352 */
 405                                  0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
 406                                 /* 415  384     447  416     479  448     511  480 */
 407                                  0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u},
 408
 409                                 /* ownDmaChannels */
 410                                 /* 31     0     63    32 */
 411                                 {0x03FFFFF0u, 0x03E0FFFFu},
 412
 413                                 /* ownQdmaChannels */
 414                                 /* 31     0 */
 415                                 {0x0000000Fu},
 416
 417                                 /* ownTccs */
 418                                 /* 31     0     63    32 */
 419                                 {0x03FFFFF0u, 0x03E0FFFFu},
 420
 421                                 /* resvdPaRAMSets */
 422                                 /* 31     0     63    32     95    64     127   96 */
 423                                 {0x03FFFFF0u, 0x0060FFFFu, 0x00000000u, 0x00000000u,
 424                                 /* 159  128     191  160     223  192     255  224 */
 425                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 426                                 /* 287  256     319  288     351  320     383  352 */
 427                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 428                                 /* 415  384     447  416     479  448     511  480 */
 429                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
 430
 431                                 /* resvdDmaChannels */
 432                                 /* 31     0     63    32 */
 433                                 {0x03FFFFF0u, 0x0060FFFFu},
 434
 435                                 /* resvdQdmaChannels */
 436                                 /* 31     0 */
 437                                 {0x00000000u},
 438
 439                                 /* resvdTccs */
 440                                 /* 31     0     63    32 */
 441                                 {0x03FFFFF0u, 0x0060FFFFu},
 442                         },
 443
 444                 /* Resources owned/reserved by region 1 */
 445                     {
 446                         /* ownPaRAMSets */
 447                         /* 31     0     63    32     95    64     127   96 */
 448                         {0xFC00FF0Fu, 0xFC1F0000u, 0x00000000u, 0x00000000u,
 449                         /* 159  128     191  160     223  192     255  224 */
 450                          0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 451                         /* 287  256     319  288     351  320     383  352 */
 452                          0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 453                         /* 415  384     447  416     479  448     511  480 */
 454                          0x00000000u, 0x00000000u, 0x00000000u, 0xFFFFFFFFu,},
 455
 456                         /* ownDmaChannels */
 457                         /* 31     0     63    32 */
 458                         {0xFC00FF0Fu, 0xFC1F0000u},
 459
 460                         /* ownQdmaChannels */
 461                         /* 31     0 */
 462                         {0x000000F0u},
 463
 464                         /* ownTccs */
 465                         /* 31     0     63    32 */
 466                         {0xFC00FF0Fu, 0xFC1F0000u},
 467
 468                         /* resvdPaRAMSets */
 469                         /* 31     0     63    32     95    64     127   96 */
 470                         {0x0000FF00u, 0x00000000u, 0x00000000u, 0x00000000u,
 471                         /* 159  128     191  160     223  192     255  224 */
 472                          0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 473                         /* 287  256     319  288     351  320     383  352 */
 474                          0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 475                         /* 415  384     447  416     479  448     511  480 */
 476                          0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
 477
 478                         /* resvdDmaChannels */
 479                                 /* 31     0     63    32 */
 480                                 {0x0000FF00u, 0x00000000u},
 481
 482                         /* resvdQdmaChannels */
 483                         /* 31     0 */
 484                         {0x00000000u},
 485
 486                         /* resvdTccs */
 487                                 /* 31     0     63    32 */
 488                                 {0x0000FF00u, 0x00000000u},
 489                     },
 490
 491                 /* Resources owned/reserved by region 2 */
 492                         {
 493                                 /* ownPaRAMSets */
 494                                 /* 31     0     63    32     95    64     127   96 */
 495                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 496                                 /* 159  128     191  160     223  192     255  224 */
 497                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 498                                 /* 287  256     319  288     351  320     383  352 */
 499                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 500                                 /* 415  384     447  416     479  448     511  480 */
 501                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
 502
 503                                 /* ownDmaChannels */
 504                                 /* 31     0     63    32 */
 505                                 {0x00000000u, 0x00000000u},
 506
 507                                 /* ownQdmaChannels */
 508                                 /* 31     0 */
 509                                 {0x00000000u},
 510
 511                                 /* ownTccs */
 512                                 /* 31     0     63    32 */
 513                                 {0x00000000u, 0x00000000u},
 514
 515                                 /* resvdPaRAMSets */
 516                                 /* 31     0     63    32     95    64     127   96 */
 517                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 518                                 /* 159  128     191  160     223  192     255  224 */
 519                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 520                                 /* 287  256     319  288     351  320     383  352 */
 521                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 522                                 /* 415  384     447  416     479  448     511  480 */
 523                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
 524
 525                                 /* resvdDmaChannels */
 526                                 /* 31     0     63    32 */
 527                                 {0x00000000u, 0x00000000u},
 528
 529                                 /* resvdQdmaChannels */
 530                                 /* 31     0 */
 531                                 {0x00000000u},
 532
 533                                 /* resvdTccs */
 534                                 /* 31     0     63    32 */
 535                                 {0x00000000u, 0x00000000u},
 536                         },
 537
 538                 /* Resources owned/reserved by region 3 */
 539                         {
 540                                 /* ownPaRAMSets */
 541                                 /* 31     0     63    32     95    64     127   96 */
 542                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 543                                 /* 159  128     191  160     223  192     255  224 */
 544                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 545                                 /* 287  256     319  288     351  320     383  352 */
 546                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 547                                 /* 415  384     447  416     479  448     511  480 */
 548                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
 549
 550                                 /* ownDmaChannels */
 551                                 /* 31     0     63    32 */
 552                                 {0x00000000u, 0x00000000u},
 553
 554                                 /* ownQdmaChannels */
 555                                 /* 31     0 */
 556                                 {0x00000000u},
 557
 558                                 /* ownTccs */
 559                                 /* 31     0     63    32 */
 560                                 {0x00000000u, 0x00000000u},
 561
 562                                 /* resvdPaRAMSets */
 563                                 /* 31     0     63    32     95    64     127   96 */
 564                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 565                                 /* 159  128     191  160     223  192     255  224 */
 566                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 567                                 /* 287  256     319  288     351  320     383  352 */
 568                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 569                                 /* 415  384     447  416     479  448     511  480 */
 570                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
 571
 572                                 /* resvdDmaChannels */
 573                                 /* 31     0     63    32 */
 574                                 {0x00000000u, 0x00000000u},
 575
 576                                 /* resvdQdmaChannels */
 577                                 /* 31     0 */
 578                                 {0x00000000u},
 579
 580                                 /* resvdTccs */
 581                                 /* 31     0     63    32 */
 582                                 {0x00000000u, 0x00000000u},
 583                         },
 584
 585                 /* Resources owned/reserved by region 4 */
 586                         {
 587                                 /* ownPaRAMSets */
 588                                 /* 31     0     63    32     95    64     127   96 */
 589                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 590                                 /* 159  128     191  160     223  192     255  224 */
 591                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 592                                 /* 287  256     319  288     351  320     383  352 */
 593                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 594                                 /* 415  384     447  416     479  448     511  480 */
 595                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
 596
 597                                 /* ownDmaChannels */
 598                                 /* 31     0     63    32 */
 599                                 {0x00000000u, 0x00000000u},
 600
 601                                 /* ownQdmaChannels */
 602                                 /* 31     0 */
 603                                 {0x00000000u},
 604
 605                                 /* ownTccs */
 606                                 /* 31     0     63    32 */
 607                                 {0x00000000u, 0x00000000u},
 608
 609                                 /* resvdPaRAMSets */
 610                                 /* 31     0     63    32     95    64     127   96 */
 611                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 612                                 /* 159  128     191  160     223  192     255  224 */
 613                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 614                                 /* 287  256     319  288     351  320     383  352 */
 615                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 616                                 /* 415  384     447  416     479  448     511  480 */
 617                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
 618
 619                                 /* resvdDmaChannels */
 620                                 /* 31     0     63    32 */
 621                                 {0x00000000u, 0x00000000u},
 622
 623                                 /* resvdQdmaChannels */
 624                                 /* 31     0 */
 625                                 {0x00000000u},
 626
 627                                 /* resvdTccs */
 628                                 /* 31     0     63    32 */
 629                                 {0x00000000u, 0x00000000u},
 630                         },
 631
 632                 /* Resources owned/reserved by region 5 */
 633                         {
 634                                 /* ownPaRAMSets */
 635                                 /* 31     0     63    32     95    64     127   96 */
 636                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 637                                 /* 159  128     191  160     223  192     255  224 */
 638                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 639                                 /* 287  256     319  288     351  320     383  352 */
 640                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 641                                 /* 415  384     447  416     479  448     511  480 */
 642                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
 643
 644                                 /* ownDmaChannels */
 645                                 /* 31     0     63    32 */
 646                                 {0x00000000u, 0x00000000u},
 647
 648                                 /* ownQdmaChannels */
 649                                 /* 31     0 */
 650                                 {0x00000000u},
 651
 652                                 /* ownTccs */
 653                                 /* 31     0     63    32 */
 654                                 {0x00000000u, 0x00000000u},
 655
 656                                 /* resvdPaRAMSets */
 657                                 /* 31     0     63    32     95    64     127   96 */
 658                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 659                                 /* 159  128     191  160     223  192     255  224 */
 660                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 661                                 /* 287  256     319  288     351  320     383  352 */
 662                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 663                                 /* 415  384     447  416     479  448     511  480 */
 664                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
 665
 666                                 /* resvdDmaChannels */
 667                                 /* 31     0     63    32 */
 668                                 {0x00000000u, 0x00000000u},
 669
 670                                 /* resvdQdmaChannels */
 671                                 /* 31     0 */
 672                                 {0x00000000u},
 673
 674                                 /* resvdTccs */
 675                                 /* 31     0     63    32 */
 676                                 {0x00000000u, 0x00000000u},
 677                         },
 678
 679                 /* Resources owned/reserved by region 6 */
 680                         {
 681                                 /* ownPaRAMSets */
 682                                 /* 31     0     63    32     95    64     127   96 */
 683                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 684                                 /* 159  128     191  160     223  192     255  224 */
 685                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 686                                 /* 287  256     319  288     351  320     383  352 */
 687                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 688                                 /* 415  384     447  416     479  448     511  480 */
 689                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
 690
 691                                 /* ownDmaChannels */
 692                                 /* 31     0     63    32 */
 693                                 {0x00000000u, 0x00000000u},
 694
 695                                 /* ownQdmaChannels */
 696                                 /* 31     0 */
 697                                 {0x00000000u},
 698
 699                                 /* ownTccs */
 700                                 /* 31     0     63    32 */
 701                                 {0x00000000u, 0x00000000u},
 702
 703                                 /* resvdPaRAMSets */
 704                                 /* 31     0     63    32     95    64     127   96 */
 705                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 706                                 /* 159  128     191  160     223  192     255  224 */
 707                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 708                                 /* 287  256     319  288     351  320     383  352 */
 709                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 710                                 /* 415  384     447  416     479  448     511  480 */
 711                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
 712
 713                                 /* resvdDmaChannels */
 714                                 /* 31     0     63    32 */
 715                                 {0x00000000u, 0x00000000u},
 716
 717                                 /* resvdQdmaChannels */
 718                                 /* 31     0 */
 719                                 {0x00000000u},
 720
 721                                 /* resvdTccs */
 722                                 /* 31     0     63    32 */
 723                                 {0x00000000u, 0x00000000u},
 724                         },
 725
 726                 /* Resources owned/reserved by region 7 */
 727                         {
 728                                 /* ownPaRAMSets */
 729                                 /* 31     0     63    32     95    64     127   96 */
 730                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 731                                 /* 159  128     191  160     223  192     255  224 */
 732                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 733                                 /* 287  256     319  288     351  320     383  352 */
 734                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 735                                 /* 415  384     447  416     479  448     511  480 */
 736                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
 737
 738                                 /* ownDmaChannels */
 739                                 /* 31     0     63    32 */
 740                                 {0x00000000u, 0x00000000u},
 741
 742                                 /* ownQdmaChannels */
 743                                 /* 31     0 */
 744                                 {0x00000000u},
 745
 746                                 /* ownTccs */
 747                                 /* 31     0     63    32 */
 748                                 {0x00000000u, 0x00000000u},
 749
 750                                 /* resvdPaRAMSets */
 751                                 /* 31     0     63    32     95    64     127   96 */
 752                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 753                                 /* 159  128     191  160     223  192     255  224 */
 754                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 755                                 /* 287  256     319  288     351  320     383  352 */
 756                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 757                                 /* 415  384     447  416     479  448     511  480 */
 758                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
 759
 760                                 /* resvdDmaChannels */
 761                                 /* 31     0     63    32 */
 762                                 {0x00000000u, 0x00000000u},
 763
 764                                 /* resvdQdmaChannels */
 765                                 /* 31     0 */
 766                                 {0x00000000u},
 767
 768                                 /* resvdTccs */
 769                                 /* 31     0     63    32 */
 770                                 {0x00000000u, 0x00000000u},
 771                         },
 772             },
 773         };
 774
 775
 776
 777 /* End of File */
 778
 779