packages/ti/sdo/edma3/rm/src/configs/edma3_c6472_cfg.c

   1 /*
   2  * edma3_c6472_cfg.c
   3  *
   4  * EDMA3 Resource Manager Adaptation Configuration File (SoC Specific).
   5  *
   6  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
   7  *
   8  *
   9  *  Redistribution and use in source and binary forms, with or without
  10  *  modification, are permitted provided that the following conditions
  11  *  are met:
  12  *
  13  *    Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  *
  16  *    Redistributions in binary form must reproduce the above copyright
  17  *    notice, this list of conditions and the following disclaimer in the
  18  *    documentation and/or other materials provided with the
  19  *    distribution.
  20  *
  21  *    Neither the name of Texas Instruments Incorporated nor the names of
  22  *    its contributors may be used to endorse or promote products derived
  23  *    from this software without specific prior written permission.
  24  *
  25  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  26  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  27  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  28  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  29  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  30  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  31  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  32  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  33  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  34  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  35  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36  *
  37 */
  38
  39 #include <ti/sdo/edma3/rm/edma3_rm.h>
  40
  41 #define NUM_EDMA3_INSTANCES                     1u
  42
  43 /* Driver Object Initialization Configuration */
  44 EDMA3_RM_GblConfigParams edma3GblCfgParams [NUM_EDMA3_INSTANCES] =
  45         {
  46                 {
  47                 /** Total number of DMA Channels supported by the EDMA3 Controller */
  48                 64u,
  49                 /** Total number of QDMA Channels supported by the EDMA3 Controller */
  50                 4u,
  51                 /** Total number of TCCs supported by the EDMA3 Controller */
  52                 64u,
  53                 /** Total number of PaRAM Sets supported by the EDMA3 Controller */
  54                 256u,
  55                 /** Total number of Event Queues in the EDMA3 Controller */
  56                 4u,
  57                 /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
  58                 4u,
  59                 /** Number of Regions on this EDMA3 controller */
  60                 8u,
  61
  62                 /**
  63                  * \brief Channel mapping existence
  64                  * A value of 0 (No channel mapping) implies that there is fixed association
  65                  * for a channel number to a parameter entry number or, in other words,
  66                  * PaRAM entry n corresponds to channel n.
  67                  */
  68                 1u,
  69
  70                 /** Existence of memory protection feature */
  71                 1u,
  72
  73                 /** Global Register Region of CC Registers */
  74                 (void *)0x02A00000u,
  75                 /** Transfer Controller (TC) Registers */
  76                 {
  77                 (void *)0x02A20000u,
  78                 (void *)0x02A28000u,
  79                 (void *)0x02A30000u,
  80                 (void *)0x02A38000u,
  81                 (void *)NULL,
  82                 (void *)NULL,
  83                 (void *)NULL,
  84                 (void *)NULL
  85                 },
  86                 /** Interrupt no. for Transfer Completion */
  87                 15u,
  88                 /** Interrupt no. for CC Error */
  89                 57u,
  90                 /** Interrupt no. for TCs Error */
  91                 {
  92                 59u,
  93                 60u,
  94                 61u,
  95                 62u,
  96                 0u,
  97                 0u,
  98                 0u,
  99                 0u,
 100                 },
 101
 102                 /**
 103                  * \brief EDMA3 TC priority setting
 104                  *
 105                  * User can program the priority of the Event Queues
 106                  * at a system-wide level.  This means that the user can set the
 107                  * priority of an IO initiated by either of the TCs (Transfer Controllers)
 108                  * relative to IO initiated by the other bus masters on the
 109                  * device (ARM, DSP, USB, etc)
 110                  */
 111                 {
 112                 0u,
 113                 1u,
 114                 2u,
 115                 3u,
 116                 0u,
 117                 0u,
 118                 0u,
 119                 0u
 120                 },
 121                 /**
 122                  * \brief To Configure the Threshold level of number of events
 123                  * that can be queued up in the Event queues. EDMA3CC error register
 124                  * (CCERR) will indicate whether or not at any instant of time the
 125                  * number of events queued up in any of the event queues exceeds
 126                  * or equals the threshold/watermark value that is set
 127                  * in the queue watermark threshold register (QWMTHRA).
 128                  */
 129                 {
 130                 16u,
 131                 16u,
 132                 16u,
 133                 16u,
 134                 0u,
 135                 0u,
 136                 0u,
 137                 0u
 138                 },
 139
 140                 /**
 141                  * \brief To Configure the Default Burst Size (DBS) of TCs.
 142                  * An optimally-sized command is defined by the transfer controller
 143                  * default burst size (DBS). Different TCs can have different
 144                  * DBS values. It is defined in Bytes.
 145                  */
 146                 {
 147                 64u,
 148                 64u,
 149                 64u,
 150                 64u,
 151                 0u,
 152                 0u,
 153                 0u,
 154                 0u
 155                 },
 156
 157                 /**
 158                  * \brief Mapping from each DMA channel to a Parameter RAM set,
 159                  * if it exists, otherwise of no use.
 160                  */
 161                 {
 162         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 163         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 164         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 165         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 166         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 167         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 168         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 169         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 170         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 171         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 172         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 173         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 174         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 175         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 176         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 177         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 178         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 179         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 180         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 181         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 182         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 183         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 184         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 185         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 186         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 187         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 188         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 189         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 190         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 191         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 192         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
 193         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP
 194                 },
 195
 196                  /**
 197                   * \brief Mapping from each DMA channel to a TCC. This specific
 198                   * TCC code will be returned when the transfer is completed
 199                   * on the mapped channel.
 200                   */
 201                 {
 202         0u, 1u, 2u, 3u,
 203         4u, 5u, 6u, 7u,
 204         8u, 9u, 10u, 11u,
 205         12u, 13u, 14u, 15u,
 206         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
 207         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
 208         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
 209         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
 210         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
 211         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
 212         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
 213         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
 214         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
 215         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
 216         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
 217         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP
 218                 },
 219
 220                 /**
 221                  * \brief Mapping of DMA channels to Hardware Events from
 222                  * various peripherals, which use EDMA for data transfer.
 223                  * All channels need not be mapped, some can be free also.
 224                  */
 225                 {
 226                 0x0000FFFFu,
 227                 0x00000000u
 228                 }
 229                 }
 230         };
 231
 232 EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
 233 {
 234         {
 235           {
 236                 /* Resources owned by Region 0 */
 237                  /* ownPaRAMSets */
 238                 /* 31     0     63    32     95    64     127   96 */
 239                 {0xFFFF0000u, 0x00FFFFFFu, 0x00000000u, 0x00000000u,
 240                 /* 159  128     191  160     223  192     255  224 */
 241                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 242                 /* 287  256     319  288     351  320     383  352 */
 243                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 244                 /* 415  384     447  416     479  448     511  480 */
 245                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
 246
 247                 /* ownDmaChannels */
 248                 /* 31     0     63    32 */
 249                 {0x00FF0000u, 0x00000000u},
 250
 251                 /* ownQdmaChannels */
 252                 /* 31     0 */
 253                 {0x00000001u},
 254
 255                 /* ownTccs */
 256                 /* 31     0     63    32 */
 257                 {0x00FF0000u, 0x00000000u},
 258
 259                 /* Resources reserved by Region 0 */
 260                 /* resvdPaRAMSets */
 261                 /* 31     0     63    32     95    64     127   96 */
 262                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 263                 /* 159  128     191  160     223  192     255  224 */
 264                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 265                 /* 287  256     319  288     351  320     383  352 */
 266                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 267                 /* 415  384     447  416     479  448     511  480 */
 268                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
 269
 270                 /* resvdDmaChannels */
 271         /* 31     0    63     32 */
 272         {0x0000FFFFu, 0x00000000u},
 273
 274                 /* resvdQdmaChannels */
 275                 /* 31     0 */
 276                 {0x00000000u},
 277
 278                 /* resvdTccs */
 279         /* 31     0    63     32 */
 280         {0x0000FFFFu, 0x00000000u},
 281           },
 282
 283           {
 284                 /* Resources owned by Region 1 */
 285                 /* ownPaRAMSets */
 286                 /* 31     0     63    32     95    64     127   96 */
 287                 {0x00000000u, 0xFF000000u, 0xFFFFFFFFu, 0x00000000u,
 288                 /* 159  128     191  160     223  192     255  224 */
 289                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 290                 /* 287  256     319  288     351  320     383  352 */
 291                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 292                 /* 415  384     447  416     479  448     511  480 */
 293                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
 294
 295                 /* ownDmaChannels */
 296                 /* 31     0     63    32 */
 297                 {0xFF000000u, 0x00000000u},
 298
 299                 /* ownQdmaChannels */
 300                 /* 31     0 */
 301                 {0x00000002u},
 302
 303                 /* ownTccs */
 304                 /* 31     0     63    32 */
 305                 {0xFF000000u, 0x00000000u},
 306
 307                 /* Resources reserved by Region 1 */
 308                 /* resvdPaRAMSets */
 309                 /* 31     0     63    32     95    64     127   96 */
 310                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 311                 /* 159  128     191  160     223  192     255  224 */
 312                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 313                 /* 287  256     319  288     351  320     383  352 */
 314                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 315                 /* 415  384     447  416     479  448     511  480 */
 316                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
 317
 318                 /* resvdDmaChannels */
 319         /* 31     0    63     32 */
 320         {0x0000FFFFu, 0x00000000u},
 321
 322                 /* resvdQdmaChannels */
 323                 /* 31     0 */
 324                 {0x00000000u},
 325
 326                 /* resvdTccs */
 327         /* 31     0    63     32 */
 328         {0x0000FFFFu, 0x00000000u},
 329           },
 330
 331           {
 332                 /* Resources owned by Region 2 */
 333                  /* ownPaRAMSets */
 334                 /* 31     0     63    32     95    64     127   96 */
 335                 {0x00000000u, 0x00000000u, 0x00000000u, 0xFFFFFFFFu,
 336                 /* 159  128     191  160     223  192     255  224 */
 337                  0x000000FFu, 0x00000000u, 0x00000000u, 0x00000000u,
 338                 /* 287  256     319  288     351  320     383  352 */
 339                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 340                 /* 415  384     447  416     479  448     511  480 */
 341                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
 342
 343                 /* ownDmaChannels */
 344                 /* 31     0     63    32 */
 345                 {0x00000000u, 0x000000FFu},
 346
 347                 /* ownQdmaChannels */
 348                 /* 31     0 */
 349                 {0x00000004u},
 350
 351                 /* ownTccs */
 352                 /* 31     0     63    32 */
 353                 {0x00000000u, 0x000000FFu},
 354
 355                 /* Resources reserved by Region 2 */
 356                 /* resvdPaRAMSets */
 357                 /* 31     0     63    32     95    64     127   96 */
 358                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 359                 /* 159  128     191  160     223  192     255  224 */
 360                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 361                 /* 287  256     319  288     351  320     383  352 */
 362                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 363                 /* 415  384     447  416     479  448     511  480 */
 364                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
 365
 366                 /* resvdDmaChannels */
 367         /* 31     0    63     32 */
 368         {0x0000FFFFu, 0x00000000u},
 369
 370                 /* resvdQdmaChannels */
 371                 /* 31     0 */
 372                 {0x00000000u},
 373
 374                 /* resvdTccs */
 375         /* 31     0    63     32 */
 376         {0x0000FFFFu, 0x00000000u},
 377           },
 378
 379           {
 380                 /* Resources owned by Region 3 */
 381                  /* ownPaRAMSets */
 382                 /* 31     0     63    32     95    64     127   96 */
 383                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 384                 /* 159  128     191  160     223  192     255  224 */
 385                  0xFFFFFF00u, 0x0000FFFFu, 0x00000000u, 0x00000000u,
 386                 /* 287  256     319  288     351  320     383  352 */
 387                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 388                 /* 415  384     447  416     479  448     511  480 */
 389                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
 390
 391                 /* ownDmaChannels */
 392                 /* 31     0     63    32 */
 393                 {0x00000000u, 0x0000FF00u},
 394
 395                 /* ownQdmaChannels */
 396                 /* 31     0 */
 397                 {0x00000008u},
 398
 399                 /* ownTccs */
 400                 /* 31     0     63    32 */
 401                 {0x00000000u, 0x0000FF00u},
 402
 403                 /* Resources reserved by Region 3 */
 404                 /* resvdPaRAMSets */
 405                 /* 31     0     63    32     95    64     127   96 */
 406                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 407                 /* 159  128     191  160     223  192     255  224 */
 408                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 409                 /* 287  256     319  288     351  320     383  352 */
 410                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 411                 /* 415  384     447  416     479  448     511  480 */
 412                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
 413
 414                 /* resvdDmaChannels */
 415                 /* 31     0     63    32 */
 416                 {0x0000FFFFu, 0x00000000u},
 417
 418                 /* resvdQdmaChannels */
 419                 /* 31     0 */
 420                 {0x00000000u},
 421
 422                 /* resvdTccs */
 423                 /* 31     0     63    32 */
 424                 {0x0000FFFFu, 0x00000000u},
 425           },
 426
 427           {
 428                 /* Resources owned by Region 4 */
 429                  /* ownPaRAMSets */
 430                 /* 31     0     63    32     95    64     127   96 */
 431                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 432                 /* 159  128     191  160     223  192     255  224 */
 433                  0x00000000u, 0xFFFF0000u, 0x00FFFFFFu, 0x00000000u,
 434                 /* 287  256     319  288     351  320     383  352 */
 435                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 436                 /* 415  384     447  416     479  448     511  480 */
 437                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
 438
 439                 /* ownDmaChannels */
 440                 /* 31     0     63    32 */
 441                 {0x00000000u, 0x00FF0000u},
 442
 443                 /* ownQdmaChannels */
 444                 /* 31     0 */
 445                 {0x00000008u},
 446
 447                 /* ownTccs */
 448                 /* 31     0     63    32 */
 449                 {0x00000000u, 0x00FF0000u},
 450
 451                 /* Resources reserved by Region 4 */
 452                 /* resvdPaRAMSets */
 453                 /* 31     0     63    32     95    64     127   96 */
 454                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 455                 /* 159  128     191  160     223  192     255  224 */
 456                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 457                 /* 287  256     319  288     351  320     383  352 */
 458                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 459                 /* 415  384     447  416     479  448     511  480 */
 460                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
 461
 462                 /* resvdDmaChannels */
 463                 /* 31     0     63    32 */
 464                 {0x0000FFFFu, 0x00000000u},
 465
 466                 /* resvdQdmaChannels */
 467                 /* 31     0 */
 468                 {0x00000000u},
 469
 470                 /* resvdTccs */
 471                 /* 31     0     63    32 */
 472                 {0x0000FFFFu, 0x00000000u},
 473           },
 474
 475           {
 476                 /* Resources owned by Region 5 */
 477                  /* ownPaRAMSets */
 478                 /* 31     0     63    32     95    64     127   96 */
 479                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 480                 /* 159  128     191  160     223  192     255  224 */
 481                  0x00000000u, 0x00000000u, 0xFF000000u, 0xFFFFFFFFu,
 482                 /* 287  256     319  288     351  320     383  352 */
 483                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 484                 /* 415  384     447  416     479  448     511  480 */
 485                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
 486
 487                 /* ownDmaChannels */
 488                 /* 31     0     63    32 */
 489                 {0x00000000u, 0xFF000000u},
 490
 491                 /* ownQdmaChannels */
 492                 /* 31     0 */
 493                 {0x00000008u},
 494
 495                 /* ownTccs */
 496                 /* 31     0     63    32 */
 497                 {0x00000000u, 0xFF000000u},
 498
 499                 /* Resources reserved by Region 5 */
 500                 /* resvdPaRAMSets */
 501                 /* 31     0     63    32     95    64     127   96 */
 502                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 503                 /* 159  128     191  160     223  192     255  224 */
 504                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 505                 /* 287  256     319  288     351  320     383  352 */
 506                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 507                 /* 415  384     447  416     479  448     511  480 */
 508                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
 509
 510                 /* resvdDmaChannels */
 511                 /* 31     0     63    32 */
 512                 {0x0000FFFFu, 0x00000000u},
 513
 514                 /* resvdQdmaChannels */
 515                 /* 31     0 */
 516                 {0x00000000u},
 517
 518                 /* resvdTccs */
 519                 /* 31     0     63    32 */
 520                 {0x0000FFFFu, 0x00000000u},
 521           },
 522
 523       {
 524         /* Resources owned by Region 6 */
 525          /* ownPaRAMSets */
 526         /* 31     0     63    32     95    64     127   96 */
 527         {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 528         /* 159  128     191  160     223  192     255  224 */
 529          0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 530         /* 287  256     319  288     351  320     383  352 */
 531          0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 532         /* 415  384     447  416     479  448     511  480 */
 533          0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
 534
 535         /* ownDmaChannels */
 536         /* 31     0     63    32 */
 537         {0x00000000u, 0x00000000u},
 538
 539         /* ownQdmaChannels */
 540         /* 31     0 */
 541         {0x00000000u},
 542
 543         /* ownTccs */
 544         /* 31     0     63    32 */
 545         {0x00000000u, 0x00000000u},
 546
 547         /* Resources reserved by Region 6 */
 548         /* resvdPaRAMSets */
 549         /* 31     0     63    32     95    64     127   96 */
 550         {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 551         /* 159  128     191  160     223  192     255  224 */
 552          0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 553         /* 287  256     319  288     351  320     383  352 */
 554          0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 555         /* 415  384     447  416     479  448     511  480 */
 556          0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
 557
 558         /* resvdDmaChannels */
 559         /* 31     0     63    32 */
 560         {0x00000000u, 0x00000000u},
 561
 562         /* resvdQdmaChannels */
 563         /* 31     0 */
 564         {0x00000000u},
 565
 566         /* resvdTccs */
 567         /* 31     0     63    32 */
 568         {0x00000000u, 0x00000000u},
 569       },
 570
 571       {
 572         /* Resources owned by Region 7 */
 573          /* ownPaRAMSets */
 574         /* 31     0     63    32     95    64     127   96 */
 575         {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 576         /* 159  128     191  160     223  192     255  224 */
 577          0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 578         /* 287  256     319  288     351  320     383  352 */
 579          0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 580         /* 415  384     447  416     479  448     511  480 */
 581          0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
 582
 583         /* ownDmaChannels */
 584         /* 31     0     63    32 */
 585         {0x00000000u, 0x00000000u},
 586
 587         /* ownQdmaChannels */
 588         /* 31     0 */
 589         {0x00000000u},
 590
 591         /* ownTccs */
 592         /* 31     0     63    32 */
 593         {0x00000000u, 0x00000000u},
 594
 595         /* Resources reserved by Region 7 */
 596         /* resvdPaRAMSets */
 597         /* 31     0     63    32     95    64     127   96 */
 598         {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 599         /* 159  128     191  160     223  192     255  224 */
 600          0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 601         /* 287  256     319  288     351  320     383  352 */
 602          0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 603         /* 415  384     447  416     479  448     511  480 */
 604          0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
 605
 606         /* resvdDmaChannels */
 607         /* 31     0     63    32 */
 608         {0x00000000u, 0x00000000u},
 609
 610         /* resvdQdmaChannels */
 611         /* 31     0 */
 612         {0x00000000u},
 613
 614         /* resvdTccs */
 615         /* 31     0     63    32 */
 616         {0x00000000u, 0x00000000u},
 617       }
 618         }
 619 };
 620
 621 /* End of File */