[keystone-rtos/edma3_lld.git] / packages / ti / sdo / edma3 / rm / src / configs / edma3_c6657_cfg.c
1 /*
2 * edma3_c6657_cfg.c
3 *
4 * EDMA3 Resource Manager Adaptation Configuration File (SoC Specific).
5 *
6 * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
7 *
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 *
13 * Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 *
16 * Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the
19 * distribution.
20 *
21 * Neither the name of Texas Instruments Incorporated nor the names of
22 * its contributors may be used to endorse or promote products derived
23 * from this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 */
39 #include <ti/sdo/edma3/rm/edma3_rm.h>
41 #define NUM_EDMA3_INSTANCES 1u
43 /* Driver Object Initialization Configuration */
44 EDMA3_RM_GblConfigParams edma3GblCfgParams [NUM_EDMA3_INSTANCES] =
45 {
46 {
47 /* EDMA3 INSTANCE# 0 */
48 /** Total number of DMA Channels supported by the EDMA3 Controller */
49 64u,
50 /** Total number of QDMA Channels supported by the EDMA3 Controller */
51 8u,
52 /** Total number of TCCs supported by the EDMA3 Controller */
53 64u,
54 /** Total number of PaRAM Sets supported by the EDMA3 Controller */
55 512u,
56 /** Total number of Event Queues in the EDMA3 Controller */
57 4u,
58 /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
59 4u,
60 /** Number of Regions on this EDMA3 controller */
61 8u,
63 /**
64 * \brief Channel mapping existence
65 * A value of 0 (No channel mapping) implies that there is fixed association
66 * for a channel number to a parameter entry number or, in other words,
67 * PaRAM entry n corresponds to channel n.
68 */
69 1u,
71 /** Existence of memory protection feature */
72 1u,
74 /** Global Register Region of CC Registers */
75 (void *)0x02740000u,
76 /** Transfer Controller (TC) Registers */
77 {
78 (void *)0x02790000u,
79 (void *)0x02798000u,
80 (void *)0x027A0000u,
81 (void *)0x027A8000u,
82 (void *)NULL,
83 (void *)NULL,
84 (void *)NULL,
85 (void *)NULL
86 },
87 /** Interrupt no. for Transfer Completion */
88 24u,
89 /** Interrupt no. for CC Error */
90 16u,
91 /** Interrupt no. for TCs Error */
92 {
93 18u,
94 19u,
95 20u,
96 21u,
97 0u,
98 0u,
99 0u,
100 0u,
101 },
103 /**
104 * \brief EDMA3 TC priority setting
105 *
106 * User can program the priority of the Event Queues
107 * at a system-wide level. This means that the user can set the
108 * priority of an IO initiated by either of the TCs (Transfer Controllers)
109 * relative to IO initiated by the other bus masters on the
110 * device (ARM, DSP, USB, etc)
111 */
112 {
113 0u,
114 1u,
115 2u,
116 3u,
117 0u,
118 0u,
119 0u,
120 0u
121 },
122 /**
123 * \brief To Configure the Threshold level of number of events
124 * that can be queued up in the Event queues. EDMA3CC error register
125 * (CCERR) will indicate whether or not at any instant of time the
126 * number of events queued up in any of the event queues exceeds
127 * or equals the threshold/watermark value that is set
128 * in the queue watermark threshold register (QWMTHRA).
129 */
130 {
131 16u,
132 16u,
133 16u,
134 16u,
135 0u,
136 0u,
137 0u,
138 0u
139 },
141 /**
142 * \brief To Configure the Default Burst Size (DBS) of TCs.
143 * An optimally-sized command is defined by the transfer controller
144 * default burst size (DBS). Different TCs can have different
145 * DBS values. It is defined in Bytes.
146 */
147 {
148 64u,
149 64u,
150 64u,
151 64u,
152 0u,
153 0u,
154 0u,
155 0u
156 },
158 /**
159 * \brief Mapping from each DMA channel to a Parameter RAM set,
160 * if it exists, otherwise of no use.
161 */
162 {
163 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
164 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
165 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
166 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
167 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
168 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
169 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
170 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
171 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
172 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
173 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
174 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
175 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
176 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
177 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
178 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
179 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
180 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
181 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
182 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
183 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
184 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
185 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
186 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
187 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
188 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
189 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
190 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
191 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
192 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
193 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
194 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP
195 },
197 /**
198 * \brief Mapping from each DMA channel to a TCC. This specific
199 * TCC code will be returned when the transfer is completed
200 * on the mapped channel.
201 */
202 {
203 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
204 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
205 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
206 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
207 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
208 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
209 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
210 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
211 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
212 56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u
213 },
215 /**
216 * \brief Mapping of DMA channels to Hardware Events from
217 * various peripherals, which use EDMA for data transfer.
218 * All channels need not be mapped, some can be free also.
219 */
220 {
221 0xFFFFFFFFu,
222 0xFF0000FFu
223 }
224 },
225 };
227 EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
228 {
229 /* EDMA3 INSTANCE# 0 */
230 {
231 /* Resources owned/reserved by region 0 */
232 {
233 /* ownPaRAMSets */
234 /* 31 0 63 32 95 64 127 96 */
235 {0x00000000u, 0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu,
236 /* 159 128 191 160 223 192 255 224 */
237 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
238 /* 287 256 319 288 351 320 383 352 */
239 0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
240 /* 415 384 447 416 479 448 511 480 */
241 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
243 /* ownDmaChannels */
244 /* 31 0 63 32 */
245 {0x00000000u, 0x0000FF00u},
247 /* ownQdmaChannels */
248 /* 31 0 */
249 {0x0000000Fu},
251 /* ownTccs */
252 /* 31 0 63 32 */
253 {0x00000000u, 0x0000FF00u},
255 /* resvdPaRAMSets */
256 /* 31 0 63 32 95 64 127 96 */
257 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
258 /* 159 128 191 160 223 192 255 224 */
259 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
260 /* 287 256 319 288 351 320 383 352 */
261 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
262 /* 415 384 447 416 479 448 511 480 */
263 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
265 /* resvdDmaChannels */
266 /* 31 0 63 32 */
267 {0xFFFFFFFFu, 0xFF0000FFu},
269 /* resvdQdmaChannels */
270 /* 31 0 */
271 {0x00000000u},
273 /* resvdTccs */
274 /* 31 0 63 32 */
275 {0xFFFFFFFFu, 0xFF0000FFu},
276 },
278 /* Resources owned/reserved by region 1 */
279 {
280 /* ownPaRAMSets */
281 /* 31 0 63 32 95 64 127 96 */
282 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
283 /* 159 128 191 160 223 192 255 224 */
284 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
285 /* 287 256 319 288 351 320 383 352 */
286 0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
287 /* 415 384 447 416 479 448 511 480 */
288 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,},
290 /* ownDmaChannels */
291 /* 31 0 63 32 */
292 {0x00000000u, 0x00FF0000u},
294 /* ownQdmaChannels */
295 /* 31 0 */
296 {0x000000F0u},
298 /* ownTccs */
299 /* 31 0 63 32 */
300 {0x00000000u, 0x00FF0000u},
302 /* resvdPaRAMSets */
303 /* 31 0 63 32 95 64 127 96 */
304 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
305 /* 159 128 191 160 223 192 255 224 */
306 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
307 /* 287 256 319 288 351 320 383 352 */
308 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
309 /* 415 384 447 416 479 448 511 480 */
310 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
312 /* resvdDmaChannels */
313 /* 31 0 63 32 */
314 {0xFFFFFFFFu, 0xFF0000FFu},
316 /* resvdQdmaChannels */
317 /* 31 0 */
318 {0x00000000u},
320 /* resvdTccs */
321 /* 31 0 63 32 */
322 {0xFFFFFFFFu, 0xFF0000FFu},
323 },
325 /* Resources owned/reserved by region 2 */
326 {
327 /* ownPaRAMSets */
328 /* 31 0 63 32 95 64 127 96 */
329 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
330 /* 159 128 191 160 223 192 255 224 */
331 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
332 /* 287 256 319 288 351 320 383 352 */
333 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
334 /* 415 384 447 416 479 448 511 480 */
335 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
337 /* ownDmaChannels */
338 /* 31 0 63 32 */
339 {0x00000000u, 0x00000000u},
341 /* ownQdmaChannels */
342 /* 31 0 */
343 {0x00000000u},
345 /* ownTccs */
346 /* 31 0 63 32 */
347 {0x00000000u, 0x00000000u},
349 /* resvdPaRAMSets */
350 /* 31 0 63 32 95 64 127 96 */
351 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
352 /* 159 128 191 160 223 192 255 224 */
353 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
354 /* 287 256 319 288 351 320 383 352 */
355 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
356 /* 415 384 447 416 479 448 511 480 */
357 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
359 /* resvdDmaChannels */
360 /* 31 0 63 32 */
361 {0x00000000u, 0x00000000u},
363 /* resvdQdmaChannels */
364 /* 31 0 */
365 {0x00000000u},
367 /* resvdTccs */
368 /* 31 0 63 32 */
369 {0x00000000u, 0x00000000u},
370 },
372 /* Resources owned/reserved by region 3 */
373 {
374 /* ownPaRAMSets */
375 /* 31 0 63 32 95 64 127 96 */
376 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
377 /* 159 128 191 160 223 192 255 224 */
378 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
379 /* 287 256 319 288 351 320 383 352 */
380 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
381 /* 415 384 447 416 479 448 511 480 */
382 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
384 /* ownDmaChannels */
385 /* 31 0 63 32 */
386 {0x00000000u, 0x00000000u},
388 /* ownQdmaChannels */
389 /* 31 0 */
390 {0x00000000u},
392 /* ownTccs */
393 /* 31 0 63 32 */
394 {0x00000000u, 0x00000000u},
396 /* resvdPaRAMSets */
397 /* 31 0 63 32 95 64 127 96 */
398 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
399 /* 159 128 191 160 223 192 255 224 */
400 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
401 /* 287 256 319 288 351 320 383 352 */
402 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
403 /* 415 384 447 416 479 448 511 480 */
404 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
406 /* resvdDmaChannels */
407 /* 31 0 63 32 */
408 {0x00000000u, 0x00000000u},
410 /* resvdQdmaChannels */
411 /* 31 0 */
412 {0x00000000u},
414 /* resvdTccs */
415 /* 31 0 63 32 */
416 {0x00000000u, 0x00000000u},
417 },
419 /* Resources owned/reserved by region 4 */
420 {
421 /* ownPaRAMSets */
422 /* 31 0 63 32 95 64 127 96 */
423 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
424 /* 159 128 191 160 223 192 255 224 */
425 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
426 /* 287 256 319 288 351 320 383 352 */
427 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
428 /* 415 384 447 416 479 448 511 480 */
429 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
431 /* ownDmaChannels */
432 /* 31 0 63 32 */
433 {0x00000000u, 0x00000000u},
435 /* ownQdmaChannels */
436 /* 31 0 */
437 {0x00000000u},
439 /* ownTccs */
440 /* 31 0 63 32 */
441 {0x00000000u, 0x00000000u},
443 /* resvdPaRAMSets */
444 /* 31 0 63 32 95 64 127 96 */
445 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
446 /* 159 128 191 160 223 192 255 224 */
447 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
448 /* 287 256 319 288 351 320 383 352 */
449 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
450 /* 415 384 447 416 479 448 511 480 */
451 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
453 /* resvdDmaChannels */
454 /* 31 0 63 32 */
455 {0x00000000u, 0x00000000u},
457 /* resvdQdmaChannels */
458 /* 31 0 */
459 {0x00000000u},
461 /* resvdTccs */
462 /* 31 0 63 32 */
463 {0x00000000u, 0x00000000u},
464 },
466 /* Resources owned/reserved by region 5 */
467 {
468 /* ownPaRAMSets */
469 /* 31 0 63 32 95 64 127 96 */
470 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
471 /* 159 128 191 160 223 192 255 224 */
472 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
473 /* 287 256 319 288 351 320 383 352 */
474 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
475 /* 415 384 447 416 479 448 511 480 */
476 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
478 /* ownDmaChannels */
479 /* 31 0 63 32 */
480 {0x00000000u, 0x00000000u},
482 /* ownQdmaChannels */
483 /* 31 0 */
484 {0x00000000u},
486 /* ownTccs */
487 /* 31 0 63 32 */
488 {0x00000000u, 0x00000000u},
490 /* resvdPaRAMSets */
491 /* 31 0 63 32 95 64 127 96 */
492 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
493 /* 159 128 191 160 223 192 255 224 */
494 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
495 /* 287 256 319 288 351 320 383 352 */
496 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
497 /* 415 384 447 416 479 448 511 480 */
498 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
500 /* resvdDmaChannels */
501 /* 31 0 63 32 */
502 {0x00000000u, 0x00000000u},
504 /* resvdQdmaChannels */
505 /* 31 0 */
506 {0x00000000u},
508 /* resvdTccs */
509 /* 31 0 63 32 */
510 {0x00000000u, 0x00000000u},
511 },
513 /* Resources owned/reserved by region 6 */
514 {
515 /* ownPaRAMSets */
516 /* 31 0 63 32 95 64 127 96 */
517 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
518 /* 159 128 191 160 223 192 255 224 */
519 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
520 /* 287 256 319 288 351 320 383 352 */
521 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
522 /* 415 384 447 416 479 448 511 480 */
523 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
525 /* ownDmaChannels */
526 /* 31 0 63 32 */
527 {0x00000000u, 0x00000000u},
529 /* ownQdmaChannels */
530 /* 31 0 */
531 {0x00000000u},
533 /* ownTccs */
534 /* 31 0 63 32 */
535 {0x00000000u, 0x00000000u},
537 /* resvdPaRAMSets */
538 /* 31 0 63 32 95 64 127 96 */
539 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
540 /* 159 128 191 160 223 192 255 224 */
541 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
542 /* 287 256 319 288 351 320 383 352 */
543 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
544 /* 415 384 447 416 479 448 511 480 */
545 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
547 /* resvdDmaChannels */
548 /* 31 0 63 32 */
549 {0x00000000u, 0x00000000u},
551 /* resvdQdmaChannels */
552 /* 31 0 */
553 {0x00000000u},
555 /* resvdTccs */
556 /* 31 0 63 32 */
557 {0x00000000u, 0x00000000u},
558 },
560 /* Resources owned/reserved by region 7 */
561 {
562 /* ownPaRAMSets */
563 /* 31 0 63 32 95 64 127 96 */
564 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
565 /* 159 128 191 160 223 192 255 224 */
566 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
567 /* 287 256 319 288 351 320 383 352 */
568 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
569 /* 415 384 447 416 479 448 511 480 */
570 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
572 /* ownDmaChannels */
573 /* 31 0 63 32 */
574 {0x00000000u, 0x00000000u},
576 /* ownQdmaChannels */
577 /* 31 0 */
578 {0x00000000u},
580 /* ownTccs */
581 /* 31 0 63 32 */
582 {0x00000000u, 0x00000000u},
584 /* resvdPaRAMSets */
585 /* 31 0 63 32 95 64 127 96 */
586 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
587 /* 159 128 191 160 223 192 255 224 */
588 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
589 /* 287 256 319 288 351 320 383 352 */
590 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
591 /* 415 384 447 416 479 448 511 480 */
592 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
594 /* resvdDmaChannels */
595 /* 31 0 63 32 */
596 {0x00000000u, 0x00000000u},
598 /* resvdQdmaChannels */
599 /* 31 0 */
600 {0x00000000u},
602 /* resvdTccs */
603 /* 31 0 63 32 */
604 {0x00000000u, 0x00000000u},
605 },
606 },
607 };
609 /* End of File */