[keystone-rtos/edma3_lld.git] / packages / ti / sdo / edma3 / rm / src / configs / edma3_c6670_cfg.c
1 /*
2 * edma3_c6670_cfg.c
3 *
4 * EDMA3 Resource Manager Adaptation Configuration File (SoC Specific).
5 *
6 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
7 *
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 *
13 * Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 *
16 * Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the
19 * distribution.
20 *
21 * Neither the name of Texas Instruments Incorporated nor the names of
22 * its contributors may be used to endorse or promote products derived
23 * from this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 */
39 #include <ti/sdo/edma3/rm/edma3_rm.h>
41 #define NUM_EDMA3_INSTANCES 3u
43 /* Driver Object Initialization Configuration */
44 EDMA3_RM_GblConfigParams edma3GblCfgParams [NUM_EDMA3_INSTANCES] =
45 {
46 {
47 /* EDMA3 INSTANCE# 0 */
48 /** Total number of DMA Channels supported by the EDMA3 Controller */
49 16u,
50 /** Total number of QDMA Channels supported by the EDMA3 Controller */
51 8u,
52 /** Total number of TCCs supported by the EDMA3 Controller */
53 16u,
54 /** Total number of PaRAM Sets supported by the EDMA3 Controller */
55 128u,
56 /** Total number of Event Queues in the EDMA3 Controller */
57 2u,
58 /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
59 2u,
60 /** Number of Regions on this EDMA3 controller */
61 8u,
63 /**
64 * \brief Channel mapping existence
65 * A value of 0 (No channel mapping) implies that there is fixed association
66 * for a channel number to a parameter entry number or, in other words,
67 * PaRAM entry n corresponds to channel n.
68 */
69 1u,
71 /** Existence of memory protection feature */
72 1u,
74 /** Global Register Region of CC Registers */
75 (void *)0x02700000u,
76 /** Transfer Controller (TC) Registers */
77 {
78 (void *)0x02760000u,
79 (void *)0x02768000u,
80 (void *)NULL,
81 (void *)NULL,
82 (void *)NULL,
83 (void *)NULL,
84 (void *)NULL,
85 (void *)NULL
86 },
87 /** Interrupt no. for Transfer Completion */
88 38u,
89 /** Interrupt no. for CC Error */
90 32u,
91 /** Interrupt no. for TCs Error */
92 {
93 34u,
94 35u,
95 0u,
96 0u,
97 0u,
98 0u,
99 0u,
100 0u,
101 },
103 /**
104 * \brief EDMA3 TC priority setting
105 *
106 * User can program the priority of the Event Queues
107 * at a system-wide level. This means that the user can set the
108 * priority of an IO initiated by either of the TCs (Transfer Controllers)
109 * relative to IO initiated by the other bus masters on the
110 * device (ARM, DSP, USB, etc)
111 */
112 {
113 0u,
114 1u,
115 0u,
116 0u,
117 0u,
118 0u,
119 0u,
120 0u
121 },
122 /**
123 * \brief To Configure the Threshold level of number of events
124 * that can be queued up in the Event queues. EDMA3CC error register
125 * (CCERR) will indicate whether or not at any instant of time the
126 * number of events queued up in any of the event queues exceeds
127 * or equals the threshold/watermark value that is set
128 * in the queue watermark threshold register (QWMTHRA).
129 */
130 {
131 16u,
132 16u,
133 0u,
134 0u,
135 0u,
136 0u,
137 0u,
138 0u
139 },
141 /**
142 * \brief To Configure the Default Burst Size (DBS) of TCs.
143 * An optimally-sized command is defined by the transfer controller
144 * default burst size (DBS). Different TCs can have different
145 * DBS values. It is defined in Bytes.
146 */
147 {
148 128u,
149 128u,
150 0u,
151 0u,
152 0u,
153 0u,
154 0u,
155 0u
156 },
158 /**
159 * \brief Mapping from each DMA channel to a Parameter RAM set,
160 * if it exists, otherwise of no use.
161 */
162 {
163 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
164 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
165 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
166 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
167 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
168 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
169 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
170 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
171 /* DMA channels 16-63 DOES NOT exist */
172 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
173 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
174 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
175 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
176 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
177 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
178 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
179 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
180 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
181 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
182 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
183 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
184 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
185 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
186 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
187 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
188 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
189 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
190 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
191 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
192 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
193 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
194 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
195 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS
196 },
198 /**
199 * \brief Mapping from each DMA channel to a TCC. This specific
200 * TCC code will be returned when the transfer is completed
201 * on the mapped channel.
202 */
203 {
204 0u, 1u, 2u, 3u,
205 4u, 5u, 6u, 7u,
206 8u, 9u, 10u, 11u,
207 12u, 13u, 14u, 15u,
208 /* DMA channels 16-63 DOES NOT exist */
209 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
210 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
211 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
212 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
213 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
214 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
215 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
216 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
217 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
218 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
219 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
220 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC
221 },
223 /**
224 * \brief Mapping of DMA channels to Hardware Events from
225 * various peripherals, which use EDMA for data transfer.
226 * All channels need not be mapped, some can be free also.
227 */
228 {
229 0x0000FFFFu,
230 0x00000000u
231 }
232 },
234 {
235 /* EDMA3 INSTANCE# 1 */
236 /** Total number of DMA Channels supported by the EDMA3 Controller */
237 64u,
238 /** Total number of QDMA Channels supported by the EDMA3 Controller */
239 8u,
240 /** Total number of TCCs supported by the EDMA3 Controller */
241 64u,
242 /** Total number of PaRAM Sets supported by the EDMA3 Controller */
243 512u,
244 /** Total number of Event Queues in the EDMA3 Controller */
245 4u,
246 /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
247 4u,
248 /** Number of Regions on this EDMA3 controller */
249 8u,
251 /**
252 * \brief Channel mapping existence
253 * A value of 0 (No channel mapping) implies that there is fixed association
254 * for a channel number to a parameter entry number or, in other words,
255 * PaRAM entry n corresponds to channel n.
256 */
257 1u,
259 /** Existence of memory protection feature */
260 1u,
262 /** Global Register Region of CC Registers */
263 (void *)0x02720000u,
264 /** Transfer Controller (TC) Registers */
265 {
266 (void *)0x02770000u,
267 (void *)0x02778000u,
268 (void *)0x02780000u,
269 (void *)0x02788000u,
270 (void *)NULL,
271 (void *)NULL,
272 (void *)NULL,
273 (void *)NULL
274 },
275 /** Interrupt no. for Transfer Completion */
276 8u,
277 /** Interrupt no. for CC Error */
278 0u,
279 /** Interrupt no. for TCs Error */
280 {
281 2u,
282 3u,
283 4u,
284 5u,
285 0u,
286 0u,
287 0u,
288 0u,
289 },
291 /**
292 * \brief EDMA3 TC priority setting
293 *
294 * User can program the priority of the Event Queues
295 * at a system-wide level. This means that the user can set the
296 * priority of an IO initiated by either of the TCs (Transfer Controllers)
297 * relative to IO initiated by the other bus masters on the
298 * device (ARM, DSP, USB, etc)
299 */
300 {
301 0u,
302 1u,
303 2u,
304 3u,
305 0u,
306 0u,
307 0u,
308 0u
309 },
310 /**
311 * \brief To Configure the Threshold level of number of events
312 * that can be queued up in the Event queues. EDMA3CC error register
313 * (CCERR) will indicate whether or not at any instant of time the
314 * number of events queued up in any of the event queues exceeds
315 * or equals the threshold/watermark value that is set
316 * in the queue watermark threshold register (QWMTHRA).
317 */
318 {
319 16u,
320 16u,
321 16u,
322 16u,
323 0u,
324 0u,
325 0u,
326 0u
327 },
329 /**
330 * \brief To Configure the Default Burst Size (DBS) of TCs.
331 * An optimally-sized command is defined by the transfer controller
332 * default burst size (DBS). Different TCs can have different
333 * DBS values. It is defined in Bytes.
334 */
335 {
336 64u,
337 64u,
338 64u,
339 64u,
340 0u,
341 0u,
342 0u,
343 0u
344 },
346 /**
347 * \brief Mapping from each DMA channel to a Parameter RAM set,
348 * if it exists, otherwise of no use.
349 */
350 {
351 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
352 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
353 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
354 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
355 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
356 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
357 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
358 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
359 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
360 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
361 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
362 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
363 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
364 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
365 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
366 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
367 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
368 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
369 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
370 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
371 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
372 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
373 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
374 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
375 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
376 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
377 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
378 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
379 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
380 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
381 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
382 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP
383 },
385 /**
386 * \brief Mapping from each DMA channel to a TCC. This specific
387 * TCC code will be returned when the transfer is completed
388 * on the mapped channel.
389 */
390 {
391 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
392 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
393 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
394 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
395 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
396 40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
397 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
398 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
399 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
400 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP
401 },
403 /**
404 * \brief Mapping of DMA channels to Hardware Events from
405 * various peripherals, which use EDMA for data transfer.
406 * All channels need not be mapped, some can be free also.
407 */
408 {
409 0xFFFFFFFFu,
410 0x0000FFFFu
411 }
412 },
414 {
415 /* EDMA3 INSTANCE# 2 */
416 /** Total number of DMA Channels supported by the EDMA3 Controller */
417 64u,
418 /** Total number of QDMA Channels supported by the EDMA3 Controller */
419 8u,
420 /** Total number of TCCs supported by the EDMA3 Controller */
421 64u,
422 /** Total number of PaRAM Sets supported by the EDMA3 Controller */
423 512u,
424 /** Total number of Event Queues in the EDMA3 Controller */
425 4u,
426 /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
427 4u,
428 /** Number of Regions on this EDMA3 controller */
429 8u,
431 /**
432 * \brief Channel mapping existence
433 * A value of 0 (No channel mapping) implies that there is fixed association
434 * for a channel number to a parameter entry number or, in other words,
435 * PaRAM entry n corresponds to channel n.
436 */
437 1u,
439 /** Existence of memory protection feature */
440 1u,
442 /** Global Register Region of CC Registers */
443 (void *)0x02740000u,
444 /** Transfer Controller (TC) Registers */
445 {
446 (void *)0x02790000u,
447 (void *)0x02798000u,
448 (void *)0x027A0000u,
449 (void *)0x027A8000u,
450 (void *)NULL,
451 (void *)NULL,
452 (void *)NULL,
453 (void *)NULL
454 },
455 /** Interrupt no. for Transfer Completion */
456 24u,
457 /** Interrupt no. for CC Error */
458 16u,
459 /** Interrupt no. for TCs Error */
460 {
461 18u,
462 19u,
463 20u,
464 21u,
465 0u,
466 0u,
467 0u,
468 0u,
469 },
471 /**
472 * \brief EDMA3 TC priority setting
473 *
474 * User can program the priority of the Event Queues
475 * at a system-wide level. This means that the user can set the
476 * priority of an IO initiated by either of the TCs (Transfer Controllers)
477 * relative to IO initiated by the other bus masters on the
478 * device (ARM, DSP, USB, etc)
479 */
480 {
481 0u,
482 1u,
483 2u,
484 3u,
485 0u,
486 0u,
487 0u,
488 0u
489 },
490 /**
491 * \brief To Configure the Threshold level of number of events
492 * that can be queued up in the Event queues. EDMA3CC error register
493 * (CCERR) will indicate whether or not at any instant of time the
494 * number of events queued up in any of the event queues exceeds
495 * or equals the threshold/watermark value that is set
496 * in the queue watermark threshold register (QWMTHRA).
497 */
498 {
499 16u,
500 16u,
501 16u,
502 16u,
503 0u,
504 0u,
505 0u,
506 0u
507 },
509 /**
510 * \brief To Configure the Default Burst Size (DBS) of TCs.
511 * An optimally-sized command is defined by the transfer controller
512 * default burst size (DBS). Different TCs can have different
513 * DBS values. It is defined in Bytes.
514 */
515 {
516 64u,
517 64u,
518 64u,
519 64u,
520 0u,
521 0u,
522 0u,
523 0u
524 },
526 /**
527 * \brief Mapping from each DMA channel to a Parameter RAM set,
528 * if it exists, otherwise of no use.
529 */
530 {
531 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
532 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
533 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
534 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
535 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
536 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
537 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
538 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
539 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
540 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
541 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
542 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
543 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
544 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
545 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
546 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
547 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
548 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
549 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
550 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
551 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
552 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
553 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
554 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
555 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
556 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
557 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
558 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
559 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
560 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
561 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
562 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP
563 },
565 /**
566 * \brief Mapping from each DMA channel to a TCC. This specific
567 * TCC code will be returned when the transfer is completed
568 * on the mapped channel.
569 */
570 {
571 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
572 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
573 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
574 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
575 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
576 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
577 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
578 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
579 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
580 56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u
581 },
583 /**
584 * \brief Mapping of DMA channels to Hardware Events from
585 * various peripherals, which use EDMA for data transfer.
586 * All channels need not be mapped, some can be free also.
587 */
588 {
589 0xFFFFFFFFu,
590 0xFF0000FFu
591 }
592 },
593 };
595 EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
596 {
597 /* EDMA3 INSTANCE# 0 */
598 {
599 /* Resources owned/reserved by region 0 */
600 {
601 /* ownPaRAMSets */
602 /* 31 0 63 32 95 64 127 96 */
603 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
604 /* 159 128 191 160 223 192 255 224 */
605 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
606 /* 287 256 319 288 351 320 383 352 */
607 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
608 /* 415 384 447 416 479 448 511 480 */
609 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
611 /* ownDmaChannels */
612 /* 31 0 63 32 */
613 {0x00000000u, 0x00000000u},
615 /* ownQdmaChannels */
616 /* 31 0 */
617 {0x00000000u},
619 /* ownTccs */
620 /* 31 0 63 32 */
621 {0x00000000u, 0x00000000u},
623 /* resvdPaRAMSets */
624 /* 31 0 63 32 95 64 127 96 */
625 {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
626 /* 159 128 191 160 223 192 255 224 */
627 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
628 /* 287 256 319 288 351 320 383 352 */
629 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
630 /* 415 384 447 416 479 448 511 480 */
631 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
633 /* resvdDmaChannels */
634 /* 31 0 63 32*/
635 {0x0000FFFFu, 0x00000000u},
637 /* resvdQdmaChannels */
638 /* 31 0 */
639 {0x000000FFu},
641 /* resvdTccs */
642 /* 31 0 63 32*/
643 {0x0000FFFFu, 0x00000000u},
644 },
646 /* Resources owned/reserved by region 1 */
647 {
648 /* ownPaRAMSets */
649 /* 31 0 63 32 95 64 127 96 */
650 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
651 /* 159 128 191 160 223 192 255 224 */
652 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
653 /* 287 256 319 288 351 320 383 352 */
654 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
655 /* 415 384 447 416 479 448 511 480 */
656 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
658 /* ownDmaChannels */
659 /* 31 0 63 32 */
660 {0x00000000u, 0x00000000u},
662 /* ownQdmaChannels */
663 /* 31 0 */
664 {0x00000000u},
666 /* ownTccs */
667 /* 31 0 63 32 */
668 {0x00000000u, 0x00000000u},
670 /* resvdPaRAMSets */
671 /* 31 0 63 32 95 64 127 96 */
672 {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
673 /* 159 128 191 160 223 192 255 224 */
674 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
675 /* 287 256 319 288 351 320 383 352 */
676 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
677 /* 415 384 447 416 479 448 511 480 */
678 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
680 /* resvdDmaChannels */
681 /* 31 0 63 32*/
682 {0x0000FFFFu, 0x00000000u},
684 /* resvdQdmaChannels */
685 /* 31 0 */
686 {0x000000FFu},
688 /* resvdTccs */
689 /* 31 0 63 32*/
690 {0x0000FFFFu, 0x00000000u},
691 },
693 /* Resources owned/reserved by region 2 */
694 {
695 /* ownPaRAMSets */
696 /* 31 0 63 32 95 64 127 96 */
697 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
698 /* 159 128 191 160 223 192 255 224 */
699 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
700 /* 287 256 319 288 351 320 383 352 */
701 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
702 /* 415 384 447 416 479 448 511 480 */
703 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
705 /* ownDmaChannels */
706 /* 31 0 63 32 */
707 {0x00000000u, 0x00000000u},
709 /* ownQdmaChannels */
710 /* 31 0 */
711 {0x00000000u},
713 /* ownTccs */
714 /* 31 0 63 32 */
715 {0x00000000u, 0x00000000u},
717 /* resvdPaRAMSets */
718 /* 31 0 63 32 95 64 127 96 */
719 {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
720 /* 159 128 191 160 223 192 255 224 */
721 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
722 /* 287 256 319 288 351 320 383 352 */
723 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
724 /* 415 384 447 416 479 448 511 480 */
725 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
727 /* resvdDmaChannels */
728 /* 31 0 63 32*/
729 {0x0000FFFFu, 0x00000000u},
731 /* resvdQdmaChannels */
732 /* 31 0 */
733 {0x000000FFu},
735 /* resvdTccs */
736 /* 31 0 63 32*/
737 {0x0000FFFFu, 0x00000000u},
738 },
740 /* Resources owned/reserved by region 3 */
741 {
742 /* ownPaRAMSets */
743 /* 31 0 63 32 95 64 127 96 */
744 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
745 /* 159 128 191 160 223 192 255 224 */
746 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
747 /* 287 256 319 288 351 320 383 352 */
748 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
749 /* 415 384 447 416 479 448 511 480 */
750 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
752 /* ownDmaChannels */
753 /* 31 0 63 32 */
754 {0x00000000u, 0x00000000u},
756 /* ownQdmaChannels */
757 /* 31 0 */
758 {0x00000000u},
760 /* ownTccs */
761 /* 31 0 63 32 */
762 {0x00000000u, 0x00000000u},
764 /* resvdPaRAMSets */
765 /* 31 0 63 32 95 64 127 96 */
766 {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
767 /* 159 128 191 160 223 192 255 224 */
768 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
769 /* 287 256 319 288 351 320 383 352 */
770 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
771 /* 415 384 447 416 479 448 511 480 */
772 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
774 /* resvdDmaChannels */
775 /* 31 0 63 32*/
776 {0x0000FFFFu, 0x00000000u},
778 /* resvdQdmaChannels */
779 /* 31 0 */
780 {0x000000FFu},
782 /* resvdTccs */
783 /* 31 0 63 32*/
784 {0x0000FFFFu, 0x00000000u},
785 },
787 /* Resources owned/reserved by region 4 */
788 {
789 /* ownPaRAMSets */
790 /* 31 0 63 32 95 64 127 96 */
791 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
792 /* 159 128 191 160 223 192 255 224 */
793 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
794 /* 287 256 319 288 351 320 383 352 */
795 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
796 /* 415 384 447 416 479 448 511 480 */
797 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
799 /* ownDmaChannels */
800 /* 31 0 63 32 */
801 {0x00000000u, 0x00000000u},
803 /* ownQdmaChannels */
804 /* 31 0 */
805 {0x00000000u},
807 /* ownTccs */
808 /* 31 0 63 32 */
809 {0x00000000u, 0x00000000u},
811 /* resvdPaRAMSets */
812 /* 31 0 63 32 95 64 127 96 */
813 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
814 /* 159 128 191 160 223 192 255 224 */
815 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
816 /* 287 256 319 288 351 320 383 352 */
817 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
818 /* 415 384 447 416 479 448 511 480 */
819 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
821 /* resvdDmaChannels */
822 /* 31 0 63 32 */
823 {0x00000000u, 0x00000000u},
825 /* resvdQdmaChannels */
826 /* 31 0 */
827 {0x00000000u},
829 /* resvdTccs */
830 /* 31 0 63 32 */
831 {0x00000000u, 0x00000000u},
832 },
834 /* Resources owned/reserved by region 5 */
835 {
836 /* ownPaRAMSets */
837 /* 31 0 63 32 95 64 127 96 */
838 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
839 /* 159 128 191 160 223 192 255 224 */
840 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
841 /* 287 256 319 288 351 320 383 352 */
842 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
843 /* 415 384 447 416 479 448 511 480 */
844 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
846 /* ownDmaChannels */
847 /* 31 0 63 32 */
848 {0x00000000u, 0x00000000u},
850 /* ownQdmaChannels */
851 /* 31 0 */
852 {0x00000000u},
854 /* ownTccs */
855 /* 31 0 63 32 */
856 {0x00000000u, 0x00000000u},
858 /* resvdPaRAMSets */
859 /* 31 0 63 32 95 64 127 96 */
860 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
861 /* 159 128 191 160 223 192 255 224 */
862 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
863 /* 287 256 319 288 351 320 383 352 */
864 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
865 /* 415 384 447 416 479 448 511 480 */
866 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
868 /* resvdDmaChannels */
869 /* 31 0 63 32 */
870 {0x00000000u, 0x00000000u},
872 /* resvdQdmaChannels */
873 /* 31 0 */
874 {0x00000000u},
876 /* resvdTccs */
877 /* 31 0 63 32 */
878 {0x00000000u, 0x00000000u},
879 },
881 /* Resources owned/reserved by region 6 */
882 {
883 /* ownPaRAMSets */
884 /* 31 0 63 32 95 64 127 96 */
885 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
886 /* 159 128 191 160 223 192 255 224 */
887 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
888 /* 287 256 319 288 351 320 383 352 */
889 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
890 /* 415 384 447 416 479 448 511 480 */
891 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
893 /* ownDmaChannels */
894 /* 31 0 63 32 */
895 {0x00000000u, 0x00000000u},
897 /* ownQdmaChannels */
898 /* 31 0 */
899 {0x00000000u},
901 /* ownTccs */
902 /* 31 0 63 32 */
903 {0x00000000u, 0x00000000u},
905 /* resvdPaRAMSets */
906 /* 31 0 63 32 95 64 127 96 */
907 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
908 /* 159 128 191 160 223 192 255 224 */
909 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
910 /* 287 256 319 288 351 320 383 352 */
911 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
912 /* 415 384 447 416 479 448 511 480 */
913 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
915 /* resvdDmaChannels */
916 /* 31 0 63 32 */
917 {0x00000000u, 0x00000000u},
919 /* resvdQdmaChannels */
920 /* 31 0 */
921 {0x00000000u},
923 /* resvdTccs */
924 /* 31 0 63 32 */
925 {0x00000000u, 0x00000000u},
926 },
928 /* Resources owned/reserved by region 7 */
929 {
930 /* ownPaRAMSets */
931 /* 31 0 63 32 95 64 127 96 */
932 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
933 /* 159 128 191 160 223 192 255 224 */
934 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
935 /* 287 256 319 288 351 320 383 352 */
936 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
937 /* 415 384 447 416 479 448 511 480 */
938 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
940 /* ownDmaChannels */
941 /* 31 0 63 32 */
942 {0x00000000u, 0x00000000u},
944 /* ownQdmaChannels */
945 /* 31 0 */
946 {0x00000000u},
948 /* ownTccs */
949 /* 31 0 63 32 */
950 {0x00000000u, 0x00000000u},
952 /* resvdPaRAMSets */
953 /* 31 0 63 32 95 64 127 96 */
954 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
955 /* 159 128 191 160 223 192 255 224 */
956 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
957 /* 287 256 319 288 351 320 383 352 */
958 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
959 /* 415 384 447 416 479 448 511 480 */
960 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
962 /* resvdDmaChannels */
963 /* 31 0 63 32 */
964 {0x00000000u, 0x00000000u},
966 /* resvdQdmaChannels */
967 /* 31 0 */
968 {0x00000000u},
970 /* resvdTccs */
971 /* 31 0 63 32 */
972 {0x00000000u, 0x00000000u},
973 },
974 },
976 /* EDMA3 INSTANCE# 1 */
977 {
978 /* Resources owned/reserved by region 0 */
979 {
980 /* ownPaRAMSets */
981 /* 31 0 63 32 95 64 127 96 */
982 {0x00000000u, 0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu,
983 /* 159 128 191 160 223 192 255 224 */
984 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
985 /* 287 256 319 288 351 320 383 352 */
986 0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
987 /* 415 384 447 416 479 448 511 480 */
988 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
990 /* ownDmaChannels */
991 /* 31 0 63 32 */
992 {0x00000000u, 0x00FF0000u},
994 /* ownQdmaChannels */
995 /* 31 0 */
996 {0x0000000Fu},
998 /* ownTccs */
999 /* 31 0 63 32 */
1000 {0x00000000u, 0x00FF0000u},
1002 /* resvdPaRAMSets */
1003 /* 31 0 63 32 95 64 127 96 */
1004 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
1005 /* 159 128 191 160 223 192 255 224 */
1006 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1007 /* 287 256 319 288 351 320 383 352 */
1008 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1009 /* 415 384 447 416 479 448 511 480 */
1010 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1012 /* resvdDmaChannels */
1013 /* 31 0 63 32 */
1014 {0xFFFFFFFFu, 0x0000FFFFu},
1016 /* resvdQdmaChannels */
1017 /* 31 0 */
1018 {0x00000000u},
1020 /* resvdTccs */
1021 /* 31 0 63 32 */
1022 {0xFFFFFFFFu, 0x0000FFFFu},
1023 },
1025 /* Resources owned/reserved by region 1 */
1026 {
1027 /* ownPaRAMSets */
1028 /* 31 0 63 32 95 64 127 96 */
1029 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1030 /* 159 128 191 160 223 192 255 224 */
1031 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1032 /* 287 256 319 288 351 320 383 352 */
1033 0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
1034 /* 415 384 447 416 479 448 511 480 */
1035 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,},
1037 /* ownDmaChannels */
1038 /* 31 0 63 32 */
1039 {0x00000000u, 0xFF000000u},
1041 /* ownQdmaChannels */
1042 /* 31 0 */
1043 {0x000000F0u},
1045 /* ownTccs */
1046 /* 31 0 63 32 */
1047 {0x00000000u, 0xFF000000u},
1049 /* resvdPaRAMSets */
1050 /* 31 0 63 32 95 64 127 96 */
1051 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
1052 /* 159 128 191 160 223 192 255 224 */
1053 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1054 /* 287 256 319 288 351 320 383 352 */
1055 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1056 /* 415 384 447 416 479 448 511 480 */
1057 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1059 /* resvdDmaChannels */
1060 /* 31 0 63 32 */
1061 {0xFFFFFFFFu, 0x0000FFFFu},
1063 /* resvdQdmaChannels */
1064 /* 31 0 */
1065 {0x00000000u},
1067 /* resvdTccs */
1068 /* 31 0 63 32 */
1069 {0xFFFFFFFFu, 0x0000FFFFu},
1070 },
1072 /* Resources owned/reserved by region 2 */
1073 {
1074 /* ownPaRAMSets */
1075 /* 31 0 63 32 95 64 127 96 */
1076 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1077 /* 159 128 191 160 223 192 255 224 */
1078 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1079 /* 287 256 319 288 351 320 383 352 */
1080 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1081 /* 415 384 447 416 479 448 511 480 */
1082 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1084 /* ownDmaChannels */
1085 /* 31 0 63 32 */
1086 {0x00000000u, 0x00000000u},
1088 /* ownQdmaChannels */
1089 /* 31 0 */
1090 {0x00000000u},
1092 /* ownTccs */
1093 /* 31 0 63 32 */
1094 {0x00000000u, 0x00000000u},
1096 /* resvdPaRAMSets */
1097 /* 31 0 63 32 95 64 127 96 */
1098 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
1099 /* 159 128 191 160 223 192 255 224 */
1100 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1101 /* 287 256 319 288 351 320 383 352 */
1102 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1103 /* 415 384 447 416 479 448 511 480 */
1104 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1106 /* resvdDmaChannels */
1107 /* 31 0 63 32 */
1108 {0xFFFFFFFFu, 0x0000FFFFu},
1110 /* resvdQdmaChannels */
1111 /* 31 0 */
1112 {0x00000000u},
1114 /* resvdTccs */
1115 /* 31 0 63 32 */
1116 {0xFFFFFFFFu, 0x0000FFFFu},
1117 },
1119 /* Resources owned/reserved by region 3 */
1120 {
1121 /* ownPaRAMSets */
1122 /* 31 0 63 32 95 64 127 96 */
1123 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1124 /* 159 128 191 160 223 192 255 224 */
1125 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1126 /* 287 256 319 288 351 320 383 352 */
1127 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1128 /* 415 384 447 416 479 448 511 480 */
1129 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1131 /* ownDmaChannels */
1132 /* 31 0 63 32 */
1133 {0x00000000u, 0x00000000u},
1135 /* ownQdmaChannels */
1136 /* 31 0 */
1137 {0x00000000u},
1139 /* ownTccs */
1140 /* 31 0 63 32 */
1141 {0x00000000u, 0x00000000u},
1143 /* resvdPaRAMSets */
1144 /* 31 0 63 32 95 64 127 96 */
1145 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
1146 /* 159 128 191 160 223 192 255 224 */
1147 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1148 /* 287 256 319 288 351 320 383 352 */
1149 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1150 /* 415 384 447 416 479 448 511 480 */
1151 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1153 /* resvdDmaChannels */
1154 /* 31 0 63 32 */
1155 {0xFFFFFFFFu, 0x0000FFFFu},
1157 /* resvdQdmaChannels */
1158 /* 31 0 */
1159 {0x00000000u},
1161 /* resvdTccs */
1162 /* 31 0 63 32 */
1163 {0xFFFFFFFFu, 0x0000FFFFu},
1164 },
1166 /* Resources owned/reserved by region 4 */
1167 {
1168 /* ownPaRAMSets */
1169 /* 31 0 63 32 95 64 127 96 */
1170 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1171 /* 159 128 191 160 223 192 255 224 */
1172 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1173 /* 287 256 319 288 351 320 383 352 */
1174 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1175 /* 415 384 447 416 479 448 511 480 */
1176 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1178 /* ownDmaChannels */
1179 /* 31 0 63 32 */
1180 {0x00000000u, 0x00000000u},
1182 /* ownQdmaChannels */
1183 /* 31 0 */
1184 {0x00000000u},
1186 /* ownTccs */
1187 /* 31 0 63 32 */
1188 {0x00000000u, 0x00000000u},
1190 /* resvdPaRAMSets */
1191 /* 31 0 63 32 95 64 127 96 */
1192 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1193 /* 159 128 191 160 223 192 255 224 */
1194 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1195 /* 287 256 319 288 351 320 383 352 */
1196 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1197 /* 415 384 447 416 479 448 511 480 */
1198 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1200 /* resvdDmaChannels */
1201 /* 31 0 63 32 */
1202 {0x00000000u, 0x00000000u},
1204 /* resvdQdmaChannels */
1205 /* 31 0 */
1206 {0x00000000u},
1208 /* resvdTccs */
1209 /* 31 0 63 32 */
1210 {0x00000000u, 0x00000000u},
1211 },
1213 /* Resources owned/reserved by region 5 */
1214 {
1215 /* ownPaRAMSets */
1216 /* 31 0 63 32 95 64 127 96 */
1217 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1218 /* 159 128 191 160 223 192 255 224 */
1219 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1220 /* 287 256 319 288 351 320 383 352 */
1221 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1222 /* 415 384 447 416 479 448 511 480 */
1223 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1225 /* ownDmaChannels */
1226 /* 31 0 63 32 */
1227 {0x00000000u, 0x00000000u},
1229 /* ownQdmaChannels */
1230 /* 31 0 */
1231 {0x00000000u},
1233 /* ownTccs */
1234 /* 31 0 63 32 */
1235 {0x00000000u, 0x00000000u},
1237 /* resvdPaRAMSets */
1238 /* 31 0 63 32 95 64 127 96 */
1239 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1240 /* 159 128 191 160 223 192 255 224 */
1241 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1242 /* 287 256 319 288 351 320 383 352 */
1243 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1244 /* 415 384 447 416 479 448 511 480 */
1245 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1247 /* resvdDmaChannels */
1248 /* 31 0 63 32 */
1249 {0x00000000u, 0x00000000u},
1251 /* resvdQdmaChannels */
1252 /* 31 0 */
1253 {0x00000000u},
1255 /* resvdTccs */
1256 /* 31 0 63 32 */
1257 {0x00000000u, 0x00000000u},
1258 },
1260 /* Resources owned/reserved by region 6 */
1261 {
1262 /* ownPaRAMSets */
1263 /* 31 0 63 32 95 64 127 96 */
1264 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1265 /* 159 128 191 160 223 192 255 224 */
1266 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1267 /* 287 256 319 288 351 320 383 352 */
1268 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1269 /* 415 384 447 416 479 448 511 480 */
1270 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1272 /* ownDmaChannels */
1273 /* 31 0 63 32 */
1274 {0x00000000u, 0x00000000u},
1276 /* ownQdmaChannels */
1277 /* 31 0 */
1278 {0x00000000u},
1280 /* ownTccs */
1281 /* 31 0 63 32 */
1282 {0x00000000u, 0x00000000u},
1284 /* resvdPaRAMSets */
1285 /* 31 0 63 32 95 64 127 96 */
1286 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1287 /* 159 128 191 160 223 192 255 224 */
1288 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1289 /* 287 256 319 288 351 320 383 352 */
1290 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1291 /* 415 384 447 416 479 448 511 480 */
1292 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1294 /* resvdDmaChannels */
1295 /* 31 0 63 32 */
1296 {0x00000000u, 0x00000000u},
1298 /* resvdQdmaChannels */
1299 /* 31 0 */
1300 {0x00000000u},
1302 /* resvdTccs */
1303 /* 31 0 63 32 */
1304 {0x00000000u, 0x00000000u},
1305 },
1307 /* Resources owned/reserved by region 7 */
1308 {
1309 /* ownPaRAMSets */
1310 /* 31 0 63 32 95 64 127 96 */
1311 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1312 /* 159 128 191 160 223 192 255 224 */
1313 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1314 /* 287 256 319 288 351 320 383 352 */
1315 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1316 /* 415 384 447 416 479 448 511 480 */
1317 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1319 /* ownDmaChannels */
1320 /* 31 0 63 32 */
1321 {0x00000000u, 0x00000000u},
1323 /* ownQdmaChannels */
1324 /* 31 0 */
1325 {0x00000000u},
1327 /* ownTccs */
1328 /* 31 0 63 32 */
1329 {0x00000000u, 0x00000000u},
1331 /* resvdPaRAMSets */
1332 /* 31 0 63 32 95 64 127 96 */
1333 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1334 /* 159 128 191 160 223 192 255 224 */
1335 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1336 /* 287 256 319 288 351 320 383 352 */
1337 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1338 /* 415 384 447 416 479 448 511 480 */
1339 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1341 /* resvdDmaChannels */
1342 /* 31 0 63 32 */
1343 {0x00000000u, 0x00000000u},
1345 /* resvdQdmaChannels */
1346 /* 31 0 */
1347 {0x00000000u},
1349 /* resvdTccs */
1350 /* 31 0 63 32 */
1351 {0x00000000u, 0x00000000u},
1352 },
1353 },
1355 /* EDMA3 INSTANCE# 2 */
1356 {
1357 /* Resources owned/reserved by region 0 */
1358 {
1359 /* ownPaRAMSets */
1360 /* 31 0 63 32 95 64 127 96 */
1361 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1362 /* 159 128 191 160 223 192 255 224 */
1363 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1364 /* 287 256 319 288 351 320 383 352 */
1365 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1366 /* 415 384 447 416 479 448 511 480 */
1367 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1369 /* ownDmaChannels */
1370 /* 31 0 63 32 */
1371 {0x00000000u, 0x00000000u},
1373 /* ownQdmaChannels */
1374 /* 31 0 */
1375 {0x00000000u},
1377 /* ownTccs */
1378 /* 31 0 63 32 */
1379 {0x00000000u, 0x00000000u},
1381 /* resvdPaRAMSets */
1382 /* 31 0 63 32 95 64 127 96 */
1383 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
1384 /* 159 128 191 160 223 192 255 224 */
1385 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1386 /* 287 256 319 288 351 320 383 352 */
1387 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1388 /* 415 384 447 416 479 448 511 480 */
1389 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1391 /* resvdDmaChannels */
1392 /* 31 0 63 32 */
1393 {0xFFFFFFFFu, 0xFF0000FFu},
1395 /* resvdQdmaChannels */
1396 /* 31 0 */
1397 {0x00000000u},
1399 /* resvdTccs */
1400 /* 31 0 63 32 */
1401 {0xFFFFFFFFu, 0xFF0000FFu},
1402 },
1404 /* Resources owned/reserved by region 1 */
1405 {
1406 /* ownPaRAMSets */
1407 /* 31 0 63 32 95 64 127 96 */
1408 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1409 /* 159 128 191 160 223 192 255 224 */
1410 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1411 /* 287 256 319 288 351 320 383 352 */
1412 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1413 /* 415 384 447 416 479 448 511 480 */
1414 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1416 /* ownDmaChannels */
1417 /* 31 0 63 32 */
1418 {0x00000000u, 0x00000000u},
1420 /* ownQdmaChannels */
1421 /* 31 0 */
1422 {0x00000000u},
1424 /* ownTccs */
1425 /* 31 0 63 32 */
1426 {0x00000000u, 0x00000000u},
1428 /* resvdPaRAMSets */
1429 /* 31 0 63 32 95 64 127 96 */
1430 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
1431 /* 159 128 191 160 223 192 255 224 */
1432 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1433 /* 287 256 319 288 351 320 383 352 */
1434 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1435 /* 415 384 447 416 479 448 511 480 */
1436 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1438 /* resvdDmaChannels */
1439 /* 31 0 63 32 */
1440 {0xFFFFFFFFu, 0xFF0000FFu},
1442 /* resvdQdmaChannels */
1443 /* 31 0 */
1444 {0x00000000u},
1446 /* resvdTccs */
1447 /* 31 0 63 32 */
1448 {0xFFFFFFFFu, 0xFF0000FFu},
1449 },
1451 /* Resources owned/reserved by region 2 */
1452 {
1453 /* ownPaRAMSets */
1454 /* 31 0 63 32 95 64 127 96 */
1455 {0x00000000u, 0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu,
1456 /* 159 128 191 160 223 192 255 224 */
1457 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
1458 /* 287 256 319 288 351 320 383 352 */
1459 0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
1460 /* 415 384 447 416 479 448 511 480 */
1461 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1463 /* ownDmaChannels */
1464 /* 31 0 63 32 */
1465 {0x00000000u, 0x0000FF00u},
1467 /* ownQdmaChannels */
1468 /* 31 0 */
1469 {0x0000000Fu},
1471 /* ownTccs */
1472 /* 31 0 63 32 */
1473 {0x00000000u, 0x0000FF00u},
1475 /* resvdPaRAMSets */
1476 /* 31 0 63 32 95 64 127 96 */
1477 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
1478 /* 159 128 191 160 223 192 255 224 */
1479 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1480 /* 287 256 319 288 351 320 383 352 */
1481 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1482 /* 415 384 447 416 479 448 511 480 */
1483 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1485 /* resvdDmaChannels */
1486 /* 31 0 63 32 */
1487 {0xFFFFFFFFu, 0xFF0000FFu},
1489 /* resvdQdmaChannels */
1490 /* 31 0 */
1491 {0x00000000u},
1493 /* resvdTccs */
1494 /* 31 0 63 32 */
1495 {0xFFFFFFFFu, 0xFF0000FFu},
1496 },
1498 /* Resources owned/reserved by region 3 */
1499 {
1500 /* ownPaRAMSets */
1501 /* 31 0 63 32 95 64 127 96 */
1502 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1503 /* 159 128 191 160 223 192 255 224 */
1504 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1505 /* 287 256 319 288 351 320 383 352 */
1506 0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
1507 /* 415 384 447 416 479 448 511 480 */
1508 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,},
1510 /* ownDmaChannels */
1511 /* 31 0 63 32 */
1512 {0x00000000u, 0x00FF0000u},
1514 /* ownQdmaChannels */
1515 /* 31 0 */
1516 {0x000000F0u},
1518 /* ownTccs */
1519 /* 31 0 63 32 */
1520 {0x00000000u, 0x00FF0000u},
1522 /* resvdPaRAMSets */
1523 /* 31 0 63 32 95 64 127 96 */
1524 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
1525 /* 159 128 191 160 223 192 255 224 */
1526 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1527 /* 287 256 319 288 351 320 383 352 */
1528 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1529 /* 415 384 447 416 479 448 511 480 */
1530 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1532 /* resvdDmaChannels */
1533 /* 31 0 63 32 */
1534 {0xFFFFFFFFu, 0xFF0000FFu},
1536 /* resvdQdmaChannels */
1537 /* 31 0 */
1538 {0x00000000u},
1540 /* resvdTccs */
1541 /* 31 0 63 32 */
1542 {0xFFFFFFFFu, 0xFF0000FFu},
1543 },
1545 /* Resources owned/reserved by region 4 */
1546 {
1547 /* ownPaRAMSets */
1548 /* 31 0 63 32 95 64 127 96 */
1549 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1550 /* 159 128 191 160 223 192 255 224 */
1551 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1552 /* 287 256 319 288 351 320 383 352 */
1553 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1554 /* 415 384 447 416 479 448 511 480 */
1555 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1557 /* ownDmaChannels */
1558 /* 31 0 63 32 */
1559 {0x00000000u, 0x00000000u},
1561 /* ownQdmaChannels */
1562 /* 31 0 */
1563 {0x00000000u},
1565 /* ownTccs */
1566 /* 31 0 63 32 */
1567 {0x00000000u, 0x00000000u},
1569 /* resvdPaRAMSets */
1570 /* 31 0 63 32 95 64 127 96 */
1571 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1572 /* 159 128 191 160 223 192 255 224 */
1573 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1574 /* 287 256 319 288 351 320 383 352 */
1575 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1576 /* 415 384 447 416 479 448 511 480 */
1577 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1579 /* resvdDmaChannels */
1580 /* 31 0 63 32 */
1581 {0x00000000u, 0x00000000u},
1583 /* resvdQdmaChannels */
1584 /* 31 0 */
1585 {0x00000000u},
1587 /* resvdTccs */
1588 /* 31 0 63 32 */
1589 {0x00000000u, 0x00000000u},
1590 },
1592 /* Resources owned/reserved by region 5 */
1593 {
1594 /* ownPaRAMSets */
1595 /* 31 0 63 32 95 64 127 96 */
1596 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1597 /* 159 128 191 160 223 192 255 224 */
1598 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1599 /* 287 256 319 288 351 320 383 352 */
1600 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1601 /* 415 384 447 416 479 448 511 480 */
1602 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1604 /* ownDmaChannels */
1605 /* 31 0 63 32 */
1606 {0x00000000u, 0x00000000u},
1608 /* ownQdmaChannels */
1609 /* 31 0 */
1610 {0x00000000u},
1612 /* ownTccs */
1613 /* 31 0 63 32 */
1614 {0x00000000u, 0x00000000u},
1616 /* resvdPaRAMSets */
1617 /* 31 0 63 32 95 64 127 96 */
1618 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1619 /* 159 128 191 160 223 192 255 224 */
1620 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1621 /* 287 256 319 288 351 320 383 352 */
1622 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1623 /* 415 384 447 416 479 448 511 480 */
1624 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1626 /* resvdDmaChannels */
1627 /* 31 0 63 32 */
1628 {0x00000000u, 0x00000000u},
1630 /* resvdQdmaChannels */
1631 /* 31 0 */
1632 {0x00000000u},
1634 /* resvdTccs */
1635 /* 31 0 63 32 */
1636 {0x00000000u, 0x00000000u},
1637 },
1639 /* Resources owned/reserved by region 6 */
1640 {
1641 /* ownPaRAMSets */
1642 /* 31 0 63 32 95 64 127 96 */
1643 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1644 /* 159 128 191 160 223 192 255 224 */
1645 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1646 /* 287 256 319 288 351 320 383 352 */
1647 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1648 /* 415 384 447 416 479 448 511 480 */
1649 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1651 /* ownDmaChannels */
1652 /* 31 0 63 32 */
1653 {0x00000000u, 0x00000000u},
1655 /* ownQdmaChannels */
1656 /* 31 0 */
1657 {0x00000000u},
1659 /* ownTccs */
1660 /* 31 0 63 32 */
1661 {0x00000000u, 0x00000000u},
1663 /* resvdPaRAMSets */
1664 /* 31 0 63 32 95 64 127 96 */
1665 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1666 /* 159 128 191 160 223 192 255 224 */
1667 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1668 /* 287 256 319 288 351 320 383 352 */
1669 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1670 /* 415 384 447 416 479 448 511 480 */
1671 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1673 /* resvdDmaChannels */
1674 /* 31 0 63 32 */
1675 {0x00000000u, 0x00000000u},
1677 /* resvdQdmaChannels */
1678 /* 31 0 */
1679 {0x00000000u},
1681 /* resvdTccs */
1682 /* 31 0 63 32 */
1683 {0x00000000u, 0x00000000u},
1684 },
1686 /* Resources owned/reserved by region 7 */
1687 {
1688 /* ownPaRAMSets */
1689 /* 31 0 63 32 95 64 127 96 */
1690 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1691 /* 159 128 191 160 223 192 255 224 */
1692 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1693 /* 287 256 319 288 351 320 383 352 */
1694 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1695 /* 415 384 447 416 479 448 511 480 */
1696 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1698 /* ownDmaChannels */
1699 /* 31 0 63 32 */
1700 {0x00000000u, 0x00000000u},
1702 /* ownQdmaChannels */
1703 /* 31 0 */
1704 {0x00000000u},
1706 /* ownTccs */
1707 /* 31 0 63 32 */
1708 {0x00000000u, 0x00000000u},
1710 /* resvdPaRAMSets */
1711 /* 31 0 63 32 95 64 127 96 */
1712 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1713 /* 159 128 191 160 223 192 255 224 */
1714 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1715 /* 287 256 319 288 351 320 383 352 */
1716 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1717 /* 415 384 447 416 479 448 511 480 */
1718 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1720 /* resvdDmaChannels */
1721 /* 31 0 63 32 */
1722 {0x00000000u, 0x00000000u},
1724 /* resvdQdmaChannels */
1725 /* 31 0 */
1726 {0x00000000u},
1728 /* resvdTccs */
1729 /* 31 0 63 32 */
1730 {0x00000000u, 0x00000000u},
1731 },
1732 },
1733 };
1735 /* End of File */