[keystone-rtos/edma3_lld.git] / packages / ti / sdo / edma3 / rm / src / configs / edma3_c6a811x_cfg.c
1 /*
2 * edma3_c6a811x_cfg.c
3 *
4 * EDMA3 Driver Adaptation Configuration File (Soc Specific) for OMAPL138.
5 *
6 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
7 *
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 *
13 * Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 *
16 * Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the
19 * distribution.
20 *
21 * Neither the name of Texas Instruments Incorporated nor the names of
22 * its contributors may be used to endorse or promote products derived
23 * from this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 */
39 #include <ti/sdo/edma3/rm/edma3_rm.h>
41 /* Number of EDMA3 controllers present in the system */
42 #define NUM_EDMA3_INSTANCES 1u
44 /**
45 * \brief Mapping of DMA channels 0-31 to Hardware Events from
46 * various peripherals, which use EDMA for data transfer.
47 * All channels need not be mapped, some can be free also.
48 * 1: Mapped
49 * 0: Not mapped
50 *
51 * This mapping will be used to allocate DMA channels when user passes
52 * EDMA3_RM_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
53 * copy). The same mapping is used to allocate the TCC when user passes
54 * EDMA3_RM_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
55 *
56 * To allocate more DMA channels or TCCs, one has to modify the event mapping.
57 */
58 /* EDMA3 0 */
59 /* 31 0 */
60 #define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0 (0xFCFF3F0Cu) /* TBD */
62 /**
63 * \brief Mapping of DMA channels 32-63 to Hardware Events from
64 * various peripherals, which use EDMA for data transfer.
65 * All channels need not be mapped, some can be free also.
66 * 1: Mapped
67 * 0: Not mapped
68 *
69 * This mapping will be used to allocate DMA channels when user passes
70 * EDMA3_RM_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
71 * copy). The same mapping is used to allocate the TCC when user passes
72 * EDMA3_RM_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
73 *
74 * To allocate more DMA channels or TCCs, one has to modify the event mapping.
75 */
76 #define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1 (0xFF003C00u) /* TBD */
78 /** Number of PaRAM Sets available */
79 #define EDMA3_NUM_PARAMSET (512u)
81 /** Number of TCCS available */
82 #define EDMA3_NUM_TCC (64u)
84 /** Number of DMA Channels available */
85 #define EDMA3_NUM_DMA_CHANNELS (64u)
87 /** Number of QDMA Channels available */
88 #define EDMA3_NUM_QDMA_CHANNELS (8u)
90 /** Number of Event Queues available */
91 #define EDMA3_NUM_EVTQUE (4u)
93 /** Number of Transfer Controllers available */
94 #define EDMA3_NUM_TC (4u)
96 /** Number of Regions */
97 #define EDMA3_NUM_REGIONS (6u)
100 /** Interrupt no. for Transfer Completion */
101 #define EDMA3_CC_XFER_COMPLETION_INT_A8 (12u)
102 #define EDMA3_CC_XFER_COMPLETION_INT_DSP (20u)
103 #define EDMA3_CC_XFER_COMPLETION_INT_M3VPSS (63u)
104 #define EDMA3_CC_XFER_COMPLETION_INT_M3VIDEO (62u)
106 #ifdef BUILD_C6A811X_A8
107 #define EDMA3_CC_XFER_COMPLETION_INT EDMA3_CC_XFER_COMPLETION_INT_A8
108 #elif defined BUILD_C6A811X_DSP
109 #define EDMA3_CC_XFER_COMPLETION_INT EDMA3_CC_XFER_COMPLETION_INT_DSP
110 #elif defined BUILD_C6A811X_M3VIDEO
111 #define EDMA3_CC_XFER_COMPLETION_INT EDMA3_CC_XFER_COMPLETION_INT_M3VIDEO
112 #elif defined BUILD_C6A811X_M3VPSS
113 #define EDMA3_CC_XFER_COMPLETION_INT EDMA3_CC_XFER_COMPLETION_INT_M3VPSS
114 #else
115 #define EDMA3_CC_XFER_COMPLETION_INT (0u)
116 #endif
118 /** Interrupt no. for CC Error */
119 #define EDMA3_CC_ERROR_INT_A8 (14u)
120 #define EDMA3_CC_ERROR_INT_DSP (21u)
122 #ifdef BUILD_C6A811X_A8
123 #define EDMA3_CC_ERROR_INT EDMA3_CC_ERROR_INT_A8
124 #elif defined BUILD_C6A811X_DSP
125 #define EDMA3_CC_ERROR_INT EDMA3_CC_ERROR_INT_DSP
126 #else
127 #define EDMA3_CC_ERROR_INT (0u)
128 #endif
130 /** Interrupt no. for TCs Error */
131 #define EDMA3_TC0_ERROR_INT_DSP (22u)
132 #define EDMA3_TC1_ERROR_INT_DSP (27u)
133 #define EDMA3_TC2_ERROR_INT_DSP (28u)
134 #define EDMA3_TC3_ERROR_INT_DSP (29u)
135 #define EDMA3_TC0_ERROR_INT_A8 (112u)
136 #define EDMA3_TC1_ERROR_INT_A8 (113u)
137 #define EDMA3_TC2_ERROR_INT_A8 (114u)
138 #define EDMA3_TC3_ERROR_INT_A8 (115u)
140 #ifdef BUILD_C6A811X_A8
141 #define EDMA3_TC0_ERROR_INT EDMA3_TC0_ERROR_INT_A8
142 #define EDMA3_TC1_ERROR_INT EDMA3_TC1_ERROR_INT_A8
143 #define EDMA3_TC2_ERROR_INT EDMA3_TC2_ERROR_INT_A8
144 #define EDMA3_TC3_ERROR_INT EDMA3_TC3_ERROR_INT_A8
145 #elif defined BUILD_C6A811X_DSP
146 #define EDMA3_TC0_ERROR_INT EDMA3_TC0_ERROR_INT_DSP
147 #define EDMA3_TC1_ERROR_INT EDMA3_TC1_ERROR_INT_DSP
148 #define EDMA3_TC2_ERROR_INT EDMA3_TC2_ERROR_INT_DSP
149 #define EDMA3_TC3_ERROR_INT EDMA3_TC3_ERROR_INT_DSP
150 #else
151 #define EDMA3_TC0_ERROR_INT (0u)
152 #define EDMA3_TC1_ERROR_INT (0u)
153 #define EDMA3_TC2_ERROR_INT (0u)
154 #define EDMA3_TC3_ERROR_INT (0u)
155 #endif
157 #define EDMA3_TC4_ERROR_INT (0u)
158 #define EDMA3_TC5_ERROR_INT (0u)
159 #define EDMA3_TC6_ERROR_INT (0u)
160 #define EDMA3_TC7_ERROR_INT (0u)
162 /**
163 * \brief Base address as seen from the different cores may be different
164 * And is defined based on the core
165 */
166 #ifdef BUILD_C6A811X_DSP
167 #define EDMA3_CC_BASE_ADDR ((void *)(0x09000000))
168 #define EDMA3_TC0_BASE_ADDR ((void *)(0x09800000))
169 #define EDMA3_TC1_BASE_ADDR ((void *)(0x09900000))
170 #define EDMA3_TC2_BASE_ADDR ((void *)(0x09A00000))
171 #define EDMA3_TC3_BASE_ADDR ((void *)(0x09B00000))
172 #else
173 #define EDMA3_CC_BASE_ADDR ((void *)(0x49000000))
174 #define EDMA3_TC0_BASE_ADDR ((void *)(0x49800000))
175 #define EDMA3_TC1_BASE_ADDR ((void *)(0x49900000))
176 #define EDMA3_TC2_BASE_ADDR ((void *)(0x49A00000))
177 #define EDMA3_TC3_BASE_ADDR ((void *)(0x49B00000))
178 #endif
180 EDMA3_RM_GblConfigParams edma3GblCfgParams [EDMA3_MAX_EDMA3_INSTANCES] =
181 {
182 /* EDMA3 INSTANCE# 0 */
183 {
184 /** Total number of DMA Channels supported by the EDMA3 Controller */
185 EDMA3_NUM_DMA_CHANNELS,
186 /** Total number of QDMA Channels supported by the EDMA3 Controller */
187 EDMA3_NUM_QDMA_CHANNELS,
188 /** Total number of TCCs supported by the EDMA3 Controller */
189 EDMA3_NUM_TCC,
190 /** Total number of PaRAM Sets supported by the EDMA3 Controller */
191 EDMA3_NUM_PARAMSET,
192 /** Total number of Event Queues in the EDMA3 Controller */
193 EDMA3_NUM_EVTQUE,
194 /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
195 EDMA3_NUM_TC,
196 /** Number of Regions on this EDMA3 controller */
197 EDMA3_NUM_REGIONS,
199 /**
200 * \brief Channel mapping existence
201 * A value of 0 (No channel mapping) implies that there is fixed association
202 * for a channel number to a parameter entry number or, in other words,
203 * PaRAM entry n corresponds to channel n.
204 */
205 0u,
207 /** Existence of memory protection feature */
208 0u,
210 /** Global Register Region of CC Registers */
211 EDMA3_CC_BASE_ADDR,
212 /** Transfer Controller (TC) Registers */
213 {
214 EDMA3_TC0_BASE_ADDR,
215 EDMA3_TC1_BASE_ADDR,
216 EDMA3_TC2_BASE_ADDR,
217 EDMA3_TC3_BASE_ADDR,
218 (void *)NULL,
219 (void *)NULL,
220 (void *)NULL,
221 (void *)NULL
222 },
223 /** Interrupt no. for Transfer Completion */
224 EDMA3_CC_XFER_COMPLETION_INT,
225 /** Interrupt no. for CC Error */
226 EDMA3_CC_ERROR_INT,
227 /** Interrupt no. for TCs Error */
228 {
229 EDMA3_TC0_ERROR_INT,
230 EDMA3_TC1_ERROR_INT,
231 EDMA3_TC2_ERROR_INT,
232 EDMA3_TC3_ERROR_INT,
233 EDMA3_TC4_ERROR_INT,
234 EDMA3_TC5_ERROR_INT,
235 EDMA3_TC6_ERROR_INT,
236 EDMA3_TC7_ERROR_INT
237 },
239 /**
240 * \brief EDMA3 TC priority setting
241 *
242 * User can program the priority of the Event Queues
243 * at a system-wide level. This means that the user can set the
244 * priority of an IO initiated by either of the TCs (Transfer Controllers)
245 * relative to IO initiated by the other bus masters on the
246 * device (ARM, DSP, USB, etc)
247 */
248 {
249 0u,
250 1u,
251 2u,
252 3u,
253 0u,
254 0u,
255 0u,
256 0u
257 },
258 /**
259 * \brief To Configure the Threshold level of number of events
260 * that can be queued up in the Event queues. EDMA3CC error register
261 * (CCERR) will indicate whether or not at any instant of time the
262 * number of events queued up in any of the event queues exceeds
263 * or equals the threshold/watermark value that is set
264 * in the queue watermark threshold register (QWMTHRA).
265 */
266 {
267 16u,
268 16u,
269 16u,
270 16u,
271 0u,
272 0u,
273 0u,
274 0u
275 },
277 /**
278 * \brief To Configure the Default Burst Size (DBS) of TCs.
279 * An optimally-sized command is defined by the transfer controller
280 * default burst size (DBS). Different TCs can have different
281 * DBS values. It is defined in Bytes.
282 */
283 {
284 16u,
285 16u,
286 16u,
287 16u,
288 0u,
289 0u,
290 0u,
291 0u
292 },
294 /**
295 * \brief Mapping from each DMA channel to a Parameter RAM set,
296 * if it exists, otherwise of no use.
297 */
298 {
299 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
300 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
301 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
302 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
303 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
304 40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
305 48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
306 56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u
307 },
309 /**
310 * \brief Mapping from each DMA channel to a TCC. This specific
311 * TCC code will be returned when the transfer is completed
312 * on the mapped channel.
313 */
314 {
315 0u, 1u, 2u, 3u,
316 4u, 5u, 6u, 7u,
317 8u, 9u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
318 12u, 13u, 14u, 15u,
319 16u, 17u, 18u, 19u,
320 20u, 21u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
321 24u, 25u, 26u, 27u,
322 28u, 29u, 30u, 31u,
323 32u, 33u, 34u, 35u,
324 36u, 37u, 38u, 39u,
325 40u, 41u, 42u, 43u,
326 44u, 45u, 46u, 47u,
327 48u, 49u, 50u, 51u,
328 52u, 53u, 54u, 55u,
329 56u, 57u, 58u, 59u,
330 60u, 61u, 62u, 63u
331 },
333 /**
334 * \brief Mapping of DMA channels to Hardware Events from
335 * various peripherals, which use EDMA for data transfer.
336 * All channels need not be mapped, some can be free also.
337 */
338 {
339 EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0,
340 EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1
341 }
342 },
343 };
344 /* Defines for Own DMA channels For different cores */
345 /* channels 0 to 31 */
346 #define EDMA3_OWN_DMA_CHANNELS_0_A8 (0xFFFFFFFFu)
347 #define EDMA3_OWN_DMA_CHANNELS_0_DSP (0xFFFFFFFFu)
348 #define EDMA3_OWN_DMA_CHANNELS_0_M3VIDEO (0xFFFFFFFFu)
349 #define EDMA3_OWN_DMA_CHANNELS_0_M3VPSS (0xFFFFFFFFu)
350 /* Channels 32 to 63 */
351 #define EDMA3_OWN_DMA_CHANNELS_1_A8 (0xFFFFFFFFu)
352 #define EDMA3_OWN_DMA_CHANNELS_1_DSP (0xFFFFFFFFu)
353 #define EDMA3_OWN_DMA_CHANNELS_1_M3VIDEO (0xFFFFFFFFu)
354 #define EDMA3_OWN_DMA_CHANNELS_1_M3VPSS (0xFFFFFFFFu)
356 /* Defines for Own QDMA channels For different cores */
357 #define EDMA3_OWN_QDMA_CHANNELS_0_A8 (0x000000FFu)
358 #define EDMA3_OWN_QDMA_CHANNELS_0_DSP (0x000000FFu)
359 #define EDMA3_OWN_QDMA_CHANNELS_0_M3VIDEO (0x000000FFu)
360 #define EDMA3_OWN_QDMA_CHANNELS_0_M3VPSS (0x000000FFu)
362 /* Defines for Own TCCs For different cores */
363 #define EDMA3_OWN_TCC_0_A8 (0xFFFFFFFFu)
364 #define EDMA3_OWN_TCC_0_DSP (0xFFFFFFFFu)
365 #define EDMA3_OWN_TCC_0_M3VIDEO (0xFFFFFFFFu)
366 #define EDMA3_OWN_TCC_0_M3VPSS (0xFFFFFFFFu)
367 /* Channels 32 to 63 */
368 #define EDMA3_OWN_TCC_1_A8 (0xFFFFFFFFu)
369 #define EDMA3_OWN_TCC_1_DSP (0xFFFFFFFFu)
370 #define EDMA3_OWN_TCC_1_M3VIDEO (0xFFFFFFFFu)
371 #define EDMA3_OWN_TCC_1_M3VPSS (0xFFFFFFFFu)
373 /* Defines for Reserved DMA channels For different cores */
374 /* channels 0 to 31 */
375 #define EDMA3_RESERVED_DMA_CHANNELS_0_A8 EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0
376 #define EDMA3_RESERVED_DMA_CHANNELS_0_DSP EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0
377 #define EDMA3_RESERVED_DMA_CHANNELS_0_M3VIDEO (0x00u)
378 #define EDMA3_RESERVED_DMA_CHANNELS_0_M3VPSS (0x00u)
379 /* Channels 32 to 63 */
380 #define EDMA3_RESERVED_DMA_CHANNELS_1_A8 EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1
381 #define EDMA3_RESERVED_DMA_CHANNELS_1_DSP EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1
382 #define EDMA3_RESERVED_DMA_CHANNELS_1_M3VIDEO (0x00u)
383 #define EDMA3_RESERVED_DMA_CHANNELS_1_M3VPSS (0x00u)
385 /* Defines for RESERVED QDMA channels For different cores */
386 #define EDMA3_RESERVED_QDMA_CHANNELS_0_A8 (0x00u)
387 #define EDMA3_RESERVED_QDMA_CHANNELS_0_DSP (0x00u)
388 #define EDMA3_RESERVED_QDMA_CHANNELS_0_M3VIDEO (0x00u)
389 #define EDMA3_RESERVED_QDMA_CHANNELS_0_M3VPSS (0x00u)
391 /* Defines for RESERVED TCCs For different cores */
392 #define EDMA3_RESERVED_TCC_0_A8 EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0
393 #define EDMA3_RESERVED_TCC_0_DSP EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0
394 #define EDMA3_RESERVED_TCC_0_M3VIDEO (0x00u)
395 #define EDMA3_RESERVED_TCC_0_M3VPSS (0x00u)
396 /* Channels 32 to 63 */
397 #define EDMA3_RESERVED_TCC_1_A8 EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1
398 #define EDMA3_RESERVED_TCC_1_DSP EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1
399 #define EDMA3_RESERVED_TCC_1_M3VIDEO (0x00u)
400 #define EDMA3_RESERVED_TCC_1_M3VPSS (0x00u)
402 /* Default RM Instance Initialization Configuration */
403 EDMA3_RM_InstanceInitConfig defInstInitConfig [EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
404 {
405 /* EDMA3 INSTANCE# 0 */
406 {
407 /* Resources owned/reserved by region 0 (Configuration for A8 Core)*/
408 {
409 /* ownPaRAMSets */
410 /* 31 0 63 32 95 64 127 96 */
411 {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
412 /* 159 128 191 160 223 192 255 224 */
413 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
414 /* 287 256 319 288 351 320 383 352 */
415 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
416 /* 415 384 447 416 479 448 511 480 */
417 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
419 /* ownDmaChannels */
420 /* 31 0 63 32 */
421 {EDMA3_OWN_DMA_CHANNELS_0_A8, EDMA3_OWN_DMA_CHANNELS_1_A8},
423 /* ownQdmaChannels */
424 /* 31 0 */
425 {EDMA3_OWN_QDMA_CHANNELS_0_A8},
427 /* ownTccs */
428 /* 31 0 63 32 */
429 {EDMA3_OWN_TCC_0_A8, EDMA3_OWN_TCC_1_A8},
431 /* resvdPaRAMSets */
432 /* 31 0 63 32 95 64 127 96 */
433 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
434 /* 159 128 191 160 223 192 255 224 */
435 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
436 /* 287 256 319 288 351 320 383 352 */
437 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
438 /* 415 384 447 416 479 448 511 480 */
439 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
441 /* resvdDmaChannels */
442 /* 31 0 63 32 */
443 {EDMA3_RESERVED_DMA_CHANNELS_0_A8, EDMA3_RESERVED_DMA_CHANNELS_1_A8},
445 /* resvdQdmaChannels */
446 /* 31 0 */
447 {EDMA3_RESERVED_QDMA_CHANNELS_0_A8},
449 /* resvdTccs */
450 /* 31 0 63 32 */
451 {EDMA3_RESERVED_TCC_0_A8, EDMA3_RESERVED_TCC_1_A8},
452 },
454 /* Resources owned/reserved by region 1 (Configuration for DSP Core)*/
455 {
456 /* ownPaRAMSets */
457 /* 31 0 63 32 95 64 127 96 */
458 {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
459 /* 159 128 191 160 223 192 255 224 */
460 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
461 /* 287 256 319 288 351 320 383 352 */
462 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
463 /* 415 384 447 416 479 448 511 480 */
464 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
466 /* ownDmaChannels */
467 /* 31 0 63 32 */
468 {EDMA3_OWN_DMA_CHANNELS_0_DSP, EDMA3_OWN_DMA_CHANNELS_1_DSP},
470 /* ownQdmaChannels */
471 /* 31 0 */
472 {EDMA3_OWN_QDMA_CHANNELS_0_DSP},
474 /* ownTccs */
475 /* 31 0 63 32 */
476 {EDMA3_OWN_TCC_0_DSP, EDMA3_OWN_TCC_1_DSP},
478 /* resvdPaRAMSets */
479 /* 31 0 63 32 95 64 127 96 */
480 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
481 /* 159 128 191 160 223 192 255 224 */
482 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
483 /* 287 256 319 288 351 320 383 352 */
484 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
485 /* 415 384 447 416 479 448 511 480 */
486 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
488 /* resvdDmaChannels */
489 /* 31 0 63 32 */
490 {EDMA3_RESERVED_DMA_CHANNELS_0_DSP, EDMA3_RESERVED_DMA_CHANNELS_1_DSP},
492 /* resvdQdmaChannels */
493 /* 31 0 */
494 {EDMA3_RESERVED_QDMA_CHANNELS_0_DSP},
496 /* resvdTccs */
497 /* 31 0 63 32 */
498 {EDMA3_RESERVED_TCC_0_DSP, EDMA3_RESERVED_TCC_1_DSP},
499 },
501 /* Resources owned/reserved by region 2 (Not Associated to any core supported)*/
502 {
503 /* ownPaRAMSets */
504 /* 31 0 63 32 95 64 127 96 */
505 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
506 /* 159 128 191 160 223 192 255 224 */
507 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
508 /* 287 256 319 288 351 320 383 352 */
509 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
510 /* 415 384 447 416 479 448 511 480 */
511 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
513 /* ownDmaChannels */
514 /* 31 0 63 32 */
515 {0x00000000u, 0x00000000u},
517 /* ownQdmaChannels */
518 /* 31 0 */
519 {0x00000000u},
521 /* ownTccs */
522 /* 31 0 63 32 */
523 {0x00000000u, 0x00000000u},
525 /* resvdPaRAMSets */
526 /* 31 0 63 32 95 64 127 96 */
527 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
528 /* 159 128 191 160 223 192 255 224 */
529 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
530 /* 287 256 319 288 351 320 383 352 */
531 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
532 /* 415 384 447 416 479 448 511 480 */
533 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
535 /* resvdDmaChannels */
536 /* 31 0 63 32 */
537 {0x00000000u, 0x00000000u},
539 /* resvdQdmaChannels */
540 /* 31 0 */
541 {0x00000000u},
543 /* resvdTccs */
544 /* 31 0 63 32 */
545 {0x00000000u, 0x00000000u},
546 },
548 /* Resources owned/reserved by region 3 (Not Associated to any core supported)*/
549 {
550 /* ownPaRAMSets */
551 /* 31 0 63 32 95 64 127 96 */
552 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
553 /* 159 128 191 160 223 192 255 224 */
554 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
555 /* 287 256 319 288 351 320 383 352 */
556 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
557 /* 415 384 447 416 479 448 511 480 */
558 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
560 /* ownDmaChannels */
561 /* 31 0 63 32 */
562 {0x00000000u, 0x00000000u},
564 /* ownQdmaChannels */
565 /* 31 0 */
566 {0x00000000u},
568 /* ownTccs */
569 /* 31 0 63 32 */
570 {0x00000000u, 0x00000000u},
572 /* resvdPaRAMSets */
573 /* 31 0 63 32 95 64 127 96 */
574 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
575 /* 159 128 191 160 223 192 255 224 */
576 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
577 /* 287 256 319 288 351 320 383 352 */
578 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
579 /* 415 384 447 416 479 448 511 480 */
580 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
582 /* resvdDmaChannels */
583 /* 31 0 63 32 */
584 {0x00000000u, 0x00000000u},
586 /* resvdQdmaChannels */
587 /* 31 0 */
588 {0x00000000u},
590 /* resvdTccs */
591 /* 31 0 63 32 */
592 {0x00000000u, 0x00000000u},
593 },
595 /* Resources owned/reserved by region 4 (Configuration for M3VIDEO Core)*/
596 {
597 /* ownPaRAMSets */
598 /* 31 0 63 32 95 64 127 96 */
599 {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
600 /* 159 128 191 160 223 192 255 224 */
601 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
602 /* 287 256 319 288 351 320 383 352 */
603 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
604 /* 415 384 447 416 479 448 511 480 */
605 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
607 /* ownDmaChannels */
608 /* 31 0 63 32 */
609 {EDMA3_OWN_DMA_CHANNELS_0_M3VIDEO, EDMA3_OWN_DMA_CHANNELS_1_M3VIDEO},
611 /* ownQdmaChannels */
612 /* 31 0 */
613 {EDMA3_OWN_QDMA_CHANNELS_0_M3VIDEO},
615 /* ownTccs */
616 /* 31 0 63 32 */
617 {EDMA3_OWN_TCC_0_M3VIDEO, EDMA3_OWN_TCC_0_M3VIDEO},
619 /* resvdPaRAMSets */
620 /* 31 0 63 32 95 64 127 96 */
621 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
622 /* 159 128 191 160 223 192 255 224 */
623 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
624 /* 287 256 319 288 351 320 383 352 */
625 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
626 /* 415 384 447 416 479 448 511 480 */
627 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
629 /* resvdDmaChannels */
630 /* 31 0 63 32 */
631 {EDMA3_RESERVED_DMA_CHANNELS_0_M3VIDEO, EDMA3_RESERVED_DMA_CHANNELS_1_M3VIDEO},
633 /* resvdQdmaChannels */
634 /* 31 0 */
635 {EDMA3_RESERVED_QDMA_CHANNELS_0_M3VIDEO},
637 /* resvdTccs */
638 /* 31 0 63 32 */
639 {EDMA3_RESERVED_TCC_0_M3VIDEO, EDMA3_RESERVED_TCC_1_M3VIDEO},
640 },
642 /* Resources owned/reserved by region 5 (Configuration for M3VPSS Core)*/
643 {
644 /* ownPaRAMSets */
645 /* 31 0 63 32 95 64 127 96 */
646 {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
647 /* 159 128 191 160 223 192 255 224 */
648 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
649 /* 287 256 319 288 351 320 383 352 */
650 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
651 /* 415 384 447 416 479 448 511 480 */
652 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
654 /* ownDmaChannels */
655 /* 31 0 63 32 */
656 {EDMA3_OWN_DMA_CHANNELS_0_M3VPSS, EDMA3_OWN_DMA_CHANNELS_1_M3VPSS},
658 /* ownQdmaChannels */
659 /* 31 0 */
660 {EDMA3_OWN_QDMA_CHANNELS_0_M3VPSS},
662 /* ownTccs */
663 /* 31 0 63 32 */
664 {EDMA3_OWN_TCC_0_M3VPSS, EDMA3_OWN_TCC_1_M3VPSS},
666 /* resvdPaRAMSets */
667 /* 31 0 63 32 95 64 127 96 */
668 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
669 /* 159 128 191 160 223 192 255 224 */
670 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
671 /* 287 256 319 288 351 320 383 352 */
672 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
673 /* 415 384 447 416 479 448 511 480 */
674 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
676 /* resvdDmaChannels */
677 /* 31 0 63 32 */
678 {EDMA3_RESERVED_DMA_CHANNELS_0_M3VPSS, EDMA3_RESERVED_DMA_CHANNELS_1_M3VPSS},
680 /* resvdQdmaChannels */
681 /* 31 0 */
682 {EDMA3_RESERVED_QDMA_CHANNELS_0_M3VPSS},
684 /* resvdTccs */
685 /* 31 0 63 32 */
686 {EDMA3_RESERVED_TCC_0_M3VPSS, EDMA3_RESERVED_TCC_1_M3VPSS},
687 },
689 /* Resources owned/reserved by region 6 (Not Associated to any core supported)*/
690 {
691 /* ownPaRAMSets */
692 /* 31 0 63 32 95 64 127 96 */
693 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
694 /* 159 128 191 160 223 192 255 224 */
695 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
696 /* 287 256 319 288 351 320 383 352 */
697 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
698 /* 415 384 447 416 479 448 511 480 */
699 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
701 /* ownDmaChannels */
702 /* 31 0 63 32 */
703 {0x00000000u, 0x00000000u},
705 /* ownQdmaChannels */
706 /* 31 0 */
707 {0x00000000u},
709 /* ownTccs */
710 /* 31 0 63 32 */
711 {0x00000000u, 0x00000000u},
713 /* resvdPaRAMSets */
714 /* 31 0 63 32 95 64 127 96 */
715 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
716 /* 159 128 191 160 223 192 255 224 */
717 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
718 /* 287 256 319 288 351 320 383 352 */
719 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
720 /* 415 384 447 416 479 448 511 480 */
721 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
723 /* resvdDmaChannels */
724 /* 31 0 63 32 */
725 {0x00000000u, 0x00000000u},
727 /* resvdQdmaChannels */
728 /* 31 0 */
729 {0x00000000u},
731 /* resvdTccs */
732 /* 31 0 63 32 */
733 {0x00000000u, 0x00000000u},
734 },
736 /* Resources owned/reserved by region 7 (Not Associated to any core supported)*/
737 {
738 /* ownPaRAMSets */
739 /* 31 0 63 32 95 64 127 96 */
740 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
741 /* 159 128 191 160 223 192 255 224 */
742 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
743 /* 287 256 319 288 351 320 383 352 */
744 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
745 /* 415 384 447 416 479 448 511 480 */
746 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
748 /* ownDmaChannels */
749 /* 31 0 63 32 */
750 {0x00000000u, 0x00000000u},
752 /* ownQdmaChannels */
753 /* 31 0 */
754 {0x00000000u},
756 /* ownTccs */
757 /* 31 0 63 32 */
758 {0x00000000u, 0x00000000u},
760 /* resvdPaRAMSets */
761 /* 31 0 63 32 95 64 127 96 */
762 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
763 /* 159 128 191 160 223 192 255 224 */
764 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
765 /* 287 256 319 288 351 320 383 352 */
766 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
767 /* 415 384 447 416 479 448 511 480 */
768 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
770 /* resvdDmaChannels */
771 /* 31 0 63 32 */
772 {0x00000000u, 0x00000000u},
774 /* resvdQdmaChannels */
775 /* 31 0 */
776 {0x00000000u},
778 /* resvdTccs */
779 /* 31 0 63 32 */
780 {0x00000000u, 0x00000000u},
781 },
782 },
783 };
785 /* Driver Instance Cross bar event to channel map Initialization Configuration */
786 EDMA3_RM_GblXbarToChanConfigParams defXbarChanInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
787 {
788 /* EDMA3 INSTANCE# 0 */
789 {
790 /* Event to channel map for region 0 */
791 {
792 {-1, -1, -1, -1, -1, -1, -1, -1,
793 -1, -1, -1, -1, -1, -1, -1, -1,
794 -1, -1, -1, -1, -1, -1, -1, -1,
795 -1, -1, -1, -1, -1, -1, -1}
796 },
797 /* Event to channel map for region 1 */
798 {
799 {-1, -1, -1, -1, -1, -1, -1, -1,
800 -1, -1, -1, -1, -1, -1, -1, -1,
801 -1, -1, -1, -1, -1, -1, -1, -1,
802 -1, -1, -1, -1, -1, -1, -1}
803 },
804 /* Event to channel map for region 2 */
805 {
806 {-1, -1, -1, -1, -1, -1, -1, -1,
807 -1, -1, -1, -1, -1, -1, -1, -1,
808 -1, -1, -1, -1, -1, -1, -1, -1,
809 -1, -1, -1, -1, -1, -1, -1}
810 },
811 /* Event to channel map for region 3 */
812 {
813 {-1, -1, -1, -1, -1, -1, -1, -1,
814 -1, -1, -1, -1, -1, -1, -1, -1,
815 -1, -1, -1, -1, -1, -1, -1, -1,
816 -1, -1, -1, -1, -1, -1, -1}
817 },
818 /* Event to channel map for region 4 */
819 {
820 {-1, -1, -1, -1, -1, -1, -1, -1,
821 -1, -1, -1, -1, -1, -1, -1, -1,
822 -1, -1, -1, -1, -1, -1, -1, -1,
823 -1, -1, -1, -1, -1, -1, -1}
824 },
825 /* Event to channel map for region 5 */
826 {
827 {-1, -1, -1, -1, -1, -1, -1, -1,
828 -1, -1, -1, -1, -1, -1, -1, -1,
829 -1, -1, -1, -1, -1, -1, -1, -1,
830 -1, -1, -1, -1, -1, -1, -1}
831 },
832 /* Event to channel map for region 6 */
833 {
834 {-1, -1, -1, -1, -1, -1, -1, -1,
835 -1, -1, -1, -1, -1, -1, -1, -1,
836 -1, -1, -1, -1, -1, -1, -1, -1,
837 -1, -1, -1, -1, -1, -1, -1}
838 },
839 /* Event to channel map for region 7 */
840 {
841 {-1, -1, -1, -1, -1, -1, -1, -1,
842 -1, -1, -1, -1, -1, -1, -1, -1,
843 -1, -1, -1, -1, -1, -1, -1, -1,
844 -1, -1, -1, -1, -1, -1, -1}
845 },
846 }
847 };
849 /* End of File */