[keystone-rtos/edma3_lld.git] / packages / ti / sdo / edma3 / rm / src / configs / edma3_da830_cfg.c
1 /*
2 * edma3_da830_cfg.c
3 *
4 * EDMA3 Resource Manager Adaptation Configuration File (SoC Specific).
5 *
6 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
7 *
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 *
13 * Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 *
16 * Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the
19 * distribution.
20 *
21 * Neither the name of Texas Instruments Incorporated nor the names of
22 * its contributors may be used to endorse or promote products derived
23 * from this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 */
39 #include <ti/sdo/edma3/rm/edma3_rm.h>
41 #define NUM_EDMA3_INSTANCES 1u
43 /** Total number of DMA Channels supported by the EDMA3 Controller */
44 #define NUM_DMA_CHANNELS (32u)
45 /** Total number of QDMA Channels supported by the EDMA3 Controller */
46 #define NUM_QDMA_CHANNELS (8u)
47 /** Total number of TCCs supported by the EDMA3 Controller */
48 #define NUM_TCC (32u)
49 /** Total number of PaRAM Sets supported by the EDMA3 Controller */
50 #define NUM_PARAM_SETS (128u)
51 /** Total number of Event Queues in the EDMA3 Controller */
52 #define NUM_EVENT_QUEUE (2u)
53 /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
54 #define NUM_TC (2u)
55 /** Number of Regions on this EDMA3 controller */
56 #define NUM_REGION (4u)
58 /**
59 * \brief Channel mapping existence
60 * A value of 0 (No channel mapping) implies that there is fixed association
61 * for a channel number to a parameter entry number or, in other words,
62 * PaRAM entry n corresponds to channel n.
63 */
64 #define CHANNEL_MAPPING_EXISTENCE (0u)
65 /** Existence of memory protection feature */
66 #define MEM_PROTECTION_EXISTENCE (0u)
68 /** Global Register Region of CC Registers */
69 #define CC_BASE_ADDRESS (0x01C00000u)
70 /** Transfer Controller 0 Registers */
71 #define TC0_BASE_ADDRESS (0x01C08000u)
72 /** Transfer Controller 1 Registers */
73 #define TC1_BASE_ADDRESS (0x01C08400u)
74 /** Transfer Controller 2 Registers */
75 #define TC2_BASE_ADDRESS NULL
76 /** Transfer Controller 3 Registers */
77 #define TC3_BASE_ADDRESS NULL
78 /** Transfer Controller 4 Registers */
79 #define TC4_BASE_ADDRESS NULL
80 /** Transfer Controller 5 Registers */
81 #define TC5_BASE_ADDRESS NULL
82 /** Transfer Controller 6 Registers */
83 #define TC6_BASE_ADDRESS NULL
84 /** Transfer Controller 7 Registers */
85 #define TC7_BASE_ADDRESS NULL
87 /** Interrupt no. for Transfer Completion */
88 #define XFER_COMPLETION_INT (8u)
89 /** Interrupt no. for CC Error */
90 #define CC_ERROR_INT (56u)
91 /** Interrupt no. for TC 0 Error */
92 #define TC0_ERROR_INT (57u)
93 /** Interrupt no. for TC 1 Error */
94 #define TC1_ERROR_INT (58u)
95 /** Interrupt no. for TC 2 Error */
96 #define TC2_ERROR_INT (0u)
97 /** Interrupt no. for TC 3 Error */
98 #define TC3_ERROR_INT (0u)
99 /** Interrupt no. for TC 4 Error */
100 #define TC4_ERROR_INT (0u)
101 /** Interrupt no. for TC 5 Error */
102 #define TC5_ERROR_INT (0u)
103 /** Interrupt no. for TC 6 Error */
104 #define TC6_ERROR_INT (0u)
105 /** Interrupt no. for TC 7 Error */
106 #define TC7_ERROR_INT (0u)
108 /**
109 * \brief Mapping of DMA channels 0-31 to Hardware Events from
110 * various peripherals, which use EDMA for data transfer.
111 * All channels need not be mapped, some can be free also.
112 * 1: Mapped
113 * 0: Not mapped
114 *
115 * This mapping will be used to allocate DMA channels when user passes
116 * EDMA3_RM_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
117 * copy). The same mapping is used to allocate the TCC when user passes
118 * EDMA3_RM_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
119 *
120 * To allocate more DMA channels or TCCs, one has to modify the event mapping.
121 */
122 /* 31 0 */
123 #define DMA_CHANNEL_TO_EVENT_MAPPING_0 (0xCF3FFFFFu)
124 /**
125 * EDMA channels 22, 23, 28 & 29 which correspond to GPIO bank interrupts will
126 * be used for memory-to-memory data transfers, since there are no free dma
127 * channels.
128 */
131 /**
132 * \brief Mapping of DMA channels 32-63 to Hardware Events from
133 * various peripherals, which use EDMA for data transfer.
134 * All channels need not be mapped, some can be free also.
135 * 1: Mapped
136 * 0: Not mapped
137 *
138 * This mapping will be used to allocate DMA channels when user passes
139 * EDMA3_RM_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
140 * copy). The same mapping is used to allocate the TCC when user passes
141 * EDMA3_RM_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
142 *
143 * To allocate more DMA channels or TCCs, one has to modify the event mapping.
144 */
145 /* DMA channels 32-63 DOES NOT exist in DA830. */
146 #define DMA_CHANNEL_TO_EVENT_MAPPING_1 (0x0u)
149 EDMA3_RM_GblConfigParams edma3GblCfgParams [NUM_EDMA3_INSTANCES] =
150 {
151 {
152 /** Total number of DMA Channels supported by the EDMA3 Controller */
153 NUM_DMA_CHANNELS,
154 /** Total number of QDMA Channels supported by the EDMA3 Controller */
155 NUM_QDMA_CHANNELS,
156 /** Total number of TCCs supported by the EDMA3 Controller */
157 NUM_TCC,
158 /** Total number of PaRAM Sets supported by the EDMA3 Controller */
159 NUM_PARAM_SETS,
160 /** Total number of Event Queues in the EDMA3 Controller */
161 NUM_EVENT_QUEUE,
162 /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
163 NUM_TC,
164 /** Number of Regions on this EDMA3 controller */
165 NUM_REGION,
167 /**
168 * \brief Channel mapping existence
169 * A value of 0 (No channel mapping) implies that there is fixed association
170 * for a channel number to a parameter entry number or, in other words,
171 * PaRAM entry n corresponds to channel n.
172 */
173 CHANNEL_MAPPING_EXISTENCE,
175 /** Existence of memory protection feature */
176 MEM_PROTECTION_EXISTENCE,
178 /** Global Register Region of CC Registers */
179 (void *)(CC_BASE_ADDRESS),
180 /** Transfer Controller (TC) Registers */
181 {
182 (void *)(TC0_BASE_ADDRESS),
183 (void *)(TC1_BASE_ADDRESS),
184 (void *)(TC2_BASE_ADDRESS),
185 (void *)(TC3_BASE_ADDRESS),
186 (void *)(TC4_BASE_ADDRESS),
187 (void *)(TC5_BASE_ADDRESS),
188 (void *)(TC6_BASE_ADDRESS),
189 (void *)(TC7_BASE_ADDRESS)
190 },
191 /** Interrupt no. for Transfer Completion */
192 XFER_COMPLETION_INT,
193 /** Interrupt no. for CC Error */
194 CC_ERROR_INT,
195 /** Interrupt no. for TCs Error */
196 {
197 TC0_ERROR_INT,
198 TC1_ERROR_INT,
199 TC2_ERROR_INT,
200 TC3_ERROR_INT,
201 TC4_ERROR_INT,
202 TC5_ERROR_INT,
203 TC6_ERROR_INT,
204 TC7_ERROR_INT
205 },
207 /**
208 * \brief EDMA3 TC priority setting
209 *
210 * User can program the priority of the Event Queues
211 * at a system-wide level. This means that the user can set the
212 * priority of an IO initiated by either of the TCs (Transfer Controllers)
213 * relative to IO initiated by the other bus masters on the
214 * device (ARM, DSP, USB, etc)
215 */
216 {
217 0u,
218 1u,
219 0u,
220 0u,
221 0u,
222 0u,
223 0u,
224 0u
225 },
226 /**
227 * \brief To Configure the Threshold level of number of events
228 * that can be queued up in the Event queues. EDMA3CC error register
229 * (CCERR) will indicate whether or not at any instant of time the
230 * number of events queued up in any of the event queues exceeds
231 * or equals the threshold/watermark value that is set
232 * in the queue watermark threshold register (QWMTHRA).
233 */
234 {
235 16u,
236 16u,
237 0u,
238 0u,
239 0u,
240 0u,
241 0u,
242 0u
243 },
245 /**
246 * \brief To Configure the Default Burst Size (DBS) of TCs.
247 * An optimally-sized command is defined by the transfer controller
248 * default burst size (DBS). Different TCs can have different
249 * DBS values. It is defined in Bytes.
250 */
251 {
252 16u,
253 16u,
254 0u,
255 0u,
256 0u,
257 0u,
258 0u,
259 0u
260 },
262 /**
263 * \brief Mapping from each DMA channel to a Parameter RAM set,
264 * if it exists, otherwise of no use.
265 */
266 {
267 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
268 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
269 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
270 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
271 /* DMA channels 32-63 DOES NOT exist in DA830. */
272 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
273 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
274 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
275 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
276 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
277 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
278 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
279 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
280 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
281 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
282 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
283 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
284 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
285 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
286 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
287 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS
288 },
290 /**
291 * \brief Mapping from each DMA channel to a TCC. This specific
292 * TCC code will be returned when the transfer is completed
293 * on the mapped channel.
294 */
295 {
296 0u, 1u, 2u, 3u,
297 4u, 5u, 6u, 7u,
298 8u, 9u, 10u, 11u,
299 12u, 13u, 14u, 15u,
300 16u, 17u, 18u, 19u,
301 20u, 21u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
302 24u, 25u, 26u, 27u,
303 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, 30, 31,
304 /* DMA channels 32-63 DOES NOT exist in DA830. */
305 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
306 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
307 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
308 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
309 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
310 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
311 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
312 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC
313 },
315 /**
316 * \brief Mapping of DMA channels to Hardware Events from
317 * various peripherals, which use EDMA for data transfer.
318 * All channels need not be mapped, some can be free also.
319 */
320 {
321 DMA_CHANNEL_TO_EVENT_MAPPING_0,
322 DMA_CHANNEL_TO_EVENT_MAPPING_1
323 }
324 }
325 };
328 /* Default RM Instance Initialization Configuration */
329 EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][NUM_REGION] =
330 {
331 {
332 {
333 /* Resources owned by Region 0 */
334 /* ownPaRAMSets */
335 /* 31 0 63 32 95 64 127 96 */
336 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
337 /* 159 128 191 160 223 192 255 224 */
338 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
339 /* 287 256 319 288 351 320 383 352 */
340 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
341 /* 415 384 447 416 479 448 511 480 */
342 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
344 /* ownDmaChannels */
345 /* 31 0 63 32 */
346 {0x00000000u, 0x00000000u},
348 /* ownQdmaChannels */
349 /* 31 0 */
350 {0x00000000u},
352 /* ownTccs */
353 /* 31 0 63 32 */
354 {0x00000000u, 0x00000000u},
356 /* Resources reserved by Region 0 */
357 /* resvdPaRAMSets */
358 /* 31 0 63 32 95 64 127 96 */
359 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
360 /* 159 128 191 160 223 192 255 224 */
361 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
362 /* 287 256 319 288 351 320 383 352 */
363 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
364 /* 415 384 447 416 479 448 511 480 */
365 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
367 /* resvdDmaChannels */
368 /* 31 0 63 32 */
369 {0x00000000u, 0x00000000u},
371 /* resvdQdmaChannels */
372 /* 31 0 */
373 {0x00000000u},
375 /* resvdTccs */
376 /* 31 0 63 32 */
377 {0x00000000u, 0x00000000u},
378 },
380 {
381 /* Resources owned by Region 1 */
382 /* ownPaRAMSets */
383 /* 31 0 63 32 95 64 127 96 */
384 {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
385 /* 159 128 191 160 223 192 255 224 */
386 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
387 /* 287 256 319 288 351 320 383 352 */
388 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
389 /* 415 384 447 416 479 448 511 480 */
390 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
392 /* ownDmaChannels */
393 /* 31 0 63 32 */
394 {0xFFFFFFFFu, 0x00000000u},
396 /* ownQdmaChannels */
397 /* 31 0 */
398 {0x000000FFu},
400 /* ownTccs */
401 /* 31 0 63 32 */
402 {0xFFFFFFFFu, 0x00000000u},
404 /* Resources reserved by Region 1 */
405 /* resvdPaRAMSets */
406 /* 31 0 63 32 95 64 127 96 */
407 {0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
408 /* 159 128 191 160 223 192 255 224 */
409 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
410 /* 287 256 319 288 351 320 383 352 */
411 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
412 /* 415 384 447 416 479 448 511 480 */
413 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
415 /* resvdDmaChannels */
416 /* 31 0 63 32 */
417 {DMA_CHANNEL_TO_EVENT_MAPPING_0, DMA_CHANNEL_TO_EVENT_MAPPING_1},
419 /* resvdQdmaChannels */
420 /* 31 0 */
421 {0x00000000u},
423 /* resvdTccs */
424 /* 31 0 63 32 */
425 {DMA_CHANNEL_TO_EVENT_MAPPING_0, DMA_CHANNEL_TO_EVENT_MAPPING_1},
426 },
428 {
429 /* Resources owned by Region 2 */
430 /* ownPaRAMSets */
431 /* 31 0 63 32 95 64 127 96 */
432 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
433 /* 159 128 191 160 223 192 255 224 */
434 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
435 /* 287 256 319 288 351 320 383 352 */
436 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
437 /* 415 384 447 416 479 448 511 480 */
438 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
440 /* ownDmaChannels */
441 /* 31 0 63 32 */
442 {0x00000000u, 0x00000000u},
444 /* ownQdmaChannels */
445 /* 31 0 */
446 {0x00000000u},
448 /* ownTccs */
449 /* 31 0 63 32 */
450 {0x00000000u, 0x00000000u},
452 /* Resources reserved by Region 2 */
453 /* resvdPaRAMSets */
454 /* 31 0 63 32 95 64 127 96 */
455 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
456 /* 159 128 191 160 223 192 255 224 */
457 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
458 /* 287 256 319 288 351 320 383 352 */
459 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
460 /* 415 384 447 416 479 448 511 480 */
461 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
463 /* resvdDmaChannels */
464 /* 31 0 63 32 */
465 {0x00000000u, 0x00000000u},
467 /* resvdQdmaChannels */
468 /* 31 0 */
469 {0x00000000u},
471 /* resvdTccs */
472 /* 31 0 63 32 */
473 {0x00000000u, 0x00000000u},
474 },
476 {
477 /* Resources owned by Region 3 */
478 /* ownPaRAMSets */
479 /* 31 0 63 32 95 64 127 96 */
480 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
481 /* 159 128 191 160 223 192 255 224 */
482 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
483 /* 287 256 319 288 351 320 383 352 */
484 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
485 /* 415 384 447 416 479 448 511 480 */
486 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
488 /* ownDmaChannels */
489 /* 31 0 63 32 */
490 {0x00000000u, 0x00000000u},
492 /* ownQdmaChannels */
493 /* 31 0 */
494 {0x00000000u},
496 /* ownTccs */
497 /* 31 0 63 32 */
498 {0x00000000u, 0x00000000u},
500 /* Resources reserved by Region 3 */
501 /* resvdPaRAMSets */
502 /* 31 0 63 32 95 64 127 96 */
503 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
504 /* 159 128 191 160 223 192 255 224 */
505 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
506 /* 287 256 319 288 351 320 383 352 */
507 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
508 /* 415 384 447 416 479 448 511 480 */
509 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
511 /* resvdDmaChannels */
512 /* 31 0 63 32 */
513 {0x00000000u, 0x00000000u},
515 /* resvdQdmaChannels */
516 /* 31 0 */
517 {0x00000000u},
519 /* resvdTccs */
520 /* 31 0 63 32 */
521 {0x00000000u, 0x00000000u},
522 }
523 }
524 };
526 /* End of File */