e27db93e13bb1b2a79640dd96d302889fc4fcd7c
[keystone-rtos/edma3_lld.git] / packages / ti / sdo / edma3 / rm / src / configs / edma3_dra72x_cfg.c
1 /*
2 * edma3_tda2xx_cfg.c
3 *
4 * EDMA3 Driver Adaptation Configuration File (Soc Specific) for OMAPL138.
5 *
6 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
7 *
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 *
13 * Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 *
16 * Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the
19 * distribution.
20 *
21 * Neither the name of Texas Instruments Incorporated nor the names of
22 * its contributors may be used to endorse or promote products derived
23 * from this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 */
39 #include <ti/sdo/edma3/rm/edma3_rm.h>
40 #ifdef BUILD_DRA72X_IPU
41 #include <ti/sysbios/family/arm/ducati/Core.h>
43 #endif
45 #define NUM_SHADOW_REGIONS (8u)
47 /* Number of EDMA3 controllers present in the system */
48 #define NUM_EDMA3_INSTANCES 2u
50 /** Number of PaRAM Sets available */
51 #define EDMA3_NUM_PARAMSET (512u)
53 /** Number of TCCS available */
54 #define EDMA3_NUM_TCC (64u)
56 /** Number of DMA Channels available */
57 #define EDMA3_NUM_DMA_CHANNELS (64u)
59 /** Number of QDMA Channels available */
60 #define EDMA3_NUM_QDMA_CHANNELS (8u)
62 /** Number of Event Queues available */
63 #define EDMA3_NUM_EVTQUE (4u)
65 /** Number of Transfer Controllers available */
66 #define EDMA3_NUM_TC (2u)
68 /** Number of Regions */
69 #define EDMA3_NUM_REGIONS (8u)
71 /** Interrupt no. for Transfer Completion */
72 #define EDMA3_CC_XFER_COMPLETION_INT_A15 (66u)
73 #define EDMA3_CC_XFER_COMPLETION_INT_DSP (38u)
74 #define EDMA3_CC_XFER_COMPLETION_INT_IPU_C0 (34u)
75 #define EDMA3_CC_XFER_COMPLETION_INT_IPU_C1 (33u)
77 /** Based on the interrupt number to be mapped define the XBAR instance number */
78 #define COMPLETION_INT_A15_XBAR_INST_NO (29u)
79 #define COMPLETION_INT_DSP_XBAR_INST_NO (7u)
80 #define COMPLETION_INT_IPU_C0_XBAR_INST_NO (12u)
81 #define COMPLETION_INT_IPU_C1_XBAR_INST_NO (11u)
83 /** Interrupt no. for CC Error */
84 #define EDMA3_CC_ERROR_INT_A15 (67u)
85 #define EDMA3_CC_ERROR_INT_DSP (39u)
86 #define EDMA3_CC_ERROR_INT_IPU (35u)
88 /** Based on the interrupt number to be mapped define the XBAR instance number */
89 #define CC_ERROR_INT_A15_XBAR_INST_NO (30u)
90 #define CC_ERROR_INT_DSP_XBAR_INST_NO (8u)
91 #define CC_ERROR_INT_IPU_XBAR_INST_NO (13u)
93 /** Interrupt no. for TCs Error */
94 #define EDMA3_TC0_ERROR_INT_A15 (68u)
95 #define EDMA3_TC0_ERROR_INT_DSP (40u)
96 #define EDMA3_TC0_ERROR_INT_IPU (36u)
97 #define EDMA3_TC1_ERROR_INT_A15 (69u)
98 #define EDMA3_TC1_ERROR_INT_DSP (41u)
99 #define EDMA3_TC1_ERROR_INT_IPU (37u)
101 /** Based on the interrupt number to be mapped define the XBAR instance number */
102 #define TC0_ERROR_INT_A15_XBAR_INST_NO (31u)
103 #define TC0_ERROR_INT_DSP_XBAR_INST_NO (9u)
104 #define TC0_ERROR_INT_IPU_XBAR_INST_NO (14u)
105 #define TC1_ERROR_INT_A15_XBAR_INST_NO (32u)
106 #define TC1_ERROR_INT_DSP_XBAR_INST_NO (10u)
107 #define TC1_ERROR_INT_IPU_XBAR_INST_NO (15u)
109 #ifdef BUILD_DRA72X_MPU
110 #define EDMA3_CC_XFER_COMPLETION_INT EDMA3_CC_XFER_COMPLETION_INT_A15
111 #define EDMA3_CC_ERROR_INT EDMA3_CC_ERROR_INT_A15
112 #define CC_ERROR_INT_XBAR_INST_NO CC_ERROR_INT_A15_XBAR_INST_NO
113 #define EDMA3_TC0_ERROR_INT EDMA3_TC0_ERROR_INT_A15
114 #define EDMA3_TC1_ERROR_INT EDMA3_TC1_ERROR_INT_A15
115 #define TC0_ERROR_INT_XBAR_INST_NO TC0_ERROR_INT_A15_XBAR_INST_NO
116 #define TC1_ERROR_INT_XBAR_INST_NO TC1_ERROR_INT_A15_XBAR_INST_NO
118 #elif defined BUILD_DRA72X_DSP
119 #define EDMA3_CC_XFER_COMPLETION_INT EDMA3_CC_XFER_COMPLETION_INT_DSP
120 #define EDMA3_CC_ERROR_INT EDMA3_CC_ERROR_INT_DSP
121 #define CC_ERROR_INT_XBAR_INST_NO CC_ERROR_INT_DSP_XBAR_INST_NO
122 #define EDMA3_TC0_ERROR_INT EDMA3_TC0_ERROR_INT_DSP
123 #define EDMA3_TC1_ERROR_INT EDMA3_TC1_ERROR_INT_DSP
124 #define TC0_ERROR_INT_XBAR_INST_NO TC0_ERROR_INT_DSP_XBAR_INST_NO
125 #define TC1_ERROR_INT_XBAR_INST_NO TC1_ERROR_INT_DSP_XBAR_INST_NO
127 #elif defined BUILD_DRA72X_IPU
128 #define EDMA3_CC_XFER_COMPLETION_INT EDMA3_CC_XFER_COMPLETION_INT_IPU_C0
129 #define EDMA3_CC_ERROR_INT EDMA3_CC_ERROR_INT_IPU
130 #define CC_ERROR_INT_XBAR_INST_NO CC_ERROR_INT_IPU_XBAR_INST_NO
131 #define EDMA3_TC0_ERROR_INT EDMA3_TC0_ERROR_INT_IPU
132 #define EDMA3_TC1_ERROR_INT EDMA3_TC1_ERROR_INT_IPU
133 #define TC0_ERROR_INT_XBAR_INST_NO TC0_ERROR_INT_IPU_XBAR_INST_NO
134 #define TC1_ERROR_INT_XBAR_INST_NO TC1_ERROR_INT_IPU_XBAR_INST_NO
136 #else
137 #define EDMA3_CC_XFER_COMPLETION_INT (0u)
138 #define EDMA3_CC_ERROR_INT (0u)
139 #define CC_ERROR_INT_XBAR_INST_NO (0u)
140 #define EDMA3_TC0_ERROR_INT (0u)
141 #define EDMA3_TC1_ERROR_INT (0u)
142 #define TC0_ERROR_INT_XBAR_INST_NO TC0_ERROR_INT_A15_XBAR_INST_NO
143 #define TC1_ERROR_INT_XBAR_INST_NO TC1_ERROR_INT_A15_XBAR_INST_NO
144 #endif
146 #define EDMA3_TC2_ERROR_INT (0u)
147 #define EDMA3_TC3_ERROR_INT (0u)
148 #define EDMA3_TC4_ERROR_INT (0u)
149 #define EDMA3_TC5_ERROR_INT (0u)
150 #define EDMA3_TC6_ERROR_INT (0u)
151 #define EDMA3_TC7_ERROR_INT (0u)
153 #define DSP1_EDMA3_CC_XFER_COMPLETION_INT (19u)
154 #define DSP1_EDMA3_CC_ERROR_INT (27u)
155 #define DSP1_EDMA3_TC0_ERROR_INT (28u)
156 #define DSP1_EDMA3_TC1_ERROR_INT (29u)
158 /** XBAR interrupt source index numbers for EDMA interrupts */
159 #define XBAR_EDMA_TPCC_IRQ_REGION0 (361u)
160 #define XBAR_EDMA_TPCC_IRQ_REGION1 (362u)
161 #define XBAR_EDMA_TPCC_IRQ_REGION2 (363u)
162 #define XBAR_EDMA_TPCC_IRQ_REGION3 (364u)
163 #define XBAR_EDMA_TPCC_IRQ_REGION4 (365u)
164 #define XBAR_EDMA_TPCC_IRQ_REGION5 (366u)
165 #define XBAR_EDMA_TPCC_IRQ_REGION6 (367u)
166 #define XBAR_EDMA_TPCC_IRQ_REGION7 (368u)
168 #define XBAR_EDMA_TPCC_IRQ_ERR (359u)
169 #define XBAR_EDMA_TC0_IRQ_ERR (370u)
170 #define XBAR_EDMA_TC1_IRQ_ERR (371u)
172 /**
173 * EDMA3 interrupts (transfer completion, CC error etc.) correspond to different
174 * ECM events (SoC specific). These ECM events come
175 * under ECM block XXX (handling those specific ECM events). Normally, block
176 * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events
177 * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)
178 * is mapped to a specific HWI_INT YYY in the tcf file.
179 * Define EDMA3_HWI_INT_XFER_COMP to specific HWI_INT, corresponding
180 * to transfer completion interrupt.
181 * Define EDMA3_HWI_INT_CC_ERR to specific HWI_INT, corresponding
182 * to CC error interrupts.
183 * Define EDMA3_HWI_INT_TC_ERR to specific HWI_INT, corresponding
184 * to TC error interrupts.
185 */
186 /* EDMA 0 */
188 #define EDMA3_HWI_INT_XFER_COMP (7u)
189 #define EDMA3_HWI_INT_CC_ERR (7u)
190 #define EDMA3_HWI_INT_TC0_ERR (10u)
191 #define EDMA3_HWI_INT_TC1_ERR (10u)
192 #define EDMA3_HWI_INT_TC2_ERR (10u)
193 #define EDMA3_HWI_INT_TC3_ERR (10u)
195 /**
196 * \brief Mapping of DMA channels 0-31 to Hardware Events from
197 * various peripherals, which use EDMA for data transfer.
198 * All channels need not be mapped, some can be free also.
199 * 1: Mapped
200 * 0: Not mapped
201 *
202 * This mapping will be used to allocate DMA channels when user passes
203 * EDMA3_RM_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
204 * copy). The same mapping is used to allocate the TCC when user passes
205 * EDMA3_RM_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
206 *
207 * For Vayu Since the xbar can be used to map event to any EDMA channel,
208 * If the application is assigning events to other channel this variable
209 * should be modified
210 *
211 * To allocate more DMA channels or TCCs, one has to modify the event mapping.
212 */
213 /* 31 0 */
214 #define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA (0x3FC0C06Eu) /* TBD */
215 #define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_DSPEDMA (0x000FFFFFu) /* TBD */
218 /**
219 * \brief Mapping of DMA channels 32-63 to Hardware Events from
220 * various peripherals, which use EDMA for data transfer.
221 * All channels need not be mapped, some can be free also.
222 * 1: Mapped
223 * 0: Not mapped
224 *
225 * This mapping will be used to allocate DMA channels when user passes
226 * EDMA3_RM_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
227 * copy). The same mapping is used to allocate the TCC when user passes
228 * EDMA3_RM_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
229 *
230 * To allocate more DMA channels or TCCs, one has to modify the event mapping.
231 */
232 #define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA (0xF3FFFFFCu) /* TBD */
233 #define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_DSPEDMA (0x00000000u) /* TBD */
238 /**
239 * \brief Base address as seen from the different cores may be different
240 * And is defined based on the core
241 */
242 #if ((defined BUILD_DRA72X_MPU) || (defined BUILD_DRA72X_DSP))
243 #define EDMA3_CC_BASE_ADDR ((void *)(0x43300000))
244 #define EDMA3_TC0_BASE_ADDR ((void *)(0x43400000))
245 #define EDMA3_TC1_BASE_ADDR ((void *)(0x43500000))
246 #elif (defined BUILD_DRA72X_IPU)
247 #define EDMA3_CC_BASE_ADDR ((void *)(0x63300000))
248 #define EDMA3_TC0_BASE_ADDR ((void *)(0x63400000))
249 #define EDMA3_TC1_BASE_ADDR ((void *)(0x63500000))
250 #else
251 #define EDMA3_CC_BASE_ADDR ((void *)(0x0))
252 #define EDMA3_TC0_BASE_ADDR ((void *)(0x0))
253 #define EDMA3_TC1_BASE_ADDR ((void *)(0x0))
254 #endif
256 #define DSP1_EDMA3_CC_BASE_ADDR ((void *)(0x01D10000))
257 #define DSP1_EDMA3_TC0_BASE_ADDR ((void *)(0x01D05000))
258 #define DSP1_EDMA3_TC1_BASE_ADDR ((void *)(0x01D06000))
260 /* Driver Object Initialization Configuration */
261 EDMA3_RM_GblConfigParams edma3GblCfgParams [NUM_EDMA3_INSTANCES] =
262 {
263 {
264 /* EDMA3 INSTANCE# 0 */
265 /** Total number of DMA Channels supported by the EDMA3 Controller */
266 EDMA3_NUM_DMA_CHANNELS,
267 /** Total number of QDMA Channels supported by the EDMA3 Controller */
268 EDMA3_NUM_QDMA_CHANNELS,
269 /** Total number of TCCs supported by the EDMA3 Controller */
270 EDMA3_NUM_TCC,
271 /** Total number of PaRAM Sets supported by the EDMA3 Controller */
272 EDMA3_NUM_PARAMSET,
273 /** Total number of Event Queues in the EDMA3 Controller */
274 EDMA3_NUM_EVTQUE,
275 /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller*/
276 EDMA3_NUM_TC,
277 /** Number of Regions on this EDMA3 controller */
278 EDMA3_NUM_REGIONS,
280 /**
281 * \brief Channel mapping existence
282 * A value of 0 (No channel mapping) implies that there is fixed association
283 * for a channel number to a parameter entry number or, in other words,
284 * PaRAM entry n corresponds to channel n.
285 */
286 1u,
288 /** Existence of memory protection feature */
289 0u,
291 /** Global Register Region of CC Registers */
292 EDMA3_CC_BASE_ADDR,
293 /** Transfer Controller (TC) Registers */
294 {
295 EDMA3_TC0_BASE_ADDR,
296 EDMA3_TC1_BASE_ADDR,
297 (void *)NULL,
298 (void *)NULL,
299 (void *)NULL,
300 (void *)NULL,
301 (void *)NULL,
302 (void *)NULL
303 },
304 /** Interrupt no. for Transfer Completion */
305 EDMA3_CC_XFER_COMPLETION_INT,
306 /** Interrupt no. for CC Error */
307 EDMA3_CC_ERROR_INT,
308 /** Interrupt no. for TCs Error */
309 {
310 EDMA3_TC0_ERROR_INT,
311 EDMA3_TC1_ERROR_INT,
312 EDMA3_TC2_ERROR_INT,
313 EDMA3_TC3_ERROR_INT,
314 EDMA3_TC4_ERROR_INT,
315 EDMA3_TC5_ERROR_INT,
316 EDMA3_TC6_ERROR_INT,
317 EDMA3_TC7_ERROR_INT
318 },
320 /**
321 * \brief EDMA3 TC priority setting
322 *
323 * User can program the priority of the Event Queues
324 * at a system-wide level. This means that the user can set the
325 * priority of an IO initiated by either of the TCs (Transfer Controllers)
326 * relative to IO initiated by the other bus masters on the
327 * device (ARM, DSP, USB, etc)
328 */
329 {
330 0u,
331 1u,
332 0u,
333 0u,
334 0u,
335 0u,
336 0u,
337 0u
338 },
339 /**
340 * \brief To Configure the Threshold level of number of events
341 * that can be queued up in the Event queues. EDMA3CC error register
342 * (CCERR) will indicate whether or not at any instant of time the
343 * number of events queued up in any of the event queues exceeds
344 * or equals the threshold/watermark value that is set
345 * in the queue watermark threshold register (QWMTHRA).
346 */
347 {
348 16u,
349 16u,
350 0u,
351 0u,
352 0u,
353 0u,
354 0u,
355 0u
356 },
358 /**
359 * \brief To Configure the Default Burst Size (DBS) of TCs.
360 * An optimally-sized command is defined by the transfer controller
361 * default burst size (DBS). Different TCs can have different
362 * DBS values. It is defined in Bytes.
363 */
364 {
365 16u,
366 16u,
367 0u,
368 0u,
369 0u,
370 0u,
371 0u,
372 0u
373 },
375 /**
376 * \brief Mapping from each DMA channel to a Parameter RAM set,
377 * if it exists, otherwise of no use.
378 */
379 {
380 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
381 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
382 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
383 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
384 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
385 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
386 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
387 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
388 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
389 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
390 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
391 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
392 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
393 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
394 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
395 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
396 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
397 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
398 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
399 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
400 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
401 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
402 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
403 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
404 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
405 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
406 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
407 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
408 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
409 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
410 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
411 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP
412 },
414 /**
415 * \brief Mapping from each DMA channel to a TCC. This specific
416 * TCC code will be returned when the transfer is completed
417 * on the mapped channel.
418 */
419 {
420 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
421 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
422 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
423 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
424 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
425 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
426 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
427 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
428 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
429 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
430 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
431 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
432 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
433 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
434 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
435 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
436 },
438 /**
439 * \brief Mapping of DMA channels to Hardware Events from
440 * various peripherals, which use EDMA for data transfer.
441 * All channels need not be mapped, some can be free also.
442 */
443 {
444 EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA,
445 EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA
446 }
447 },
448 {
449 /* EDMA3 INSTANCE# 1 */
450 /** Total number of DMA Channels supported by the EDMA3 Controller */
451 EDMA3_NUM_DMA_CHANNELS,
452 /** Total number of QDMA Channels supported by the EDMA3 Controller */
453 EDMA3_NUM_QDMA_CHANNELS,
454 /** Total number of TCCs supported by the EDMA3 Controller */
455 EDMA3_NUM_TCC,
456 /** Total number of PaRAM Sets supported by the EDMA3 Controller */
457 EDMA3_NUM_PARAMSET,
458 /** Total number of Event Queues in the EDMA3 Controller */
459 EDMA3_NUM_EVTQUE,
460 /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller*/
461 EDMA3_NUM_TC,
462 /** Number of Regions on this EDMA3 controller */
463 EDMA3_NUM_REGIONS,
465 /**
466 * \brief Channel mapping existence
467 * A value of 0 (No channel mapping) implies that there is fixed association
468 * for a channel number to a parameter entry number or, in other words,
469 * PaRAM entry n corresponds to channel n.
470 */
471 1u,
473 /** Existence of memory protection feature */
474 0u,
476 /** Global Register Region of CC Registers */
477 DSP1_EDMA3_CC_BASE_ADDR,
478 /** Transfer Controller (TC) Registers */
479 {
480 DSP1_EDMA3_TC0_BASE_ADDR,
481 DSP1_EDMA3_TC1_BASE_ADDR,
482 (void *)NULL,
483 (void *)NULL,
484 (void *)NULL,
485 (void *)NULL,
486 (void *)NULL,
487 (void *)NULL
488 },
489 /** Interrupt no. for Transfer Completion */
490 DSP1_EDMA3_CC_XFER_COMPLETION_INT,
491 /** Interrupt no. for CC Error */
492 DSP1_EDMA3_CC_ERROR_INT,
493 /** Interrupt no. for TCs Error */
494 {
495 DSP1_EDMA3_TC0_ERROR_INT,
496 DSP1_EDMA3_TC1_ERROR_INT,
497 EDMA3_TC2_ERROR_INT,
498 EDMA3_TC3_ERROR_INT,
499 EDMA3_TC4_ERROR_INT,
500 EDMA3_TC5_ERROR_INT,
501 EDMA3_TC6_ERROR_INT,
502 EDMA3_TC7_ERROR_INT
503 },
505 /**
506 * \brief EDMA3 TC priority setting
507 *
508 * User can program the priority of the Event Queues
509 * at a system-wide level. This means that the user can set the
510 * priority of an IO initiated by either of the TCs (Transfer Controllers)
511 * relative to IO initiated by the other bus masters on the
512 * device (ARM, DSP, USB, etc)
513 */
514 {
515 0u,
516 1u,
517 0u,
518 0u,
519 0u,
520 0u,
521 0u,
522 0u
523 },
524 /**
525 * \brief To Configure the Threshold level of number of events
526 * that can be queued up in the Event queues. EDMA3CC error register
527 * (CCERR) will indicate whether or not at any instant of time the
528 * number of events queued up in any of the event queues exceeds
529 * or equals the threshold/watermark value that is set
530 * in the queue watermark threshold register (QWMTHRA).
531 */
532 {
533 16u,
534 16u,
535 0u,
536 0u,
537 0u,
538 0u,
539 0u,
540 0u
541 },
543 /**
544 * \brief To Configure the Default Burst Size (DBS) of TCs.
545 * An optimally-sized command is defined by the transfer controller
546 * default burst size (DBS). Different TCs can have different
547 * DBS values. It is defined in Bytes.
548 */
549 {
550 16u,
551 16u,
552 0u,
553 0u,
554 0u,
555 0u,
556 0u,
557 0u
558 },
560 /**
561 * \brief Mapping from each DMA channel to a Parameter RAM set,
562 * if it exists, otherwise of no use.
563 */
564 {
565 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
566 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
567 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
568 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
569 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
570 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
571 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
572 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
573 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
574 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
575 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
576 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
577 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
578 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
579 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
580 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
581 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
582 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
583 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
584 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
585 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
586 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
587 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
588 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
589 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
590 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
591 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
592 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
593 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
594 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
595 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
596 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP
597 },
599 /**
600 * \brief Mapping from each DMA channel to a TCC. This specific
601 * TCC code will be returned when the transfer is completed
602 * on the mapped channel.
603 */
604 {
605 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
606 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
607 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
608 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
609 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
610 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
611 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
612 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
613 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
614 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
615 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
616 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
617 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
618 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
619 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
620 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
621 },
623 /**
624 * \brief Mapping of DMA channels to Hardware Events from
625 * various peripherals, which use EDMA for data transfer.
626 * All channels need not be mapped, some can be free also.
627 */
628 {
629 EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_DSPEDMA,
630 EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_DSPEDMA
631 }
632 }
633 };
635 /**
636 * \brief Resource splitting defines for Own/Reserved DMA/QDMA channels and TCCs
637 * For PaRAMs explicit defines are not present but should be replaced in the structure sampleInstInitConfig
638 * Default configuration has all resources owned by all cores and none reserved except for first 64 PaRAMs corrosponding to DMA channels
639 * Resources to be Split properly by application and rebuild the sample library to avoid resource conflict
640 *
641 * Only Resources owned by a perticular core are allocated by Driver
642 * Reserved resources are not allocated if requested for any available resource
643 */
645 /* Default RM Instance Initialization Configuration */
646 EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][NUM_SHADOW_REGIONS] =
647 {
648 /* EDMA3 INSTANCE# 0 */
649 {
650 /* Resources owned/reserved by region 0 (Associated to any MPU core)*/
651 {
652 /* ownPaRAMSets */
653 /* 31 0 63 32 95 64 127 96 */
654 {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
655 /* 159 128 191 160 223 192 255 224 */
656 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
657 /* 287 256 319 288 351 320 383 352 */
658 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
659 /* 415 384 447 416 479 448 511 480 */
660 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
662 /* ownDmaChannels */
663 /* 31 0 63 32 */
664 {0xFFFFFFFFu, 0xFFFFFFFFu},
666 /* ownQdmaChannels */
667 /* 31 0 */
668 {0x000000FFu},
670 /* ownTccs */
671 /* 31 0 63 32 */
672 {0xFFFFFFFFu, 0xFFFFFFFFu},
674 /* resvdPaRAMSets */
675 /* 31 0 63 32 95 64 127 96 */
676 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
677 /* 159 128 191 160 223 192 255 224 */
678 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
679 /* 287 256 319 288 351 320 383 352 */
680 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
681 /* 415 384 447 416 479 448 511 480 */
682 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
684 /* resvdDmaChannels */
685 /* 31 0 63 32 */
686 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA},
688 /* resvdQdmaChannels */
689 /* 31 0 */
690 {0x00u},
692 /* resvdTccs */
693 /* 31 0 63 32 */
694 {0x00u, 0x00u},
695 },
697 /* Resources owned/reserved by region 1 (Associated to MPU core 1) */
698 {
699 /* ownPaRAMSets */
700 /* 31 0 63 32 95 64 127 96 */
701 {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
702 /* 159 128 191 160 223 192 255 224 */
703 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
704 /* 287 256 319 288 351 320 383 352 */
705 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
706 /* 415 384 447 416 479 448 511 480 */
707 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
709 /* ownDmaChannels */
710 /* 31 0 63 32 */
711 {0xFFFFFFFFu, 0xFFFFFFFFu},
713 /* ownQdmaChannels */
714 /* 31 0 */
715 {0x000000FFu},
717 /* ownTccs */
718 /* 31 0 63 32 */
719 {0xFFFFFFFFu, 0xFFFFFFFFu},
721 /* resvdPaRAMSets */
722 /* 31 0 63 32 95 64 127 96 */
723 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
724 /* 159 128 191 160 223 192 255 224 */
725 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
726 /* 287 256 319 288 351 320 383 352 */
727 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
728 /* 415 384 447 416 479 448 511 480 */
729 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
731 /* resvdDmaChannels */
732 /* 31 0 63 32 */
733 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA},
735 /* resvdQdmaChannels */
736 /* 31 0 */
737 {0x00u},
739 /* resvdTccs */
740 /* 31 0 63 32 */
741 {0x00u, 0x00u},
742 },
744 /* Resources owned/reserved by region 2 (Associated to DSP1)*/
745 {
746 /* ownPaRAMSets */
747 /* 31 0 63 32 95 64 127 96 */
748 {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
749 /* 159 128 191 160 223 192 255 224 */
750 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
751 /* 287 256 319 288 351 320 383 352 */
752 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
753 /* 415 384 447 416 479 448 511 480 */
754 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
756 /* ownDmaChannels */
757 /* 31 0 63 32 */
758 {0xFFFFFFFFu, 0xFFFFFFFFu},
760 /* ownQdmaChannels */
761 /* 31 0 */
762 {0x000000FFu},
764 /* ownTccs */
765 /* 31 0 63 32 */
766 {0xFFFFFFFFu, 0xFFFFFFFFu},
768 /* resvdPaRAMSets */
769 /* 31 0 63 32 95 64 127 96 */
770 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
771 /* 159 128 191 160 223 192 255 224 */
772 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
773 /* 287 256 319 288 351 320 383 352 */
774 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
775 /* 415 384 447 416 479 448 511 480 */
776 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
778 /* resvdDmaChannels */
779 /* 31 0 63 32 */
780 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA},
782 /* resvdQdmaChannels */
783 /* 31 0 */
784 {0x00u},
786 /* resvdTccs */
787 /* 31 0 63 32 */
788 {0x00u, 0x00u},
789 },
791 /* Resources owned/reserved by region 3 (Not Associated to any core supported)*/
792 {
793 /* ownPaRAMSets */
794 /* 31 0 63 32 95 64 127 96 */
795 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
796 /* 159 128 191 160 223 192 255 224 */
797 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
798 /* 287 256 319 288 351 320 383 352 */
799 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
800 /* 415 384 447 416 479 448 511 480 */
801 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
803 /* ownDmaChannels */
804 /* 31 0 63 32 */
805 {0x00000000u, 0x00000000u},
807 /* ownQdmaChannels */
808 /* 31 0 */
809 {0x00000000u},
811 /* ownTccs */
812 /* 31 0 63 32 */
813 {0x00000000u, 0x00000000u},
815 /* resvdPaRAMSets */
816 /* 31 0 63 32 95 64 127 96 */
817 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
818 /* 159 128 191 160 223 192 255 224 */
819 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
820 /* 287 256 319 288 351 320 383 352 */
821 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
822 /* 415 384 447 416 479 448 511 480 */
823 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
825 /* resvdDmaChannels */
826 /* 31 0 63 32 */
827 {0x00000000u, 0x00000000u},
829 /* resvdQdmaChannels */
830 /* 31 0 */
831 {0x00000000u},
833 /* resvdTccs */
834 /* 31 0 63 32 */
835 {0x00000000u, 0x00000000u},
836 },
838 /* Resources owned/reserved by region 4 (Associated to any IPU1 core 0)*/
839 {
840 /* ownPaRAMSets */
841 /* 31 0 63 32 95 64 127 96 */
842 {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
843 /* 159 128 191 160 223 192 255 224 */
844 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
845 /* 287 256 319 288 351 320 383 352 */
846 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
847 /* 415 384 447 416 479 448 511 480 */
848 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
850 /* ownDmaChannels */
851 /* 31 0 63 32 */
852 {0xFFFFFFFFu, 0xFFFFFFFFu},
854 /* ownQdmaChannels */
855 /* 31 0 */
856 {0x000000FFu},
858 /* ownTccs */
859 /* 31 0 63 32 */
860 {0xFFFFFFFFu, 0xFFFFFFFFu},
862 /* resvdPaRAMSets */
863 /* 31 0 63 32 95 64 127 96 */
864 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
865 /* 159 128 191 160 223 192 255 224 */
866 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
867 /* 287 256 319 288 351 320 383 352 */
868 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
869 /* 415 384 447 416 479 448 511 480 */
870 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
872 /* resvdDmaChannels */
873 /* 31 0 63 32 */
874 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA},
876 /* resvdQdmaChannels */
877 /* 31 0 */
878 {0x00u},
880 /* resvdTccs */
881 /* 31 0 63 32 */
882 {0x00u, 0x00u},
883 },
885 /* Resources owned/reserved by region 5 (Associated to any IPU1 core 1)*/
886 {
887 /* ownPaRAMSets */
888 /* 31 0 63 32 95 64 127 96 */
889 {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
890 /* 159 128 191 160 223 192 255 224 */
891 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
892 /* 287 256 319 288 351 320 383 352 */
893 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
894 /* 415 384 447 416 479 448 511 480 */
895 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
897 /* ownDmaChannels */
898 /* 31 0 63 32 */
899 {0xFFFFFFFFu, 0xFFFFFFFFu},
901 /* ownQdmaChannels */
902 /* 31 0 */
903 {0x000000FFu},
905 /* ownTccs */
906 /* 31 0 63 32 */
907 {0xFFFFFFFFu, 0xFFFFFFFFu},
909 /* resvdPaRAMSets */
910 /* 31 0 63 32 95 64 127 96 */
911 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
912 /* 159 128 191 160 223 192 255 224 */
913 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
914 /* 287 256 319 288 351 320 383 352 */
915 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
916 /* 415 384 447 416 479 448 511 480 */
917 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
919 /* resvdDmaChannels */
920 /* 31 0 63 32 */
921 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA},
923 /* resvdQdmaChannels */
924 /* 31 0 */
925 {0x00u},
927 /* resvdTccs */
928 /* 31 0 63 32 */
929 {0x00u, 0x00u},
930 },
932 /* Resources owned/reserved by region 6 (Associated to any IPU2 core 0)*/
933 {
934 /* ownPaRAMSets */
935 /* 31 0 63 32 95 64 127 96 */
936 {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
937 /* 159 128 191 160 223 192 255 224 */
938 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
939 /* 287 256 319 288 351 320 383 352 */
940 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
941 /* 415 384 447 416 479 448 511 480 */
942 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
944 /* ownDmaChannels */
945 /* 31 0 63 32 */
946 {0xFFFFFFFFu, 0xFFFFFFFFu},
948 /* ownQdmaChannels */
949 /* 31 0 */
950 {0x000000FFu},
952 /* ownTccs */
953 /* 31 0 63 32 */
954 {0xFFFFFFFFu, 0xFFFFFFFFu},
956 /* resvdPaRAMSets */
957 /* 31 0 63 32 95 64 127 96 */
958 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
959 /* 159 128 191 160 223 192 255 224 */
960 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
961 /* 287 256 319 288 351 320 383 352 */
962 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
963 /* 415 384 447 416 479 448 511 480 */
964 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
966 /* resvdDmaChannels */
967 /* 31 0 63 32 */
968 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA},
970 /* resvdQdmaChannels */
971 /* 31 0 */
972 {0x00u},
974 /* resvdTccs */
975 /* 31 0 63 32 */
976 {0x00u, 0x00u},
977 },
979 /* Resources owned/reserved by region 7 (Associated to any IPU2 core 1)*/
980 {
981 /* ownPaRAMSets */
982 /* 31 0 63 32 95 64 127 96 */
983 {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
984 /* 159 128 191 160 223 192 255 224 */
985 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
986 /* 287 256 319 288 351 320 383 352 */
987 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
988 /* 415 384 447 416 479 448 511 480 */
989 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
991 /* ownDmaChannels */
992 /* 31 0 63 32 */
993 {0xFFFFFFFFu, 0xFFFFFFFFu},
995 /* ownQdmaChannels */
996 /* 31 0 */
997 {0x000000FFu},
999 /* ownTccs */
1000 /* 31 0 63 32 */
1001 {0xFFFFFFFFu, 0xFFFFFFFFu},
1003 /* resvdPaRAMSets */
1004 /* 31 0 63 32 95 64 127 96 */
1005 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1006 /* 159 128 191 160 223 192 255 224 */
1007 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1008 /* 287 256 319 288 351 320 383 352 */
1009 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1010 /* 415 384 447 416 479 448 511 480 */
1011 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1013 /* resvdDmaChannels */
1014 /* 31 0 63 32 */
1015 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA},
1017 /* resvdQdmaChannels */
1018 /* 31 0 */
1019 {0x00u},
1021 /* resvdTccs */
1022 /* 31 0 63 32 */
1023 {0x00u, 0x00u},
1024 },
1025 },
1026 /* EDMA3 INSTANCE# 1 DSP1 EDMA*/
1027 {
1028 /* Resources owned/reserved by region 0 (Not Associated to any core supported)*/
1029 {
1030 /* ownPaRAMSets */
1031 /* 31 0 63 32 95 64 127 96 */
1032 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1033 /* 159 128 191 160 223 192 255 224 */
1034 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1035 /* 287 256 319 288 351 320 383 352 */
1036 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1037 /* 415 384 447 416 479 448 511 480 */
1038 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1040 /* ownDmaChannels */
1041 /* 31 0 63 32 */
1042 {0x00000000u, 0x00000000u},
1044 /* ownQdmaChannels */
1045 /* 31 0 */
1046 {0x00000000u},
1048 /* ownTccs */
1049 /* 31 0 63 32 */
1050 {0x00000000u, 0x00000000u},
1052 /* resvdPaRAMSets */
1053 /* 31 0 63 32 95 64 127 96 */
1054 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1055 /* 159 128 191 160 223 192 255 224 */
1056 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1057 /* 287 256 319 288 351 320 383 352 */
1058 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1059 /* 415 384 447 416 479 448 511 480 */
1060 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1062 /* resvdDmaChannels */
1063 /* 31 0 63 32 */
1064 {0x00000000u, 0x00000000u},
1066 /* resvdQdmaChannels */
1067 /* 31 0 */
1068 {0x00000000u},
1070 /* resvdTccs */
1071 /* 31 0 63 32 */
1072 {0x00000000u, 0x00000000u},
1073 },
1075 /* Resources owned/reserved by region 1 (Not Associated to any core supported) */
1076 {
1077 /* ownPaRAMSets */
1078 /* 31 0 63 32 95 64 127 96 */
1079 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1080 /* 159 128 191 160 223 192 255 224 */
1081 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1082 /* 287 256 319 288 351 320 383 352 */
1083 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1084 /* 415 384 447 416 479 448 511 480 */
1085 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1087 /* ownDmaChannels */
1088 /* 31 0 63 32 */
1089 {0x00000000u, 0x00000000u},
1091 /* ownQdmaChannels */
1092 /* 31 0 */
1093 {0x00000000u},
1095 /* ownTccs */
1096 /* 31 0 63 32 */
1097 {0x00000000u, 0x00000000u},
1099 /* resvdPaRAMSets */
1100 /* 31 0 63 32 95 64 127 96 */
1101 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1102 /* 159 128 191 160 223 192 255 224 */
1103 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1104 /* 287 256 319 288 351 320 383 352 */
1105 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1106 /* 415 384 447 416 479 448 511 480 */
1107 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1109 /* resvdDmaChannels */
1110 /* 31 0 63 32 */
1111 {0x00000000u, 0x00000000u},
1113 /* resvdQdmaChannels */
1114 /* 31 0 */
1115 {0x00000000u},
1117 /* resvdTccs */
1118 /* 31 0 63 32 */
1119 {0x00000000u, 0x00000000u},
1120 },
1122 /* Resources owned/reserved by region 2 (Associated to DSP core)*/
1123 {
1124 /* ownPaRAMSets */
1125 /* 31 0 63 32 95 64 127 96 */
1126 {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
1127 /* 159 128 191 160 223 192 255 224 */
1128 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
1129 /* 287 256 319 288 351 320 383 352 */
1130 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
1131 /* 415 384 447 416 479 448 511 480 */
1132 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
1134 /* ownDmaChannels */
1135 /* 31 0 63 32 */
1136 {0xFFFFFFFFu, 0xFFFFFFFFu},
1138 /* ownQdmaChannels */
1139 /* 31 0 */
1140 {0x000000FFu},
1142 /* ownTccs */
1143 /* 31 0 63 32 */
1144 {0xFFFFFFFFu, 0xFFFFFFFFu},
1146 /* resvdPaRAMSets */
1147 /* 31 0 63 32 95 64 127 96 */
1148 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1149 /* 159 128 191 160 223 192 255 224 */
1150 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1151 /* 287 256 319 288 351 320 383 352 */
1152 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1153 /* 415 384 447 416 479 448 511 480 */
1154 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1156 /* resvdDmaChannels */
1157 /* 31 0 63 32 */
1158 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_DSPEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_DSPEDMA},
1160 /* resvdQdmaChannels */
1161 /* 31 0 */
1162 {0x00u},
1164 /* resvdTccs */
1165 /* 31 0 63 32 */
1166 {0x00u, 0x00u},
1167 },
1169 /* Resources owned/reserved by region 3 (Not Associated to any core supported)*/
1170 {
1171 /* ownPaRAMSets */
1172 /* 31 0 63 32 95 64 127 96 */
1173 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1174 /* 159 128 191 160 223 192 255 224 */
1175 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1176 /* 287 256 319 288 351 320 383 352 */
1177 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1178 /* 415 384 447 416 479 448 511 480 */
1179 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1181 /* ownDmaChannels */
1182 /* 31 0 63 32 */
1183 {0x00000000u, 0x00000000u},
1185 /* ownQdmaChannels */
1186 /* 31 0 */
1187 {0x00000000u},
1189 /* ownTccs */
1190 /* 31 0 63 32 */
1191 {0x00000000u, 0x00000000u},
1193 /* resvdPaRAMSets */
1194 /* 31 0 63 32 95 64 127 96 */
1195 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1196 /* 159 128 191 160 223 192 255 224 */
1197 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1198 /* 287 256 319 288 351 320 383 352 */
1199 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1200 /* 415 384 447 416 479 448 511 480 */
1201 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1203 /* resvdDmaChannels */
1204 /* 31 0 63 32 */
1205 {0x00000000u, 0x00000000u},
1207 /* resvdQdmaChannels */
1208 /* 31 0 */
1209 {0x00000000u},
1211 /* resvdTccs */
1212 /* 31 0 63 32 */
1213 {0x00000000u, 0x00000000u},
1214 },
1216 /* Resources owned/reserved by region 4 (Not Associated to any core supported)*/
1217 {
1218 /* ownPaRAMSets */
1219 /* 31 0 63 32 95 64 127 96 */
1220 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1221 /* 159 128 191 160 223 192 255 224 */
1222 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1223 /* 287 256 319 288 351 320 383 352 */
1224 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1225 /* 415 384 447 416 479 448 511 480 */
1226 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1228 /* ownDmaChannels */
1229 /* 31 0 63 32 */
1230 {0x00000000u, 0x00000000u},
1232 /* ownQdmaChannels */
1233 /* 31 0 */
1234 {0x00000000u},
1236 /* ownTccs */
1237 /* 31 0 63 32 */
1238 {0x00000000u, 0x00000000u},
1240 /* resvdPaRAMSets */
1241 /* 31 0 63 32 95 64 127 96 */
1242 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1243 /* 159 128 191 160 223 192 255 224 */
1244 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1245 /* 287 256 319 288 351 320 383 352 */
1246 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1247 /* 415 384 447 416 479 448 511 480 */
1248 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1250 /* resvdDmaChannels */
1251 /* 31 0 63 32 */
1252 {0x00000000u, 0x00000000u},
1254 /* resvdQdmaChannels */
1255 /* 31 0 */
1256 {0x00000000u},
1258 /* resvdTccs */
1259 /* 31 0 63 32 */
1260 {0x00000000u, 0x00000000u},
1261 },
1263 /* Resources owned/reserved by region 5 (Not Associated to any core supported)*/
1264 {
1265 /* ownPaRAMSets */
1266 /* 31 0 63 32 95 64 127 96 */
1267 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1268 /* 159 128 191 160 223 192 255 224 */
1269 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1270 /* 287 256 319 288 351 320 383 352 */
1271 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1272 /* 415 384 447 416 479 448 511 480 */
1273 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1275 /* ownDmaChannels */
1276 /* 31 0 63 32 */
1277 {0x00000000u, 0x00000000u},
1279 /* ownQdmaChannels */
1280 /* 31 0 */
1281 {0x00000000u},
1283 /* ownTccs */
1284 /* 31 0 63 32 */
1285 {0x00000000u, 0x00000000u},
1287 /* resvdPaRAMSets */
1288 /* 31 0 63 32 95 64 127 96 */
1289 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1290 /* 159 128 191 160 223 192 255 224 */
1291 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1292 /* 287 256 319 288 351 320 383 352 */
1293 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1294 /* 415 384 447 416 479 448 511 480 */
1295 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1297 /* resvdDmaChannels */
1298 /* 31 0 63 32 */
1299 {0x00000000u, 0x00000000u},
1301 /* resvdQdmaChannels */
1302 /* 31 0 */
1303 {0x00000000u},
1305 /* resvdTccs */
1306 /* 31 0 63 32 */
1307 {0x00000000u, 0x00000000u},
1308 },
1310 /* Resources owned/reserved by region 6 (Not Associated to any core supported)*/
1311 {
1312 /* ownPaRAMSets */
1313 /* 31 0 63 32 95 64 127 96 */
1314 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1315 /* 159 128 191 160 223 192 255 224 */
1316 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1317 /* 287 256 319 288 351 320 383 352 */
1318 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1319 /* 415 384 447 416 479 448 511 480 */
1320 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1322 /* ownDmaChannels */
1323 /* 31 0 63 32 */
1324 {0x00000000u, 0x00000000u},
1326 /* ownQdmaChannels */
1327 /* 31 0 */
1328 {0x00000000u},
1330 /* ownTccs */
1331 /* 31 0 63 32 */
1332 {0x00000000u, 0x00000000u},
1334 /* resvdPaRAMSets */
1335 /* 31 0 63 32 95 64 127 96 */
1336 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1337 /* 159 128 191 160 223 192 255 224 */
1338 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1339 /* 287 256 319 288 351 320 383 352 */
1340 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1341 /* 415 384 447 416 479 448 511 480 */
1342 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1344 /* resvdDmaChannels */
1345 /* 31 0 63 32 */
1346 {0x00000000u, 0x00000000u},
1348 /* resvdQdmaChannels */
1349 /* 31 0 */
1350 {0x00000000u},
1352 /* resvdTccs */
1353 /* 31 0 63 32 */
1354 {0x00000000u, 0x00000000u},
1355 },
1357 /* Resources owned/reserved by region 7 (Not Associated to any core supported)*/
1358 {
1359 /* ownPaRAMSets */
1360 /* 31 0 63 32 95 64 127 96 */
1361 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1362 /* 159 128 191 160 223 192 255 224 */
1363 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1364 /* 287 256 319 288 351 320 383 352 */
1365 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1366 /* 415 384 447 416 479 448 511 480 */
1367 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1369 /* ownDmaChannels */
1370 /* 31 0 63 32 */
1371 {0x00000000u, 0x00000000u},
1373 /* ownQdmaChannels */
1374 /* 31 0 */
1375 {0x00000000u},
1377 /* ownTccs */
1378 /* 31 0 63 32 */
1379 {0x00000000u, 0x00000000u},
1381 /* resvdPaRAMSets */
1382 /* 31 0 63 32 95 64 127 96 */
1383 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1384 /* 159 128 191 160 223 192 255 224 */
1385 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1386 /* 287 256 319 288 351 320 383 352 */
1387 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1388 /* 415 384 447 416 479 448 511 480 */
1389 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1391 /* resvdDmaChannels */
1392 /* 31 0 63 32 */
1393 {0x00000000u, 0x00000000u},
1395 /* resvdQdmaChannels */
1396 /* 31 0 */
1397 {0x00000000u},
1399 /* resvdTccs */
1400 /* 31 0 63 32 */
1401 {0x00000000u, 0x00000000u},
1402 },
1403 }
1404 };
1406 /* Driver Instance Cross bar event to channel map Initialization Configuration */
1407 EDMA3_RM_GblXbarToChanConfigParams defXbarChanInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
1408 {
1409 /* EDMA3 INSTANCE# 0 */
1410 {
1411 /* Event to channel map for region 0 */
1412 {
1413 {-1, -1, -1, -1, -1, -1, -1, -1,
1414 -1, -1, -1, -1, -1, -1, -1, -1,
1415 -1, -1, -1, -1, -1, -1, -1, -1,
1416 -1, -1, -1, -1, -1, -1, -1, -1,
1417 -1, -1, -1, -1, -1, -1, -1, -1,
1418 -1, -1, -1, -1, -1, -1, -1, -1,
1419 -1, -1, -1, -1, -1, -1, -1, -1,
1420 -1, -1, -1, -1, -1, -1, -1}
1421 },
1422 /* Event to channel map for region 1 */
1423 {
1424 {-1, -1, -1, -1, -1, -1, -1, -1,
1425 -1, -1, -1, -1, -1, -1, -1, -1,
1426 -1, -1, -1, -1, -1, -1, -1, -1,
1427 -1, -1, -1, -1, -1, -1, -1, -1,
1428 -1, -1, -1, -1, -1, -1, -1, -1,
1429 -1, -1, -1, -1, -1, -1, -1, -1,
1430 -1, -1, -1, -1, -1, -1, -1, -1,
1431 -1, -1, -1, -1, -1, -1, -1}
1432 },
1433 /* Event to channel map for region 2 */
1434 {
1435 {-1, -1, -1, -1, -1, -1, -1, -1,
1436 -1, -1, -1, -1, -1, -1, -1, -1,
1437 -1, -1, -1, -1, -1, -1, -1, -1,
1438 -1, -1, -1, -1, -1, -1, -1, -1,
1439 -1, -1, -1, -1, -1, -1, -1, -1,
1440 -1, -1, -1, -1, -1, -1, -1, -1,
1441 -1, -1, -1, -1, -1, -1, -1, -1,
1442 -1, -1, -1, -1, -1, -1, -1}
1443 },
1444 /* Event to channel map for region 3 */
1445 {
1446 {-1, -1, -1, -1, -1, -1, -1, -1,
1447 -1, -1, -1, -1, -1, -1, -1, -1,
1448 -1, -1, -1, -1, -1, -1, -1, -1,
1449 -1, -1, -1, -1, -1, -1, -1, -1,
1450 -1, -1, -1, -1, -1, -1, -1, -1,
1451 -1, -1, -1, -1, -1, -1, -1, -1,
1452 -1, -1, -1, -1, -1, -1, -1, -1,
1453 -1, -1, -1, -1, -1, -1, -1}
1454 },
1455 /* Event to channel map for region 4 */
1456 {
1457 {-1, -1, -1, -1, -1, -1, -1, -1,
1458 -1, -1, -1, -1, -1, -1, -1, -1,
1459 -1, -1, -1, -1, -1, -1, -1, -1,
1460 -1, -1, -1, -1, -1, -1, -1, -1,
1461 -1, -1, -1, -1, -1, -1, -1, -1,
1462 -1, -1, -1, -1, -1, -1, -1, -1,
1463 -1, -1, -1, -1, -1, -1, -1, -1,
1464 -1, -1, -1, -1, -1, -1, -1}
1465 },
1466 /* Event to channel map for region 5 */
1467 {
1468 {-1, -1, -1, -1, -1, -1, -1, -1,
1469 -1, -1, -1, -1, -1, -1, -1, -1,
1470 -1, -1, -1, -1, -1, -1, -1, -1,
1471 -1, -1, -1, -1, -1, -1, -1, -1,
1472 -1, -1, -1, -1, -1, -1, -1, -1,
1473 -1, -1, -1, -1, -1, -1, -1, -1,
1474 -1, -1, -1, -1, -1, -1, -1, -1,
1475 -1, -1, -1, -1, -1, -1, -1}
1476 },
1477 /* Event to channel map for region 6 */
1478 {
1479 {-1, -1, -1, -1, -1, -1, -1, -1,
1480 -1, -1, -1, -1, -1, -1, -1, -1,
1481 -1, -1, -1, -1, -1, -1, -1, -1,
1482 -1, -1, -1, -1, -1, -1, -1, -1,
1483 -1, -1, -1, -1, -1, -1, -1, -1,
1484 -1, -1, -1, -1, -1, -1, -1, -1,
1485 -1, -1, -1, -1, -1, -1, -1, -1,
1486 -1, -1, -1, -1, -1, -1, -1}
1487 },
1488 /* Event to channel map for region 7 */
1489 {
1490 {-1, -1, -1, -1, -1, -1, -1, -1,
1491 -1, -1, -1, -1, -1, -1, -1, -1,
1492 -1, -1, -1, -1, -1, -1, -1, -1,
1493 -1, -1, -1, -1, -1, -1, -1, -1,
1494 -1, -1, -1, -1, -1, -1, -1, -1,
1495 -1, -1, -1, -1, -1, -1, -1, -1,
1496 -1, -1, -1, -1, -1, -1, -1, -1,
1497 -1, -1, -1, -1, -1, -1, -1}
1498 },
1499 },
1500 /* EDMA3 INSTANCE# 0 */
1501 {
1502 /* Event to channel map for region 0 */
1503 {
1504 {-1, -1, -1, -1, -1, -1, -1, -1,
1505 -1, -1, -1, -1, -1, -1, -1, -1,
1506 -1, -1, -1, -1, -1, -1, -1, -1,
1507 -1, -1, -1, -1, -1, -1, -1, -1,
1508 -1, -1, -1, -1, -1, -1, -1, -1,
1509 -1, -1, -1, -1, -1, -1, -1, -1,
1510 -1, -1, -1, -1, -1, -1, -1, -1,
1511 -1, -1, -1, -1, -1, -1, -1}
1512 },
1513 /* Event to channel map for region 1 */
1514 {
1515 {-1, -1, -1, -1, -1, -1, -1, -1,
1516 -1, -1, -1, -1, -1, -1, -1, -1,
1517 -1, -1, -1, -1, -1, -1, -1, -1,
1518 -1, -1, -1, -1, -1, -1, -1, -1,
1519 -1, -1, -1, -1, -1, -1, -1, -1,
1520 -1, -1, -1, -1, -1, -1, -1, -1,
1521 -1, -1, -1, -1, -1, -1, -1, -1,
1522 -1, -1, -1, -1, -1, -1, -1}
1523 },
1524 /* Event to channel map for region 2 */
1525 {
1526 {-1, -1, -1, -1, -1, -1, -1, -1,
1527 -1, -1, -1, -1, -1, -1, -1, -1,
1528 -1, -1, -1, -1, -1, -1, -1, -1,
1529 -1, -1, -1, -1, -1, -1, -1, -1,
1530 -1, -1, -1, -1, -1, -1, -1, -1,
1531 -1, -1, -1, -1, -1, -1, -1, -1,
1532 -1, -1, -1, -1, -1, -1, -1, -1,
1533 -1, -1, -1, -1, -1, -1, -1}
1534 },
1535 /* Event to channel map for region 3 */
1536 {
1537 {-1, -1, -1, -1, -1, -1, -1, -1,
1538 -1, -1, -1, -1, -1, -1, -1, -1,
1539 -1, -1, -1, -1, -1, -1, -1, -1,
1540 -1, -1, -1, -1, -1, -1, -1, -1,
1541 -1, -1, -1, -1, -1, -1, -1, -1,
1542 -1, -1, -1, -1, -1, -1, -1, -1,
1543 -1, -1, -1, -1, -1, -1, -1, -1,
1544 -1, -1, -1, -1, -1, -1, -1}
1545 },
1546 /* Event to channel map for region 4 */
1547 {
1548 {-1, -1, -1, -1, -1, -1, -1, -1,
1549 -1, -1, -1, -1, -1, -1, -1, -1,
1550 -1, -1, -1, -1, -1, -1, -1, -1,
1551 -1, -1, -1, -1, -1, -1, -1, -1,
1552 -1, -1, -1, -1, -1, -1, -1, -1,
1553 -1, -1, -1, -1, -1, -1, -1, -1,
1554 -1, -1, -1, -1, -1, -1, -1, -1,
1555 -1, -1, -1, -1, -1, -1, -1}
1556 },
1557 /* Event to channel map for region 5 */
1558 {
1559 {-1, -1, -1, -1, -1, -1, -1, -1,
1560 -1, -1, -1, -1, -1, -1, -1, -1,
1561 -1, -1, -1, -1, -1, -1, -1, -1,
1562 -1, -1, -1, -1, -1, -1, -1, -1,
1563 -1, -1, -1, -1, -1, -1, -1, -1,
1564 -1, -1, -1, -1, -1, -1, -1, -1,
1565 -1, -1, -1, -1, -1, -1, -1, -1,
1566 -1, -1, -1, -1, -1, -1, -1}
1567 },
1568 /* Event to channel map for region 6 */
1569 {
1570 {-1, -1, -1, -1, -1, -1, -1, -1,
1571 -1, -1, -1, -1, -1, -1, -1, -1,
1572 -1, -1, -1, -1, -1, -1, -1, -1,
1573 -1, -1, -1, -1, -1, -1, -1, -1,
1574 -1, -1, -1, -1, -1, -1, -1, -1,
1575 -1, -1, -1, -1, -1, -1, -1, -1,
1576 -1, -1, -1, -1, -1, -1, -1, -1,
1577 -1, -1, -1, -1, -1, -1, -1}
1578 },
1579 /* Event to channel map for region 7 */
1580 {
1581 {-1, -1, -1, -1, -1, -1, -1, -1,
1582 -1, -1, -1, -1, -1, -1, -1, -1,
1583 -1, -1, -1, -1, -1, -1, -1, -1,
1584 -1, -1, -1, -1, -1, -1, -1, -1,
1585 -1, -1, -1, -1, -1, -1, -1, -1,
1586 -1, -1, -1, -1, -1, -1, -1, -1,
1587 -1, -1, -1, -1, -1, -1, -1, -1,
1588 -1, -1, -1, -1, -1, -1, -1}
1589 },
1590 }
1591 };
1593 /* End of File */