[keystone-rtos/edma3_lld.git] / packages / ti / sdo / edma3 / rm / src / configs / edma3_omapl137_cfg.c
1 /*
2 * edma3_omapl137_cfg.c
3 *
4 * EDMA3 Driver Adaptation Configuration File (Soc Specific) for OMAPL138.
5 *
6 * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
7 *
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 *
13 * Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 *
16 * Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the
19 * distribution.
20 *
21 * Neither the name of Texas Instruments Incorporated nor the names of
22 * its contributors may be used to endorse or promote products derived
23 * from this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 */
39 #include <ti/sdo/edma3/rm/edma3_rm.h>
41 #define NUM_SHADOW_REGIONS (4u)
43 /**
44 * \brief Mapping of DMA channels 0-31 to Hardware Events from
45 * various peripherals, which use EDMA for data transfer.
46 * All channels need not be mapped, some can be free also.
47 * 1: Mapped
48 * 0: Not mapped
49 *
50 * This mapping will be used to allocate DMA channels when user passes
51 * EDMA3_RM_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
52 * copy). The same mapping is used to allocate the TCC when user passes
53 * EDMA3_RM_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
54 *
55 * To allocate more DMA channels or TCCs, one has to modify the event mapping.
56 */
57 /* EDMA3 0 */
58 /* 31 0 */
59 #define DMA_CHANNEL_TO_EVENT_MAPPING_0_0 (0xFF3FF3FFu)
60 /**
61 * EDMA channels 22 and 23, which correspond to GPIO
62 * bank interrupts will be used for memory-to-memory data transfers.
63 */
65 /**
66 * \brief Mapping of DMA channels 32-63 to Hardware Events from
67 * various peripherals, which use EDMA for data transfer.
68 * All channels need not be mapped, some can be free also.
69 * 1: Mapped
70 * 0: Not mapped
71 *
72 * This mapping will be used to allocate DMA channels when user passes
73 * EDMA3_RM_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
74 * copy). The same mapping is used to allocate the TCC when user passes
75 * EDMA3_RM_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
76 *
77 * To allocate more DMA channels or TCCs, one has to modify the event mapping.
78 */
79 /* DMA channels 32-63 DOES NOT exist in OMAPL138. */
80 /* EDMA3 0 */
81 #define DMA_CHANNEL_TO_EVENT_MAPPING_0_1 (0x0u)
83 EDMA3_RM_GblConfigParams edma3GblCfgParams [EDMA3_MAX_EDMA3_INSTANCES] =
84 {
85 /* EDMA3 INSTANCE# 0 */
86 {
87 /** Total number of DMA Channels supported by the EDMA3 Controller */
88 32u,
89 /** Total number of QDMA Channels supported by the EDMA3 Controller */
90 8u,
91 /** Total number of TCCs supported by the EDMA3 Controller */
92 32u,
93 /** Total number of PaRAM Sets supported by the EDMA3 Controller */
94 128u,
95 /** Total number of Event Queues in the EDMA3 Controller */
96 2u,
97 /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
98 2u,
99 /** Number of Regions on this EDMA3 controller */
100 4u,
102 /**
103 * \brief Channel mapping existence
104 * A value of 0 (No channel mapping) implies that there is fixed association
105 * for a channel number to a parameter entry number or, in other words,
106 * PaRAM entry n corresponds to channel n.
107 */
108 0u,
110 /** Existence of memory protection feature */
111 0u,
113 /** Global Register Region of CC Registers */
114 (void *)(0x01C00000u),
115 /** Transfer Controller (TC) Registers */
116 {
117 (void *)(0x01C08000u),
118 (void *)(0x01C08400u),
119 (void *)NULL,
120 (void *)NULL,
121 (void *)NULL,
122 (void *)NULL,
123 (void *)NULL,
124 (void *)NULL,
125 },
126 /** Interrupt no. for Transfer Completion */
127 8u,
128 /** Interrupt no. for CC Error */
129 56u,
130 /** Interrupt no. for TCs Error */
131 {
132 57u,
133 58u,
134 0u,
135 0u,
136 0u,
137 0u,
138 0u,
139 0u,
140 },
142 /**
143 * \brief EDMA3 TC priority setting
144 *
145 * User can program the priority of the Event Queues
146 * at a system-wide level. This means that the user can set the
147 * priority of an IO initiated by either of the TCs (Transfer Controllers)
148 * relative to IO initiated by the other bus masters on the
149 * device (ARM, DSP, USB, etc)
150 */
151 {
152 0u,
153 1u,
154 0u,
155 0u,
156 0u,
157 0u,
158 0u,
159 0u
160 },
161 /**
162 * \brief To Configure the Threshold level of number of events
163 * that can be queued up in the Event queues. EDMA3CC error register
164 * (CCERR) will indicate whether or not at any instant of time the
165 * number of events queued up in any of the event queues exceeds
166 * or equals the threshold/watermark value that is set
167 * in the queue watermark threshold register (QWMTHRA).
168 */
169 {
170 16u,
171 16u,
172 0u,
173 0u,
174 0u,
175 0u,
176 0u,
177 0u
178 },
180 /**
181 * \brief To Configure the Default Burst Size (DBS) of TCs.
182 * An optimally-sized command is defined by the transfer controller
183 * default burst size (DBS). Different TCs can have different
184 * DBS values. It is defined in Bytes.
185 */
186 {
187 16u,
188 16u,
189 0u,
190 0u,
191 0u,
192 0u,
193 0u,
194 0u
195 },
197 /**
198 * \brief Mapping from each DMA channel to a Parameter RAM set,
199 * if it exists, otherwise of no use.
200 */
201 {
202 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
203 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
204 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
205 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
206 /* DMA channels 32-63 DOES NOT exist in OMAPL138. */
207 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
208 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
209 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
210 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
211 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
212 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
213 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
214 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
215 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
216 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
217 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
218 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
219 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
220 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
221 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
222 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS
223 },
225 /**
226 * \brief Mapping from each DMA channel to a TCC. This specific
227 * TCC code will be returned when the transfer is completed
228 * on the mapped channel.
229 */
230 {
231 0u, 1u, 2u, 3u,
232 4u, 5u, 6u, 7u,
233 8u, 9u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
234 12u, 13u, 14u, 15u,
235 16u, 17u, 18u, 19u,
236 20u, 21u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
237 24u, 25u, 26u, 27u,
238 28u, 29u, 30u, 31u,
239 /* DMA channels 32-63 DOES NOT exist in OMAPL138. */
240 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
241 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
242 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
243 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
244 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
245 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
246 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
247 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC
248 },
250 /**
251 * \brief Mapping of DMA channels to Hardware Events from
252 * various peripherals, which use EDMA for data transfer.
253 * All channels need not be mapped, some can be free also.
254 */
255 {
256 DMA_CHANNEL_TO_EVENT_MAPPING_0_0,
257 DMA_CHANNEL_TO_EVENT_MAPPING_0_1
258 }
259 },
260 };
263 /* Default RM Instance Initialization Configuration */
264 EDMA3_RM_InstanceInitConfig defInstInitConfig [EDMA3_MAX_EDMA3_INSTANCES][NUM_SHADOW_REGIONS] =
265 {
266 /* EDMA3 INSTANCE# 0 */
267 {
268 {
269 /* Resources owned by Region 0 */
270 /* ownPaRAMSets */
271 /* 31 0 63 32 95 64 127 96 */
272 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
273 /* 159 128 191 160 223 192 255 224 */
274 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
275 /* 287 256 319 288 351 320 383 352 */
276 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
277 /* 415 384 447 416 479 448 511 480 */
278 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
280 /* ownDmaChannels */
281 /* 31 0 63 32 */
282 {0x00000000u, 0x00000000u},
284 /* ownQdmaChannels */
285 /* 31 0 */
286 {0x00000000u},
288 /* ownTccs */
289 /* 31 0 63 32 */
290 {0x00000000u, 0x00000000u},
292 /* Resources reserved by Region 0 */
293 /* resvdPaRAMSets */
294 /* 31 0 63 32 95 64 127 96 */
295 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
296 /* 159 128 191 160 223 192 255 224 */
297 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
298 /* 287 256 319 288 351 320 383 352 */
299 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
300 /* 415 384 447 416 479 448 511 480 */
301 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
303 /* resvdDmaChannels */
304 /* 31 0 63 32 */
305 {0x00000000u, 0x00000000u},
307 /* resvdQdmaChannels */
308 /* 31 0 */
309 {0x00000000u},
311 /* resvdTccs */
312 /* 31 0 63 32 */
313 {0x00000000u, 0x00000000u},
314 },
316 {
317 /* Resources owned by Region 1 */
318 /* ownPaRAMSets */
319 /* 31 0 63 32 95 64 127 96 */
320 {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
321 /* 159 128 191 160 223 192 255 224 */
322 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
323 /* 287 256 319 288 351 320 383 352 */
324 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
325 /* 415 384 447 416 479 448 511 480 */
326 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
328 /* ownDmaChannels */
329 /* 31 0 63 32 */
330 {0xFFFFFFFFu, 0x00000000u},
332 /* ownQdmaChannels */
333 /* 31 0 */
334 {0x000000FFu},
336 /* ownTccs */
337 /* 31 0 63 32 */
338 {0xFFFFFFFFu, 0x00000000u},
340 /* Resources reserved by Region 1 */
341 /* resvdPaRAMSets */
342 /* 31 0 63 32 95 64 127 96 */
343 {0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
344 /* 159 128 191 160 223 192 255 224 */
345 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
346 /* 287 256 319 288 351 320 383 352 */
347 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
348 /* 415 384 447 416 479 448 511 480 */
349 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
351 /* resvdDmaChannels */
352 /* 31 0 63..32 */
353 {DMA_CHANNEL_TO_EVENT_MAPPING_0_0, DMA_CHANNEL_TO_EVENT_MAPPING_0_1},
355 /* resvdQdmaChannels */
356 /* 31 0 */
357 {0x00000000u},
359 /* resvdTccs */
360 /* 31 0 63..32 */
361 {DMA_CHANNEL_TO_EVENT_MAPPING_0_0, DMA_CHANNEL_TO_EVENT_MAPPING_0_1},
362 },
364 {
365 /* Resources owned by Region 2 */
366 /* ownPaRAMSets */
367 /* 31 0 63 32 95 64 127 96 */
368 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
369 /* 159 128 191 160 223 192 255 224 */
370 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
371 /* 287 256 319 288 351 320 383 352 */
372 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
373 /* 415 384 447 416 479 448 511 480 */
374 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
376 /* ownDmaChannels */
377 /* 31 0 63 32 */
378 {0x00000000u, 0x00000000u},
380 /* ownQdmaChannels */
381 /* 31 0 */
382 {0x00000000u},
384 /* ownTccs */
385 /* 31 0 63 32 */
386 {0x00000000u, 0x00000000u},
388 /* Resources reserved by Region 2 */
389 /* resvdPaRAMSets */
390 /* 31 0 63 32 95 64 127 96 */
391 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
392 /* 159 128 191 160 223 192 255 224 */
393 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
394 /* 287 256 319 288 351 320 383 352 */
395 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
396 /* 415 384 447 416 479 448 511 480 */
397 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
399 /* resvdDmaChannels */
400 /* 31 0 63 32 */
401 {0x00000000u, 0x00000000u},
403 /* resvdQdmaChannels */
404 /* 31 0 */
405 {0x00000000u},
407 /* resvdTccs */
408 /* 31 0 63 32 */
409 {0x00000000u, 0x00000000u},
410 },
412 {
413 /* Resources owned by Region 3 */
414 /* ownPaRAMSets */
415 /* 31 0 63 32 95 64 127 96 */
416 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
417 /* 159 128 191 160 223 192 255 224 */
418 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
419 /* 287 256 319 288 351 320 383 352 */
420 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
421 /* 415 384 447 416 479 448 511 480 */
422 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
424 /* ownDmaChannels */
425 /* 31 0 63 32 */
426 {0x00000000u, 0x00000000u},
428 /* ownQdmaChannels */
429 /* 31 0 */
430 {0x00000000u},
432 /* ownTccs */
433 /* 31 0 63 32 */
434 {0x00000000u, 0x00000000u},
436 /* Resources reserved by Region 3 */
437 /* resvdPaRAMSets */
438 /* 31 0 63 32 95 64 127 96 */
439 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
440 /* 159 128 191 160 223 192 255 224 */
441 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
442 /* 287 256 319 288 351 320 383 352 */
443 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
444 /* 415 384 447 416 479 448 511 480 */
445 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
447 /* resvdDmaChannels */
448 /* 31 0 63 32 */
449 {0x00000000u, 0x00000000u},
451 /* resvdQdmaChannels */
452 /* 31 0 */
453 {0x00000000u},
455 /* resvdTccs */
456 /* 31 0 63 32 */
457 {0x00000000u, 0x00000000u},
458 },
459 },
460 };
462 /* End of File */