Moved SoC specific config files in rm/src/configs
[keystone-rtos/edma3_lld.git] / packages / ti / sdo / edma3 / rm / src / configs / edma3_tci6498_cfg.c
1 /*
2  * edma3_tci6498_cfg.c
3  *
4  * EDMA3 Driver Adaptation Configuration File (Soc Specific) for TCI6498.
5  *
6  * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
7  *
8  *
9  *  Redistribution and use in source and binary forms, with or without
10  *  modification, are permitted provided that the following conditions
11  *  are met:
12  *
13  *    Redistributions of source code must retain the above copyright
14  *    notice, this list of conditions and the following disclaimer.
15  *
16  *    Redistributions in binary form must reproduce the above copyright
17  *    notice, this list of conditions and the following disclaimer in the
18  *    documentation and/or other materials provided with the
19  *    distribution.
20  *
21  *    Neither the name of Texas Instruments Incorporated nor the names of
22  *    its contributors may be used to endorse or promote products derived
23  *    from this software without specific prior written permission.
24  *
25  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36  *
37 */
39 #include <ti/sdo/edma3/drv/edma3_drv.h>
41 #define NUM_EDMA3_INSTANCES                     3u
43 /* Driver Object Initialization Configuration */
44 EDMA3_RM_GblConfigParams edma3GblCfgParams [NUM_EDMA3_INSTANCES] =
45         {
46                 {
47                 /* EDMA3 INSTANCE# 0 */
48                 /** Total number of DMA Channels supported by the EDMA3 Controller */
49                 16u,
50                 /** Total number of QDMA Channels supported by the EDMA3 Controller */
51                 8u,
52                 /** Total number of TCCs supported by the EDMA3 Controller */
53                 16u,
54                 /** Total number of PaRAM Sets supported by the EDMA3 Controller */
55                 128u,
56                 /** Total number of Event Queues in the EDMA3 Controller */
57                 2u,
58                 /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
59                 2u,
60                 /** Number of Regions on this EDMA3 controller */
61                 8u,
63                 /**
64                  * \brief Channel mapping existence
65                  * A value of 0 (No channel mapping) implies that there is fixed association
66                  * for a channel number to a parameter entry number or, in other words,
67                  * PaRAM entry n corresponds to channel n.
68                  */
69                 1u,
71                 /** Existence of memory protection feature */
72                 1u,
74                 /** Global Register Region of CC Registers */
75                 (void *)0x02700000u,
76                 /** Transfer Controller (TC) Registers */
77                 {
78                 (void *)0x02760000u,
79                 (void *)0x02768000u,
80                 (void *)NULL,
81                 (void *)NULL,
82                 (void *)NULL,
83                 (void *)NULL,
84                 (void *)NULL,
85                 (void *)NULL
86                 },
87                 /** Interrupt no. for Transfer Completion */
88                 38u,
89                 /** Interrupt no. for CC Error */
90                 32u,
91                 /** Interrupt no. for TCs Error */
92                 {
93                 34u,
94                 35u,
95                 0u,
96                 0u,
97                 0u,
98                 0u,
99                 0u,
100                 0u,
101                 },
103                 /**
104                  * \brief EDMA3 TC priority setting
105                  *
106                  * User can program the priority of the Event Queues
107                  * at a system-wide level.  This means that the user can set the
108                  * priority of an IO initiated by either of the TCs (Transfer Controllers)
109                  * relative to IO initiated by the other bus masters on the
110                  * device (ARM, DSP, USB, etc)
111                  */
112                 {
113                 0u,
114                 1u,
115                 0u,
116                 0u,
117                 0u,
118                 0u,
119                 0u,
120                 0u
121                 },
122                 /**
123                  * \brief To Configure the Threshold level of number of events
124                  * that can be queued up in the Event queues. EDMA3CC error register
125                  * (CCERR) will indicate whether or not at any instant of time the
126                  * number of events queued up in any of the event queues exceeds
127                  * or equals the threshold/watermark value that is set
128                  * in the queue watermark threshold register (QWMTHRA).
129                  */
130                 {
131                 16u,
132                 16u,
133                 0u,
134                 0u,
135                 0u,
136                 0u,
137                 0u,
138                 0u
139                 },
141                 /**
142                  * \brief To Configure the Default Burst Size (DBS) of TCs.
143                  * An optimally-sized command is defined by the transfer controller
144                  * default burst size (DBS). Different TCs can have different
145                  * DBS values. It is defined in Bytes.
146                  */
147                 {
148                 16u,
149                 16u,
150                 0u,
151                 0u,
152                 0u,
153                 0u,
154                 0u,
155                 0u
156                 },
158                 /**
159                  * \brief Mapping from each DMA channel to a Parameter RAM set,
160                  * if it exists, otherwise of no use.
161                  */
162                 {
163                 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
164                 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
165                 /* DMA channels 16-63 DOES NOT exist */
166                 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
167                 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
168                 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
169                 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
170                 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
171                 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
172                 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
173                 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
174                 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
175                 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
176                 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
177                 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
178                 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
179                 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
180                 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
181                 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
182                 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
183                 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
184                 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
185                 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
186                 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
187                 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
188                 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
189                 EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS
190                 },
192                  /**
193                   * \brief Mapping from each DMA channel to a TCC. This specific
194                   * TCC code will be returned when the transfer is completed
195                   * on the mapped channel.
196                   */
197                 {
198                 0u, 1u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
199                 4u, 5u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
200                 8u, 9u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
201                 12u, 13u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
202                 /* DMA channels 16-63 DOES NOT exist */
203                 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
204                 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
205                 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
206                 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
207                 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
208                 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
209                 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
210                 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
211                 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
212                 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
213                 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
214                 EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC
215                 },
217                 /**
218                  * \brief Mapping of DMA channels to Hardware Events from
219                  * various peripherals, which use EDMA for data transfer.
220                  * All channels need not be mapped, some can be free also.
221                  */
222                 {
223                 0x00003333u,
224                 0x00000000u
225                 }
226                 },
228                 {
229                 /* EDMA3 INSTANCE# 1 */
230                 /** Total number of DMA Channels supported by the EDMA3 Controller */
231                 64u,
232                 /** Total number of QDMA Channels supported by the EDMA3 Controller */
233                 8u,
234                 /** Total number of TCCs supported by the EDMA3 Controller */
235                 64u,
236                 /** Total number of PaRAM Sets supported by the EDMA3 Controller */
237                 512u,
238                 /** Total number of Event Queues in the EDMA3 Controller */
239                 4u,
240                 /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
241                 4u,
242                 /** Number of Regions on this EDMA3 controller */
243                 8u,
245                 /**
246                  * \brief Channel mapping existence
247                  * A value of 0 (No channel mapping) implies that there is fixed association
248                  * for a channel number to a parameter entry number or, in other words,
249                  * PaRAM entry n corresponds to channel n.
250                  */
251                 1u,
253                 /** Existence of memory protection feature */
254                 1u,
256                 /** Global Register Region of CC Registers */
257                 (void *)0x02720000u,
258                 /** Transfer Controller (TC) Registers */
259                 {
260                 (void *)0x02770000u,
261                 (void *)0x02778000u,
262                 (void *)0x02780000u,
263                 (void *)0x02788000u,
264                 (void *)NULL,
265                 (void *)NULL,
266                 (void *)NULL,
267                 (void *)NULL
268                 },
269                 /** Interrupt no. for Transfer Completion */
270                 8u,
271                 /** Interrupt no. for CC Error */
272                 0u,
273                 /** Interrupt no. for TCs Error */
274                 {
275                 2u,
276                 3u,
277                 4u,
278                 5u,
279                 0u,
280                 0u,
281                 0u,
282                 0u,
283                 },
285                 /**
286                  * \brief EDMA3 TC priority setting
287                  *
288                  * User can program the priority of the Event Queues
289                  * at a system-wide level.  This means that the user can set the
290                  * priority of an IO initiated by either of the TCs (Transfer Controllers)
291                  * relative to IO initiated by the other bus masters on the
292                  * device (ARM, DSP, USB, etc)
293                  */
294                 {
295                 0u,
296                 1u,
297                 2u,
298                 3u,
299                 0u,
300                 0u,
301                 0u,
302                 0u
303                 },
304                 /**
305                  * \brief To Configure the Threshold level of number of events
306                  * that can be queued up in the Event queues. EDMA3CC error register
307                  * (CCERR) will indicate whether or not at any instant of time the
308                  * number of events queued up in any of the event queues exceeds
309                  * or equals the threshold/watermark value that is set
310                  * in the queue watermark threshold register (QWMTHRA).
311                  */
312                 {
313                 16u,
314                 16u,
315                 16u,
316                 16u,
317                 0u,
318                 0u,
319                 0u,
320                 0u
321                 },
323                 /**
324                  * \brief To Configure the Default Burst Size (DBS) of TCs.
325                  * An optimally-sized command is defined by the transfer controller
326                  * default burst size (DBS). Different TCs can have different
327                  * DBS values. It is defined in Bytes.
328                  */
329                 {
330                 8u,
331                 8u,
332                 8u,
333                 8u,
334                 0u,
335                 0u,
336                 0u,
337                 0u
338                 },
340                 /**
341                  * \brief Mapping from each DMA channel to a Parameter RAM set,
342                  * if it exists, otherwise of no use.
343                  */
344                 {
345                 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
346                 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
347                 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
348                 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
349                 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
350                 40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
351                 48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
352                 56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u
353                 },
355                  /**
356                   * \brief Mapping from each DMA channel to a TCC. This specific
357                   * TCC code will be returned when the transfer is completed
358                   * on the mapped channel.
359                   */
360                 {
361                 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
362                 8u, 9u, 10u, 11u, 12u, 13u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
363                 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
364                 24u, 25u, 26u, 27u, 28u, 29u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
365                 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
366                 40u, 41u, 42u, 43u, 44u, 45u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
367                 48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
368                 56u, 57u, 58u, 59u, 60u, 61u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP
369                 },
371                 /**
372                  * \brief Mapping of DMA channels to Hardware Events from
373                  * various peripherals, which use EDMA for data transfer.
374                  * All channels need not be mapped, some can be free also.
375                  */
376                 {
377                 0x3FFF3FFFu,
378                 0x3FFF3FFFu
379                 }
380                 },
382                 {
383                 /* EDMA3 INSTANCE# 2 */
384                 /** Total number of DMA Channels supported by the EDMA3 Controller */
385                 64u,
386                 /** Total number of QDMA Channels supported by the EDMA3 Controller */
387                 8u,
388                 /** Total number of TCCs supported by the EDMA3 Controller */
389                 64u,
390                 /** Total number of PaRAM Sets supported by the EDMA3 Controller */
391                 512u,
392                 /** Total number of Event Queues in the EDMA3 Controller */
393                 4u,
394                 /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
395                 4u,
396                 /** Number of Regions on this EDMA3 controller */
397                 8u,
399                 /**
400                  * \brief Channel mapping existence
401                  * A value of 0 (No channel mapping) implies that there is fixed association
402                  * for a channel number to a parameter entry number or, in other words,
403                  * PaRAM entry n corresponds to channel n.
404                  */
405                 1u,
407                 /** Existence of memory protection feature */
408                 1u,
410                 /** Global Register Region of CC Registers */
411                 (void *)0x02740000u,
412                 /** Transfer Controller (TC) Registers */
413                 {
414                 (void *)0x02790000u,
415                 (void *)0x02798000u,
416                 (void *)0x027A0000u,
417                 (void *)0x027A8000u,
418                 (void *)NULL,
419                 (void *)NULL,
420                 (void *)NULL,
421                 (void *)NULL
422                 },
423                 /** Interrupt no. for Transfer Completion */
424                 24u,
425                 /** Interrupt no. for CC Error */
426                 16u,
427                 /** Interrupt no. for TCs Error */
428                 {
429                 18u,
430                 19u,
431                 20u,
432                 21u,
433                 0u,
434                 0u,
435                 0u,
436                 0u,
437                 },
439                 /**
440                  * \brief EDMA3 TC priority setting
441                  *
442                  * User can program the priority of the Event Queues
443                  * at a system-wide level.  This means that the user can set the
444                  * priority of an IO initiated by either of the TCs (Transfer Controllers)
445                  * relative to IO initiated by the other bus masters on the
446                  * device (ARM, DSP, USB, etc)
447                  */
448                 {
449                 0u,
450                 1u,
451                 2u,
452                 3u,
453                 0u,
454                 0u,
455                 0u,
456                 0u
457                 },
458                 /**
459                  * \brief To Configure the Threshold level of number of events
460                  * that can be queued up in the Event queues. EDMA3CC error register
461                  * (CCERR) will indicate whether or not at any instant of time the
462                  * number of events queued up in any of the event queues exceeds
463                  * or equals the threshold/watermark value that is set
464                  * in the queue watermark threshold register (QWMTHRA).
465                  */
466                 {
467                 16u,
468                 16u,
469                 16u,
470                 16u,
471                 0u,
472                 0u,
473                 0u,
474                 0u
475                 },
477                 /**
478                  * \brief To Configure the Default Burst Size (DBS) of TCs.
479                  * An optimally-sized command is defined by the transfer controller
480                  * default burst size (DBS). Different TCs can have different
481                  * DBS values. It is defined in Bytes.
482                  */
483                 {
484                 8u,
485                 8u,
486                 8u,
487                 8u,
488                 0u,
489                 0u,
490                 0u,
491                 0u
492                 },
494                 /**
495                  * \brief Mapping from each DMA channel to a Parameter RAM set,
496                  * if it exists, otherwise of no use.
497                  */
498                 {
499                 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
500                 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
501                 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
502                 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
503                 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
504                 40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
505                 48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
506                 56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u
507                 },
509                  /**
510                   * \brief Mapping from each DMA channel to a TCC. This specific
511                   * TCC code will be returned when the transfer is completed
512                   * on the mapped channel.
513                   */
514                 {
515                 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
516                 8u, 9u, 10u, 11u, 12u, 13u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
517                 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
518                 24u, 25u, 26u, 27u, 28u, 29u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
519                 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
520                 40u, 41u, 42u, 43u, 44u, 45u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
521                 48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
522                 56u, 57u, 58u, 59u, 60u, 61u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP
523                 },
525                 /**
526                  * \brief Mapping of DMA channels to Hardware Events from
527                  * various peripherals, which use EDMA for data transfer.
528                  * All channels need not be mapped, some can be free also.
529                  */
530                 {
531                 0x3FFF3FFFu,
532                 0x3FFF3FFFu
533                 }
534                 },
535         };
537 EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
538         {
539                 /* EDMA3 INSTANCE# 0 */
540                 {
541                         /* Resources owned/reserved by region 0 */
542                         {
543                                 /* ownPaRAMSets */
544                                 /* 31     0     63    32     95    64     127   96 */
545                                 {0xFFFF000Fu, 0x00000FFFu, 0x00000000u, 0x00000000u,
546                                 /* 159  128     191  160     223  192     255  224 */
547                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
548                                 /* 287  256     319  288     351  320     383  352 */
549                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
550                                 /* 415  384     447  416     479  448     511  480 */
551                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
553                                 /* ownDmaChannels */
554                                 /* 31     0     63    32 */
555                                 {0x0000000Fu, 0x00000000u},
557                                 /* ownQdmaChannels */
558                                 /* 31     0 */
559                                 {0x00000003u},
561                                 /* ownTccs */
562                                 /* 31     0     63    32 */
563                                 {0x0000000Fu, 0x00000000u},
565                                 /* resvdPaRAMSets */
566                                 /* 31     0     63    32     95    64     127   96 */
567                                 {0x00000003u, 0x00000000u, 0x00000000u, 0x00000000u,
568                                 /* 159  128     191  160     223  192     255  224 */
569                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
570                                 /* 287  256     319  288     351  320     383  352 */
571                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
572                                 /* 415  384     447  416     479  448     511  480 */
573                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
575                                 /* resvdDmaChannels */
576                                 /* 31           0 */
577                                 {0x00000003u, 0x00000000u},
579                                 /* resvdQdmaChannels */
580                                 /* 31     0 */
581                                 {0x00000000u},
583                                 /* resvdTccs */
584                                 /* 31           0 */
585                                 {0x00000003u, 0x00000000u},
586                         },
588                 /* Resources owned/reserved by region 1 */
589                         {
590                                 /* ownPaRAMSets */
591                                 /* 31     0     63    32     95    64     127   96 */
592                                 {0x000000F0u, 0xFFFFF000u, 0x000000FFu, 0x00000000u,
593                                 /* 159  128     191  160     223  192     255  224 */
594                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
595                                 /* 287  256     319  288     351  320     383  352 */
596                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
597                                 /* 415  384     447  416     479  448     511  480 */
598                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
600                                 /* ownDmaChannels */
601                                 /* 31     0     63    32 */
602                                 {0x000000F0u, 0x00000000u},
604                                 /* ownQdmaChannels */
605                                 /* 31     0 */
606                                 {0x0000000Cu},
608                                 /* ownTccs */
609                                 /* 31     0     63    32 */
610                                 {0x000000F0u, 0x00000000u},
612                                 /* resvdPaRAMSets */
613                                 /* 31     0     63    32     95    64     127   96 */
614                                 {0x00000030u, 0x00000000u, 0x00000000u, 0x00000000u,
615                                 /* 159  128     191  160     223  192     255  224 */
616                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
617                                 /* 287  256     319  288     351  320     383  352 */
618                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
619                                 /* 415  384     447  416     479  448     511  480 */
620                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
622                                 /* resvdDmaChannels */
623                                 /* 31     0     63    32 */
624                                 {0x00000030u, 0x00000000u},
626                                 /* resvdQdmaChannels */
627                                 /* 31     0 */
628                                 {0x00000000u},
630                                 /* resvdTccs */
631                                 /* 31     0     63    32 */
632                                 {0x00000030u, 0x00000000u},
633                         },
635                 /* Resources owned/reserved by region 2 */
636                         {
637                                 /* ownPaRAMSets */
638                                 /* 31     0     63    32     95    64     127   96 */
639                                 {0x00000F00u, 0x00000000u, 0xFFFFFF00u, 0x0000000Fu,
640                                 /* 159  128     191  160     223  192     255  224 */
641                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
642                                 /* 287  256     319  288     351  320     383  352 */
643                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
644                                 /* 415  384     447  416     479  448     511  480 */
645                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
647                                 /* ownDmaChannels */
648                                 /* 31     0     63    32 */
649                                 {0x00000F00u, 0x00000000u},
651                                 /* ownQdmaChannels */
652                                 /* 31     0 */
653                                 {0x00000030u},
655                                 /* ownTccs */
656                                 /* 31     0     63    32 */
657                                 {0x00000F00u, 0x00000000u},
659                                 /* resvdPaRAMSets */
660                                 /* 31     0     63    32     95    64     127   96 */
661                                 {0x00000300u, 0x00000000u, 0x00000000u, 0x00000000u,
662                                 /* 159  128     191  160     223  192     255  224 */
663                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
664                                 /* 287  256     319  288     351  320     383  352 */
665                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
666                                 /* 415  384     447  416     479  448     511  480 */
667                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
669                                 /* resvdDmaChannels */
670                                 /* 31     0     63    32 */
671                                 {0x00000300u, 0x00000000u},
673                                 /* resvdQdmaChannels */
674                                 /* 31     0 */
675                                 {0x00000000u},
677                                 /* resvdTccs */
678                                 /* 31     0     63    32 */
679                                 {0x00000300u, 0x00000000u},
680                         },
682                 /* Resources owned/reserved by region 3 */
683                         {
684                                 /* ownPaRAMSets */
685                                 /* 31     0     63    32     95    64     127   96 */
686                                 {0x0000F000u, 0x00000000u, 0x00000000u, 0xFFFFFFF0u,
687                                 /* 159  128     191  160     223  192     255  224 */
688                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
689                                 /* 287  256     319  288     351  320     383  352 */
690                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
691                                 /* 415  384     447  416     479  448     511  480 */
692                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
694                                 /* ownDmaChannels */
695                                 /* 31     0     63    32 */
696                                 {0x0000F000u, 0x00000000u},
698                                 /* ownQdmaChannels */
699                                 /* 31     0 */
700                                 {0x000000C0u},
702                                 /* ownTccs */
703                                 /* 31     0     63    32 */
704                                 {0x0000F000u, 0x00000000u},
706                                 /* resvdPaRAMSets */
707                                 /* 31     0     63    32     95    64     127   96 */
708                                 {0x00003000u, 0x00000000u, 0x00000000u, 0x00000000u,
709                                 /* 159  128     191  160     223  192     255  224 */
710                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
711                                 /* 287  256     319  288     351  320     383  352 */
712                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
713                                 /* 415  384     447  416     479  448     511  480 */
714                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
716                                 /* resvdDmaChannels */
717                                 /* 31     0     63    32 */
718                                 {0x00003000u, 0x00000000u},
720                                 /* resvdQdmaChannels */
721                                 /* 31     0 */
722                                 {0x00000000u},
724                                 /* resvdTccs */
725                                 /* 31     0     63    32 */
726                                 {0x00003000u, 0x00000000u},
727                         },
729                 /* Resources owned/reserved by region 4 */
730                         {
731                                 /* ownPaRAMSets */
732                                 /* 31     0     63    32     95    64     127   96 */
733                                 {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
734                                 /* 159  128     191  160     223  192     255  224 */
735                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
736                                 /* 287  256     319  288     351  320     383  352 */
737                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
738                                 /* 415  384     447  416     479  448     511  480 */
739                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
741                                 /* ownDmaChannels */
742                                 /* 31     0     63    32 */
743                                 {0x00000000u, 0x00000000u},
745                                 /* ownQdmaChannels */
746                                 /* 31     0 */
747                                 {0x00000000u},
749                                 /* ownTccs */
750                                 /* 31     0     63    32 */
751                                 {0x00000000u, 0x00000000u},
753                                 /* resvdPaRAMSets */
754                                 /* 31     0     63    32     95    64     127   96 */
755                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
756                                 /* 159  128     191  160     223  192     255  224 */
757                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
758                                 /* 287  256     319  288     351  320     383  352 */
759                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
760                                 /* 415  384     447  416     479  448     511  480 */
761                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
763                                 /* resvdDmaChannels */
764                                 /* 31     0     63    32 */
765                                 {0x00000000u, 0x00000000u},
767                                 /* resvdQdmaChannels */
768                                 /* 31     0 */
769                                 {0x00000000u},
771                                 /* resvdTccs */
772                                 /* 31     0     63    32 */
773                                 {0x00000000u, 0x00000000u},
774                         },
776                 /* Resources owned/reserved by region 5 */
777                         {
778                                 /* ownPaRAMSets */
779                                 /* 31     0     63    32     95    64     127   96 */
780                                 {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
781                                 /* 159  128     191  160     223  192     255  224 */
782                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
783                                 /* 287  256     319  288     351  320     383  352 */
784                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
785                                 /* 415  384     447  416     479  448     511  480 */
786                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
788                                 /* ownDmaChannels */
789                                 /* 31     0     63    32 */
790                                 {0x00000000u, 0x00000000u},
792                                 /* ownQdmaChannels */
793                                 /* 31     0 */
794                                 {0x00000000u},
796                                 /* ownTccs */
797                                 /* 31     0     63    32 */
798                                 {0x00000000u, 0x00000000u},
800                                 /* resvdPaRAMSets */
801                                 /* 31     0     63    32     95    64     127   96 */
802                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
803                                 /* 159  128     191  160     223  192     255  224 */
804                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
805                                 /* 287  256     319  288     351  320     383  352 */
806                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
807                                 /* 415  384     447  416     479  448     511  480 */
808                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
810                                 /* resvdDmaChannels */
811                                 /* 31     0     63    32 */
812                                 {0x00000000u, 0x00000000u},
814                                 /* resvdQdmaChannels */
815                                 /* 31     0 */
816                                 {0x00000000u},
818                                 /* resvdTccs */
819                                 /* 31     0     63    32 */
820                                 {0x00000000u, 0x00000000u},
821                         },
823                 /* Resources owned/reserved by region 6 */
824                         {
825                                 /* ownPaRAMSets */
826                                 /* 31     0     63    32     95    64     127   96 */
827                                 {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
828                                 /* 159  128     191  160     223  192     255  224 */
829                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
830                                 /* 287  256     319  288     351  320     383  352 */
831                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
832                                 /* 415  384     447  416     479  448     511  480 */
833                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
835                                 /* ownDmaChannels */
836                                 /* 31     0     63    32 */
837                                 {0x00000000u, 0x00000000u},
839                                 /* ownQdmaChannels */
840                                 /* 31     0 */
841                                 {0x00000000u},
843                                 /* ownTccs */
844                                 /* 31     0     63    32 */
845                                 {0x00000000u, 0x00000000u},
847                                 /* resvdPaRAMSets */
848                                 /* 31     0     63    32     95    64     127   96 */
849                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
850                                 /* 159  128     191  160     223  192     255  224 */
851                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
852                                 /* 287  256     319  288     351  320     383  352 */
853                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
854                                 /* 415  384     447  416     479  448     511  480 */
855                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
857                                 /* resvdDmaChannels */
858                                 /* 31     0     63    32 */
859                                 {0x00000000u, 0x00000000u},
861                                 /* resvdQdmaChannels */
862                                 /* 31     0 */
863                                 {0x00000000u},
865                                 /* resvdTccs */
866                                 /* 31     0     63    32 */
867                                 {0x00000000u, 0x00000000u},
868                         },
870                 /* Resources owned/reserved by region 7 */
871                         {
872                                 /* ownPaRAMSets */
873                                 /* 31     0     63    32     95    64     127   96 */
874                                 {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
875                                 /* 159  128     191  160     223  192     255  224 */
876                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
877                                 /* 287  256     319  288     351  320     383  352 */
878                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
879                                 /* 415  384     447  416     479  448     511  480 */
880                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
882                                 /* ownDmaChannels */
883                                 /* 31     0     63    32 */
884                                 {0x00000000u, 0x00000000u},
886                                 /* ownQdmaChannels */
887                                 /* 31     0 */
888                                 {0x00000000u},
890                                 /* ownTccs */
891                                 /* 31     0     63    32 */
892                                 {0x00000000u, 0x00000000u},
894                                 /* resvdPaRAMSets */
895                                 /* 31     0     63    32     95    64     127   96 */
896                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
897                                 /* 159  128     191  160     223  192     255  224 */
898                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
899                                 /* 287  256     319  288     351  320     383  352 */
900                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
901                                 /* 415  384     447  416     479  448     511  480 */
902                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
904                                 /* resvdDmaChannels */
905                                 /* 31     0     63    32 */
906                                 {0x00000000u, 0x00000000u},
908                                 /* resvdQdmaChannels */
909                                 /* 31     0 */
910                                 {0x00000000u},
912                                 /* resvdTccs */
913                                 /* 31     0     63    32 */
914                                 {0x00000000u, 0x00000000u},
915                         },
916             },
918                 /* EDMA3 INSTANCE# 1 */
919             {
920                 /* Resources owned/reserved by region 0 */
921                         {
922                                 /* ownPaRAMSets */
923                                 /* 31     0     63    32     95    64     127   96 */
924                                 {0x0000FFFFu, 0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu,
925                                 /* 159  128     191  160     223  192     255  224 */
926                                  0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
927                                 /* 287  256     319  288     351  320     383  352 */
928                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
929                                 /* 415  384     447  416     479  448     511  480 */
930                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
932                                 /* ownDmaChannels */
933                                 /* 31     0     63    32 */
934                                 {0x0000FFFFu, 0x00000000u},
936                                 /* ownQdmaChannels */
937                                 /* 31     0 */
938                                 {0x00000003u},
940                                 /* ownTccs */
941                                 /* 31     0     63    32 */
942                                 {0x0000FFFFu, 0x00000000u},
944                                 /* resvdPaRAMSets */
945                                 /* 31     0     63    32     95    64     127   96 */
946                                 {0x00003FFFu, 0x00000000u, 0x00000000u, 0x00000000u,
947                                 /* 159  128     191  160     223  192     255  224 */
948                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
949                                 /* 287  256     319  288     351  320     383  352 */
950                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
951                                 /* 415  384     447  416     479  448     511  480 */
952                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
954                                 /* resvdDmaChannels */
955                                 /* 31     0     63    32 */
956                                 {0x00003FFFu, 0x00000000u},
958                                 /* resvdQdmaChannels */
959                                 /* 31     0 */
960                                 {0x00000000u},
962                                 /* resvdTccs */
963                                 /* 31     0     63    32 */
964                                 {0x00003FFFu, 0x00000000u},
965                         },
967                 /* Resources owned/reserved by region 1 */
968                         {
969                                 /* ownPaRAMSets */
970                                 /* 31     0     63    32     95    64     127   96 */
971                                 {0xFFFF0000u, 0x00000000u, 0x00000000u, 0x00000000u,
972                                 /* 159  128     191  160     223  192     255  224 */
973                                  0x00000000u, 0xFFFF0000u, 0xFFFFFFFFu, 0xFFFFFFFFu,
974                                 /* 287  256     319  288     351  320     383  352 */
975                                  0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
976                                 /* 415  384     447  416     479  448     511  480 */
977                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
979                                 /* ownDmaChannels */
980                                 /* 31     0     63    32 */
981                                 {0xFFFF0000u, 0x00000000u},
983                                 /* ownQdmaChannels */
984                                 /* 31     0 */
985                                 {0x0000000Cu},
987                                 /* ownTccs */
988                                 /* 31     0     63    32 */
989                                 {0xFFFF0000u, 0x00000000u},
991                                 /* resvdPaRAMSets */
992                                 /* 31     0     63    32     95    64     127   96 */
993                                 {0x3FFF0000u, 0x00000000u, 0x00000000u, 0x00000000u,
994                                 /* 159  128     191  160     223  192     255  224 */
995                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
996                                 /* 287  256     319  288     351  320     383  352 */
997                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
998                                 /* 415  384     447  416     479  448     511  480 */
999                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1001                                 /* resvdDmaChannels */
1002                                 /* 31     0     63    32 */
1003                                 {0x3FFF0000u, 0x00000000u},
1005                                 /* resvdQdmaChannels */
1006                                 /* 31     0 */
1007                                 {0x00000000u},
1009                                 /* resvdTccs */
1010                                 /* 31     0     63    32 */
1011                                 {0x3FFF0000u, 0x00000000u},
1012                         },
1014                 /* Resources owned/reserved by region 2 */
1015                         {
1016                                 /* ownPaRAMSets */
1017                                 /* 31     0     63    32     95    64     127   96 */
1018                                 {0x00000000u, 0x0000FFFFu, 0x00000000u, 0x00000000u,
1019                                 /* 159  128     191  160     223  192     255  224 */
1020                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1021                                 /* 287  256     319  288     351  320     383  352 */
1022                                  0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
1023                                 /* 415  384     447  416     479  448     511  480 */
1024                                  0x0000FFFFu, 0x00000000u, 0x00000000u, 0x00000000u,},
1026                                 /* ownDmaChannels */
1027                                 /* 31     0     63    32 */
1028                                 {0x00000000u, 0x0000FFFFu},
1030                                 /* ownQdmaChannels */
1031                                 /* 31     0 */
1032                                 {0x00000030u},
1034                                 /* ownTccs */
1035                                 /* 31     0     63    32 */
1036                                 {0x00000000u, 0x0000FFFFu},
1038                                 /* resvdPaRAMSets */
1039                                 /* 31     0     63    32     95    64     127   96 */
1040                                 {0x00000000u, 0x00003FFFu, 0x00000000u, 0x00000000u,
1041                                 /* 159  128     191  160     223  192     255  224 */
1042                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1043                                 /* 287  256     319  288     351  320     383  352 */
1044                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1045                                 /* 415  384     447  416     479  448     511  480 */
1046                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1048                                 /* resvdDmaChannels */
1049                                 /* 31     0     63    32 */
1050                                 {0x00000000u, 0x00003FFFu},
1052                                 /* resvdQdmaChannels */
1053                                 /* 31     0 */
1054                                 {0x00000000u},
1056                                 /* resvdTccs */
1057                                 /* 31     0     63    32 */
1058                                 {0x00000000u, 0x00003FFFu},
1059                         },
1061                 /* Resources owned/reserved by region 3 */
1062                         {
1063                                 /* ownPaRAMSets */
1064                                 /* 31     0     63    32     95    64     127   96 */
1065                                 {0x00000000u, 0xFFFF0000u, 0x00000000u, 0x00000000u,
1066                                 /* 159  128     191  160     223  192     255  224 */
1067                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1068                                 /* 287  256     319  288     351  320     383  352 */
1069                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1070                                 /* 415  384     447  416     479  448     511  480 */
1071                                  0xFFFF0000u, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,},
1073                                 /* ownDmaChannels */
1074                                 /* 31     0     63    32 */
1075                                 {0x00000000u, 0xFFFF0000u},
1077                                 /* ownQdmaChannels */
1078                                 /* 31     0 */
1079                                 {0x000000C0u},
1081                                 /* ownTccs */
1082                                 /* 31     0     63    32 */
1083                                 {0x00000000u, 0xFFFF0000u},
1085                                 /* resvdPaRAMSets */
1086                                 /* 31     0     63    32     95    64     127   96 */
1087                                 {0x00000000u, 0x3FFF0000u, 0x00000000u, 0x00000000u,
1088                                 /* 159  128     191  160     223  192     255  224 */
1089                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1090                                 /* 287  256     319  288     351  320     383  352 */
1091                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1092                                 /* 415  384     447  416     479  448     511  480 */
1093                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1095                                 /* resvdDmaChannels */
1096                                 /* 31     0     63    32 */
1097                                 {0x00000000u, 0x3FFF0000u},
1099                                 /* resvdQdmaChannels */
1100                                 /* 31     0 */
1101                                 {0x00000000u},
1103                                 /* resvdTccs */
1104                                 /* 31     0     63    32 */
1105                                 {0x00000000u, 0x3FFF0000u},
1106                         },
1108                 /* Resources owned/reserved by region 4 */
1109                         {
1110                                 /* ownPaRAMSets */
1111                                 /* 31     0     63    32     95    64     127   96 */
1112                                 {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
1113                                 /* 159  128     191  160     223  192     255  224 */
1114                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1115                                 /* 287  256     319  288     351  320     383  352 */
1116                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1117                                 /* 415  384     447  416     479  448     511  480 */
1118                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1120                                 /* ownDmaChannels */
1121                                 /* 31     0     63    32 */
1122                                 {0x00000000u, 0x00000000u},
1124                                 /* ownQdmaChannels */
1125                                 /* 31     0 */
1126                                 {0x00000000u},
1128                                 /* ownTccs */
1129                                 /* 31     0     63    32 */
1130                                 {0x00000000u, 0x00000000u},
1132                                 /* resvdPaRAMSets */
1133                                 /* 31     0     63    32     95    64     127   96 */
1134                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1135                                 /* 159  128     191  160     223  192     255  224 */
1136                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1137                                 /* 287  256     319  288     351  320     383  352 */
1138                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1139                                 /* 415  384     447  416     479  448     511  480 */
1140                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1142                                 /* resvdDmaChannels */
1143                                 /* 31     0     63    32 */
1144                                 {0x00000000u, 0x00000000u},
1146                                 /* resvdQdmaChannels */
1147                                 /* 31     0 */
1148                                 {0x00000000u},
1150                                 /* resvdTccs */
1151                                 /* 31     0     63    32 */
1152                                 {0x00000000u, 0x00000000u},
1153                         },
1155                 /* Resources owned/reserved by region 5 */
1156                         {
1157                                 /* ownPaRAMSets */
1158                                 /* 31     0     63    32     95    64     127   96 */
1159                                 {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
1160                                 /* 159  128     191  160     223  192     255  224 */
1161                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1162                                 /* 287  256     319  288     351  320     383  352 */
1163                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1164                                 /* 415  384     447  416     479  448     511  480 */
1165                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1167                                 /* ownDmaChannels */
1168                                 /* 31     0     63    32 */
1169                                 {0x00000000u, 0x00000000u},
1171                                 /* ownQdmaChannels */
1172                                 /* 31     0 */
1173                                 {0x00000000u},
1175                                 /* ownTccs */
1176                                 /* 31     0     63    32 */
1177                                 {0x00000000u, 0x00000000u},
1179                                 /* resvdPaRAMSets */
1180                                 /* 31     0     63    32     95    64     127   96 */
1181                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1182                                 /* 159  128     191  160     223  192     255  224 */
1183                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1184                                 /* 287  256     319  288     351  320     383  352 */
1185                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1186                                 /* 415  384     447  416     479  448     511  480 */
1187                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1189                                 /* resvdDmaChannels */
1190                                 /* 31     0     63    32 */
1191                                 {0x00000000u, 0x00000000u},
1193                                 /* resvdQdmaChannels */
1194                                 /* 31     0 */
1195                                 {0x00000000u},
1197                                 /* resvdTccs */
1198                                 /* 31     0     63    32 */
1199                                 {0x00000000u, 0x00000000u},
1200                         },
1202                 /* Resources owned/reserved by region 6 */
1203                         {
1204                                 /* ownPaRAMSets */
1205                                 /* 31     0     63    32     95    64     127   96 */
1206                                 {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
1207                                 /* 159  128     191  160     223  192     255  224 */
1208                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1209                                 /* 287  256     319  288     351  320     383  352 */
1210                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1211                                 /* 415  384     447  416     479  448     511  480 */
1212                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1214                                 /* ownDmaChannels */
1215                                 /* 31     0     63    32 */
1216                                 {0x00000000u, 0x00000000u},
1218                                 /* ownQdmaChannels */
1219                                 /* 31     0 */
1220                                 {0x00000000u},
1222                                 /* ownTccs */
1223                                 /* 31     0     63    32 */
1224                                 {0x00000000u, 0x00000000u},
1226                                 /* resvdPaRAMSets */
1227                                 /* 31     0     63    32     95    64     127   96 */
1228                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1229                                 /* 159  128     191  160     223  192     255  224 */
1230                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1231                                 /* 287  256     319  288     351  320     383  352 */
1232                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1233                                 /* 415  384     447  416     479  448     511  480 */
1234                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1236                                 /* resvdDmaChannels */
1237                                 /* 31     0     63    32 */
1238                                 {0x00000000u, 0x00000000u},
1240                                 /* resvdQdmaChannels */
1241                                 /* 31     0 */
1242                                 {0x00000000u},
1244                                 /* resvdTccs */
1245                                 /* 31     0     63    32 */
1246                                 {0x00000000u, 0x00000000u},
1247                         },
1249                 /* Resources owned/reserved by region 7 */
1250                         {
1251                                 /* ownPaRAMSets */
1252                                 /* 31     0     63    32     95    64     127   96 */
1253                                 {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
1254                                 /* 159  128     191  160     223  192     255  224 */
1255                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1256                                 /* 287  256     319  288     351  320     383  352 */
1257                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1258                                 /* 415  384     447  416     479  448     511  480 */
1259                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1261                                 /* ownDmaChannels */
1262                                 /* 31     0     63    32 */
1263                                 {0x00000000u, 0x00000000u},
1265                                 /* ownQdmaChannels */
1266                                 /* 31     0 */
1267                                 {0x00000000u},
1269                                 /* ownTccs */
1270                                 /* 31     0     63    32 */
1271                                 {0x00000000u, 0x00000000u},
1273                                 /* resvdPaRAMSets */
1274                                 /* 31     0     63    32     95    64     127   96 */
1275                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1276                                 /* 159  128     191  160     223  192     255  224 */
1277                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1278                                 /* 287  256     319  288     351  320     383  352 */
1279                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1280                                 /* 415  384     447  416     479  448     511  480 */
1281                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1283                                 /* resvdDmaChannels */
1284                                 /* 31     0     63    32 */
1285                                 {0x00000000u, 0x00000000u},
1287                                 /* resvdQdmaChannels */
1288                                 /* 31     0 */
1289                                 {0x00000000u},
1291                                 /* resvdTccs */
1292                                 /* 31     0     63    32 */
1293                                 {0x00000000u, 0x00000000u},
1294                         },
1295             },
1297                 /* EDMA3 INSTANCE# 2 */
1298                 {
1299                 /* Resources owned/reserved by region 0 */
1300                         {
1301                                 /* ownPaRAMSets */
1302                                 /* 31     0     63    32     95    64     127   96 */
1303                                 {0x0000FFFFu, 0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu,
1304                                 /* 159  128     191  160     223  192     255  224 */
1305                                  0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
1306                                 /* 287  256     319  288     351  320     383  352 */
1307                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1308                                 /* 415  384     447  416     479  448     511  480 */
1309                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1311                                 /* ownDmaChannels */
1312                                 /* 31     0     63    32 */
1313                                 {0x0000FFFFu, 0x00000000u},
1315                                 /* ownQdmaChannels */
1316                                 /* 31     0 */
1317                                 {0x00000003u},
1319                                 /* ownTccs */
1320                                 /* 31     0     63    32 */
1321                                 {0x0000FFFFu, 0x00000000u},
1323                                 /* resvdPaRAMSets */
1324                                 /* 31     0     63    32     95    64     127   96 */
1325                                 {0x00003FFFu, 0x00000000u, 0x00000000u, 0x00000000u,
1326                                 /* 159  128     191  160     223  192     255  224 */
1327                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1328                                 /* 287  256     319  288     351  320     383  352 */
1329                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1330                                 /* 415  384     447  416     479  448     511  480 */
1331                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1333                                 /* resvdDmaChannels */
1334                                 /* 31     0     63    32 */
1335                                 {0x00003FFFu, 0x00000000u},
1337                                 /* resvdQdmaChannels */
1338                                 /* 31     0 */
1339                                 {0x00000000u},
1341                                 /* resvdTccs */
1342                                 /* 31     0     63    32 */
1343                                 {0x00003FFFu, 0x00000000u},
1344                         },
1346                 /* Resources owned/reserved by region 1 */
1347                         {
1348                                 /* ownPaRAMSets */
1349                                 /* 31     0     63    32     95    64     127   96 */
1350                                 {0xFFFF0000u, 0x00000000u, 0x00000000u, 0x00000000u,
1351                                 /* 159  128     191  160     223  192     255  224 */
1352                                  0x00000000u, 0xFFFF0000u, 0xFFFFFFFFu, 0xFFFFFFFFu,
1353                                 /* 287  256     319  288     351  320     383  352 */
1354                                  0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
1355                                 /* 415  384     447  416     479  448     511  480 */
1356                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1358                                 /* ownDmaChannels */
1359                                 /* 31     0     63    32 */
1360                                 {0xFFFF0000u, 0x00000000u},
1362                                 /* ownQdmaChannels */
1363                                 /* 31     0 */
1364                                 {0x0000000Cu},
1366                                 /* ownTccs */
1367                                 /* 31     0     63    32 */
1368                                 {0xFFFF0000u, 0x00000000u},
1370                                 /* resvdPaRAMSets */
1371                                 /* 31     0     63    32     95    64     127   96 */
1372                                 {0x3FFF0000u, 0x00000000u, 0x00000000u, 0x00000000u,
1373                                 /* 159  128     191  160     223  192     255  224 */
1374                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1375                                 /* 287  256     319  288     351  320     383  352 */
1376                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1377                                 /* 415  384     447  416     479  448     511  480 */
1378                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1380                                 /* resvdDmaChannels */
1381                                 /* 31     0     63    32 */
1382                                 {0x3FFF0000u, 0x00000000u},
1384                                 /* resvdQdmaChannels */
1385                                 /* 31     0 */
1386                                 {0x00000000u},
1388                                 /* resvdTccs */
1389                                 /* 31     0     63    32 */
1390                                 {0x3FFF0000u, 0x00000000u},
1391                         },
1393                 /* Resources owned/reserved by region 2 */
1394                         {
1395                                 /* ownPaRAMSets */
1396                                 /* 31     0     63    32     95    64     127   96 */
1397                                 {0x00000000u, 0x0000FFFFu, 0x00000000u, 0x00000000u,
1398                                 /* 159  128     191  160     223  192     255  224 */
1399                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1400                                 /* 287  256     319  288     351  320     383  352 */
1401                                  0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
1402                                 /* 415  384     447  416     479  448     511  480 */
1403                                  0x0000FFFFu, 0x00000000u, 0x00000000u, 0x00000000u,},
1405                                 /* ownDmaChannels */
1406                                 /* 31     0     63    32 */
1407                                 {0x00000000u, 0x0000FFFFu},
1409                                 /* ownQdmaChannels */
1410                                 /* 31     0 */
1411                                 {0x00000030u},
1413                                 /* ownTccs */
1414                                 /* 31     0     63    32 */
1415                                 {0x00000000u, 0x0000FFFFu},
1417                                 /* resvdPaRAMSets */
1418                                 /* 31     0     63    32     95    64     127   96 */
1419                                 {0x00000000u, 0x00003FFFu, 0x00000000u, 0x00000000u,
1420                                 /* 159  128     191  160     223  192     255  224 */
1421                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1422                                 /* 287  256     319  288     351  320     383  352 */
1423                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1424                                 /* 415  384     447  416     479  448     511  480 */
1425                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1427                                 /* resvdDmaChannels */
1428                                 /* 31     0     63    32 */
1429                                 {0x00000000u, 0x00003FFFu},
1431                                 /* resvdQdmaChannels */
1432                                 /* 31     0 */
1433                                 {0x00000000u},
1435                                 /* resvdTccs */
1436                                 /* 31     0     63    32 */
1437                                 {0x00000000u, 0x00003FFFu},
1438                         },
1440                 /* Resources owned/reserved by region 3 */
1441                         {
1442                                 /* ownPaRAMSets */
1443                                 /* 31     0     63    32     95    64     127   96 */
1444                                 {0x00000000u, 0xFFFF0000u, 0x00000000u, 0x00000000u,
1445                                 /* 159  128     191  160     223  192     255  224 */
1446                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1447                                 /* 287  256     319  288     351  320     383  352 */
1448                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1449                                 /* 415  384     447  416     479  448     511  480 */
1450                                  0xFFFF0000u, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,},
1452                                 /* ownDmaChannels */
1453                                 /* 31     0     63    32 */
1454                                 {0x00000000u, 0xFFFF0000u},
1456                                 /* ownQdmaChannels */
1457                                 /* 31     0 */
1458                                 {0x000000C0u},
1460                                 /* ownTccs */
1461                                 /* 31     0     63    32 */
1462                                 {0x00000000u, 0xFFFF0000u},
1464                                 /* resvdPaRAMSets */
1465                                 /* 31     0     63    32     95    64     127   96 */
1466                                 {0x00000000u, 0x3FFF0000u, 0x00000000u, 0x00000000u,
1467                                 /* 159  128     191  160     223  192     255  224 */
1468                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1469                                 /* 287  256     319  288     351  320     383  352 */
1470                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1471                                 /* 415  384     447  416     479  448     511  480 */
1472                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1474                                 /* resvdDmaChannels */
1475                                 /* 31     0     63    32 */
1476                                 {0x00000000u, 0x3FFF0000u},
1478                                 /* resvdQdmaChannels */
1479                                 /* 31     0 */
1480                                 {0x00000000u},
1482                                 /* resvdTccs */
1483                                 /* 31     0     63    32 */
1484                                 {0x00000000u, 0x3FFF0000u},
1485                         },
1487                 /* Resources owned/reserved by region 4 */
1488                         {
1489                                 /* ownPaRAMSets */
1490                                 /* 31     0     63    32     95    64     127   96 */
1491                                 {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
1492                                 /* 159  128     191  160     223  192     255  224 */
1493                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1494                                 /* 287  256     319  288     351  320     383  352 */
1495                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1496                                 /* 415  384     447  416     479  448     511  480 */
1497                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1499                                 /* ownDmaChannels */
1500                                 /* 31     0     63    32 */
1501                                 {0x00000000u, 0x00000000u},
1503                                 /* ownQdmaChannels */
1504                                 /* 31     0 */
1505                                 {0x00000000u},
1507                                 /* ownTccs */
1508                                 /* 31     0     63    32 */
1509                                 {0x00000000u, 0x00000000u},
1511                                 /* resvdPaRAMSets */
1512                                 /* 31     0     63    32     95    64     127   96 */
1513                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1514                                 /* 159  128     191  160     223  192     255  224 */
1515                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1516                                 /* 287  256     319  288     351  320     383  352 */
1517                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1518                                 /* 415  384     447  416     479  448     511  480 */
1519                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1521                                 /* resvdDmaChannels */
1522                                 /* 31     0     63    32 */
1523                                 {0x00000000u, 0x00000000u},
1525                                 /* resvdQdmaChannels */
1526                                 /* 31     0 */
1527                                 {0x00000000u},
1529                                 /* resvdTccs */
1530                                 /* 31     0     63    32 */
1531                                 {0x00000000u, 0x00000000u},
1532                         },
1534                 /* Resources owned/reserved by region 5 */
1535                         {
1536                                 /* ownPaRAMSets */
1537                                 /* 31     0     63    32     95    64     127   96 */
1538                                 {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
1539                                 /* 159  128     191  160     223  192     255  224 */
1540                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1541                                 /* 287  256     319  288     351  320     383  352 */
1542                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1543                                 /* 415  384     447  416     479  448     511  480 */
1544                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1546                                 /* ownDmaChannels */
1547                                 /* 31     0     63    32 */
1548                                 {0x00000000u, 0x00000000u},
1550                                 /* ownQdmaChannels */
1551                                 /* 31     0 */
1552                                 {0x00000000u},
1554                                 /* ownTccs */
1555                                 /* 31     0     63    32 */
1556                                 {0x00000000u, 0x00000000u},
1558                                 /* resvdPaRAMSets */
1559                                 /* 31     0     63    32     95    64     127   96 */
1560                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1561                                 /* 159  128     191  160     223  192     255  224 */
1562                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1563                                 /* 287  256     319  288     351  320     383  352 */
1564                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1565                                 /* 415  384     447  416     479  448     511  480 */
1566                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1568                                 /* resvdDmaChannels */
1569                                 /* 31     0     63    32 */
1570                                 {0x00000000u, 0x00000000u},
1572                                 /* resvdQdmaChannels */
1573                                 /* 31     0 */
1574                                 {0x00000000u},
1576                                 /* resvdTccs */
1577                                 /* 31     0     63    32 */
1578                                 {0x00000000u, 0x00000000u},
1579                         },
1581                 /* Resources owned/reserved by region 6 */
1582                         {
1583                                 /* ownPaRAMSets */
1584                                 /* 31     0     63    32     95    64     127   96 */
1585                                 {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
1586                                 /* 159  128     191  160     223  192     255  224 */
1587                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1588                                 /* 287  256     319  288     351  320     383  352 */
1589                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1590                                 /* 415  384     447  416     479  448     511  480 */
1591                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1593                                 /* ownDmaChannels */
1594                                 /* 31     0     63    32 */
1595                                 {0x00000000u, 0x00000000u},
1597                                 /* ownQdmaChannels */
1598                                 /* 31     0 */
1599                                 {0x00000000u},
1601                                 /* ownTccs */
1602                                 /* 31     0     63    32 */
1603                                 {0x00000000u, 0x00000000u},
1605                                 /* resvdPaRAMSets */
1606                                 /* 31     0     63    32     95    64     127   96 */
1607                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1608                                 /* 159  128     191  160     223  192     255  224 */
1609                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1610                                 /* 287  256     319  288     351  320     383  352 */
1611                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1612                                 /* 415  384     447  416     479  448     511  480 */
1613                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1615                                 /* resvdDmaChannels */
1616                                 /* 31     0     63    32 */
1617                                 {0x00000000u, 0x00000000u},
1619                                 /* resvdQdmaChannels */
1620                                 /* 31     0 */
1621                                 {0x00000000u},
1623                                 /* resvdTccs */
1624                                 /* 31     0     63    32 */
1625                                 {0x00000000u, 0x00000000u},
1626                         },
1628                 /* Resources owned/reserved by region 7 */
1629                         {
1630                                 /* ownPaRAMSets */
1631                                 /* 31     0     63    32     95    64     127   96 */
1632                                 {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
1633                                 /* 159  128     191  160     223  192     255  224 */
1634                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1635                                 /* 287  256     319  288     351  320     383  352 */
1636                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1637                                 /* 415  384     447  416     479  448     511  480 */
1638                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1640                                 /* ownDmaChannels */
1641                                 /* 31     0     63    32 */
1642                                 {0x00000000u, 0x00000000u},
1644                                 /* ownQdmaChannels */
1645                                 /* 31     0 */
1646                                 {0x00000000u},
1648                                 /* ownTccs */
1649                                 /* 31     0     63    32 */
1650                                 {0x00000000u, 0x00000000u},
1652                                 /* resvdPaRAMSets */
1653                                 /* 31     0     63    32     95    64     127   96 */
1654                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1655                                 /* 159  128     191  160     223  192     255  224 */
1656                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1657                                 /* 287  256     319  288     351  320     383  352 */
1658                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1659                                 /* 415  384     447  416     479  448     511  480 */
1660                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1662                                 /* resvdDmaChannels */
1663                                 /* 31     0     63    32 */
1664                                 {0x00000000u, 0x00000000u},
1666                                 /* resvdQdmaChannels */
1667                                 /* 31     0 */
1668                                 {0x00000000u},
1670                                 /* resvdTccs */
1671                                 /* 31     0     63    32 */
1672                                 {0x00000000u, 0x00000000u},
1673                         },
1674             },
1675         };
1677 /* End of File */