Misra C fixes:
[keystone-rtos/edma3_lld.git] / packages / ti / sdo / edma3 / rm / src / configs / edma3_tda2xx_cfg.c
1 /*\r
2  * edma3_tda2xx_cfg.c\r
3  *\r
4  * EDMA3 Driver Adaptation Configuration File (Soc Specific) for OMAPL138.\r
5  *\r
6  * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/\r
7  *\r
8  *\r
9  *  Redistribution and use in source and binary forms, with or without\r
10  *  modification, are permitted provided that the following conditions\r
11  *  are met:\r
12  *\r
13  *    Redistributions of source code must retain the above copyright\r
14  *    notice, this list of conditions and the following disclaimer.\r
15  *\r
16  *    Redistributions in binary form must reproduce the above copyright\r
17  *    notice, this list of conditions and the following disclaimer in the\r
18  *    documentation and/or other materials provided with the\r
19  *    distribution.\r
20  *\r
21  *    Neither the name of Texas Instruments Incorporated nor the names of\r
22  *    its contributors may be used to endorse or promote products derived\r
23  *    from this software without specific prior written permission.\r
24  *\r
25  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
26  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
27  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
28  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
29  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
30  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
31  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
32  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
33  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
34  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
35  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
36  *\r
37 */\r
38 \r
39 #include <ti/sdo/edma3/rm/edma3_rm.h>\r
40 \r
41 #define NUM_SHADOW_REGIONS                      (8U)\r
42 \r
43 /* Number of EDMA3 controllers present in the system */\r
44 #define NUM_EDMA3_INSTANCES         1U\r
45 \r
46 /** Number of PaRAM Sets available                                            */\r
47 #define EDMA3_NUM_PARAMSET                              (512U)\r
48 \r
49 /** Number of TCCS available                                                  */\r
50 #define EDMA3_NUM_TCC                                   (64U)\r
51 \r
52 /** Number of DMA Channels available                                          */\r
53 #define EDMA3_NUM_DMA_CHANNELS                          (64U)\r
54 \r
55 /** Number of QDMA Channels available                                         */\r
56 #define EDMA3_NUM_QDMA_CHANNELS                         (8U)\r
57 \r
58 /** Number of Event Queues available                                          */\r
59 #define EDMA3_0_NUM_EVTQUE                              (4U)\r
60 \r
61 /** Number of Transfer Controllers available                                  */\r
62 #define EDMA3_0_NUM_TC                                  (4U)\r
63 \r
64 /** Number of Regions                                                         */\r
65 #define EDMA3_0_NUM_REGIONS                             (2U)\r
66 \r
67 /** Interrupt no. for Transfer Completion                                     */\r
68 #define EDMA3_0_CC_XFER_COMPLETION_INT                  (34U)\r
69 /** Interrupt no. for CC Error                                                */\r
70 #define EDMA3_0_CC_ERROR_INT                            (35U)\r
71 /** Interrupt no. for TCs Error                                               */\r
72 #define EDMA3_0_TC0_ERROR_INT                           (36U)\r
73 #define EDMA3_0_TC1_ERROR_INT                           (37U)\r
74 #define EDMA3_0_TC2_ERROR_INT                           (0U)\r
75 #define EDMA3_0_TC3_ERROR_INT                           (0U)\r
76 #define EDMA3_0_TC4_ERROR_INT                           (0U)\r
77 #define EDMA3_0_TC5_ERROR_INT                           (0U)\r
78 #define EDMA3_0_TC6_ERROR_INT                           (0U)\r
79 #define EDMA3_0_TC7_ERROR_INT                           (0U)\r
80 \r
81 /** XBAR interrupt source index numbers for EDMA interrupts */\r
82 #define XBAR_EDMA_TPCC_IRQ_REGION0                      (361U)\r
83 #define XBAR_EDMA_TPCC_IRQ_REGION1                      (362U)\r
84 #define XBAR_EDMA_TPCC_IRQ_REGION2                      (363U)\r
85 #define XBAR_EDMA_TPCC_IRQ_REGION3                      (364U)\r
86 #define XBAR_EDMA_TPCC_IRQ_REGION4                      (365U)\r
87 #define XBAR_EDMA_TPCC_IRQ_REGION5                      (366U)\r
88 #define XBAR_EDMA_TPCC_IRQ_REGION6                      (367U)\r
89 #define XBAR_EDMA_TPCC_IRQ_REGION7                      (368U)\r
90 \r
91 #define XBAR_EDMA_TPCC_IRQ_ERR                          (359U)\r
92 #define XBAR_EDMA_TC0_IRQ_ERR                           (370U)\r
93 #define XBAR_EDMA_TC1_IRQ_ERR                           (371U)\r
94 \r
95 /**\r
96  * \brief Mapping of DMA channels 0-31 to Hardware Events from\r
97  * various peripherals, which use EDMA for data transfer.\r
98  * All channels need not be mapped, some can be free also.\r
99  * 1: Mapped\r
100  * 0: Not mapped\r
101  *\r
102  * This mapping will be used to allocate DMA channels when user passes\r
103  * EDMA3_RM_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory\r
104  * copy). The same mapping is used to allocate the TCC when user passes\r
105  * EDMA3_RM_TCC_ANY as tcc id (for eg to do memory-to-memory copy).\r
106  *\r
107  * To allocate more DMA channels or TCCs, one has to modify the event mapping.\r
108  */\r
109                                                 /* 31     0 */\r
110 #define DMA_CHANNEL_TO_EVENT_MAPPING_0_0        (0x00000000U)\r
111 \r
112 \r
113 /**\r
114  * \brief Mapping of DMA channels 32-63 to Hardware Events from\r
115  * various peripherals, which use EDMA for data transfer.\r
116  * All channels need not be mapped, some can be free also.\r
117  * 1: Mapped\r
118  * 0: Not mapped\r
119  *\r
120  * This mapping will be used to allocate DMA channels when user passes\r
121  * EDMA3_RM_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory\r
122  * copy). The same mapping is used to allocate the TCC when user passes\r
123  * EDMA3_RM_TCC_ANY as tcc id (for eg to do memory-to-memory copy).\r
124  *\r
125  * To allocate more DMA channels or TCCs, one has to modify the event mapping.\r
126  */\r
127 #define DMA_CHANNEL_TO_EVENT_MAPPING_0_1        (0x00000000U)\r
128 \r
129 \r
130 \r
131 \r
132 /**\r
133  * \brief Base address as seen from the different cores may be different\r
134  * And is defined based on the core\r
135  */\r
136 #define EDMA3_CC_BASE_ADDR                          ((void *)(0x43300000))\r
137 #define EDMA3_TC0_BASE_ADDR                         ((void *)(0x43400000))\r
138 #define EDMA3_TC1_BASE_ADDR                         ((void *)(0x43500000))\r
139 EDMA3_RM_GblConfigParams edma3GblCfgParams [EDMA3_MAX_EDMA3_INSTANCES] =\r
140 {\r
141     /* EDMA3 INSTANCE# 0 */\r
142     {\r
143     /** Total number of DMA Channels supported by the EDMA3 Controller */\r
144     EDMA3_NUM_DMA_CHANNELS,\r
145     /** Total number of QDMA Channels supported by the EDMA3 Controller */\r
146     EDMA3_NUM_QDMA_CHANNELS,\r
147     /** Total number of TCCs supported by the EDMA3 Controller */\r
148     EDMA3_NUM_TCC,\r
149     /** Total number of PaRAM Sets supported by the EDMA3 Controller */\r
150     EDMA3_NUM_PARAMSET,\r
151     /** Total number of Event Queues in the EDMA3 Controller */\r
152     EDMA3_0_NUM_EVTQUE,\r
153     /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */\r
154     EDMA3_0_NUM_TC,\r
155     /** Number of Regions on this EDMA3 controller */\r
156     EDMA3_0_NUM_REGIONS,\r
157 \r
158     /**\r
159      * \brief Channel mapping existence\r
160      * A value of 0 (No channel mapping) implies that there is fixed association\r
161      * for a channel number to a parameter entry number or, in other words,\r
162      * PaRAM entry n corresponds to channel n.\r
163      */\r
164     0U,\r
165 \r
166     /** Existence of memory protection feature */\r
167     0U,\r
168 \r
169         /** Global Register Region of CC Registers */\r
170         EDMA3_CC_BASE_ADDR,\r
171         /** Transfer Controller (TC) Registers */\r
172         {\r
173                 EDMA3_TC0_BASE_ADDR,\r
174                 EDMA3_TC1_BASE_ADDR,\r
175                 (void *)NULL,\r
176                 (void *)NULL,\r
177             (void *)NULL,\r
178             (void *)NULL,\r
179             (void *)NULL,\r
180             (void *)NULL\r
181         },\r
182     /** Interrupt no. for Transfer Completion */\r
183     EDMA3_0_CC_XFER_COMPLETION_INT,\r
184     /** Interrupt no. for CC Error */\r
185     EDMA3_0_CC_ERROR_INT,\r
186     /** Interrupt no. for TCs Error */\r
187         {\r
188         EDMA3_0_TC0_ERROR_INT,\r
189         EDMA3_0_TC1_ERROR_INT,\r
190         EDMA3_0_TC2_ERROR_INT,\r
191         EDMA3_0_TC3_ERROR_INT,\r
192         EDMA3_0_TC4_ERROR_INT,\r
193         EDMA3_0_TC5_ERROR_INT,\r
194         EDMA3_0_TC6_ERROR_INT,\r
195         EDMA3_0_TC7_ERROR_INT\r
196         },\r
197 \r
198    /**\r
199      * \brief EDMA3 TC priority setting\r
200      *\r
201      * User can program the priority of the Event Queues\r
202      * at a system-wide level.  This means that the user can set the\r
203      * priority of an IO initiated by either of the TCs (Transfer Controllers)\r
204      * relative to IO initiated by the other bus masters on the\r
205      * device (ARM, DSP, USB, etc)\r
206      */\r
207         {\r
208         0U,\r
209         1U,\r
210         2U,\r
211         3U,\r
212         0U,\r
213         0U,\r
214         0U,\r
215         0U\r
216         },\r
217     /**\r
218      * \brief To Configure the Threshold level of number of events\r
219      * that can be queued up in the Event queues. EDMA3CC error register\r
220      * (CCERR) will indicate whether or not at any instant of time the\r
221      * number of events queued up in any of the event queues exceeds\r
222      * or equals the threshold/watermark value that is set\r
223      * in the queue watermark threshold register (QWMTHRA).\r
224      */\r
225         {\r
226         16U,\r
227         16U,\r
228         16U,\r
229         16U,\r
230         0U,\r
231         0U,\r
232         0U,\r
233         0U\r
234         },\r
235 \r
236     /**\r
237      * \brief To Configure the Default Burst Size (DBS) of TCs.\r
238      * An optimally-sized command is defined by the transfer controller\r
239      * default burst size (DBS). Different TCs can have different\r
240      * DBS values. It is defined in Bytes.\r
241      */\r
242         {\r
243         16U,\r
244         16U,\r
245         16U,\r
246         16U,\r
247         0U,\r
248         0U,\r
249         0U,\r
250         0U\r
251         },\r
252 \r
253     /**\r
254      * \brief Mapping from each DMA channel to a Parameter RAM set,\r
255      * if it exists, otherwise of no use.\r
256      */\r
257         {\r
258         0U, 1U, 2U, 3U, 4U, 5U, 6U, 7U,\r
259         8U, 9U, 10U, 11U, 12U, 13U, 14U, 15U,\r
260         16U, 17U, 18U, 19U, 20U, 21U, 22U, 23U,\r
261         24U, 25U, 26U, 27U, 28U, 29U, 30U, 31U,\r
262             32U, 33U, 34U, 35U, 36U, 37U, 38U, 39U, \r
263             40U, 41U, 42U, 43U, 44U, 45U, 46U, 47U,\r
264             48U, 49U, 50U, 51U, 52U, 53U, 54U, 55U,\r
265             56U, 57U, 58U, 59U, 60U, 61U, 62U, 63U\r
266         },\r
267 \r
268      /**\r
269       * \brief Mapping from each DMA channel to a TCC. This specific\r
270       * TCC code will be returned when the transfer is completed\r
271       * on the mapped channel.\r
272       */\r
273         {\r
274         0U, 1U, 2U, 3U,\r
275         4U, 5U, 6U, 7U,\r
276         8U, 9U, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
277         12U, 13U, 14U, 15U,\r
278         16U, 17U, 18U, 19U,\r
279         20U, 21U, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
280         24U, 25U, 26U, 27U,\r
281         28U, 29U, 30U, 31U,\r
282             32U, 33U, 34U, 35U,\r
283             36U, 37U, 38U, 39U,\r
284             40U, 41U, 42U, 43U,\r
285             44U, 45U, 46U, 47U,\r
286             48U, 49U, 50U, 51U,\r
287             52U, 53U, 54U, 55U,\r
288             56U, 57U, 58U, 59U,\r
289             60U, 61U, 62U, 63U\r
290         },\r
291 \r
292     /**\r
293      * \brief Mapping of DMA channels to Hardware Events from\r
294      * various peripherals, which use EDMA for data transfer.\r
295      * All channels need not be mapped, some can be free also.\r
296      */\r
297         {\r
298         DMA_CHANNEL_TO_EVENT_MAPPING_0_0,\r
299         DMA_CHANNEL_TO_EVENT_MAPPING_0_1\r
300         }\r
301     },\r
302 };\r
303 \r
304 \r
305 /* Default RM Instance Initialization Configuration */\r
306 EDMA3_RM_InstanceInitConfig defInstInitConfig [EDMA3_MAX_EDMA3_INSTANCES][NUM_SHADOW_REGIONS] =\r
307 {\r
308         /* EDMA3 INSTANCE# 0 */\r
309         {\r
310                         /* Resources owned/reserved by region 0 (Associated to any MPU core)*/\r
311                         {\r
312                                 /* ownPaRAMSets */\r
313                                 /* 31     0     63    32     95    64     127   96 */\r
314                                 {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
315                                 /* 159  128     191  160     223  192     255  224 */\r
316                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
317                                 /* 287  256     319  288     351  320     383  352 */\r
318                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
319                                 /* 415  384     447  416     479  448     511  480 */\r
320                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},\r
321 \r
322                                 /* ownDmaChannels */\r
323                                 /* 31     0     63    32 */\r
324                                 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
325 \r
326                                 /* ownQdmaChannels */\r
327                                 /* 31     0 */\r
328                                 {0x000000FFU},\r
329 \r
330                                 /* ownTccs */\r
331                                 /* 31     0     63    32 */\r
332                                 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
333 \r
334                                 /* resvdPaRAMSets */\r
335                                 /* 31     0     63    32     95    64     127   96 */\r
336                                 {0xFFFFFFFFU, 0xFFFFFFFFU, 0x00000000U, 0x00000000U,\r
337                                 /* 159  128     191  160     223  192     255  224 */\r
338                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
339                                 /* 287  256     319  288     351  320     383  352 */\r
340                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
341                                 /* 415  384     447  416     479  448     511  480 */\r
342                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
343 \r
344                                 /* resvdDmaChannels */\r
345                                 /* 31     0     63    32 */\r
346                                 {0x00U, 0x00U},\r
347 \r
348                                 /* resvdQdmaChannels */\r
349                                 /* 31     0 */\r
350                                 {0x00U},\r
351 \r
352                                 /* resvdTccs */\r
353                                 /* 31     0     63    32 */\r
354                                 {0x00U, 0x00U},\r
355                         },\r
356 \r
357                         /* Resources owned/reserved by region 1 (Associated to any DSP core) */\r
358                         {\r
359                                 /* ownPaRAMSets */\r
360                                 /* 31     0     63    32     95    64     127   96 */\r
361                                 {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
362                                 /* 159  128     191  160     223  192     255  224 */\r
363                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
364                                 /* 287  256     319  288     351  320     383  352 */\r
365                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
366                                 /* 415  384     447  416     479  448     511  480 */\r
367                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},\r
368 \r
369                                 /* ownDmaChannels */\r
370                                 /* 31     0     63    32 */\r
371                                 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
372 \r
373                                 /* ownQdmaChannels */\r
374                                 /* 31     0 */\r
375                                 {0x000000FFU},\r
376 \r
377                                 /* ownTccs */\r
378                                 /* 31     0     63    32 */\r
379                                 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
380 \r
381                                 /* resvdPaRAMSets */\r
382                                 /* 31     0     63    32     95    64     127   96 */\r
383                                 {0xFFFFFFFFU, 0xFFFFFFFFU, 0x00000000U, 0x00000000U,\r
384                                 /* 159  128     191  160     223  192     255  224 */\r
385                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
386                                 /* 287  256     319  288     351  320     383  352 */\r
387                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
388                                 /* 415  384     447  416     479  448     511  480 */\r
389                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
390 \r
391                                 /* resvdDmaChannels */\r
392                                 /* 31     0     63    32 */\r
393                                 {0x00U, 0x00U},\r
394 \r
395                                 /* resvdQdmaChannels */\r
396                                 /* 31     0 */\r
397                                 {0x00U},\r
398 \r
399                                 /* resvdTccs */\r
400                                 /* 31     0     63    32 */\r
401                                 {0x00U, 0x00U},\r
402                         },\r
403 \r
404                 /* Resources owned/reserved by region 2 (Associated to any IPU0 core)*/\r
405                         {\r
406                                 /* ownPaRAMSets */\r
407                                 /* 31     0     63    32     95    64     127   96 */\r
408                                 {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
409                                 /* 159  128     191  160     223  192     255  224 */\r
410                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
411                                 /* 287  256     319  288     351  320     383  352 */\r
412                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
413                                 /* 415  384     447  416     479  448     511  480 */\r
414                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},\r
415 \r
416                                 /* ownDmaChannels */\r
417                                 /* 31     0     63    32 */\r
418                                 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
419 \r
420                                 /* ownQdmaChannels */\r
421                                 /* 31     0 */\r
422                                 {0x000000FFU},\r
423 \r
424                                 /* ownTccs */\r
425                                 /* 31     0     63    32 */\r
426                                 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
427 \r
428                                 /* resvdPaRAMSets */\r
429                                 /* 31     0     63    32     95    64     127   96 */\r
430                                 {0xFFFFFFFFU, 0xFFFFFFFFU, 0x00000000U, 0x00000000U,\r
431                                 /* 159  128     191  160     223  192     255  224 */\r
432                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
433                                 /* 287  256     319  288     351  320     383  352 */\r
434                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
435                                 /* 415  384     447  416     479  448     511  480 */\r
436                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
437 \r
438                                 /* resvdDmaChannels */\r
439                                 /* 31     0     63    32 */\r
440                                 {0x00U, 0x00U},\r
441 \r
442                                 /* resvdQdmaChannels */\r
443                                 /* 31     0 */\r
444                                 {0x00U},\r
445 \r
446                                 /* resvdTccs */\r
447                                 /* 31     0     63    32 */\r
448                                 {0x00U, 0x00U},\r
449                         },\r
450 \r
451                 /* Resources owned/reserved by region 3 (Associated to any IPU1 core)*/\r
452                         {\r
453                                 /* ownPaRAMSets */\r
454                                 /* 31     0     63    32     95    64     127   96 */\r
455                                 {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
456                                 /* 159  128     191  160     223  192     255  224 */\r
457                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
458                                 /* 287  256     319  288     351  320     383  352 */\r
459                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
460                                 /* 415  384     447  416     479  448     511  480 */\r
461                                  0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},\r
462 \r
463                                 /* ownDmaChannels */\r
464                                 /* 31     0     63    32 */\r
465                                 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
466 \r
467                                 /* ownQdmaChannels */\r
468                                 /* 31     0 */\r
469                                 {0x000000FFU},\r
470 \r
471                                 /* ownTccs */\r
472                                 /* 31     0     63    32 */\r
473                                 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
474 \r
475                                 /* resvdPaRAMSets */\r
476                                 /* 31     0     63    32     95    64     127   96 */\r
477                                 {0xFFFFFFFFU, 0xFFFFFFFFU, 0x00000000U, 0x00000000U,\r
478                                 /* 159  128     191  160     223  192     255  224 */\r
479                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
480                                 /* 287  256     319  288     351  320     383  352 */\r
481                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
482                                 /* 415  384     447  416     479  448     511  480 */\r
483                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
484 \r
485                                 /* resvdDmaChannels */\r
486                                 /* 31     0     63    32 */\r
487                                 {0x00U, 0x00U},\r
488 \r
489                                 /* resvdQdmaChannels */\r
490                                 /* 31     0 */\r
491                                 {0x00U},\r
492 \r
493                                 /* resvdTccs */\r
494                                 /* 31     0     63    32 */\r
495                                 {0x00U, 0x00U},\r
496                         },\r
497 \r
498                 /* Resources owned/reserved by region 4 (Not Associated to any core supported)*/\r
499                         {\r
500                                 /* ownPaRAMSets */\r
501                                 /* 31     0     63    32     95    64     127   96 */\r
502                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
503                                 /* 159  128     191  160     223  192     255  224 */\r
504                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
505                                 /* 287  256     319  288     351  320     383  352 */\r
506                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
507                                 /* 415  384     447  416     479  448     511  480 */\r
508                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
509 \r
510                                 /* ownDmaChannels */\r
511                                 /* 31     0     63    32 */\r
512                                 {0x00000000U, 0x00000000U},\r
513 \r
514                                 /* ownQdmaChannels */\r
515                                 /* 31     0 */\r
516                                 {0x00000000U},\r
517 \r
518                                 /* ownTccs */\r
519                                 /* 31     0     63    32 */\r
520                                 {0x00000000U, 0x00000000U},\r
521 \r
522                                 /* resvdPaRAMSets */\r
523                                 /* 31     0     63    32     95    64     127   96 */\r
524                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
525                                 /* 159  128     191  160     223  192     255  224 */\r
526                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
527                                 /* 287  256     319  288     351  320     383  352 */\r
528                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
529                                 /* 415  384     447  416     479  448     511  480 */\r
530                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
531 \r
532                                 /* resvdDmaChannels */\r
533                                 /* 31     0     63    32 */\r
534                                 {0x00000000U, 0x00000000U},\r
535 \r
536                                 /* resvdQdmaChannels */\r
537                                 /* 31     0 */\r
538                                 {0x00000000U},\r
539 \r
540                                 /* resvdTccs */\r
541                                 /* 31     0     63    32 */\r
542                                 {0x00000000U, 0x00000000U},\r
543                         },\r
544 \r
545                 /* Resources owned/reserved by region 5 (Not Associated to any core supported)*/\r
546                         {\r
547                                 /* ownPaRAMSets */\r
548                                 /* 31     0     63    32     95    64     127   96 */\r
549                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
550                                 /* 159  128     191  160     223  192     255  224 */\r
551                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
552                                 /* 287  256     319  288     351  320     383  352 */\r
553                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
554                                 /* 415  384     447  416     479  448     511  480 */\r
555                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
556 \r
557                                 /* ownDmaChannels */\r
558                                 /* 31     0     63    32 */\r
559                                 {0x00000000U, 0x00000000U},\r
560 \r
561                                 /* ownQdmaChannels */\r
562                                 /* 31     0 */\r
563                                 {0x00000000U},\r
564 \r
565                                 /* ownTccs */\r
566                                 /* 31     0     63    32 */\r
567                                 {0x00000000U, 0x00000000U},\r
568 \r
569                                 /* resvdPaRAMSets */\r
570                                 /* 31     0     63    32     95    64     127   96 */\r
571                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
572                                 /* 159  128     191  160     223  192     255  224 */\r
573                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
574                                 /* 287  256     319  288     351  320     383  352 */\r
575                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
576                                 /* 415  384     447  416     479  448     511  480 */\r
577                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
578 \r
579                                 /* resvdDmaChannels */\r
580                                 /* 31     0     63    32 */\r
581                                 {0x00000000U, 0x00000000U},\r
582 \r
583                                 /* resvdQdmaChannels */\r
584                                 /* 31     0 */\r
585                                 {0x00000000U},\r
586 \r
587                                 /* resvdTccs */\r
588                                 /* 31     0     63    32 */\r
589                                 {0x00000000U, 0x00000000U},\r
590                         },\r
591 \r
592                 /* Resources owned/reserved by region 6 (Not Associated to any core supported)*/\r
593                         {\r
594                                 /* ownPaRAMSets */\r
595                                 /* 31     0     63    32     95    64     127   96 */\r
596                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
597                                 /* 159  128     191  160     223  192     255  224 */\r
598                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
599                                 /* 287  256     319  288     351  320     383  352 */\r
600                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
601                                 /* 415  384     447  416     479  448     511  480 */\r
602                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
603 \r
604                                 /* ownDmaChannels */\r
605                                 /* 31     0     63    32 */\r
606                                 {0x00000000U, 0x00000000U},\r
607 \r
608                                 /* ownQdmaChannels */\r
609                                 /* 31     0 */\r
610                                 {0x00000000U},\r
611 \r
612                                 /* ownTccs */\r
613                                 /* 31     0     63    32 */\r
614                                 {0x00000000U, 0x00000000U},\r
615 \r
616                                 /* resvdPaRAMSets */\r
617                                 /* 31     0     63    32     95    64     127   96 */\r
618                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
619                                 /* 159  128     191  160     223  192     255  224 */\r
620                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
621                                 /* 287  256     319  288     351  320     383  352 */\r
622                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
623                                 /* 415  384     447  416     479  448     511  480 */\r
624                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
625 \r
626                                 /* resvdDmaChannels */\r
627                                 /* 31     0     63    32 */\r
628                                 {0x00000000U, 0x00000000U},\r
629 \r
630                                 /* resvdQdmaChannels */\r
631                                 /* 31     0 */\r
632                                 {0x00000000U},\r
633 \r
634                                 /* resvdTccs */\r
635                                 /* 31     0     63    32 */\r
636                                 {0x00000000U, 0x00000000U},\r
637                         },\r
638 \r
639                 /* Resources owned/reserved by region 7 (Not Associated to any core supported)*/\r
640                         {\r
641                                 /* ownPaRAMSets */\r
642                                 /* 31     0     63    32     95    64     127   96 */\r
643                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
644                                 /* 159  128     191  160     223  192     255  224 */\r
645                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
646                                 /* 287  256     319  288     351  320     383  352 */\r
647                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
648                                 /* 415  384     447  416     479  448     511  480 */\r
649                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
650 \r
651                                 /* ownDmaChannels */\r
652                                 /* 31     0     63    32 */\r
653                                 {0x00000000U, 0x00000000U},\r
654 \r
655                                 /* ownQdmaChannels */\r
656                                 /* 31     0 */\r
657                                 {0x00000000U},\r
658 \r
659                                 /* ownTccs */\r
660                                 /* 31     0     63    32 */\r
661                                 {0x00000000U, 0x00000000U},\r
662 \r
663                                 /* resvdPaRAMSets */\r
664                                 /* 31     0     63    32     95    64     127   96 */\r
665                                 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
666                                 /* 159  128     191  160     223  192     255  224 */\r
667                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
668                                 /* 287  256     319  288     351  320     383  352 */\r
669                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
670                                 /* 415  384     447  416     479  448     511  480 */\r
671                                  0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
672 \r
673                                 /* resvdDmaChannels */\r
674                                 /* 31     0     63    32 */\r
675                                 {0x00000000U, 0x00000000U},\r
676 \r
677                                 /* resvdQdmaChannels */\r
678                                 /* 31     0 */\r
679                                 {0x00000000U},\r
680 \r
681                                 /* resvdTccs */\r
682                                 /* 31     0     63    32 */\r
683                                 {0x00000000U, 0x00000000U},\r
684                         },\r
685         },\r
686 };\r
687 \r
688 /* Driver Instance Cross bar event to channel map Initialization Configuration */\r
689 EDMA3_RM_GblXbarToChanConfigParams defXbarChanInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
690 {\r
691     /* EDMA3 INSTANCE# 0 */\r
692     {\r
693         /* Event to channel map for region 0 */\r
694         {\r
695             {-1, -1, -1, -1, -1, -1, -1, -1,\r
696             -1, -1, -1, -1, -1, -1, -1, -1,\r
697             -1, -1, -1, -1, -1, -1, -1, -1,\r
698             -1, -1, -1, -1, -1, -1, -1}\r
699         },\r
700         /* Event to channel map for region 1 */\r
701         {\r
702             {-1, -1, -1, -1, -1, -1, -1, -1,\r
703             -1, -1, -1, -1, -1, -1, -1, -1,\r
704             -1, -1, -1, -1, -1, -1, -1, -1,\r
705             -1, -1, -1, -1, -1, -1, -1}\r
706         },\r
707         /* Event to channel map for region 2 */\r
708         {\r
709             {-1, -1, -1, -1, -1, -1, -1, -1,\r
710             -1, -1, -1, -1, -1, -1, -1, -1,\r
711             -1, -1, -1, -1, -1, -1, -1, -1,\r
712             -1, -1, -1, -1, -1, -1, -1}\r
713         },\r
714         /* Event to channel map for region 3 */\r
715         {\r
716             {-1, -1, -1, -1, -1, -1, -1, -1,\r
717             -1, -1, -1, -1, -1, -1, -1, -1,\r
718             -1, -1, -1, -1, -1, -1, -1, -1,\r
719             -1, -1, -1, -1, -1, -1, -1}\r
720         },\r
721         /* Event to channel map for region 4 */\r
722         {\r
723             {-1, -1, -1, -1, -1, -1, -1, -1,\r
724             -1, -1, -1, -1, -1, -1, -1, -1,\r
725             -1, -1, -1, -1, -1, -1, -1, -1,\r
726             -1, -1, -1, -1, -1, -1, -1}\r
727         },\r
728         /* Event to channel map for region 5 */\r
729         {\r
730             {-1, -1, -1, -1, -1, -1, -1, -1,\r
731             -1, -1, -1, -1, -1, -1, -1, -1,\r
732             -1, -1, -1, -1, -1, -1, -1, -1,\r
733             -1, -1, -1, -1, -1, -1, -1}\r
734         },\r
735         /* Event to channel map for region 6 */\r
736         {\r
737             {-1, -1, -1, -1, -1, -1, -1, -1,\r
738             -1, -1, -1, -1, -1, -1, -1, -1,\r
739             -1, -1, -1, -1, -1, -1, -1, -1,\r
740             -1, -1, -1, -1, -1, -1, -1}\r
741         },\r
742         /* Event to channel map for region 7 */\r
743         {\r
744             {-1, -1, -1, -1, -1, -1, -1, -1,\r
745             -1, -1, -1, -1, -1, -1, -1, -1,\r
746             -1, -1, -1, -1, -1, -1, -1, -1,\r
747             -1, -1, -1, -1, -1, -1, -1}\r
748         },\r
749     }\r
750 };\r
751 \r
752 /* End of File */\r
753 \r
754 \r
755 \r