[keystone-rtos/edma3_lld.git] / packages / ti / sdo / edma3 / rm / src / configs / edma3_tda2xx_cfg.c
1 /*\r
2 * edma3_tda2xx_cfg.c\r
3 *\r
4 * EDMA3 Driver Adaptation Configuration File (Soc Specific) for OMAPL138.\r
5 *\r
6 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/\r
7 *\r
8 *\r
9 * Redistribution and use in source and binary forms, with or without\r
10 * modification, are permitted provided that the following conditions\r
11 * are met:\r
12 *\r
13 * Redistributions of source code must retain the above copyright\r
14 * notice, this list of conditions and the following disclaimer.\r
15 *\r
16 * Redistributions in binary form must reproduce the above copyright\r
17 * notice, this list of conditions and the following disclaimer in the\r
18 * documentation and/or other materials provided with the\r
19 * distribution.\r
20 *\r
21 * Neither the name of Texas Instruments Incorporated nor the names of\r
22 * its contributors may be used to endorse or promote products derived\r
23 * from this software without specific prior written permission.\r
24 *\r
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
36 *\r
37 */\r
38 \r
39 #include <ti/sdo/edma3/rm/edma3_rm.h>\r
40 #ifdef BUILD_TDA2XX_IPU\r
41 #include <ti/sysbios/family/arm/ducati/Core.h> \r
42 #endif\r
43 #define NUM_SHADOW_REGIONS (8U)\r
44 \r
45 /* Number of EDMA3 controllers present in the system */\r
46 #define NUM_EDMA3_INSTANCES 3U\r
47 \r
48 /** Number of PaRAM Sets available */\r
49 #define EDMA3_NUM_PARAMSET (512U)\r
50 \r
51 /** Number of TCCS available */\r
52 #define EDMA3_NUM_TCC (64U)\r
53 \r
54 /** Number of DMA Channels available */\r
55 #define EDMA3_NUM_DMA_CHANNELS (64U)\r
56 \r
57 /** Number of QDMA Channels available */\r
58 #define EDMA3_NUM_QDMA_CHANNELS (8U)\r
59 \r
60 /** Number of Event Queues available */\r
61 #define EDMA3_NUM_EVTQUE (4U)\r
62 \r
63 /** Number of Transfer Controllers available */\r
64 #define EDMA3_NUM_TC (2U)\r
65 \r
66 /** Number of Regions */\r
67 #define EDMA3_NUM_REGIONS (8U)\r
68 \r
69 /** Interrupt no. for Transfer Completion */\r
70 #define EDMA3_CC_XFER_COMPLETION_INT_A15 (66U)\r
71 #define EDMA3_CC_XFER_COMPLETION_INT_DSP (38U)\r
72 #define EDMA3_CC_XFER_COMPLETION_INT_IPU_C0 (34U)\r
73 #define EDMA3_CC_XFER_COMPLETION_INT_IPU_C1 (33U)\r
74 #define EDMA3_CC_XFER_COMPLETION_INT_EVE (8U)\r
75 \r
76 /** Based on the interrupt number to be mapped define the XBAR instance number */\r
77 #define COMPLETION_INT_A15_XBAR_INST_NO (29U)\r
78 #define COMPLETION_INT_DSP_XBAR_INST_NO (7U)\r
79 #define COMPLETION_INT_IPU_C0_XBAR_INST_NO (12U)\r
80 #define COMPLETION_INT_IPU_C1_XBAR_INST_NO (11U)\r
81 \r
82 /** Interrupt no. for CC Error */\r
83 #define EDMA3_CC_ERROR_INT_A15 (67U)\r
84 #define EDMA3_CC_ERROR_INT_DSP (39U)\r
85 #define EDMA3_CC_ERROR_INT_IPU (35U)\r
86 #define EDMA3_CC_ERROR_INT_EVE (23U)\r
87 \r
88 /** Based on the interrupt number to be mapped define the XBAR instance number */\r
89 #define CC_ERROR_INT_A15_XBAR_INST_NO (30U)\r
90 #define CC_ERROR_INT_DSP_XBAR_INST_NO (8U)\r
91 #define CC_ERROR_INT_IPU_XBAR_INST_NO (13U)\r
92 \r
93 /** Interrupt no. for TCs Error */\r
94 #define EDMA3_TC0_ERROR_INT_A15 (68U)\r
95 #define EDMA3_TC0_ERROR_INT_DSP (40U)\r
96 #define EDMA3_TC0_ERROR_INT_IPU (36U)\r
97 #define EDMA3_TC0_ERROR_INT_EVE (24U)\r
98 #define EDMA3_TC1_ERROR_INT_A15 (69U)\r
99 #define EDMA3_TC1_ERROR_INT_DSP (41U)\r
100 #define EDMA3_TC1_ERROR_INT_IPU (37U)\r
101 #define EDMA3_TC1_ERROR_INT_EVE (25U)\r
102 \r
103 /** Based on the interrupt number to be mapped define the XBAR instance number */\r
104 #define TC0_ERROR_INT_A15_XBAR_INST_NO (31U)\r
105 #define TC0_ERROR_INT_DSP_XBAR_INST_NO (9U) \r
106 #define TC0_ERROR_INT_IPU_XBAR_INST_NO (14U)\r
107 #define TC1_ERROR_INT_A15_XBAR_INST_NO (32U)\r
108 #define TC1_ERROR_INT_DSP_XBAR_INST_NO (10U)\r
109 #define TC1_ERROR_INT_IPU_XBAR_INST_NO (15U)\r
110 \r
111 #ifdef BUILD_TDA2XX_MPU\r
112 #define EDMA3_CC_XFER_COMPLETION_INT (EDMA3_CC_XFER_COMPLETION_INT_A15)\r
113 #define EDMA3_CC_ERROR_INT (EDMA3_CC_ERROR_INT_A15)\r
114 #define CC_ERROR_INT_XBAR_INST_NO (CC_ERROR_INT_A15_XBAR_INST_NO)\r
115 #define EDMA3_TC0_ERROR_INT (EDMA3_TC0_ERROR_INT_A15)\r
116 #define EDMA3_TC1_ERROR_INT (EDMA3_TC1_ERROR_INT_A15)\r
117 #define TC0_ERROR_INT_XBAR_INST_NO (TC0_ERROR_INT_A15_XBAR_INST_NO)\r
118 #define TC1_ERROR_INT_XBAR_INST_NO (TC1_ERROR_INT_A15_XBAR_INST_NO)\r
119 \r
120 #elif defined BUILD_TDA2XX_DSP\r
121 #define EDMA3_CC_XFER_COMPLETION_INT (EDMA3_CC_XFER_COMPLETION_INT_DSP)\r
122 #define EDMA3_CC_ERROR_INT (EDMA3_CC_ERROR_INT_DSP)\r
123 #define CC_ERROR_INT_XBAR_INST_NO (CC_ERROR_INT_DSP_XBAR_INST_NO)\r
124 #define EDMA3_TC0_ERROR_INT (EDMA3_TC0_ERROR_INT_DSP)\r
125 #define EDMA3_TC1_ERROR_INT (EDMA3_TC1_ERROR_INT_DSP)\r
126 #define TC0_ERROR_INT_XBAR_INST_NO (TC0_ERROR_INT_DSP_XBAR_INST_NO)\r
127 #define TC1_ERROR_INT_XBAR_INST_NO (TC1_ERROR_INT_DSP_XBAR_INST_NO)\r
128 \r
129 #elif defined BUILD_TDA2XX_IPU\r
130 #define EDMA3_CC_XFER_COMPLETION_INT (EDMA3_CC_XFER_COMPLETION_INT_IPU_C0)\r
131 #define EDMA3_CC_ERROR_INT (EDMA3_CC_ERROR_INT_IPU)\r
132 #define CC_ERROR_INT_XBAR_INST_NO (CC_ERROR_INT_IPU_XBAR_INST_NO)\r
133 #define EDMA3_TC0_ERROR_INT (EDMA3_TC0_ERROR_INT_IPU)\r
134 #define EDMA3_TC1_ERROR_INT (EDMA3_TC1_ERROR_INT_IPU)\r
135 #define TC0_ERROR_INT_XBAR_INST_NO (TC0_ERROR_INT_IPU_XBAR_INST_NO)\r
136 #define TC1_ERROR_INT_XBAR_INST_NO (TC1_ERROR_INT_IPU_XBAR_INST_NO)\r
137 \r
138 #elif defined BUILD_TDA2XX_EVE\r
139 #define EDMA3_CC_XFER_COMPLETION_INT (EDMA3_CC_XFER_COMPLETION_INT_EVE)\r
140 #define EDMA3_CC_ERROR_INT (EDMA3_CC_ERROR_INT_EVE)\r
141 #define EDMA3_TC0_ERROR_INT (EDMA3_TC0_ERROR_INT_EVE)\r
142 #define EDMA3_TC1_ERROR_INT (EDMA3_TC1_ERROR_INT_EVE)\r
143 /* For accessing EVE internal edma, there is no need to configure Xbar */\r
144 #define CC_ERROR_INT_XBAR_INST_NO (0U)\r
145 #define TC0_ERROR_INT_XBAR_INST_NO (0U)\r
146 #define TC1_ERROR_INT_XBAR_INST_NO (0U)\r
147 \r
148 #else\r
149 #define EDMA3_CC_XFER_COMPLETION_INT (0U)\r
150 #define EDMA3_CC_ERROR_INT (0U)\r
151 #define CC_ERROR_INT_XBAR_INST_NO (0U)\r
152 #define EDMA3_TC0_ERROR_INT (0U)\r
153 #define EDMA3_TC1_ERROR_INT (0U)\r
154 #define TC0_ERROR_INT_XBAR_INST_NO (TC0_ERROR_INT_A15_XBAR_INST_NO)\r
155 #define TC1_ERROR_INT_XBAR_INST_NO (TC1_ERROR_INT_A15_XBAR_INST_NO)\r
156 #endif\r
157 \r
158 #define EDMA3_TC2_ERROR_INT (0U)\r
159 #define EDMA3_TC3_ERROR_INT (0U)\r
160 #define EDMA3_TC4_ERROR_INT (0U)\r
161 #define EDMA3_TC5_ERROR_INT (0U)\r
162 #define EDMA3_TC6_ERROR_INT (0U)\r
163 #define EDMA3_TC7_ERROR_INT (0U)\r
164 \r
165 #define DSP1_EDMA3_CC_XFER_COMPLETION_INT (19U)\r
166 #define DSP2_EDMA3_CC_XFER_COMPLETION_INT (20U)\r
167 #define DSP1_EDMA3_CC_ERROR_INT (27U)\r
168 #define DSP1_EDMA3_TC0_ERROR_INT (28U)\r
169 #define DSP1_EDMA3_TC1_ERROR_INT (29U)\r
170 \r
171 /** XBAR interrupt source index numbers for EDMA interrupts */\r
172 #define XBAR_EDMA_TPCC_IRQ_REGION0 (361U)\r
173 #define XBAR_EDMA_TPCC_IRQ_REGION1 (362U)\r
174 #define XBAR_EDMA_TPCC_IRQ_REGION2 (363U)\r
175 #define XBAR_EDMA_TPCC_IRQ_REGION3 (364U)\r
176 #define XBAR_EDMA_TPCC_IRQ_REGION4 (365U)\r
177 #define XBAR_EDMA_TPCC_IRQ_REGION5 (366U)\r
178 #define XBAR_EDMA_TPCC_IRQ_REGION6 (367U)\r
179 #define XBAR_EDMA_TPCC_IRQ_REGION7 (368U)\r
180 \r
181 #define XBAR_EDMA_TPCC_IRQ_ERR (359U)\r
182 #define XBAR_EDMA_TC0_IRQ_ERR (370U)\r
183 #define XBAR_EDMA_TC1_IRQ_ERR (371U)\r
184 \r
185 /**\r
186 * EDMA3 interrupts (transfer completion, CC error etc.) correspond to different\r
187 * ECM events (SoC specific). These ECM events come\r
188 * under ECM block XXX (handling those specific ECM events). Normally, block\r
189 * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events\r
190 * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)\r
191 * is mapped to a specific HWI_INT YYY in the tcf file.\r
192 * Define EDMA3_HWI_INT_XFER_COMP to specific HWI_INT, corresponding\r
193 * to transfer completion interrupt.\r
194 * Define EDMA3_HWI_INT_CC_ERR to specific HWI_INT, corresponding\r
195 * to CC error interrupts.\r
196 * Define EDMA3_HWI_INT_TC_ERR to specific HWI_INT, corresponding\r
197 * to TC error interrupts.\r
198 */\r
199 /* EDMA 0 */\r
200 \r
201 #define EDMA3_HWI_INT_XFER_COMP (7U)\r
202 #define EDMA3_HWI_INT_CC_ERR (7U)\r
203 #define EDMA3_HWI_INT_TC0_ERR (10U)\r
204 #define EDMA3_HWI_INT_TC1_ERR (10U)\r
205 #define EDMA3_HWI_INT_TC2_ERR (10U)\r
206 #define EDMA3_HWI_INT_TC3_ERR (10U)\r
207 \r
208 /**\r
209 * \brief Mapping of DMA channels 0-31 to Hardware Events from\r
210 * various peripherals, which use EDMA for data transfer.\r
211 * All channels need not be mapped, some can be free also.\r
212 * 1: Mapped\r
213 * 0: Not mapped (channel available)\r
214 *\r
215 * This mapping will be used to allocate DMA channels when user passes\r
216 * EDMA3_RM_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory\r
217 * copy). The same mapping is used to allocate the TCC when user passes\r
218 * EDMA3_RM_TCC_ANY as tcc id (for eg to do memory-to-memory copy).\r
219 *\r
220 * To allocate more DMA channels or TCCs, one has to modify the event mapping.\r
221 */\r
222 /* 31 0 */\r
223 #define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA (0x3FC0C06EU) /* TBD */\r
224 #define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_DSPEDMA (0x000FFFFFU) /* TBD */\r
225 #define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_EVEEDMA (0x00000000U) /* TBD */\r
226 \r
227 /**\r
228 * \brief Mapping of DMA channels 32-63 to Hardware Events from\r
229 * various peripherals, which use EDMA for data transfer.\r
230 * All channels need not be mapped, some can be free also.\r
231 * 1: Mapped\r
232 * 0: Not mapped (channel available)\r
233 *\r
234 * This mapping will be used to allocate DMA channels when user passes\r
235 * EDMA3_RM_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory\r
236 * copy). The same mapping is used to allocate the TCC when user passes\r
237 * EDMA3_RM_TCC_ANY as tcc id (for eg to do memory-to-memory copy).\r
238 *\r
239 * To allocate more DMA channels or TCCs, one has to modify the event mapping.\r
240 */\r
241 #define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA (0xF3FFFFFCU) /* TBD */\r
242 #define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_DSPEDMA (0x00000000U) /* TBD */\r
243 #define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_EVEEDMA (0x00000000U) /* TBD */\r
244 \r
245 \r
246 \r
247 \r
248 /**\r
249 * \brief Base address as seen from the different cores may be different\r
250 * And is defined based on the core\r
251 */\r
252 #if ((defined BUILD_TDA2XX_MPU) || (defined BUILD_TDA2XX_DSP))\r
253 #define EDMA3_CC_BASE_ADDR ((void *)(0x43300000))\r
254 #define EDMA3_TC0_BASE_ADDR ((void *)(0x43400000))\r
255 #define EDMA3_TC1_BASE_ADDR ((void *)(0x43500000))\r
256 #elif (defined BUILD_TDA2XX_IPU)\r
257 #define EDMA3_CC_BASE_ADDR ((void *)(0x63300000))\r
258 #define EDMA3_TC0_BASE_ADDR ((void *)(0x63400000))\r
259 #define EDMA3_TC1_BASE_ADDR ((void *)(0x63500000))\r
260 #elif (defined BUILD_TDA2XX_EVE)\r
261 #define EDMA3_CC_BASE_ADDR ((void *)(0x400A0000))\r
262 #define EDMA3_TC0_BASE_ADDR ((void *)(0x40086000))\r
263 #define EDMA3_TC1_BASE_ADDR ((void *)(0x40087000))\r
264 #else\r
265 #define EDMA3_CC_BASE_ADDR ((void *)(0x0))\r
266 #define EDMA3_TC0_BASE_ADDR ((void *)(0x0))\r
267 #define EDMA3_TC1_BASE_ADDR ((void *)(0x0))\r
268 #endif\r
269 \r
270 #define DSP1_EDMA3_CC_BASE_ADDR ((void *)(0x01D10000))\r
271 #define DSP1_EDMA3_TC0_BASE_ADDR ((void *)(0x01D05000))\r
272 #define DSP1_EDMA3_TC1_BASE_ADDR ((void *)(0x01D06000))\r
273 \r
274 /* Driver Object Initialization Configuration */\r
275 EDMA3_RM_GblConfigParams edma3GblCfgParams [NUM_EDMA3_INSTANCES] =\r
276 {\r
277 {\r
278 /* EDMA3 INSTANCE# 0 */\r
279 /** Total number of DMA Channels supported by the EDMA3 Controller */\r
280 EDMA3_NUM_DMA_CHANNELS,\r
281 /** Total number of QDMA Channels supported by the EDMA3 Controller */\r
282 EDMA3_NUM_QDMA_CHANNELS,\r
283 /** Total number of TCCs supported by the EDMA3 Controller */\r
284 EDMA3_NUM_TCC,\r
285 /** Total number of PaRAM Sets supported by the EDMA3 Controller */\r
286 EDMA3_NUM_PARAMSET,\r
287 /** Total number of Event Queues in the EDMA3 Controller */\r
288 EDMA3_NUM_EVTQUE,\r
289 /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller*/\r
290 EDMA3_NUM_TC,\r
291 /** Number of Regions on this EDMA3 controller */\r
292 EDMA3_NUM_REGIONS,\r
293 \r
294 /**\r
295 * \brief Channel mapping existence\r
296 * A value of 0 (No channel mapping) implies that there is fixed association\r
297 * for a channel number to a parameter entry number or, in other words,\r
298 * PaRAM entry n corresponds to channel n.\r
299 */\r
300 1U,\r
301 \r
302 /** Existence of memory protection feature */\r
303 0U,\r
304 \r
305 /** Global Register Region of CC Registers */\r
306 EDMA3_CC_BASE_ADDR,\r
307 /** Transfer Controller (TC) Registers */\r
308 {\r
309 EDMA3_TC0_BASE_ADDR,\r
310 EDMA3_TC1_BASE_ADDR,\r
311 (void *)NULL,\r
312 (void *)NULL,\r
313 (void *)NULL,\r
314 (void *)NULL,\r
315 (void *)NULL,\r
316 (void *)NULL\r
317 },\r
318 /** Interrupt no. for Transfer Completion */\r
319 EDMA3_CC_XFER_COMPLETION_INT,\r
320 /** Interrupt no. for CC Error */\r
321 EDMA3_CC_ERROR_INT,\r
322 /** Interrupt no. for TCs Error */\r
323 {\r
324 EDMA3_TC0_ERROR_INT,\r
325 EDMA3_TC1_ERROR_INT,\r
326 EDMA3_TC2_ERROR_INT,\r
327 EDMA3_TC3_ERROR_INT,\r
328 EDMA3_TC4_ERROR_INT,\r
329 EDMA3_TC5_ERROR_INT,\r
330 EDMA3_TC6_ERROR_INT,\r
331 EDMA3_TC7_ERROR_INT\r
332 },\r
333 \r
334 /**\r
335 * \brief EDMA3 TC priority setting\r
336 *\r
337 * User can program the priority of the Event Queues\r
338 * at a system-wide level. This means that the user can set the\r
339 * priority of an IO initiated by either of the TCs (Transfer Controllers)\r
340 * relative to IO initiated by the other bus masters on the\r
341 * device (ARM, DSP, USB, etc)\r
342 */\r
343 {\r
344 0U,\r
345 1U,\r
346 0U,\r
347 0U,\r
348 0U,\r
349 0U,\r
350 0U,\r
351 0U\r
352 },\r
353 /**\r
354 * \brief To Configure the Threshold level of number of events\r
355 * that can be queued up in the Event queues. EDMA3CC error register\r
356 * (CCERR) will indicate whether or not at any instant of time the\r
357 * number of events queued up in any of the event queues exceeds\r
358 * or equals the threshold/watermark value that is set\r
359 * in the queue watermark threshold register (QWMTHRA).\r
360 */\r
361 {\r
362 16U,\r
363 16U,\r
364 0U,\r
365 0U,\r
366 0U,\r
367 0U,\r
368 0U,\r
369 0U\r
370 },\r
371 \r
372 /**\r
373 * \brief To Configure the Default Burst Size (DBS) of TCs.\r
374 * An optimally-sized command is defined by the transfer controller\r
375 * default burst size (DBS). Different TCs can have different\r
376 * DBS values. It is defined in Bytes.\r
377 */\r
378 {\r
379 16U,\r
380 16U,\r
381 0U,\r
382 0U,\r
383 0U,\r
384 0U,\r
385 0U,\r
386 0U\r
387 },\r
388 \r
389 /**\r
390 * \brief Mapping from each DMA channel to a Parameter RAM set,\r
391 * if it exists, otherwise of no use.\r
392 */\r
393 {\r
394 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
395 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
396 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
397 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
398 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
399 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
400 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
401 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
402 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
403 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
404 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
405 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
406 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
407 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
408 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
409 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
410 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
411 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
412 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
413 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
414 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
415 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
416 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
417 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
418 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
419 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
420 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
421 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
422 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
423 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
424 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
425 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP\r
426 },\r
427 \r
428 /**\r
429 * \brief Mapping from each DMA channel to a TCC. This specific\r
430 * TCC code will be returned when the transfer is completed\r
431 * on the mapped channel.\r
432 */\r
433 {\r
434 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
435 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
436 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
437 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
438 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
439 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
440 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
441 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
442 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
443 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
444 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
445 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
446 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
447 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
448 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
449 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
450 },\r
451 \r
452 /**\r
453 * \brief Mapping of DMA channels to Hardware Events from\r
454 * various peripherals, which use EDMA for data transfer.\r
455 * All channels need not be mapped, some can be free also.\r
456 */\r
457 {\r
458 EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA,\r
459 EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA\r
460 }\r
461 },\r
462 {\r
463 /* EDMA3 INSTANCE# 1 */\r
464 /** Total number of DMA Channels supported by the EDMA3 Controller */\r
465 EDMA3_NUM_DMA_CHANNELS,\r
466 /** Total number of QDMA Channels supported by the EDMA3 Controller */\r
467 EDMA3_NUM_QDMA_CHANNELS,\r
468 /** Total number of TCCs supported by the EDMA3 Controller */\r
469 EDMA3_NUM_TCC,\r
470 /** Total number of PaRAM Sets supported by the EDMA3 Controller */\r
471 EDMA3_NUM_PARAMSET,\r
472 /** Total number of Event Queues in the EDMA3 Controller */\r
473 EDMA3_NUM_EVTQUE,\r
474 /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller*/\r
475 EDMA3_NUM_TC,\r
476 /** Number of Regions on this EDMA3 controller */\r
477 EDMA3_NUM_REGIONS,\r
478 \r
479 /**\r
480 * \brief Channel mapping existence\r
481 * A value of 0 (No channel mapping) implies that there is fixed association\r
482 * for a channel number to a parameter entry number or, in other words,\r
483 * PaRAM entry n corresponds to channel n.\r
484 */\r
485 1U,\r
486 \r
487 /** Existence of memory protection feature */\r
488 0U,\r
489 \r
490 /** Global Register Region of CC Registers */\r
491 DSP1_EDMA3_CC_BASE_ADDR,\r
492 /** Transfer Controller (TC) Registers */\r
493 {\r
494 DSP1_EDMA3_TC0_BASE_ADDR,\r
495 DSP1_EDMA3_TC1_BASE_ADDR,\r
496 (void *)NULL,\r
497 (void *)NULL,\r
498 (void *)NULL,\r
499 (void *)NULL,\r
500 (void *)NULL,\r
501 (void *)NULL\r
502 },\r
503 /** Interrupt no. for Transfer Completion */\r
504 DSP1_EDMA3_CC_XFER_COMPLETION_INT,\r
505 /** Interrupt no. for CC Error */\r
506 DSP1_EDMA3_CC_ERROR_INT,\r
507 /** Interrupt no. for TCs Error */\r
508 {\r
509 DSP1_EDMA3_TC0_ERROR_INT,\r
510 DSP1_EDMA3_TC1_ERROR_INT,\r
511 EDMA3_TC2_ERROR_INT,\r
512 EDMA3_TC3_ERROR_INT,\r
513 EDMA3_TC4_ERROR_INT,\r
514 EDMA3_TC5_ERROR_INT,\r
515 EDMA3_TC6_ERROR_INT,\r
516 EDMA3_TC7_ERROR_INT\r
517 },\r
518 \r
519 /**\r
520 * \brief EDMA3 TC priority setting\r
521 *\r
522 * User can program the priority of the Event Queues\r
523 * at a system-wide level. This means that the user can set the\r
524 * priority of an IO initiated by either of the TCs (Transfer Controllers)\r
525 * relative to IO initiated by the other bus masters on the\r
526 * device (ARM, DSP, USB, etc)\r
527 */\r
528 {\r
529 0U,\r
530 1U,\r
531 0U,\r
532 0U,\r
533 0U,\r
534 0U,\r
535 0U,\r
536 0U\r
537 },\r
538 /**\r
539 * \brief To Configure the Threshold level of number of events\r
540 * that can be queued up in the Event queues. EDMA3CC error register\r
541 * (CCERR) will indicate whether or not at any instant of time the\r
542 * number of events queued up in any of the event queues exceeds\r
543 * or equals the threshold/watermark value that is set\r
544 * in the queue watermark threshold register (QWMTHRA).\r
545 */\r
546 {\r
547 16U,\r
548 16U,\r
549 0U,\r
550 0U,\r
551 0U,\r
552 0U,\r
553 0U,\r
554 0U\r
555 },\r
556 \r
557 /**\r
558 * \brief To Configure the Default Burst Size (DBS) of TCs.\r
559 * An optimally-sized command is defined by the transfer controller\r
560 * default burst size (DBS). Different TCs can have different\r
561 * DBS values. It is defined in Bytes.\r
562 */\r
563 {\r
564 16U,\r
565 16U,\r
566 0U,\r
567 0U,\r
568 0U,\r
569 0U,\r
570 0U,\r
571 0U\r
572 },\r
573 \r
574 /**\r
575 * \brief Mapping from each DMA channel to a Parameter RAM set,\r
576 * if it exists, otherwise of no use.\r
577 */\r
578 {\r
579 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
580 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
581 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
582 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
583 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
584 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
585 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
586 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
587 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
588 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
589 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
590 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
591 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
592 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
593 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
594 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
595 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
596 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
597 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
598 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
599 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
600 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
601 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
602 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
603 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
604 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
605 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
606 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
607 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
608 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
609 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
610 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP\r
611 },\r
612 \r
613 /**\r
614 * \brief Mapping from each DMA channel to a TCC. This specific\r
615 * TCC code will be returned when the transfer is completed\r
616 * on the mapped channel.\r
617 */\r
618 {\r
619 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
620 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
621 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
622 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
623 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
624 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
625 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
626 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
627 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
628 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
629 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
630 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
631 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
632 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
633 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
634 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
635 },\r
636 \r
637 /**\r
638 * \brief Mapping of DMA channels to Hardware Events from\r
639 * various peripherals, which use EDMA for data transfer.\r
640 * All channels need not be mapped, some can be free also.\r
641 */\r
642 {\r
643 EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_DSPEDMA,\r
644 EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_DSPEDMA\r
645 }\r
646 },\r
647 {\r
648 /* EDMA3 INSTANCE# 2 */\r
649 /** Total number of DMA Channels supported by the EDMA3 Controller */\r
650 EDMA3_NUM_DMA_CHANNELS,\r
651 /** Total number of QDMA Channels supported by the EDMA3 Controller */\r
652 EDMA3_NUM_QDMA_CHANNELS,\r
653 /** Total number of TCCs supported by the EDMA3 Controller */\r
654 EDMA3_NUM_TCC,\r
655 /** Total number of PaRAM Sets supported by the EDMA3 Controller */\r
656 EDMA3_NUM_PARAMSET,\r
657 /** Total number of Event Queues in the EDMA3 Controller */\r
658 EDMA3_NUM_EVTQUE,\r
659 /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller*/\r
660 EDMA3_NUM_TC,\r
661 /** Number of Regions on this EDMA3 controller */\r
662 EDMA3_NUM_REGIONS,\r
663 \r
664 /**\r
665 * \brief Channel mapping existence\r
666 * A value of 0 (No channel mapping) implies that there is fixed association\r
667 * for a channel number to a parameter entry number or, in other words,\r
668 * PaRAM entry n corresponds to channel n.\r
669 */\r
670 1U,\r
671 \r
672 /** Existence of memory protection feature */\r
673 0U,\r
674 \r
675 /** Global Register Region of CC Registers */\r
676 EDMA3_CC_BASE_ADDR,\r
677 /** Transfer Controller (TC) Registers */\r
678 {\r
679 EDMA3_TC0_BASE_ADDR,\r
680 EDMA3_TC1_BASE_ADDR,\r
681 (void *)NULL,\r
682 (void *)NULL,\r
683 (void *)NULL,\r
684 (void *)NULL,\r
685 (void *)NULL,\r
686 (void *)NULL\r
687 },\r
688 /** Interrupt no. for Transfer Completion */\r
689 EDMA3_CC_XFER_COMPLETION_INT,\r
690 /** Interrupt no. for CC Error */\r
691 EDMA3_CC_ERROR_INT,\r
692 /** Interrupt no. for TCs Error */\r
693 {\r
694 EDMA3_TC0_ERROR_INT,\r
695 EDMA3_TC1_ERROR_INT,\r
696 EDMA3_TC2_ERROR_INT,\r
697 EDMA3_TC3_ERROR_INT,\r
698 EDMA3_TC4_ERROR_INT,\r
699 EDMA3_TC5_ERROR_INT,\r
700 EDMA3_TC6_ERROR_INT,\r
701 EDMA3_TC7_ERROR_INT\r
702 },\r
703 \r
704 /**\r
705 * \brief EDMA3 TC priority setting\r
706 *\r
707 * User can program the priority of the Event Queues\r
708 * at a system-wide level. This means that the user can set the\r
709 * priority of an IO initiated by either of the TCs (Transfer Controllers)\r
710 * relative to IO initiated by the other bus masters on the\r
711 * device (ARM, DSP, USB, etc)\r
712 */\r
713 {\r
714 0U,\r
715 1U,\r
716 0U,\r
717 0U,\r
718 0U,\r
719 0U,\r
720 0U,\r
721 0U\r
722 },\r
723 /**\r
724 * \brief To Configure the Threshold level of number of events\r
725 * that can be queued up in the Event queues. EDMA3CC error register\r
726 * (CCERR) will indicate whether or not at any instant of time the\r
727 * number of events queued up in any of the event queues exceeds\r
728 * or equals the threshold/watermark value that is set\r
729 * in the queue watermark threshold register (QWMTHRA).\r
730 */\r
731 {\r
732 16U,\r
733 16U,\r
734 0U,\r
735 0U,\r
736 0U,\r
737 0U,\r
738 0U,\r
739 0U\r
740 },\r
741 \r
742 /**\r
743 * \brief To Configure the Default Burst Size (DBS) of TCs.\r
744 * An optimally-sized command is defined by the transfer controller\r
745 * default burst size (DBS). Different TCs can have different\r
746 * DBS values. It is defined in Bytes.\r
747 */\r
748 {\r
749 16U,\r
750 16U,\r
751 0U,\r
752 0U,\r
753 0U,\r
754 0U,\r
755 0U,\r
756 0U\r
757 },\r
758 \r
759 /**\r
760 * \brief Mapping from each DMA channel to a Parameter RAM set,\r
761 * if it exists, otherwise of no use.\r
762 */\r
763 {\r
764 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
765 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
766 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
767 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
768 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
769 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
770 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
771 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
772 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
773 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
774 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
775 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
776 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
777 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
778 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
779 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
780 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
781 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
782 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
783 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
784 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
785 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
786 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
787 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
788 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
789 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
790 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
791 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
792 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
793 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
794 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
795 EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP\r
796 },\r
797 \r
798 /**\r
799 * \brief Mapping from each DMA channel to a TCC. This specific\r
800 * TCC code will be returned when the transfer is completed\r
801 * on the mapped channel.\r
802 */\r
803 {\r
804 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
805 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
806 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
807 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
808 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
809 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
810 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
811 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
812 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
813 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
814 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
815 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
816 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
817 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
818 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
819 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
820 },\r
821 \r
822 /**\r
823 * \brief Mapping of DMA channels to Hardware Events from\r
824 * various peripherals, which use EDMA for data transfer.\r
825 * All channels need not be mapped, some can be free also.\r
826 */\r
827 {\r
828 EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_EVEEDMA,\r
829 EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_EVEEDMA\r
830 }\r
831 },\r
832 \r
833 };\r
834 \r
835 /**\r
836 * \brief Resource splitting defines for Own/Reserved DMA/QDMA channels and TCCs\r
837 * For PaRAMs explicit defines are not present but should be replaced in the structure sampleInstInitConfig\r
838 * Default configuration has all resources owned by all cores and none reserved except for first 64 PaRAMs corrosponding to DMA channels\r
839 * Resources to be Split properly by application and rebuild the sample library to avoid resource conflict\r
840 *\r
841 * Only Resources owned by a perticular core are allocated by Driver\r
842 * Reserved resources are not allocated if requested for any available resource\r
843 */\r
844 \r
845 /* Default RM Instance Initialization Configuration */\r
846 EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][NUM_SHADOW_REGIONS] =\r
847 {\r
848 /* EDMA3 INSTANCE# 0 */\r
849 {\r
850 /* Resources owned/reserved by region 0 (Associated to MPU core 0)*/\r
851 {\r
852 /* ownPaRAMSets */\r
853 /* 31 0 63 32 95 64 127 96 */\r
854 {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
855 /* 159 128 191 160 223 192 255 224 */\r
856 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
857 /* 287 256 319 288 351 320 383 352 */\r
858 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
859 /* 415 384 447 416 479 448 511 480 */\r
860 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},\r
861 \r
862 /* ownDmaChannels */\r
863 /* 31 0 63 32 */\r
864 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
865 \r
866 /* ownQdmaChannels */\r
867 /* 31 0 */\r
868 {0x000000FFU},\r
869 \r
870 /* ownTccs */\r
871 /* 31 0 63 32 */\r
872 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
873 \r
874 /* resvdPaRAMSets */\r
875 /* 31 0 63 32 95 64 127 96 */\r
876 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
877 /* 159 128 191 160 223 192 255 224 */\r
878 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
879 /* 287 256 319 288 351 320 383 352 */\r
880 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
881 /* 415 384 447 416 479 448 511 480 */\r
882 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
883 \r
884 /* resvdDmaChannels */\r
885 /* 31 0 63 32 */\r
886 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA},\r
887 \r
888 /* resvdQdmaChannels */\r
889 /* 31 0 */\r
890 {0x00U},\r
891 \r
892 /* resvdTccs */\r
893 /* 31 0 63 32 */\r
894 {0x00U, 0x00U},\r
895 },\r
896 \r
897 /* Resources owned/reserved by region 1 (Associated to MPU core 1) */\r
898 {\r
899 /* ownPaRAMSets */\r
900 /* 31 0 63 32 95 64 127 96 */\r
901 {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
902 /* 159 128 191 160 223 192 255 224 */\r
903 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
904 /* 287 256 319 288 351 320 383 352 */\r
905 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
906 /* 415 384 447 416 479 448 511 480 */\r
907 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},\r
908 /* \r
909 * This instance 0 and region 1 is only accessible to MPU core 1.\r
910 * So other cores should not be access.\r
911 */\r
912 #ifdef BUILD_TDA2XX_MPU\r
913 /* ownDmaChannels */\r
914 /* 31 0 63 32 */\r
915 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
916 #else\r
917 /* ownDmaChannels */\r
918 /* 31 0 63 32 */\r
919 {0x00000000U, 0x00000000U},\r
920 #endif\r
921 /* ownQdmaChannels */\r
922 /* 31 0 */\r
923 {0x000000FFU},\r
924 \r
925 /* ownTccs */\r
926 /* 31 0 63 32 */\r
927 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
928 \r
929 /* resvdPaRAMSets */\r
930 /* 31 0 63 32 95 64 127 96 */\r
931 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
932 /* 159 128 191 160 223 192 255 224 */\r
933 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
934 /* 287 256 319 288 351 320 383 352 */\r
935 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
936 /* 415 384 447 416 479 448 511 480 */\r
937 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
938 \r
939 /* resvdDmaChannels */\r
940 /* 31 0 63 32 */\r
941 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA},\r
942 \r
943 /* resvdQdmaChannels */\r
944 /* 31 0 */\r
945 {0x00U},\r
946 \r
947 /* resvdTccs */\r
948 /* 31 0 63 32 */\r
949 {0x00U, 0x00U},\r
950 },\r
951 \r
952 /* Resources owned/reserved by region 2 (Associated to any DSP1)*/\r
953 {\r
954 /* ownPaRAMSets */\r
955 /* 31 0 63 32 95 64 127 96 */\r
956 {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
957 /* 159 128 191 160 223 192 255 224 */\r
958 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
959 /* 287 256 319 288 351 320 383 352 */\r
960 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
961 /* 415 384 447 416 479 448 511 480 */\r
962 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},\r
963 \r
964 /* ownDmaChannels */\r
965 /* 31 0 63 32 */\r
966 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
967 \r
968 /* ownQdmaChannels */\r
969 /* 31 0 */\r
970 {0x000000FFU},\r
971 \r
972 /* ownTccs */\r
973 /* 31 0 63 32 */\r
974 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
975 \r
976 /* resvdPaRAMSets */\r
977 /* 31 0 63 32 95 64 127 96 */\r
978 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
979 /* 159 128 191 160 223 192 255 224 */\r
980 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
981 /* 287 256 319 288 351 320 383 352 */\r
982 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
983 /* 415 384 447 416 479 448 511 480 */\r
984 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
985 \r
986 /* resvdDmaChannels */\r
987 /* 31 0 63 32 */\r
988 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA},\r
989 \r
990 /* resvdQdmaChannels */\r
991 /* 31 0 */\r
992 {0x00U},\r
993 \r
994 /* resvdTccs */\r
995 /* 31 0 63 32 */\r
996 {0x00U, 0x00U},\r
997 },\r
998 \r
999 /* Resources owned/reserved by region 3 (Associated to any DSP2)*/\r
1000 {\r
1001 /* ownPaRAMSets */\r
1002 /* 31 0 63 32 95 64 127 96 */\r
1003 {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1004 /* 159 128 191 160 223 192 255 224 */\r
1005 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1006 /* 287 256 319 288 351 320 383 352 */\r
1007 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1008 /* 415 384 447 416 479 448 511 480 */\r
1009 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},\r
1010 \r
1011 /* ownDmaChannels */\r
1012 /* 31 0 63 32 */\r
1013 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
1014 \r
1015 /* ownQdmaChannels */\r
1016 /* 31 0 */\r
1017 {0x000000FFU},\r
1018 \r
1019 /* ownTccs */\r
1020 /* 31 0 63 32 */\r
1021 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
1022 \r
1023 /* resvdPaRAMSets */\r
1024 /* 31 0 63 32 95 64 127 96 */\r
1025 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1026 /* 159 128 191 160 223 192 255 224 */\r
1027 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1028 /* 287 256 319 288 351 320 383 352 */\r
1029 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1030 /* 415 384 447 416 479 448 511 480 */\r
1031 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1032 \r
1033 /* resvdDmaChannels */\r
1034 /* 31 0 63 32 */\r
1035 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA},\r
1036 \r
1037 /* resvdQdmaChannels */\r
1038 /* 31 0 */\r
1039 {0x00U},\r
1040 \r
1041 /* resvdTccs */\r
1042 /* 31 0 63 32 */\r
1043 {0x00U, 0x00U},\r
1044 },\r
1045 \r
1046 /* Resources owned/reserved by region 4 (Associated to any IPU1 core 0)*/\r
1047 {\r
1048 /* ownPaRAMSets */\r
1049 /* 31 0 63 32 95 64 127 96 */\r
1050 {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1051 /* 159 128 191 160 223 192 255 224 */\r
1052 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1053 /* 287 256 319 288 351 320 383 352 */\r
1054 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1055 /* 415 384 447 416 479 448 511 480 */\r
1056 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},\r
1057 \r
1058 /* ownDmaChannels */\r
1059 /* 31 0 63 32 */\r
1060 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
1061 \r
1062 /* ownQdmaChannels */\r
1063 /* 31 0 */\r
1064 {0x000000FFU},\r
1065 \r
1066 /* ownTccs */\r
1067 /* 31 0 63 32 */\r
1068 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
1069 \r
1070 /* resvdPaRAMSets */\r
1071 /* 31 0 63 32 95 64 127 96 */\r
1072 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1073 /* 159 128 191 160 223 192 255 224 */\r
1074 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1075 /* 287 256 319 288 351 320 383 352 */\r
1076 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1077 /* 415 384 447 416 479 448 511 480 */\r
1078 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1079 \r
1080 /* resvdDmaChannels */\r
1081 /* 31 0 63 32 */\r
1082 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA},\r
1083 \r
1084 /* resvdQdmaChannels */\r
1085 /* 31 0 */\r
1086 {0x00U},\r
1087 \r
1088 /* resvdTccs */\r
1089 /* 31 0 63 32 */\r
1090 {0x00U, 0x00U},\r
1091 },\r
1092 \r
1093 /* Resources owned/reserved by region 5 (Associated to any IPU1 core 1)*/\r
1094 {\r
1095 /* ownPaRAMSets */\r
1096 /* 31 0 63 32 95 64 127 96 */\r
1097 {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1098 /* 159 128 191 160 223 192 255 224 */\r
1099 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1100 /* 287 256 319 288 351 320 383 352 */\r
1101 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1102 /* 415 384 447 416 479 448 511 480 */\r
1103 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},\r
1104 \r
1105 /* ownDmaChannels */\r
1106 /* 31 0 63 32 */\r
1107 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
1108 \r
1109 /* ownQdmaChannels */\r
1110 /* 31 0 */\r
1111 {0x000000FFU},\r
1112 \r
1113 /* ownTccs */\r
1114 /* 31 0 63 32 */\r
1115 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
1116 \r
1117 /* resvdPaRAMSets */\r
1118 /* 31 0 63 32 95 64 127 96 */\r
1119 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1120 /* 159 128 191 160 223 192 255 224 */\r
1121 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1122 /* 287 256 319 288 351 320 383 352 */\r
1123 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1124 /* 415 384 447 416 479 448 511 480 */\r
1125 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1126 \r
1127 /* resvdDmaChannels */\r
1128 /* 31 0 63 32 */\r
1129 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA},\r
1130 \r
1131 /* resvdQdmaChannels */\r
1132 /* 31 0 */\r
1133 {0x00U},\r
1134 \r
1135 /* resvdTccs */\r
1136 /* 31 0 63 32 */\r
1137 {0x00U, 0x00U},\r
1138 },\r
1139 \r
1140 /* Resources owned/reserved by region 6 (Associated to any IPU2 core 0)*/\r
1141 {\r
1142 /* ownPaRAMSets */\r
1143 /* 31 0 63 32 95 64 127 96 */\r
1144 {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1145 /* 159 128 191 160 223 192 255 224 */\r
1146 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1147 /* 287 256 319 288 351 320 383 352 */\r
1148 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1149 /* 415 384 447 416 479 448 511 480 */\r
1150 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},\r
1151 \r
1152 /* ownDmaChannels */\r
1153 /* 31 0 63 32 */\r
1154 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
1155 \r
1156 /* ownQdmaChannels */\r
1157 /* 31 0 */\r
1158 {0x000000FFU},\r
1159 \r
1160 /* ownTccs */\r
1161 /* 31 0 63 32 */\r
1162 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
1163 \r
1164 /* resvdPaRAMSets */\r
1165 /* 31 0 63 32 95 64 127 96 */\r
1166 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1167 /* 159 128 191 160 223 192 255 224 */\r
1168 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1169 /* 287 256 319 288 351 320 383 352 */\r
1170 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1171 /* 415 384 447 416 479 448 511 480 */\r
1172 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1173 \r
1174 /* resvdDmaChannels */\r
1175 /* 31 0 63 32 */\r
1176 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA},\r
1177 \r
1178 /* resvdQdmaChannels */\r
1179 /* 31 0 */\r
1180 {0x00U},\r
1181 \r
1182 /* resvdTccs */\r
1183 /* 31 0 63 32 */\r
1184 {0x00U, 0x00U},\r
1185 },\r
1186 \r
1187 /* Resources owned/reserved by region 7 (Associated to any IPU2 core 1)*/\r
1188 {\r
1189 /* ownPaRAMSets */\r
1190 /* 31 0 63 32 95 64 127 96 */\r
1191 {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1192 /* 159 128 191 160 223 192 255 224 */\r
1193 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1194 /* 287 256 319 288 351 320 383 352 */\r
1195 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1196 /* 415 384 447 416 479 448 511 480 */\r
1197 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},\r
1198 \r
1199 /* ownDmaChannels */\r
1200 /* 31 0 63 32 */\r
1201 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
1202 \r
1203 /* ownQdmaChannels */\r
1204 /* 31 0 */\r
1205 {0x000000FFU},\r
1206 \r
1207 /* ownTccs */\r
1208 /* 31 0 63 32 */\r
1209 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
1210 \r
1211 /* resvdPaRAMSets */\r
1212 /* 31 0 63 32 95 64 127 96 */\r
1213 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1214 /* 159 128 191 160 223 192 255 224 */\r
1215 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1216 /* 287 256 319 288 351 320 383 352 */\r
1217 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1218 /* 415 384 447 416 479 448 511 480 */\r
1219 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1220 \r
1221 /* resvdDmaChannels */\r
1222 /* 31 0 63 32 */\r
1223 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA},\r
1224 \r
1225 /* resvdQdmaChannels */\r
1226 /* 31 0 */\r
1227 {0x00U},\r
1228 \r
1229 /* resvdTccs */\r
1230 /* 31 0 63 32 */\r
1231 {0x00U, 0x00U},\r
1232 },\r
1233 },\r
1234 /* EDMA3 INSTANCE# 1 DSP1 EDMA*/\r
1235 {\r
1236 /* Resources owned/reserved by region 0 (Not Associated to any core supported)*/\r
1237 {\r
1238 /* ownPaRAMSets */\r
1239 /* 31 0 63 32 95 64 127 96 */\r
1240 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1241 /* 159 128 191 160 223 192 255 224 */\r
1242 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1243 /* 287 256 319 288 351 320 383 352 */\r
1244 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1245 /* 415 384 447 416 479 448 511 480 */\r
1246 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1247 \r
1248 /* ownDmaChannels */\r
1249 /* 31 0 63 32 */\r
1250 {0x00000000U, 0x00000000U},\r
1251 \r
1252 /* ownQdmaChannels */\r
1253 /* 31 0 */\r
1254 {0x00000000U},\r
1255 \r
1256 /* ownTccs */\r
1257 /* 31 0 63 32 */\r
1258 {0x00000000U, 0x00000000U},\r
1259 \r
1260 /* resvdPaRAMSets */\r
1261 /* 31 0 63 32 95 64 127 96 */\r
1262 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1263 /* 159 128 191 160 223 192 255 224 */\r
1264 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1265 /* 287 256 319 288 351 320 383 352 */\r
1266 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1267 /* 415 384 447 416 479 448 511 480 */\r
1268 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1269 \r
1270 /* resvdDmaChannels */\r
1271 /* 31 0 63 32 */\r
1272 {0x00000000U, 0x00000000U},\r
1273 \r
1274 /* resvdQdmaChannels */\r
1275 /* 31 0 */\r
1276 {0x00000000U},\r
1277 \r
1278 /* resvdTccs */\r
1279 /* 31 0 63 32 */\r
1280 {0x00000000U, 0x00000000U},\r
1281 },\r
1282 \r
1283 /* Resources owned/reserved by region 1 (Not Associated to any core supported) */\r
1284 {\r
1285 /* ownPaRAMSets */\r
1286 /* 31 0 63 32 95 64 127 96 */\r
1287 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1288 /* 159 128 191 160 223 192 255 224 */\r
1289 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1290 /* 287 256 319 288 351 320 383 352 */\r
1291 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1292 /* 415 384 447 416 479 448 511 480 */\r
1293 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1294 \r
1295 /* ownDmaChannels */\r
1296 /* 31 0 63 32 */\r
1297 {0x00000000U, 0x00000000U},\r
1298 \r
1299 /* ownQdmaChannels */\r
1300 /* 31 0 */\r
1301 {0x00000000U},\r
1302 \r
1303 /* ownTccs */\r
1304 /* 31 0 63 32 */\r
1305 {0x00000000U, 0x00000000U},\r
1306 \r
1307 /* resvdPaRAMSets */\r
1308 /* 31 0 63 32 95 64 127 96 */\r
1309 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1310 /* 159 128 191 160 223 192 255 224 */\r
1311 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1312 /* 287 256 319 288 351 320 383 352 */\r
1313 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1314 /* 415 384 447 416 479 448 511 480 */\r
1315 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1316 \r
1317 /* resvdDmaChannels */\r
1318 /* 31 0 63 32 */\r
1319 {0x00000000U, 0x00000000U},\r
1320 \r
1321 /* resvdQdmaChannels */\r
1322 /* 31 0 */\r
1323 {0x00000000U},\r
1324 \r
1325 /* resvdTccs */\r
1326 /* 31 0 63 32 */\r
1327 {0x00000000U, 0x00000000U},\r
1328 },\r
1329 \r
1330 /* Resources owned/reserved by region 2 (Associated to any DSP core 0)*/\r
1331 {\r
1332 /* ownPaRAMSets */\r
1333 /* 31 0 63 32 95 64 127 96 */\r
1334 {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1335 /* 159 128 191 160 223 192 255 224 */\r
1336 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1337 /* 287 256 319 288 351 320 383 352 */\r
1338 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1339 /* 415 384 447 416 479 448 511 480 */\r
1340 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},\r
1341 \r
1342 /* ownDmaChannels */\r
1343 /* 31 0 63 32 */\r
1344 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
1345 \r
1346 /* ownQdmaChannels */\r
1347 /* 31 0 */\r
1348 {0x000000FFU},\r
1349 \r
1350 /* ownTccs */\r
1351 /* 31 0 63 32 */\r
1352 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
1353 \r
1354 /* resvdPaRAMSets */\r
1355 /* 31 0 63 32 95 64 127 96 */\r
1356 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1357 /* 159 128 191 160 223 192 255 224 */\r
1358 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1359 /* 287 256 319 288 351 320 383 352 */\r
1360 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1361 /* 415 384 447 416 479 448 511 480 */\r
1362 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1363 \r
1364 /* resvdDmaChannels */\r
1365 /* 31 0 63 32 */\r
1366 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_DSPEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_DSPEDMA},\r
1367 \r
1368 /* resvdQdmaChannels */\r
1369 /* 31 0 */\r
1370 {0x00U},\r
1371 \r
1372 /* resvdTccs */\r
1373 /* 31 0 63 32 */\r
1374 {0x00U, 0x00U},\r
1375 },\r
1376 \r
1377 /* Resources owned/reserved by region 3 (Associated to any DSP core 1)*/\r
1378 {\r
1379 /* ownPaRAMSets */\r
1380 /* 31 0 63 32 95 64 127 96 */\r
1381 {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1382 /* 159 128 191 160 223 192 255 224 */\r
1383 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1384 /* 287 256 319 288 351 320 383 352 */\r
1385 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1386 /* 415 384 447 416 479 448 511 480 */\r
1387 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},\r
1388 \r
1389 /* ownDmaChannels */\r
1390 /* 31 0 63 32 */\r
1391 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
1392 \r
1393 /* ownQdmaChannels */\r
1394 /* 31 0 */\r
1395 {0x000000FFU},\r
1396 \r
1397 /* ownTccs */\r
1398 /* 31 0 63 32 */\r
1399 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
1400 \r
1401 /* resvdPaRAMSets */\r
1402 /* 31 0 63 32 95 64 127 96 */\r
1403 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1404 /* 159 128 191 160 223 192 255 224 */\r
1405 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1406 /* 287 256 319 288 351 320 383 352 */\r
1407 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1408 /* 415 384 447 416 479 448 511 480 */\r
1409 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1410 \r
1411 /* resvdDmaChannels */\r
1412 /* 31 0 63 32 */\r
1413 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_DSPEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_DSPEDMA},\r
1414 \r
1415 /* resvdQdmaChannels */\r
1416 /* 31 0 */\r
1417 {0x00U},\r
1418 \r
1419 /* resvdTccs */\r
1420 /* 31 0 63 32 */\r
1421 {0x00U, 0x00U},\r
1422 },\r
1423 \r
1424 /* Resources owned/reserved by region 4 (Not Associated to any core supported)*/\r
1425 {\r
1426 /* ownPaRAMSets */\r
1427 /* 31 0 63 32 95 64 127 96 */\r
1428 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1429 /* 159 128 191 160 223 192 255 224 */\r
1430 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1431 /* 287 256 319 288 351 320 383 352 */\r
1432 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1433 /* 415 384 447 416 479 448 511 480 */\r
1434 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1435 \r
1436 /* ownDmaChannels */\r
1437 /* 31 0 63 32 */\r
1438 {0x00000000U, 0x00000000U},\r
1439 \r
1440 /* ownQdmaChannels */\r
1441 /* 31 0 */\r
1442 {0x00000000U},\r
1443 \r
1444 /* ownTccs */\r
1445 /* 31 0 63 32 */\r
1446 {0x00000000U, 0x00000000U},\r
1447 \r
1448 /* resvdPaRAMSets */\r
1449 /* 31 0 63 32 95 64 127 96 */\r
1450 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1451 /* 159 128 191 160 223 192 255 224 */\r
1452 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1453 /* 287 256 319 288 351 320 383 352 */\r
1454 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1455 /* 415 384 447 416 479 448 511 480 */\r
1456 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1457 \r
1458 /* resvdDmaChannels */\r
1459 /* 31 0 63 32 */\r
1460 {0x00000000U, 0x00000000U},\r
1461 \r
1462 /* resvdQdmaChannels */\r
1463 /* 31 0 */\r
1464 {0x00000000U},\r
1465 \r
1466 /* resvdTccs */\r
1467 /* 31 0 63 32 */\r
1468 {0x00000000U, 0x00000000U},\r
1469 },\r
1470 \r
1471 /* Resources owned/reserved by region 5 (Not Associated to any core supported)*/\r
1472 {\r
1473 /* ownPaRAMSets */\r
1474 /* 31 0 63 32 95 64 127 96 */\r
1475 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1476 /* 159 128 191 160 223 192 255 224 */\r
1477 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1478 /* 287 256 319 288 351 320 383 352 */\r
1479 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1480 /* 415 384 447 416 479 448 511 480 */\r
1481 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1482 \r
1483 /* ownDmaChannels */\r
1484 /* 31 0 63 32 */\r
1485 {0x00000000U, 0x00000000U},\r
1486 \r
1487 /* ownQdmaChannels */\r
1488 /* 31 0 */\r
1489 {0x00000000U},\r
1490 \r
1491 /* ownTccs */\r
1492 /* 31 0 63 32 */\r
1493 {0x00000000U, 0x00000000U},\r
1494 \r
1495 /* resvdPaRAMSets */\r
1496 /* 31 0 63 32 95 64 127 96 */\r
1497 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1498 /* 159 128 191 160 223 192 255 224 */\r
1499 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1500 /* 287 256 319 288 351 320 383 352 */\r
1501 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1502 /* 415 384 447 416 479 448 511 480 */\r
1503 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1504 \r
1505 /* resvdDmaChannels */\r
1506 /* 31 0 63 32 */\r
1507 {0x00000000U, 0x00000000U},\r
1508 \r
1509 /* resvdQdmaChannels */\r
1510 /* 31 0 */\r
1511 {0x00000000U},\r
1512 \r
1513 /* resvdTccs */\r
1514 /* 31 0 63 32 */\r
1515 {0x00000000U, 0x00000000U},\r
1516 },\r
1517 \r
1518 /* Resources owned/reserved by region 6 (Not Associated to any core supported)*/\r
1519 {\r
1520 /* ownPaRAMSets */\r
1521 /* 31 0 63 32 95 64 127 96 */\r
1522 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1523 /* 159 128 191 160 223 192 255 224 */\r
1524 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1525 /* 287 256 319 288 351 320 383 352 */\r
1526 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1527 /* 415 384 447 416 479 448 511 480 */\r
1528 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1529 \r
1530 /* ownDmaChannels */\r
1531 /* 31 0 63 32 */\r
1532 {0x00000000U, 0x00000000U},\r
1533 \r
1534 /* ownQdmaChannels */\r
1535 /* 31 0 */\r
1536 {0x00000000U},\r
1537 \r
1538 /* ownTccs */\r
1539 /* 31 0 63 32 */\r
1540 {0x00000000U, 0x00000000U},\r
1541 \r
1542 /* resvdPaRAMSets */\r
1543 /* 31 0 63 32 95 64 127 96 */\r
1544 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1545 /* 159 128 191 160 223 192 255 224 */\r
1546 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1547 /* 287 256 319 288 351 320 383 352 */\r
1548 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1549 /* 415 384 447 416 479 448 511 480 */\r
1550 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1551 \r
1552 /* resvdDmaChannels */\r
1553 /* 31 0 63 32 */\r
1554 {0x00000000U, 0x00000000U},\r
1555 \r
1556 /* resvdQdmaChannels */\r
1557 /* 31 0 */\r
1558 {0x00000000U},\r
1559 \r
1560 /* resvdTccs */\r
1561 /* 31 0 63 32 */\r
1562 {0x00000000U, 0x00000000U},\r
1563 },\r
1564 \r
1565 /* Resources owned/reserved by region 7 (Not Associated to any core supported)*/\r
1566 {\r
1567 /* ownPaRAMSets */\r
1568 /* 31 0 63 32 95 64 127 96 */\r
1569 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1570 /* 159 128 191 160 223 192 255 224 */\r
1571 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1572 /* 287 256 319 288 351 320 383 352 */\r
1573 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1574 /* 415 384 447 416 479 448 511 480 */\r
1575 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1576 \r
1577 /* ownDmaChannels */\r
1578 /* 31 0 63 32 */\r
1579 {0x00000000U, 0x00000000U},\r
1580 \r
1581 /* ownQdmaChannels */\r
1582 /* 31 0 */\r
1583 {0x00000000U},\r
1584 \r
1585 /* ownTccs */\r
1586 /* 31 0 63 32 */\r
1587 {0x00000000U, 0x00000000U},\r
1588 \r
1589 /* resvdPaRAMSets */\r
1590 /* 31 0 63 32 95 64 127 96 */\r
1591 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1592 /* 159 128 191 160 223 192 255 224 */\r
1593 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1594 /* 287 256 319 288 351 320 383 352 */\r
1595 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1596 /* 415 384 447 416 479 448 511 480 */\r
1597 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1598 \r
1599 /* resvdDmaChannels */\r
1600 /* 31 0 63 32 */\r
1601 {0x00000000U, 0x00000000U},\r
1602 \r
1603 /* resvdQdmaChannels */\r
1604 /* 31 0 */\r
1605 {0x00000000U},\r
1606 \r
1607 /* resvdTccs */\r
1608 /* 31 0 63 32 */\r
1609 {0x00000000U, 0x00000000U},\r
1610 },\r
1611 },\r
1612 /* EDMA3 INSTANCE# 2 EVE EDMA*/\r
1613 {\r
1614 /* Resources owned/reserved by region 0 (Not Associated to any core supported)*/\r
1615 {\r
1616 /* ownPaRAMSets */\r
1617 /* 31 0 63 32 95 64 127 96 */\r
1618 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1619 /* 159 128 191 160 223 192 255 224 */\r
1620 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1621 /* 287 256 319 288 351 320 383 352 */\r
1622 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1623 /* 415 384 447 416 479 448 511 480 */\r
1624 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1625 \r
1626 /* ownDmaChannels */\r
1627 /* 31 0 63 32 */\r
1628 {0x00000000U, 0x00000000U},\r
1629 \r
1630 /* ownQdmaChannels */\r
1631 /* 31 0 */\r
1632 {0x00000000U},\r
1633 \r
1634 /* ownTccs */\r
1635 /* 31 0 63 32 */\r
1636 {0x00000000U, 0x00000000U},\r
1637 \r
1638 /* resvdPaRAMSets */\r
1639 /* 31 0 63 32 95 64 127 96 */\r
1640 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1641 /* 159 128 191 160 223 192 255 224 */\r
1642 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1643 /* 287 256 319 288 351 320 383 352 */\r
1644 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1645 /* 415 384 447 416 479 448 511 480 */\r
1646 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1647 \r
1648 /* resvdDmaChannels */\r
1649 /* 31 0 63 32 */\r
1650 {0x00000000U, 0x00000000U},\r
1651 \r
1652 /* resvdQdmaChannels */\r
1653 /* 31 0 */\r
1654 {0x00000000U},\r
1655 \r
1656 /* resvdTccs */\r
1657 /* 31 0 63 32 */\r
1658 {0x00000000U, 0x00000000U},\r
1659 },\r
1660 \r
1661 /* Resources owned/reserved by region 1 (Associated to any EVE core)*/\r
1662 {\r
1663 /* ownPaRAMSets */\r
1664 /* 31 0 63 32 95 64 127 96 */\r
1665 {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
1666 /* 159 128 191 160 223 192 255 224 */\r
1667 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1668 /* 287 256 319 288 351 320 383 352 */\r
1669 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1670 /* 415 384 447 416 479 448 511 480 */\r
1671 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,},\r
1672 \r
1673 /* ownDmaChannels */\r
1674 /* 31 0 63 32 */\r
1675 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
1676 \r
1677 /* ownQdmaChannels */\r
1678 /* 31 0 */\r
1679 {0x000000FFU},\r
1680 \r
1681 /* ownTccs */\r
1682 /* 31 0 63 32 */\r
1683 {0xFFFFFFFFU, 0xFFFFFFFFU},\r
1684 \r
1685 /* resvdPaRAMSets */\r
1686 /* 31 0 63 32 95 64 127 96 */\r
1687 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1688 /* 159 128 191 160 223 192 255 224 */\r
1689 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1690 /* 287 256 319 288 351 320 383 352 */\r
1691 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1692 /* 415 384 447 416 479 448 511 480 */\r
1693 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1694 \r
1695 /* resvdDmaChannels */\r
1696 /* 31 0 63 32 */\r
1697 {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_EVEEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_EVEEDMA},\r
1698 \r
1699 /* resvdQdmaChannels */\r
1700 /* 31 0 */\r
1701 {0x00U},\r
1702 \r
1703 /* resvdTccs */\r
1704 /* 31 0 63 32 */\r
1705 {0x00U, 0x00U},\r
1706 },\r
1707 \r
1708 /* Resources owned/reserved by region 2 (Not Associated to any core supported)*/\r
1709 {\r
1710 /* ownPaRAMSets */\r
1711 /* 31 0 63 32 95 64 127 96 */\r
1712 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1713 /* 159 128 191 160 223 192 255 224 */\r
1714 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1715 /* 287 256 319 288 351 320 383 352 */\r
1716 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1717 /* 415 384 447 416 479 448 511 480 */\r
1718 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1719 \r
1720 /* ownDmaChannels */\r
1721 /* 31 0 63 32 */\r
1722 {0x00000000U, 0x00000000U},\r
1723 \r
1724 /* ownQdmaChannels */\r
1725 /* 31 0 */\r
1726 {0x00000000U},\r
1727 \r
1728 /* ownTccs */\r
1729 /* 31 0 63 32 */\r
1730 {0x00000000U, 0x00000000U},\r
1731 \r
1732 /* resvdPaRAMSets */\r
1733 /* 31 0 63 32 95 64 127 96 */\r
1734 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1735 /* 159 128 191 160 223 192 255 224 */\r
1736 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1737 /* 287 256 319 288 351 320 383 352 */\r
1738 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1739 /* 415 384 447 416 479 448 511 480 */\r
1740 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1741 \r
1742 /* resvdDmaChannels */\r
1743 /* 31 0 63 32 */\r
1744 {0x00000000U, 0x00000000U},\r
1745 \r
1746 /* resvdQdmaChannels */\r
1747 /* 31 0 */\r
1748 {0x00000000U},\r
1749 \r
1750 /* resvdTccs */\r
1751 /* 31 0 63 32 */\r
1752 {0x00000000U, 0x00000000U},\r
1753 },\r
1754 \r
1755 /* Resources owned/reserved by region 3 (Not Associated to any core supported)*/\r
1756 {\r
1757 /* ownPaRAMSets */\r
1758 /* 31 0 63 32 95 64 127 96 */\r
1759 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1760 /* 159 128 191 160 223 192 255 224 */\r
1761 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1762 /* 287 256 319 288 351 320 383 352 */\r
1763 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1764 /* 415 384 447 416 479 448 511 480 */\r
1765 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1766 \r
1767 /* ownDmaChannels */\r
1768 /* 31 0 63 32 */\r
1769 {0x00000000U, 0x00000000U},\r
1770 \r
1771 /* ownQdmaChannels */\r
1772 /* 31 0 */\r
1773 {0x00000000U},\r
1774 \r
1775 /* ownTccs */\r
1776 /* 31 0 63 32 */\r
1777 {0x00000000U, 0x00000000U},\r
1778 \r
1779 /* resvdPaRAMSets */\r
1780 /* 31 0 63 32 95 64 127 96 */\r
1781 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1782 /* 159 128 191 160 223 192 255 224 */\r
1783 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1784 /* 287 256 319 288 351 320 383 352 */\r
1785 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1786 /* 415 384 447 416 479 448 511 480 */\r
1787 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1788 \r
1789 /* resvdDmaChannels */\r
1790 /* 31 0 63 32 */\r
1791 {0x00000000U, 0x00000000U},\r
1792 \r
1793 /* resvdQdmaChannels */\r
1794 /* 31 0 */\r
1795 {0x00000000U},\r
1796 \r
1797 /* resvdTccs */\r
1798 /* 31 0 63 32 */\r
1799 {0x00000000U, 0x00000000U},\r
1800 },\r
1801 \r
1802 /* Resources owned/reserved by region 4 (Not Associated to any core supported)*/\r
1803 {\r
1804 /* ownPaRAMSets */\r
1805 /* 31 0 63 32 95 64 127 96 */\r
1806 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1807 /* 159 128 191 160 223 192 255 224 */\r
1808 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1809 /* 287 256 319 288 351 320 383 352 */\r
1810 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1811 /* 415 384 447 416 479 448 511 480 */\r
1812 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1813 \r
1814 /* ownDmaChannels */\r
1815 /* 31 0 63 32 */\r
1816 {0x00000000U, 0x00000000U},\r
1817 \r
1818 /* ownQdmaChannels */\r
1819 /* 31 0 */\r
1820 {0x00000000U},\r
1821 \r
1822 /* ownTccs */\r
1823 /* 31 0 63 32 */\r
1824 {0x00000000U, 0x00000000U},\r
1825 \r
1826 /* resvdPaRAMSets */\r
1827 /* 31 0 63 32 95 64 127 96 */\r
1828 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1829 /* 159 128 191 160 223 192 255 224 */\r
1830 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1831 /* 287 256 319 288 351 320 383 352 */\r
1832 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1833 /* 415 384 447 416 479 448 511 480 */\r
1834 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1835 \r
1836 /* resvdDmaChannels */\r
1837 /* 31 0 63 32 */\r
1838 {0x00000000U, 0x00000000U},\r
1839 \r
1840 /* resvdQdmaChannels */\r
1841 /* 31 0 */\r
1842 {0x00000000U},\r
1843 \r
1844 /* resvdTccs */\r
1845 /* 31 0 63 32 */\r
1846 {0x00000000U, 0x00000000U},\r
1847 },\r
1848 \r
1849 /* Resources owned/reserved by region 5 (Not Associated to any core supported)*/\r
1850 {\r
1851 /* ownPaRAMSets */\r
1852 /* 31 0 63 32 95 64 127 96 */\r
1853 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1854 /* 159 128 191 160 223 192 255 224 */\r
1855 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1856 /* 287 256 319 288 351 320 383 352 */\r
1857 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1858 /* 415 384 447 416 479 448 511 480 */\r
1859 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1860 \r
1861 /* ownDmaChannels */\r
1862 /* 31 0 63 32 */\r
1863 {0x00000000U, 0x00000000U},\r
1864 \r
1865 /* ownQdmaChannels */\r
1866 /* 31 0 */\r
1867 {0x00000000U},\r
1868 \r
1869 /* ownTccs */\r
1870 /* 31 0 63 32 */\r
1871 {0x00000000U, 0x00000000U},\r
1872 \r
1873 /* resvdPaRAMSets */\r
1874 /* 31 0 63 32 95 64 127 96 */\r
1875 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1876 /* 159 128 191 160 223 192 255 224 */\r
1877 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1878 /* 287 256 319 288 351 320 383 352 */\r
1879 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1880 /* 415 384 447 416 479 448 511 480 */\r
1881 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1882 \r
1883 /* resvdDmaChannels */\r
1884 /* 31 0 63 32 */\r
1885 {0x00000000U, 0x00000000U},\r
1886 \r
1887 /* resvdQdmaChannels */\r
1888 /* 31 0 */\r
1889 {0x00000000U},\r
1890 \r
1891 /* resvdTccs */\r
1892 /* 31 0 63 32 */\r
1893 {0x00000000U, 0x00000000U},\r
1894 },\r
1895 \r
1896 /* Resources owned/reserved by region 6 (Not Associated to any core supported)*/\r
1897 {\r
1898 /* ownPaRAMSets */\r
1899 /* 31 0 63 32 95 64 127 96 */\r
1900 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1901 /* 159 128 191 160 223 192 255 224 */\r
1902 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1903 /* 287 256 319 288 351 320 383 352 */\r
1904 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1905 /* 415 384 447 416 479 448 511 480 */\r
1906 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1907 \r
1908 /* ownDmaChannels */\r
1909 /* 31 0 63 32 */\r
1910 {0x00000000U, 0x00000000U},\r
1911 \r
1912 /* ownQdmaChannels */\r
1913 /* 31 0 */\r
1914 {0x00000000U},\r
1915 \r
1916 /* ownTccs */\r
1917 /* 31 0 63 32 */\r
1918 {0x00000000U, 0x00000000U},\r
1919 \r
1920 /* resvdPaRAMSets */\r
1921 /* 31 0 63 32 95 64 127 96 */\r
1922 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1923 /* 159 128 191 160 223 192 255 224 */\r
1924 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1925 /* 287 256 319 288 351 320 383 352 */\r
1926 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1927 /* 415 384 447 416 479 448 511 480 */\r
1928 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1929 \r
1930 /* resvdDmaChannels */\r
1931 /* 31 0 63 32 */\r
1932 {0x00000000U, 0x00000000U},\r
1933 \r
1934 /* resvdQdmaChannels */\r
1935 /* 31 0 */\r
1936 {0x00000000U},\r
1937 \r
1938 /* resvdTccs */\r
1939 /* 31 0 63 32 */\r
1940 {0x00000000U, 0x00000000U},\r
1941 },\r
1942 \r
1943 /* Resources owned/reserved by region 7 (Not Associated to any core supported)*/\r
1944 {\r
1945 /* ownPaRAMSets */\r
1946 /* 31 0 63 32 95 64 127 96 */\r
1947 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1948 /* 159 128 191 160 223 192 255 224 */\r
1949 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1950 /* 287 256 319 288 351 320 383 352 */\r
1951 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1952 /* 415 384 447 416 479 448 511 480 */\r
1953 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1954 \r
1955 /* ownDmaChannels */\r
1956 /* 31 0 63 32 */\r
1957 {0x00000000U, 0x00000000U},\r
1958 \r
1959 /* ownQdmaChannels */\r
1960 /* 31 0 */\r
1961 {0x00000000U},\r
1962 \r
1963 /* ownTccs */\r
1964 /* 31 0 63 32 */\r
1965 {0x00000000U, 0x00000000U},\r
1966 \r
1967 /* resvdPaRAMSets */\r
1968 /* 31 0 63 32 95 64 127 96 */\r
1969 {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1970 /* 159 128 191 160 223 192 255 224 */\r
1971 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1972 /* 287 256 319 288 351 320 383 352 */\r
1973 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
1974 /* 415 384 447 416 479 448 511 480 */\r
1975 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
1976 \r
1977 /* resvdDmaChannels */\r
1978 /* 31 0 63 32 */\r
1979 {0x00000000U, 0x00000000U},\r
1980 \r
1981 /* resvdQdmaChannels */\r
1982 /* 31 0 */\r
1983 {0x00000000U},\r
1984 \r
1985 /* resvdTccs */\r
1986 /* 31 0 63 32 */\r
1987 {0x00000000U, 0x00000000U},\r
1988 },\r
1989 },\r
1990 };\r
1991 \r
1992 /* Driver Instance Cross bar event to channel map Initialization Configuration */\r
1993 EDMA3_RM_GblXbarToChanConfigParams defXbarChanInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
1994 {\r
1995 /* EDMA3 INSTANCE# 0 */\r
1996 {\r
1997 /* Event to channel map for region 0 */\r
1998 {\r
1999 {-1, -1, -1, -1, -1, -1, -1, -1,\r
2000 -1, -1, -1, -1, -1, -1, -1, -1,\r
2001 -1, -1, -1, -1, -1, -1, -1, -1,\r
2002 -1, -1, -1, -1, -1, -1, -1, -1,\r
2003 -1, -1, -1, -1, -1, -1, -1, -1,\r
2004 -1, -1, -1, -1, -1, -1, -1, -1,\r
2005 -1, -1, -1, -1, -1, -1, -1, -1,\r
2006 -1, -1, -1, -1, -1, -1, -1}\r
2007 },\r
2008 /* Event to channel map for region 1 */\r
2009 {\r
2010 {-1, -1, -1, -1, -1, -1, -1, -1,\r
2011 -1, -1, -1, -1, -1, -1, -1, -1,\r
2012 -1, -1, -1, -1, -1, -1, -1, -1,\r
2013 -1, -1, -1, -1, -1, -1, -1, -1,\r
2014 -1, -1, -1, -1, -1, -1, -1, -1,\r
2015 -1, -1, -1, -1, -1, -1, -1, -1,\r
2016 -1, -1, -1, -1, -1, -1, -1, -1,\r
2017 -1, -1, -1, -1, -1, -1, -1}\r
2018 },\r
2019 /* Event to channel map for region 2 */\r
2020 {\r
2021 {-1, -1, -1, -1, -1, -1, -1, -1,\r
2022 -1, -1, -1, -1, -1, -1, -1, -1,\r
2023 -1, -1, -1, -1, -1, -1, -1, -1,\r
2024 -1, -1, -1, -1, -1, -1, -1, -1,\r
2025 -1, -1, -1, -1, -1, -1, -1, -1,\r
2026 -1, -1, -1, -1, -1, -1, -1, -1,\r
2027 -1, -1, -1, -1, -1, -1, -1, -1,\r
2028 -1, -1, -1, -1, -1, -1, -1}\r
2029 },\r
2030 /* Event to channel map for region 3 */\r
2031 {\r
2032 {-1, -1, -1, -1, -1, -1, -1, -1,\r
2033 -1, -1, -1, -1, -1, -1, -1, -1,\r
2034 -1, -1, -1, -1, -1, -1, -1, -1,\r
2035 -1, -1, -1, -1, -1, -1, -1, -1,\r
2036 -1, -1, -1, -1, -1, -1, -1, -1,\r
2037 -1, -1, -1, -1, -1, -1, -1, -1,\r
2038 -1, -1, -1, -1, -1, -1, -1, -1,\r
2039 -1, -1, -1, -1, -1, -1, -1}\r
2040 },\r
2041 /* Event to channel map for region 4 */\r
2042 {\r
2043 {-1, -1, -1, -1, -1, -1, -1, -1,\r
2044 -1, -1, -1, -1, -1, -1, -1, -1,\r
2045 -1, -1, -1, -1, -1, -1, -1, -1,\r
2046 -1, -1, -1, -1, -1, -1, -1, -1,\r
2047 -1, -1, -1, -1, -1, -1, -1, -1,\r
2048 -1, -1, -1, -1, -1, -1, -1, -1,\r
2049 -1, -1, -1, -1, -1, -1, -1, -1,\r
2050 -1, -1, -1, -1, -1, -1, -1}\r
2051 },\r
2052 /* Event to channel map for region 5 */\r
2053 {\r
2054 {-1, -1, -1, -1, -1, -1, -1, -1,\r
2055 -1, -1, -1, -1, -1, -1, -1, -1,\r
2056 -1, -1, -1, -1, -1, -1, -1, -1,\r
2057 -1, -1, -1, -1, -1, -1, -1, -1,\r
2058 -1, -1, -1, -1, -1, -1, -1, -1,\r
2059 -1, -1, -1, -1, -1, -1, -1, -1,\r
2060 -1, -1, -1, -1, -1, -1, -1, -1,\r
2061 -1, -1, -1, -1, -1, -1, -1}\r
2062 },\r
2063 /* Event to channel map for region 6 */\r
2064 {\r
2065 {-1, -1, -1, -1, -1, -1, -1, -1,\r
2066 -1, -1, -1, -1, -1, -1, -1, -1,\r
2067 -1, -1, -1, -1, -1, -1, -1, -1,\r
2068 -1, -1, -1, -1, -1, -1, -1, -1,\r
2069 -1, -1, -1, -1, -1, -1, -1, -1,\r
2070 -1, -1, -1, -1, -1, -1, -1, -1,\r
2071 -1, -1, -1, -1, -1, -1, -1, -1,\r
2072 -1, -1, -1, -1, -1, -1, -1}\r
2073 },\r
2074 /* Event to channel map for region 7 */\r
2075 {\r
2076 {-1, -1, -1, -1, -1, -1, -1, -1,\r
2077 -1, -1, -1, -1, -1, -1, -1, -1,\r
2078 -1, -1, -1, -1, -1, -1, -1, -1,\r
2079 -1, -1, -1, -1, -1, -1, -1, -1,\r
2080 -1, -1, -1, -1, -1, -1, -1, -1,\r
2081 -1, -1, -1, -1, -1, -1, -1, -1,\r
2082 -1, -1, -1, -1, -1, -1, -1, -1,\r
2083 -1, -1, -1, -1, -1, -1, -1}\r
2084 },\r
2085 },\r
2086 \r
2087 /* EDMA3 INSTANCE# 1 */\r
2088 {\r
2089 /* Event to channel map for region 0 */\r
2090 {\r
2091 {-1, -1, -1, -1, -1, -1, -1, -1,\r
2092 -1, -1, -1, -1, -1, -1, -1, -1,\r
2093 -1, -1, -1, -1, -1, -1, -1, -1,\r
2094 -1, -1, -1, -1, -1, -1, -1, -1,\r
2095 -1, -1, -1, -1, -1, -1, -1, -1,\r
2096 -1, -1, -1, -1, -1, -1, -1, -1,\r
2097 -1, -1, -1, -1, -1, -1, -1, -1,\r
2098 -1, -1, -1, -1, -1, -1, -1}\r
2099 },\r
2100 /* Event to channel map for region 1 */\r
2101 {\r
2102 {-1, -1, -1, -1, -1, -1, -1, -1,\r
2103 -1, -1, -1, -1, -1, -1, -1, -1,\r
2104 -1, -1, -1, -1, -1, -1, -1, -1,\r
2105 -1, -1, -1, -1, -1, -1, -1, -1,\r
2106 -1, -1, -1, -1, -1, -1, -1, -1,\r
2107 -1, -1, -1, -1, -1, -1, -1, -1,\r
2108 -1, -1, -1, -1, -1, -1, -1, -1,\r
2109 -1, -1, -1, -1, -1, -1, -1}\r
2110 },\r
2111 /* Event to channel map for region 2 */\r
2112 {\r
2113 {-1, -1, -1, -1, -1, -1, -1, -1,\r
2114 -1, -1, -1, -1, -1, -1, -1, -1,\r
2115 -1, -1, -1, -1, -1, -1, -1, -1,\r
2116 -1, -1, -1, -1, -1, -1, -1, -1,\r
2117 -1, -1, -1, -1, -1, -1, -1, -1,\r
2118 -1, -1, -1, -1, -1, -1, -1, -1,\r
2119 -1, -1, -1, -1, -1, -1, -1, -1,\r
2120 -1, -1, -1, -1, -1, -1, -1}\r
2121 },\r
2122 /* Event to channel map for region 3 */\r
2123 {\r
2124 {-1, -1, -1, -1, -1, -1, -1, -1,\r
2125 -1, -1, -1, -1, -1, -1, -1, -1,\r
2126 -1, -1, -1, -1, -1, -1, -1, -1,\r
2127 -1, -1, -1, -1, -1, -1, -1, -1,\r
2128 -1, -1, -1, -1, -1, -1, -1, -1,\r
2129 -1, -1, -1, -1, -1, -1, -1, -1,\r
2130 -1, -1, -1, -1, -1, -1, -1, -1,\r
2131 -1, -1, -1, -1, -1, -1, -1}\r
2132 },\r
2133 /* Event to channel map for region 4 */\r
2134 {\r
2135 {-1, -1, -1, -1, -1, -1, -1, -1,\r
2136 -1, -1, -1, -1, -1, -1, -1, -1,\r
2137 -1, -1, -1, -1, -1, -1, -1, -1,\r
2138 -1, -1, -1, -1, -1, -1, -1, -1,\r
2139 -1, -1, -1, -1, -1, -1, -1, -1,\r
2140 -1, -1, -1, -1, -1, -1, -1, -1,\r
2141 -1, -1, -1, -1, -1, -1, -1, -1,\r
2142 -1, -1, -1, -1, -1, -1, -1}\r
2143 },\r
2144 /* Event to channel map for region 5 */\r
2145 {\r
2146 {-1, -1, -1, -1, -1, -1, -1, -1,\r
2147 -1, -1, -1, -1, -1, -1, -1, -1,\r
2148 -1, -1, -1, -1, -1, -1, -1, -1,\r
2149 -1, -1, -1, -1, -1, -1, -1, -1,\r
2150 -1, -1, -1, -1, -1, -1, -1, -1,\r
2151 -1, -1, -1, -1, -1, -1, -1, -1,\r
2152 -1, -1, -1, -1, -1, -1, -1, -1,\r
2153 -1, -1, -1, -1, -1, -1, -1}\r
2154 },\r
2155 /* Event to channel map for region 6 */\r
2156 {\r
2157 {-1, -1, -1, -1, -1, -1, -1, -1,\r
2158 -1, -1, -1, -1, -1, -1, -1, -1,\r
2159 -1, -1, -1, -1, -1, -1, -1, -1,\r
2160 -1, -1, -1, -1, -1, -1, -1, -1,\r
2161 -1, -1, -1, -1, -1, -1, -1, -1,\r
2162 -1, -1, -1, -1, -1, -1, -1, -1,\r
2163 -1, -1, -1, -1, -1, -1, -1, -1,\r
2164 -1, -1, -1, -1, -1, -1, -1}\r
2165 },\r
2166 /* Event to channel map for region 7 */\r
2167 {\r
2168 {-1, -1, -1, -1, -1, -1, -1, -1,\r
2169 -1, -1, -1, -1, -1, -1, -1, -1,\r
2170 -1, -1, -1, -1, -1, -1, -1, -1,\r
2171 -1, -1, -1, -1, -1, -1, -1, -1,\r
2172 -1, -1, -1, -1, -1, -1, -1, -1,\r
2173 -1, -1, -1, -1, -1, -1, -1, -1,\r
2174 -1, -1, -1, -1, -1, -1, -1, -1,\r
2175 -1, -1, -1, -1, -1, -1, -1}\r
2176 },\r
2177 },\r
2178 \r
2179 /* EDMA3 INSTANCE# 2 */\r
2180 {\r
2181 /* Event to channel map for region 0 */\r
2182 {\r
2183 {-1, -1, -1, -1, -1, -1, -1, -1,\r
2184 -1, -1, -1, -1, -1, -1, -1, -1,\r
2185 -1, -1, -1, -1, -1, -1, -1, -1,\r
2186 -1, -1, -1, -1, -1, -1, -1, -1,\r
2187 -1, -1, -1, -1, -1, -1, -1, -1,\r
2188 -1, -1, -1, -1, -1, -1, -1, -1,\r
2189 -1, -1, -1, -1, -1, -1, -1, -1,\r
2190 -1, -1, -1, -1, -1, -1, -1}\r
2191 },\r
2192 /* Event to channel map for region 1 */\r
2193 {\r
2194 {-1, -1, -1, -1, -1, -1, -1, -1,\r
2195 -1, -1, -1, -1, -1, -1, -1, -1,\r
2196 -1, -1, -1, -1, -1, -1, -1, -1,\r
2197 -1, -1, -1, -1, -1, -1, -1, -1,\r
2198 -1, -1, -1, -1, -1, -1, -1, -1,\r
2199 -1, -1, -1, -1, -1, -1, -1, -1,\r
2200 -1, -1, -1, -1, -1, -1, -1, -1,\r
2201 -1, -1, -1, -1, -1, -1, -1}\r
2202 },\r
2203 /* Event to channel map for region 2 */\r
2204 {\r
2205 {-1, -1, -1, -1, -1, -1, -1, -1,\r
2206 -1, -1, -1, -1, -1, -1, -1, -1,\r
2207 -1, -1, -1, -1, -1, -1, -1, -1,\r
2208 -1, -1, -1, -1, -1, -1, -1, -1,\r
2209 -1, -1, -1, -1, -1, -1, -1, -1,\r
2210 -1, -1, -1, -1, -1, -1, -1, -1,\r
2211 -1, -1, -1, -1, -1, -1, -1, -1,\r
2212 -1, -1, -1, -1, -1, -1, -1}\r
2213 },\r
2214 /* Event to channel map for region 3 */\r
2215 {\r
2216 {-1, -1, -1, -1, -1, -1, -1, -1,\r
2217 -1, -1, -1, -1, -1, -1, -1, -1,\r
2218 -1, -1, -1, -1, -1, -1, -1, -1,\r
2219 -1, -1, -1, -1, -1, -1, -1, -1,\r
2220 -1, -1, -1, -1, -1, -1, -1, -1,\r
2221 -1, -1, -1, -1, -1, -1, -1, -1,\r
2222 -1, -1, -1, -1, -1, -1, -1, -1,\r
2223 -1, -1, -1, -1, -1, -1, -1}\r
2224 },\r
2225 /* Event to channel map for region 4 */\r
2226 {\r
2227 {-1, -1, -1, -1, -1, -1, -1, -1,\r
2228 -1, -1, -1, -1, -1, -1, -1, -1,\r
2229 -1, -1, -1, -1, -1, -1, -1, -1,\r
2230 -1, -1, -1, -1, -1, -1, -1, -1,\r
2231 -1, -1, -1, -1, -1, -1, -1, -1,\r
2232 -1, -1, -1, -1, -1, -1, -1, -1,\r
2233 -1, -1, -1, -1, -1, -1, -1, -1,\r
2234 -1, -1, -1, -1, -1, -1, -1}\r
2235 },\r
2236 /* Event to channel map for region 5 */\r
2237 {\r
2238 {-1, -1, -1, -1, -1, -1, -1, -1,\r
2239 -1, -1, -1, -1, -1, -1, -1, -1,\r
2240 -1, -1, -1, -1, -1, -1, -1, -1,\r
2241 -1, -1, -1, -1, -1, -1, -1, -1,\r
2242 -1, -1, -1, -1, -1, -1, -1, -1,\r
2243 -1, -1, -1, -1, -1, -1, -1, -1,\r
2244 -1, -1, -1, -1, -1, -1, -1, -1,\r
2245 -1, -1, -1, -1, -1, -1, -1}\r
2246 },\r
2247 /* Event to channel map for region 6 */\r
2248 {\r
2249 {-1, -1, -1, -1, -1, -1, -1, -1,\r
2250 -1, -1, -1, -1, -1, -1, -1, -1,\r
2251 -1, -1, -1, -1, -1, -1, -1, -1,\r
2252 -1, -1, -1, -1, -1, -1, -1, -1,\r
2253 -1, -1, -1, -1, -1, -1, -1, -1,\r
2254 -1, -1, -1, -1, -1, -1, -1, -1,\r
2255 -1, -1, -1, -1, -1, -1, -1, -1,\r
2256 -1, -1, -1, -1, -1, -1, -1}\r
2257 },\r
2258 /* Event to channel map for region 7 */\r
2259 {\r
2260 {-1, -1, -1, -1, -1, -1, -1, -1,\r
2261 -1, -1, -1, -1, -1, -1, -1, -1,\r
2262 -1, -1, -1, -1, -1, -1, -1, -1,\r
2263 -1, -1, -1, -1, -1, -1, -1, -1,\r
2264 -1, -1, -1, -1, -1, -1, -1, -1,\r
2265 -1, -1, -1, -1, -1, -1, -1, -1,\r
2266 -1, -1, -1, -1, -1, -1, -1, -1,\r
2267 -1, -1, -1, -1, -1, -1, -1}\r
2268 },\r
2269 }\r
2270 };\r
2271 \r
2272 /* End of File */\r
2273 \r
2274 \r
2275 \r