1 /*******************************************************************************\r
2 **+--------------------------------------------------------------------------+**\r
3 **| **** |**\r
4 **| **** |**\r
5 **| ******o*** |**\r
6 **| ********_///_**** |**\r
7 **| ***** /_//_/ **** |**\r
8 **| ** ** (__/ **** |**\r
9 **| ********* |**\r
10 **| **** |**\r
11 **| *** |**\r
12 **| |**\r
13 **| Copyright (c) 1998-2006 Texas Instruments Incorporated |**\r
14 **| ALL RIGHTS RESERVED |**\r
15 **| |**\r
16 **| Permission is hereby granted to licensees of Texas Instruments |**\r
17 **| Incorporated (TI) products to use this computer program for the sole |**\r
18 **| purpose of implementing a licensee product based on TI products. |**\r
19 **| No other rights to reproduce, use, or disseminate this computer |**\r
20 **| program, whether in part or in whole, are granted. |**\r
21 **| |**\r
22 **| TI makes no representation or warranties with respect to the |**\r
23 **| performance of this computer program, and specifically disclaims |**\r
24 **| any responsibility for any damages, special or consequential, |**\r
25 **| connected with the use of this program. |**\r
26 **| |**\r
27 **+--------------------------------------------------------------------------+**\r
28 *******************************************************************************/\r
29 \r
30 /** \file edma3resmgr.h\r
31 \brief EDMA3 Resource Manager Internal header file.\r
32 \r
33 This file contains implementation specific details used by the RM internally\r
34 \r
35 (C) Copyright 2006, Texas Instruments, Inc\r
36 \r
37 */\r
38 \r
39 #ifndef _EDMA3_RES_MGR_H_\r
40 #define _EDMA3_RES_MGR_H_\r
41 \r
42 \r
43 /** Include Resource Manager header file */\r
44 #include <ti/sdo/edma3/rm/edma3_rm.h>\r
45 \r
46 /* For the EDMA3 Register Layer functionality. */\r
47 #include <ti/sdo/edma3/rm/src/edma3_rl_cc.h>\r
48 #include <ti/sdo/edma3/rm/src/edma3_rl_tc.h>\r
49 \r
50 #ifdef __cplusplus\r
51 extern "C" {\r
52 #endif\r
53 \r
54 /**\r
55 * Number of PaRAM Sets actually present on the SoC. This will be updated\r
56 * while creating the Resource Manager Object.\r
57 */\r
58 extern unsigned int edma3NumPaRAMSets;\r
59 \r
60 \r
61 /** Define for setting all bits of the EDMA3 Controller Registers */\r
62 #define EDMA3_RM_SET_ALL_BITS (0xFFFFFFFFu)\r
63 \r
64 /* Other Mask defines */\r
65 /** DCHMAP-PaRAMEntry bitfield Clear */\r
66 #define EDMA3_RM_DCH_PARAM_CLR_MASK (~EDMA3_CCRL_DCHMAP_PAENTRY_MASK)\r
67 /** DCHMAP-PaRAMEntry bitfield Set */\r
68 #define EDMA3_RM_DCH_PARAM_SET_MASK(paRAMId) (((EDMA3_CCRL_DCHMAP_PAENTRY_MASK >> EDMA3_CCRL_DCHMAP_PAENTRY_SHIFT) & (paRAMId)) << EDMA3_CCRL_DCHMAP_PAENTRY_SHIFT)\r
69 /** QCHMAP-PaRAMEntry bitfield Clear */\r
70 #define EDMA3_RM_QCH_PARAM_CLR_MASK (~EDMA3_CCRL_QCHMAP_PAENTRY_MASK)\r
71 /** QCHMAP-PaRAMEntry bitfield Set */\r
72 #define EDMA3_RM_QCH_PARAM_SET_MASK(paRAMId) (((EDMA3_CCRL_QCHMAP_PAENTRY_MASK >> EDMA3_CCRL_QCHMAP_PAENTRY_SHIFT) & (paRAMId)) << EDMA3_CCRL_QCHMAP_PAENTRY_SHIFT)\r
73 /** QCHMAP-TrigWord bitfield Clear */\r
74 #define EDMA3_RM_QCH_TRWORD_CLR_MASK (~EDMA3_CCRL_QCHMAP_TRWORD_MASK)\r
75 /** QCHMAP-TrigWord bitfield Set */\r
76 #define EDMA3_RM_QCH_TRWORD_SET_MASK(paRAMId) (((EDMA3_CCRL_QCHMAP_TRWORD_MASK >> EDMA3_CCRL_QCHMAP_TRWORD_SHIFT) & (paRAMId)) << EDMA3_CCRL_QCHMAP_TRWORD_SHIFT)\r
77 /** QUEPRI bits Clear */\r
78 #define EDMA3_RM_QUEPRI_CLR_MASK(queNum) (~(EDMA3_CCRL_QUEPRI_PRIQ0_MASK << ((queNum) * EDMA3_CCRL_QUEPRI_PRIQ1_SHIFT)))\r
79 /** QUEPRI bits Set */\r
80 #define EDMA3_RM_QUEPRI_SET_MASK(queNum,quePri) ((EDMA3_CCRL_QUEPRI_PRIQ0_MASK & (quePri)) << ((queNum) * EDMA3_CCRL_QUEPRI_PRIQ1_SHIFT))\r
81 /** QUEWMTHR bits Clear */\r
82 #define EDMA3_RM_QUEWMTHR_CLR_MASK(queNum) (~(EDMA3_CCRL_QWMTHRA_Q0_MASK << ((queNum) * EDMA3_CCRL_QWMTHRA_Q1_SHIFT)))\r
83 /** QUEWMTHR bits Set */\r
84 #define EDMA3_RM_QUEWMTHR_SET_MASK(queNum,queThr) ((EDMA3_CCRL_QWMTHRA_Q0_MASK & (queThr)) << ((queNum) * EDMA3_CCRL_QWMTHRA_Q1_SHIFT))\r
85 \r
86 /** OPT-TCC bitfield Clear */\r
87 #define EDMA3_RM_OPT_TCC_CLR_MASK (~EDMA3_CCRL_OPT_TCC_MASK)\r
88 /** OPT-TCC bitfield Set */\r
89 #define EDMA3_RM_OPT_TCC_SET_MASK(tcc) (((EDMA3_CCRL_OPT_TCC_MASK >> EDMA3_CCRL_OPT_TCC_SHIFT) & (tcc)) << EDMA3_CCRL_OPT_TCC_SHIFT)\r
90 \r
91 /** PaRAM Set Entry for Link and B count Reload field */\r
92 #define EDMA3_RM_PARAM_ENTRY_LINK_BCNTRLD (5u)\r
93 \r
94 \r
95 /**\r
96 * \defgroup Edma3ResMgrInt Internal Interface Definition for Resource Manager\r
97 *\r
98 * Documentation of the Internal Interface of Resource Manager\r
99 *\r
100 * @{\r
101 */\r
102 \r
103 \r
104 /**\r
105 * \defgroup Edma3ResMgrIntObjMaint Object Maintenance\r
106 *\r
107 * Maintenance of the EDMA3 Resource Manager Object\r
108 *\r
109 * @{\r
110 */\r
111 \r
112 \r
113 /** To maintain the state of the EDMA3 Resource Manager Object */\r
114 typedef enum {\r
115 /** Object deleted */\r
116 EDMA3_RM_DELETED = 0,\r
117 /** Obect Created */\r
118 EDMA3_RM_CREATED = 1,\r
119 /** Object Opened */\r
120 EDMA3_RM_OPENED = 2,\r
121 /** Object Closed */\r
122 EDMA3_RM_CLOSED = 3\r
123 } EDMA3_RM_ObjState;\r
124 \r
125 \r
126 \r
127 /**\r
128 * \defgroup Edma3RMIntBoundVals Boundary Values\r
129 *\r
130 * Boundary Values for Logical Channel Ranges\r
131 *\r
132 * @{\r
133 */\r
134 /** Max of DMA Channels */\r
135 #define EDMA3_RM_DMA_CH_MAX_VAL (EDMA3_MAX_DMA_CH - 1u)\r
136 \r
137 /** Min of Link Channels */\r
138 #define EDMA3_RM_LINK_CH_MIN_VAL (EDMA3_MAX_DMA_CH)\r
139 \r
140 /** Max of Link Channels */\r
141 #define EDMA3_RM_LINK_CH_MAX_VAL (EDMA3_MAX_DMA_CH + EDMA3_MAX_PARAM_SETS - 1u)\r
142 \r
143 /** Min of QDMA Channels */\r
144 #define EDMA3_RM_QDMA_CH_MIN_VAL (EDMA3_MAX_DMA_CH + EDMA3_MAX_PARAM_SETS)\r
145 \r
146 /** Max of QDMA Channels */\r
147 #define EDMA3_RM_QDMA_CH_MAX_VAL (EDMA3_MAX_DMA_CH + EDMA3_MAX_PARAM_SETS + EDMA3_MAX_QDMA_CH - 1u)\r
148 \r
149 /** Max of Logical Channels */\r
150 #define EDMA3_RM_LOG_CH_MAX_VAL (EDMA3_RM_QDMA_CH_MAX_VAL)\r
151 \r
152 \r
153 \r
154 /* @} Edma3RMIntBoundVals */\r
155 \r
156 \r
157 \r
158 \r
159 \r
160 /**\r
161 * \brief EDMA3 Hardware Instance Configuration Structure.\r
162 *\r
163 * Used to maintain information of the EDMA3 HW configuration.\r
164 * One such storage exists for each instance of the EDMA 3 HW.\r
165 */\r
166 typedef struct\r
167 {\r
168 /** HW Instance Id of the EDMA3 Controller */\r
169 unsigned int phyCtrllerInstId;\r
170 \r
171 /** State information of the Resource Manager object */\r
172 EDMA3_RM_ObjState state;\r
173 \r
174 /** Number of active opens of RM Instances */\r
175 unsigned int numOpens;\r
176 \r
177 /**\r
178 * \brief Init-time Configuration structure for EDMA3\r
179 * controller, to provide Global SoC specific Information.\r
180 *\r
181 * This configuration will can be provided by the user at run-time,\r
182 * while calling EDMA3_RM_create().\r
183 */\r
184 EDMA3_RM_GblConfigParams gblCfgParams;\r
185 \r
186 } EDMA3_RM_Obj;\r
187 \r
188 \r
189 /**\r
190 * \brief EDMA3 RM Instance Specific Configuration Structure.\r
191 *\r
192 * Used to maintain information of the EDMA3 Res Mgr instances.\r
193 * One such storage exists for each instance of the EDMA3 Res Mgr.\r
194 *\r
195 * Maximum EDMA3_MAX_RM_INSTANCES instances are allowed for\r
196 * each EDMA3 hardware instance, for same or different shadow regions.\r
197 */\r
198 typedef struct\r
199 {\r
200 /**\r
201 * Configuration such as region id, IsMaster, Callback function\r
202 * This configuration is passed to the "Open" API.\r
203 * For a single EDMA3 HW controller, there can be EDMA3_MAX_REGIONS\r
204 * different instances tied to different regions.\r
205 */\r
206 EDMA3_RM_Param initParam;\r
207 \r
208 /** Pointer to appropriate Shadow Register region of CC Registers */\r
209 EDMA3_CCRL_ShadowRegs *shadowRegs;\r
210 \r
211 /**\r
212 * Pointer to the EDMA3 RM Object (HW specific)\r
213 * opened by RM instance.\r
214 */\r
215 EDMA3_RM_Obj *pResMgrObjHandle;\r
216 \r
217 /** Available DMA Channels to the RM Instance */\r
218 unsigned int avlblDmaChannels[EDMA3_MAX_DMA_CHAN_DWRDS];\r
219 \r
220 /** Available QDMA Channels to the RM Instance */\r
221 unsigned int avlblQdmaChannels[EDMA3_MAX_QDMA_CHAN_DWRDS];\r
222 \r
223 /** Available PaRAM Sets to the RM Instance */\r
224 unsigned int avlblPaRAMSets[EDMA3_MAX_PARAM_DWRDS];\r
225 \r
226 /** Available TCCs to the RM Instance */\r
227 unsigned int avlblTccs[EDMA3_MAX_TCC_DWRDS];\r
228 \r
229 /**\r
230 * Sometimes, PaRAM clearing is not required for some particular RM\r
231 * Instances. In that case, PaRAM Sets allocated will NOT be cleared before\r
232 * allocating to any particular user. It is the responsibility of user\r
233 * to program it accordingly, without assuming anything for a specific\r
234 * field because the PaRAM Set might contain junk values. Not programming\r
235 * it fully might result in erroneous behavior.\r
236 * On the other hand, RM instances can also use this variable to get the\r
237 * PaRAM Sets cleared before allocating them to the specific user.\r
238 * User can program only the selected fields in this case.\r
239 *\r
240 * Value '0' : PaRAM Sets will NOT be cleared during their allocation.\r
241 * Value '1' : PaRAM Sets will be cleared during their allocation.\r
242 *\r
243 * This value can be modified using the IOCTL commands.\r
244 */\r
245 unsigned int paramInitRequired;\r
246 \r
247 /**\r
248 * Sometimes, global EDMA3 registers (DCHMAP/QCHMAP) and PaRAM Sets should\r
249 * not be modified during EDMA3_RM_allocLogicalChannel (), for some particular RM\r
250 * Instances. In that case, it is the responsibility of user\r
251 * to program them accordingly, when needed, without assuming anything because\r
252 * they might contain junk values. Not programming\r
253 * the registers/PaRAMs fully might result in erroneous behavior.\r
254 * On the other hand, RM instances can also use this variable to get the\r
255 * global registers and PaRAM Sets minimally programmed before allocating them to\r
256 * the specific user.\r
257 * User can program only the remaining fields in this case.\r
258 *\r
259 * Value '0' : EDMA3 registers (DCHMAP/QCHMAP) and PaRAM Sets will NOT be programmed during their allocation.\r
260 * Value '1' : EDMA3 registers (DCHMAP/QCHMAP) and PaRAM Sets will be programmed during their allocation.\r
261 *\r
262 * This value can be modified using the IOCTL commands.\r
263 */\r
264 unsigned int regModificationRequired;\r
265 \r
266 }EDMA3_RM_Instance;\r
267 \r
268 /* @} Edma3ResMgrIntObjMaint */\r
269 \r
270 \r
271 /**\r
272 * \brief EDMA3 Channel-Bound resources.\r
273 *\r
274 * Used to maintain information of the EDMA3 resources\r
275 * (specifically Parameter RAM set and TCC), bound to the\r
276 * particular channel within EDMA3_RM_allocLogicalChannel ().\r
277 */\r
278 typedef struct {\r
279 /** PaRAM Set number associated with the particular channel */\r
280 int paRAMId;\r
281 \r
282 /** TCC associated with the particular channel */\r
283 unsigned int tcc;\r
284 } EDMA3_RM_ChBoundResources;\r
285 \r
286 \r
287 /**\r
288 * \brief TCC Callback - Caters to channel specific status reporting.\r
289 */\r
290 typedef struct {\r
291 /** Callback function */\r
292 EDMA3_RM_TccCallback tccCb;\r
293 \r
294 /** Callback data, passed to the Callback function */\r
295 void *cbData;\r
296 } EDMA3_RM_TccCallbackParams;\r
297 \r
298 \r
299 /* @} Edma3ResMgrInt */\r
300 \r
301 #ifdef __cplusplus\r
302 }\r
303 #endif /* extern "C" */\r
304 \r
305 #endif /* _EDMA3_RES_MGR_H_ */\r