/* * edma3_tda2xx_cfg.c * * EDMA3 Driver Adaptation Configuration File (Soc Specific) for OMAPL138. * * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ * * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * */ #include #define NUM_SHADOW_REGIONS (8U) /* Number of EDMA3 controllers present in the system */ #define NUM_EDMA3_INSTANCES 1U /** Number of PaRAM Sets available */ #define EDMA3_NUM_PARAMSET (512U) /** Number of TCCS available */ #define EDMA3_NUM_TCC (64U) /** Number of DMA Channels available */ #define EDMA3_NUM_DMA_CHANNELS (64U) /** Number of QDMA Channels available */ #define EDMA3_NUM_QDMA_CHANNELS (8U) /** Number of Event Queues available */ #define EDMA3_0_NUM_EVTQUE (4U) /** Number of Transfer Controllers available */ #define EDMA3_0_NUM_TC (4U) /** Number of Regions */ #define EDMA3_0_NUM_REGIONS (2U) /** Interrupt no. for Transfer Completion */ #define EDMA3_0_CC_XFER_COMPLETION_INT (34U) /** Interrupt no. for CC Error */ #define EDMA3_0_CC_ERROR_INT (35U) /** Interrupt no. for TCs Error */ #define EDMA3_0_TC0_ERROR_INT (36U) #define EDMA3_0_TC1_ERROR_INT (37U) #define EDMA3_0_TC2_ERROR_INT (0U) #define EDMA3_0_TC3_ERROR_INT (0U) #define EDMA3_0_TC4_ERROR_INT (0U) #define EDMA3_0_TC5_ERROR_INT (0U) #define EDMA3_0_TC6_ERROR_INT (0U) #define EDMA3_0_TC7_ERROR_INT (0U) /** XBAR interrupt source index numbers for EDMA interrupts */ #define XBAR_EDMA_TPCC_IRQ_REGION0 (361U) #define XBAR_EDMA_TPCC_IRQ_REGION1 (362U) #define XBAR_EDMA_TPCC_IRQ_REGION2 (363U) #define XBAR_EDMA_TPCC_IRQ_REGION3 (364U) #define XBAR_EDMA_TPCC_IRQ_REGION4 (365U) #define XBAR_EDMA_TPCC_IRQ_REGION5 (366U) #define XBAR_EDMA_TPCC_IRQ_REGION6 (367U) #define XBAR_EDMA_TPCC_IRQ_REGION7 (368U) #define XBAR_EDMA_TPCC_IRQ_ERR (359U) #define XBAR_EDMA_TC0_IRQ_ERR (370U) #define XBAR_EDMA_TC1_IRQ_ERR (371U) /** * \brief Mapping of DMA channels 0-31 to Hardware Events from * various peripherals, which use EDMA for data transfer. * All channels need not be mapped, some can be free also. * 1: Mapped * 0: Not mapped * * This mapping will be used to allocate DMA channels when user passes * EDMA3_RM_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory * copy). The same mapping is used to allocate the TCC when user passes * EDMA3_RM_TCC_ANY as tcc id (for eg to do memory-to-memory copy). * * To allocate more DMA channels or TCCs, one has to modify the event mapping. */ /* 31 0 */ #define DMA_CHANNEL_TO_EVENT_MAPPING_0_0 (0x00000000U) /** * \brief Mapping of DMA channels 32-63 to Hardware Events from * various peripherals, which use EDMA for data transfer. * All channels need not be mapped, some can be free also. * 1: Mapped * 0: Not mapped * * This mapping will be used to allocate DMA channels when user passes * EDMA3_RM_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory * copy). The same mapping is used to allocate the TCC when user passes * EDMA3_RM_TCC_ANY as tcc id (for eg to do memory-to-memory copy). * * To allocate more DMA channels or TCCs, one has to modify the event mapping. */ #define DMA_CHANNEL_TO_EVENT_MAPPING_0_1 (0x00000000U) /** * \brief Base address as seen from the different cores may be different * And is defined based on the core */ #define EDMA3_CC_BASE_ADDR ((void *)(0x43300000)) #define EDMA3_TC0_BASE_ADDR ((void *)(0x43400000)) #define EDMA3_TC1_BASE_ADDR ((void *)(0x43500000)) EDMA3_RM_GblConfigParams edma3GblCfgParams [EDMA3_MAX_EDMA3_INSTANCES] = { /* EDMA3 INSTANCE# 0 */ { /** Total number of DMA Channels supported by the EDMA3 Controller */ EDMA3_NUM_DMA_CHANNELS, /** Total number of QDMA Channels supported by the EDMA3 Controller */ EDMA3_NUM_QDMA_CHANNELS, /** Total number of TCCs supported by the EDMA3 Controller */ EDMA3_NUM_TCC, /** Total number of PaRAM Sets supported by the EDMA3 Controller */ EDMA3_NUM_PARAMSET, /** Total number of Event Queues in the EDMA3 Controller */ EDMA3_0_NUM_EVTQUE, /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */ EDMA3_0_NUM_TC, /** Number of Regions on this EDMA3 controller */ EDMA3_0_NUM_REGIONS, /** * \brief Channel mapping existence * A value of 0 (No channel mapping) implies that there is fixed association * for a channel number to a parameter entry number or, in other words, * PaRAM entry n corresponds to channel n. */ 0U, /** Existence of memory protection feature */ 0U, /** Global Register Region of CC Registers */ EDMA3_CC_BASE_ADDR, /** Transfer Controller (TC) Registers */ { EDMA3_TC0_BASE_ADDR, EDMA3_TC1_BASE_ADDR, (void *)NULL, (void *)NULL, (void *)NULL, (void *)NULL, (void *)NULL, (void *)NULL }, /** Interrupt no. for Transfer Completion */ EDMA3_0_CC_XFER_COMPLETION_INT, /** Interrupt no. for CC Error */ EDMA3_0_CC_ERROR_INT, /** Interrupt no. for TCs Error */ { EDMA3_0_TC0_ERROR_INT, EDMA3_0_TC1_ERROR_INT, EDMA3_0_TC2_ERROR_INT, EDMA3_0_TC3_ERROR_INT, EDMA3_0_TC4_ERROR_INT, EDMA3_0_TC5_ERROR_INT, EDMA3_0_TC6_ERROR_INT, EDMA3_0_TC7_ERROR_INT }, /** * \brief EDMA3 TC priority setting * * User can program the priority of the Event Queues * at a system-wide level. This means that the user can set the * priority of an IO initiated by either of the TCs (Transfer Controllers) * relative to IO initiated by the other bus masters on the * device (ARM, DSP, USB, etc) */ { 0U, 1U, 2U, 3U, 0U, 0U, 0U, 0U }, /** * \brief To Configure the Threshold level of number of events * that can be queued up in the Event queues. EDMA3CC error register * (CCERR) will indicate whether or not at any instant of time the * number of events queued up in any of the event queues exceeds * or equals the threshold/watermark value that is set * in the queue watermark threshold register (QWMTHRA). */ { 16U, 16U, 16U, 16U, 0U, 0U, 0U, 0U }, /** * \brief To Configure the Default Burst Size (DBS) of TCs. * An optimally-sized command is defined by the transfer controller * default burst size (DBS). Different TCs can have different * DBS values. It is defined in Bytes. */ { 16U, 16U, 16U, 16U, 0U, 0U, 0U, 0U }, /** * \brief Mapping from each DMA channel to a Parameter RAM set, * if it exists, otherwise of no use. */ { 0U, 1U, 2U, 3U, 4U, 5U, 6U, 7U, 8U, 9U, 10U, 11U, 12U, 13U, 14U, 15U, 16U, 17U, 18U, 19U, 20U, 21U, 22U, 23U, 24U, 25U, 26U, 27U, 28U, 29U, 30U, 31U, 32U, 33U, 34U, 35U, 36U, 37U, 38U, 39U, 40U, 41U, 42U, 43U, 44U, 45U, 46U, 47U, 48U, 49U, 50U, 51U, 52U, 53U, 54U, 55U, 56U, 57U, 58U, 59U, 60U, 61U, 62U, 63U }, /** * \brief Mapping from each DMA channel to a TCC. This specific * TCC code will be returned when the transfer is completed * on the mapped channel. */ { 0U, 1U, 2U, 3U, 4U, 5U, 6U, 7U, 8U, 9U, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, 12U, 13U, 14U, 15U, 16U, 17U, 18U, 19U, 20U, 21U, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, 24U, 25U, 26U, 27U, 28U, 29U, 30U, 31U, 32U, 33U, 34U, 35U, 36U, 37U, 38U, 39U, 40U, 41U, 42U, 43U, 44U, 45U, 46U, 47U, 48U, 49U, 50U, 51U, 52U, 53U, 54U, 55U, 56U, 57U, 58U, 59U, 60U, 61U, 62U, 63U }, /** * \brief Mapping of DMA channels to Hardware Events from * various peripherals, which use EDMA for data transfer. * All channels need not be mapped, some can be free also. */ { DMA_CHANNEL_TO_EVENT_MAPPING_0_0, DMA_CHANNEL_TO_EVENT_MAPPING_0_1 } }, }; /* Default RM Instance Initialization Configuration */ EDMA3_RM_InstanceInitConfig defInstInitConfig [EDMA3_MAX_EDMA3_INSTANCES][NUM_SHADOW_REGIONS] = { /* EDMA3 INSTANCE# 0 */ { /* Resources owned/reserved by region 0 (Associated to any MPU core)*/ { /* ownPaRAMSets */ /* 31 0 63 32 95 64 127 96 */ {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, /* 159 128 191 160 223 192 255 224 */ 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, /* 287 256 319 288 351 320 383 352 */ 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, /* 415 384 447 416 479 448 511 480 */ 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU}, /* ownDmaChannels */ /* 31 0 63 32 */ {0xFFFFFFFFU, 0xFFFFFFFFU}, /* ownQdmaChannels */ /* 31 0 */ {0x000000FFU}, /* ownTccs */ /* 31 0 63 32 */ {0xFFFFFFFFU, 0xFFFFFFFFU}, /* resvdPaRAMSets */ /* 31 0 63 32 95 64 127 96 */ {0xFFFFFFFFU, 0xFFFFFFFFU, 0x00000000U, 0x00000000U, /* 159 128 191 160 223 192 255 224 */ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U, /* 287 256 319 288 351 320 383 352 */ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U, /* 415 384 447 416 479 448 511 480 */ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U}, /* resvdDmaChannels */ /* 31 0 63 32 */ {0x00U, 0x00U}, /* resvdQdmaChannels */ /* 31 0 */ {0x00U}, /* resvdTccs */ /* 31 0 63 32 */ {0x00U, 0x00U}, }, /* Resources owned/reserved by region 1 (Associated to any DSP core) */ { /* ownPaRAMSets */ /* 31 0 63 32 95 64 127 96 */ {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, /* 159 128 191 160 223 192 255 224 */ 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, /* 287 256 319 288 351 320 383 352 */ 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, /* 415 384 447 416 479 448 511 480 */ 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU}, /* ownDmaChannels */ /* 31 0 63 32 */ {0xFFFFFFFFU, 0xFFFFFFFFU}, /* ownQdmaChannels */ /* 31 0 */ {0x000000FFU}, /* ownTccs */ /* 31 0 63 32 */ {0xFFFFFFFFU, 0xFFFFFFFFU}, /* resvdPaRAMSets */ /* 31 0 63 32 95 64 127 96 */ {0xFFFFFFFFU, 0xFFFFFFFFU, 0x00000000U, 0x00000000U, /* 159 128 191 160 223 192 255 224 */ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U, /* 287 256 319 288 351 320 383 352 */ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U, /* 415 384 447 416 479 448 511 480 */ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U}, /* resvdDmaChannels */ /* 31 0 63 32 */ {0x00U, 0x00U}, /* resvdQdmaChannels */ /* 31 0 */ {0x00U}, /* resvdTccs */ /* 31 0 63 32 */ {0x00U, 0x00U}, }, /* Resources owned/reserved by region 2 (Associated to any IPU0 core)*/ { /* ownPaRAMSets */ /* 31 0 63 32 95 64 127 96 */ {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, /* 159 128 191 160 223 192 255 224 */ 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, /* 287 256 319 288 351 320 383 352 */ 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, /* 415 384 447 416 479 448 511 480 */ 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU}, /* ownDmaChannels */ /* 31 0 63 32 */ {0xFFFFFFFFU, 0xFFFFFFFFU}, /* ownQdmaChannels */ /* 31 0 */ {0x000000FFU}, /* ownTccs */ /* 31 0 63 32 */ {0xFFFFFFFFU, 0xFFFFFFFFU}, /* resvdPaRAMSets */ /* 31 0 63 32 95 64 127 96 */ {0xFFFFFFFFU, 0xFFFFFFFFU, 0x00000000U, 0x00000000U, /* 159 128 191 160 223 192 255 224 */ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U, /* 287 256 319 288 351 320 383 352 */ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U, /* 415 384 447 416 479 448 511 480 */ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U}, /* resvdDmaChannels */ /* 31 0 63 32 */ {0x00U, 0x00U}, /* resvdQdmaChannels */ /* 31 0 */ {0x00U}, /* resvdTccs */ /* 31 0 63 32 */ {0x00U, 0x00U}, }, /* Resources owned/reserved by region 3 (Associated to any IPU1 core)*/ { /* ownPaRAMSets */ /* 31 0 63 32 95 64 127 96 */ {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, /* 159 128 191 160 223 192 255 224 */ 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, /* 287 256 319 288 351 320 383 352 */ 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, /* 415 384 447 416 479 448 511 480 */ 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU}, /* ownDmaChannels */ /* 31 0 63 32 */ {0xFFFFFFFFU, 0xFFFFFFFFU}, /* ownQdmaChannels */ /* 31 0 */ {0x000000FFU}, /* ownTccs */ /* 31 0 63 32 */ {0xFFFFFFFFU, 0xFFFFFFFFU}, /* resvdPaRAMSets */ /* 31 0 63 32 95 64 127 96 */ {0xFFFFFFFFU, 0xFFFFFFFFU, 0x00000000U, 0x00000000U, /* 159 128 191 160 223 192 255 224 */ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U, /* 287 256 319 288 351 320 383 352 */ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U, /* 415 384 447 416 479 448 511 480 */ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U}, /* resvdDmaChannels */ /* 31 0 63 32 */ {0x00U, 0x00U}, /* resvdQdmaChannels */ /* 31 0 */ {0x00U}, /* resvdTccs */ /* 31 0 63 32 */ {0x00U, 0x00U}, }, /* Resources owned/reserved by region 4 (Not Associated to any core supported)*/ { /* ownPaRAMSets */ /* 31 0 63 32 95 64 127 96 */ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U, /* 159 128 191 160 223 192 255 224 */ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U, /* 287 256 319 288 351 320 383 352 */ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U, /* 415 384 447 416 479 448 511 480 */ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U}, /* ownDmaChannels */ /* 31 0 63 32 */ {0x00000000U, 0x00000000U}, /* ownQdmaChannels */ /* 31 0 */ {0x00000000U}, /* ownTccs */ /* 31 0 63 32 */ {0x00000000U, 0x00000000U}, /* resvdPaRAMSets */ /* 31 0 63 32 95 64 127 96 */ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U, /* 159 128 191 160 223 192 255 224 */ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U, /* 287 256 319 288 351 320 383 352 */ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U, /* 415 384 447 416 479 448 511 480 */ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U}, /* resvdDmaChannels */ /* 31 0 63 32 */ {0x00000000U, 0x00000000U}, /* resvdQdmaChannels */ /* 31 0 */ {0x00000000U}, /* resvdTccs */ /* 31 0 63 32 */ {0x00000000U, 0x00000000U}, }, /* Resources owned/reserved by region 5 (Not Associated to any core supported)*/ { /* ownPaRAMSets */ /* 31 0 63 32 95 64 127 96 */ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U, /* 159 128 191 160 223 192 255 224 */ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U, /* 287 256 319 288 351 320 383 352 */ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U, /* 415 384 447 416 479 448 511 480 */ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U}, /* ownDmaChannels */ /* 31 0 63 32 */ {0x00000000U, 0x00000000U}, /* ownQdmaChannels */ /* 31 0 */ {0x00000000U}, /* ownTccs */ /* 31 0 63 32 */ {0x00000000U, 0x00000000U}, /* resvdPaRAMSets */ /* 31 0 63 32 95 64 127 96 */ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U, /* 159 128 191 160 223 192 255 224 */ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U, /* 287 256 319 288 351 320 383 352 */ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U, /* 415 384 447 416 479 448 511 480 */ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U}, /* resvdDmaChannels */ /* 31 0 63 32 */ {0x00000000U, 0x00000000U}, /* resvdQdmaChannels */ /* 31 0 */ {0x00000000U}, /* resvdTccs */ /* 31 0 63 32 */ {0x00000000U, 0x00000000U}, }, /* Resources owned/reserved by region 6 (Not Associated to any core supported)*/ { /* ownPaRAMSets */ /* 31 0 63 32 95 64 127 96 */ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U, /* 159 128 191 160 223 192 255 224 */ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U, /* 287 256 319 288 351 320 383 352 */ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U, /* 415 384 447 416 479 448 511 480 */ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U}, /* ownDmaChannels */ /* 31 0 63 32 */ {0x00000000U, 0x00000000U}, /* ownQdmaChannels */ /* 31 0 */ {0x00000000U}, /* ownTccs */ /* 31 0 63 32 */ {0x00000000U, 0x00000000U}, /* resvdPaRAMSets */ /* 31 0 63 32 95 64 127 96 */ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U, /* 159 128 191 160 223 192 255 224 */ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U, /* 287 256 319 288 351 320 383 352 */ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U, /* 415 384 447 416 479 448 511 480 */ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U}, /* resvdDmaChannels */ /* 31 0 63 32 */ {0x00000000U, 0x00000000U}, /* resvdQdmaChannels */ /* 31 0 */ {0x00000000U}, /* resvdTccs */ /* 31 0 63 32 */ {0x00000000U, 0x00000000U}, }, /* Resources owned/reserved by region 7 (Not Associated to any core supported)*/ { /* ownPaRAMSets */ /* 31 0 63 32 95 64 127 96 */ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U, /* 159 128 191 160 223 192 255 224 */ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U, /* 287 256 319 288 351 320 383 352 */ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U, /* 415 384 447 416 479 448 511 480 */ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U}, /* ownDmaChannels */ /* 31 0 63 32 */ {0x00000000U, 0x00000000U}, /* ownQdmaChannels */ /* 31 0 */ {0x00000000U}, /* ownTccs */ /* 31 0 63 32 */ {0x00000000U, 0x00000000U}, /* resvdPaRAMSets */ /* 31 0 63 32 95 64 127 96 */ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U, /* 159 128 191 160 223 192 255 224 */ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U, /* 287 256 319 288 351 320 383 352 */ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U, /* 415 384 447 416 479 448 511 480 */ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U}, /* resvdDmaChannels */ /* 31 0 63 32 */ {0x00000000U, 0x00000000U}, /* resvdQdmaChannels */ /* 31 0 */ {0x00000000U}, /* resvdTccs */ /* 31 0 63 32 */ {0x00000000U, 0x00000000U}, }, }, }; /* Driver Instance Cross bar event to channel map Initialization Configuration */ EDMA3_RM_GblXbarToChanConfigParams defXbarChanInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = { /* EDMA3 INSTANCE# 0 */ { /* Event to channel map for region 0 */ { {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1} }, /* Event to channel map for region 1 */ { {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1} }, /* Event to channel map for region 2 */ { {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1} }, /* Event to channel map for region 3 */ { {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1} }, /* Event to channel map for region 4 */ { {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1} }, /* Event to channel map for region 5 */ { {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1} }, /* Event to channel map for region 6 */ { {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1} }, /* Event to channel map for region 7 */ { {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1} }, } }; /* End of File */