diff --git a/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_legacyhal.h b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_legacyhal.h
+++ /dev/null
@@ -1,9689 +0,0 @@
-/*\r
- * Copyright 2001 by Texas Instruments Incorporated.\r
- * All rights reserved. Property of Texas Instruments Incorporated.\r
- * Restricted rights to use, duplicate or disclose this code are\r
- * granted through contract.\r
- * \r
- */\r
-/* "@(#) DSP/BIOS 4.60.22 12-07-01 (barracuda-j15)" */\r
-/******************************************************************************\\r
-* Copyright (C) 2000 Texas Instruments Incorporated.\r
-* All Rights Reserved\r
-*------------------------------------------------------------------------------\r
-* FILENAME...... csl_legacyhal.h\r
-* DATE CREATED.. 09/01/2000\r
-* LAST MODIFIED. 03/08/2002\r
-\******************************************************************************/\r
-#ifndef _CSL_LEGACYHAL_H_\r
-#define _CSL_LEGACYHAL_H_\r
-\r
-#include "csl_stdinc.h"\r
-#include "csl_chiphal.h"\r
-\r
-/*----------------------------------------------------------------------------*/\r
-/* Legacy HAL support macro definitions */\r
-/*----------------------------------------------------------------------------*/\r
- #define _VALUEOF(x) ((Uint32)(x))\r
-\r
-#ifndef UNREFERENCED_PARAMETER\r
- #define UNREFERENCED_PARAMETER(P) ((P)=(P))\r
-#endif\r
-\r
-#ifndef REG32\r
- #define REG32(addr) (*(volatile unsigned int*)(addr))\r
- #define REG16(addr) (*(volatile unsigned short*)(addr))\r
- #define REG8(addr) (*(volatile unsigned char*)(addr))\r
-#endif\r
-\r
-/* memory mapped register macros */\r
-#define HFIELD_GET(RegAddr,FIELD) (Uint32)( \\r
- (REG32(RegAddr)&##FIELD##_MASK)>>##FIELD##_SHIFT \\r
-)\r
-\r
-#define HFIELD_SET(RegAddr,FIELD,Val) REG32(RegAddr)=(Uint32)( \\r
- (REG32(RegAddr)&~##FIELD##_MASK)| \\r
- (((Uint32)(Val)<<##FIELD##_SHIFT)&##FIELD##_MASK) \\r
-)\r
-\r
-#define HFIELD_SHIFT(FIELD,Val) \\r
- (((Uint32)(Val)<<##FIELD##_SHIFT)&##FIELD##_MASK)\r
-\r
-#define HREG32_GET(RegAddr) \\r
- (Uint32)REG32(RegAddr)\r
-\r
-#define HREG32_SET(RegAddr,Val) \\r
- REG32(RegAddr)=(Uint32)(Val)\r
-\r
-/* control register macros */\r
-#define HCRFIELD_GET(CRREG,FIELD) (Uint32)( \\r
- (((CRREG)&##FIELD##_MASK)>>##FIELD##_SHIFT) \\r
-)\r
-\r
-\r
-\r
-#define HCRFIELD_SET(CRREG,FIELD,Val) CRREG = (Uint32)( \\r
- ((CRREG)&~##FIELD##_MASK)| \\r
- (((Uint32)(Val)<<##FIELD##_SHIFT)&##FIELD##_MASK) \\r
-)\r
-\r
-#define HCRFIELD_SHIFT(FIELD,Val) \\r
- (((Uint32)(Val)<<##FIELD##_SHIFT)&##FIELD##_MASK)\r
-\r
-#define HCRREG32_GET(CRREG) \\r
- (Uint32)(CRREG)\r
-\r
-#define HCRREG32_SET(CRREG,Val) \\r
- (CRREG)=(Uint32)(Val)\r
-\r
-\r
-/******************************************************************************\\r
-* Copyright (C) 1999-2000 Texas Instruments Incorporated.\r
-* All Rights Reserved\r
-*------------------------------------------------------------------------------\r
-* FILENAME...... chiphal.h\r
-* DATE CREATED.. 08/19/1999 \r
-* LAST MODIFIED. 03/08/2000\r
-* \r
-*------------------------------------------------------------------------------\r
-* DESCRIPTION: (HAL interface file for the CHIP module)\r
-* \r
-* CHIP Control Registers Covered\r
-* HCHIP_CSR - control status register\r
-* HCHIP_IFR - interrupt flag register\r
-* HCHIP_ISR - interrupt set register\r
-* HCHIP_ICR - interrupt clear register\r
-* HCHIP_IER - interrupt enable register\r
-* HCHIP_ISTP - interrupt service table pointer\r
-* HCHIP_IRP - interrrupt return pointer\r
-* HCHIP_NRP - nonmaskable interrupt return pointer\r
-* HCHIP_AMR - addressing mode register\r
-* HCHIP_FADCR - floating-point adder config register (1)\r
-* HCHIP_FAUCR - floating-point auxiliary config register (1)\r
-* HCHIP_FMCR - floating-point multiplier config register (1)\r
-*\r
-* (1) only on devices with an FPU\r
-*\r
-\******************************************************************************/\r
-#ifndef _CHIPHAL_H_\r
-#define _CHIPHAL_H_\r
-\r
-/*----------------------------------------------------------------*/\r
-\r
-#define HCHIP_PERBASE_ADDR (0x01800000)\r
-\r
-/******************************************************************************\\r
-* HCHIP_NULL - dummy register\r
-*\r
-\******************************************************************************/\r
- #define HCHIP_NULL_ADDR ((UINT32)(0x01840074))\r
- #define HCHIP_NULL REG32(HCHIP_NULL_ADDR)\r
-\r
-/******************************************************************************\\r
-* HCHIP_CSR - control status register\r
-*\r
-* Fields:\r
-* (RW) HCHIP_CSR_GIE\r
-* (RW) HCHIP_CSR_PGIE\r
-* (RW) HCHIP_CSR_DCC\r
-* (RW) HCHIP_CSR_PCC\r
-* (R) HCHIP_CSR_EN\r
-* (RC) HCHIP_CSR_SAT\r
-* (RW) HCHIP_CSR_PWRD\r
-* (R) HCHIP_CSR_REVID\r
-* (R) HCHIP_CSR_CPUID\r
-*\r
-\******************************************************************************/\r
- extern far cregister volatile unsigned int CSR;\r
- #define HCHIP_CSR CSR\r
- \r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_CSR_GIE\r
-\*----------------------------------------------------------------------------*/ \r
- #define HCHIP_CSR_GIE_MASK (0x00000001)\r
- #define HCHIP_CSR_GIE_SHIFT (0x00000000)\r
- \r
- #define HCHIP_CSR_GIE_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_CSR_GIE)\r
-\r
- #define HCHIP_CSR_GIE_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_CSR_GIE,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_CSR_PGIE\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_CSR_PGIE_MASK (0x00000002)\r
- #define HCHIP_CSR_PGIE_SHIFT (0x00000001) \r
-\r
- #define HCHIP_CSR_PGIE_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_CSR_PGIE)\r
-\r
- #define HCHIP_CSR_PGIE_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_CSR_PGIE,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_CSR_DCC\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_CSR_DCC_MASK (0x0000001C)\r
- #define HCHIP_CSR_DCC_SHIFT (0x00000002)\r
-\r
- #define HCHIP_CSR_DCC_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_CSR_DCC)\r
-\r
- #define HCHIP_CSR_DCC_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_CSR_DCC,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_CSR_PCC\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_CSR_PCC_MASK (0x000000E0)\r
- #define HCHIP_CSR_PCC_SHIFT (0x00000005)\r
-\r
- #define HCHIP_CSR_PCC_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_CSR_PCC)\r
-\r
- #define HCHIP_CSR_PCC_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_CSR_PCC,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (R) HCHIP_CSR_EN\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_CSR_EN_MASK (0x00000100)\r
- #define HCHIP_CSR_EN_SHIFT (0x00000008)\r
- \r
- #define HCHIP_CSR_EN_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_CSR_EN)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RC) HCHIP_CSR_SAT\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_CSR_SAT_MASK (0x00000200)\r
- #define HCHIP_CSR_SAT_SHIFT (0x00000009)\r
-\r
- #define HCHIP_CSR_SAT_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_CSR_SAT)\r
-\r
- #define HCHIP_CSR_SAT_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_CSR_SAT,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (W) HCHIP_CSR_PWRD\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_CSR_PWRD_MASK (0x0000FC00)\r
- #define HCHIP_CSR_PWRD_SHIFT (0x0000000A)\r
-\r
- #define HCHIP_CSR_PWRD_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_CSR_PWRD,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (R) HCHIP_CSR_REVID\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_CSR_REVID_MASK (0x00FF0000)\r
- #define HCHIP_CSR_REVID_SHIFT (0x00000010) \r
- \r
- #define HCHIP_CSR_REVID_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_CSR_REVID)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (R) HCHIP_CSR_CPUID\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_CSR_CPUID_MASK (0xFF000000)\r
- #define HCHIP_CSR_CPUID_SHIFT (0x00000018)\r
-\r
- #define HCHIP_CSR_CPUID_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_CSR_CPUID)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_CSR\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_CSR_GET(CrReg) HCRREG32_GET(CrReg)\r
-\r
- #define HCHIP_CSR_SET(CrReg,Val) HCRREG32_SET(CrReg,Val)\r
-\r
- #define HCHIP_CSR_CFG(CrReg,gie,pgie,dcc,pcc,pwrd) CrReg=(UINT32)( \\r
- HCRFIELD_SHIFT(HCHIP_CSR_GIE, gie) |\\r
- HCRFIELD_SHIFT(HCHIP_CSR_PGIE,pgie)|\\r
- HCRFIELD_SHIFT(HCHIP_CSR_DCC, dcc) |\\r
- HCRFIELD_SHIFT(HCHIP_CSR_PCC, pcc) |\\r
- HCRFIELD_SHIFT(HCHIP_CSR_PWRD,pwrd) \\r
- )\r
-\r
-/******************************************************************************\\r
-* HCHIP_IFR - interrupt flag register\r
-*\r
-* Fields:\r
-* (R) HCHIP_IFR_NMIF\r
-* (R) HCHIP_IFR_IF4\r
-* (R) HCHIP_IFR_IF5\r
-* (R) HCHIP_IFR_IF6\r
-* (R) HCHIP_IFR_IF7\r
-* (R) HCHIP_IFR_IF8\r
-* (R) HCHIP_IFR_IF9\r
-* (R) HCHIP_IFR_IF10\r
-* (R) HCHIP_IFR_IF11\r
-* (R) HCHIP_IFR_IF12\r
-* (R) HCHIP_IFR_IF13\r
-* (R) HCHIP_IFR_IF14\r
-* (R) HCHIP_IFR_IF15\r
-*\r
-\******************************************************************************/\r
- extern far cregister volatile unsigned int IFR;\r
- #define HCHIP_IFR IFR\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (R) HCHIP_IFR_NMIF\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_IFR_NMIF_MASK (0x00000002)\r
- #define HCHIP_IFR_NMIF_SHIFT (0x00000001)\r
-\r
- #define HCHIP_IFR_NMIF_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_IFR_NMIF)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (R) HCHIP_IFR_IF4\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_IFR_IF4_MASK (0x00000010)\r
- #define HCHIP_IFR_IF4_SHIFT (0x00000004)\r
-\r
- #define HCHIP_IFR_IF4_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_IFR_IF4)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (R) HCHIP_IFR_IF5\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_IFR_IF5_MASK (0x00000020)\r
- #define HCHIP_IFR_IF5_SHIFT (0x00000005)\r
-\r
- #define HCHIP_IFR_IF5_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_IFR_IF5)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (R) HCHIP_IFR_IF6\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_IFR_IF6_MASK (0x00000040)\r
- #define HCHIP_IFR_IF6_SHIFT (0x00000006)\r
-\r
- #define HCHIP_IFR_IF6_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_IFR_IF6)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (R) HCHIP_IFR_IF7\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_IFR_IF7_MASK (0x00000080)\r
- #define HCHIP_IFR_IF7_SHIFT (0x00000007)\r
-\r
- #define HCHIP_IFR_IF7_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_IFR_IF7)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (R) HCHIP_IFR_IF8\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_IFR_IF8_MASK (0x00000100)\r
- #define HCHIP_IFR_IF8_SHIFT (0x00000008)\r
-\r
- #define HCHIP_IFR_IF8_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_IFR_IF8)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (R) HCHIP_IFR_IF9\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_IFR_IF9_MASK (0x00000200)\r
- #define HCHIP_IFR_IF9_SHIFT (0x00000009)\r
-\r
- #define HCHIP_IFR_IF9_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_IFR_IF9)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (R) HCHIP_IFR_IF10\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_IFR_IF10_MASK (0x00000400)\r
- #define HCHIP_IFR_IF10_SHIFT (0x0000000A)\r
-\r
- #define HCHIP_IFR_IF10_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_IFR_IF10)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (R) HCHIP_IFR_IF11\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_IFR_IF11_MASK (0x00000800)\r
- #define HCHIP_IFR_IF11_SHIFT (0x0000000B)\r
-\r
- #define HCHIP_IFR_IF11_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_IFR_IF11)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (R) HCHIP_IFR_IF12\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_IFR_IF12_MASK (0x00001000)\r
- #define HCHIP_IFR_IF12_SHIFT (0x0000000C)\r
-\r
- #define HCHIP_IFR_IF12_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_IFR_IF12)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (R) HCHIP_IFR_IF13\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_IFR_IF13_MASK (0x00002000)\r
- #define HCHIP_IFR_IF13_SHIFT (0x0000000D)\r
-\r
- #define HCHIP_IFR_IF13_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_IFR_IF13)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (R) HCHIP_IFR_IF14\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_IFR_IF14_MASK (0x00004000)\r
- #define HCHIP_IFR_IF14_SHIFT (0x0000000E)\r
-\r
- #define HCHIP_IFR_IF14_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_IFR_IF14)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (R) HCHIP_IFR_IF15\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_IFR_IF15_MASK (0x00008000)\r
- #define HCHIP_IFR_IF15_SHIFT (0x0000000F)\r
-\r
- #define HCHIP_IFR_IF15_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_IFR_IF15)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (R) HCHIP_IFR\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_IFR_GET(CrReg) HCRREG32_GET(CrReg)\r
-\r
-/******************************************************************************\\r
-* HCHIP_ISR - interrupt set register\r
-*\r
-* Fields:\r
-* (W) HCHIP_ISR_IS4\r
-* (W) HCHIP_ISR_IS5\r
-* (W) HCHIP_ISR_IS6\r
-* (W) HCHIP_ISR_IS7\r
-* (W) HCHIP_ISR_IS8\r
-* (W) HCHIP_ISR_IS9\r
-* (W) HCHIP_ISR_IS10\r
-* (W) HCHIP_ISR_IS11\r
-* (W) HCHIP_ISR_IS12\r
-* (W) HCHIP_ISR_IS13\r
-* (W) HCHIP_ISR_IS14\r
-* (W) HCHIP_ISR_IS15\r
-*\r
-\******************************************************************************/\r
- extern far cregister volatile unsigned int ISR;\r
- #define HCHIP_ISR ISR\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (W) HCHIP_ISR_IS4\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_ISR_IS4_MASK (0x00000010)\r
- #define HCHIP_ISR_IS4_SHIFT (0x00000004)\r
-\r
- #define HCHIP_ISR_IS4_SET(CrReg,Val) \\r
- HCRREG32_SET(CrReg,HFIELD_SHIFT(HCHIP_ISR_IS4,Val))\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (W) HCHIP_ISR_IS5\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_ISR_IS5_MASK (0x00000020)\r
- #define HCHIP_ISR_IS5_SHIFT (0x00000005)\r
-\r
- #define HCHIP_ISR_IS5_SET(CrReg,Val) \\r
- HCRREG32_SET(CrReg,HFIELD_SHIFT(HCHIP_ISR_IS5,Val))\r
- \r
-/*----------------------------------------------------------------------------*\\r
-* (W) HCHIP_ISR_IS6\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_ISR_IS6_MASK (0x00000040)\r
- #define HCHIP_ISR_IS6_SHIFT (0x00000006)\r
-\r
- #define HCHIP_ISR_IS6_SET(CrReg,Val) \\r
- HCRREG32_SET(CrReg,HFIELD_SHIFT(HCHIP_ISR_IS6,Val))\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (W) HCHIP_ISR_IS7\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_ISR_IS7_MASK (0x00000080)\r
- #define HCHIP_ISR_IS7_SHIFT (0x00000007)\r
-\r
- #define HCHIP_ISR_IS7_SET(CrReg,Val) \\r
- HCRREG32_SET(CrReg,HFIELD_SHIFT(HCHIP_ISR_IS7,Val))\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (W) HCHIP_ISR_IS8\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_ISR_IS8_MASK (0x00000100)\r
- #define HCHIP_ISR_IS8_SHIFT (0x00000008)\r
-\r
- #define HCHIP_ISR_IS8_SET(CrReg,Val) \\r
- HCRREG32_SET(CrReg,HFIELD_SHIFT(HCHIP_ISR_IS8,Val))\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (W) HCHIP_ISR_IS9\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_ISR_IS9_MASK (0x00000200)\r
- #define HCHIP_ISR_IS9_SHIFT (0x00000009)\r
-\r
- #define HCHIP_ISR_IS9_SET(CrReg,Val) \\r
- HCRREG32_SET(CrReg,HFIELD_SHIFT(HCHIP_ISR_IS9,Val))\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (W) HCHIP_ISR_IS10\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_ISR_IS10_MASK (0x00000400)\r
- #define HCHIP_ISR_IS10_SHIFT (0x0000000A)\r
-\r
- #define HCHIP_ISR_IS10_SET(CrReg,Val) \\r
- HCRREG32_SET(CrReg,HFIELD_SHIFT(HCHIP_ISR_IS10,Val))\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (W) HCHIP_ISR_IS11\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_ISR_IS11_MASK (0x00000800)\r
- #define HCHIP_ISR_IS11_SHIFT (0x0000000B)\r
-\r
- #define HCHIP_ISR_IS11_SET(CrReg,Val) \\r
- HCRREG32_SET(CrReg,HFIELD_SHIFT(HCHIP_ISR_IS11,Val))\r
-/*----------------------------------------------------------------------------*\\r
-* (W) HCHIP_ISR_IS12\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_ISR_IS12_MASK (0x00001000)\r
- #define HCHIP_ISR_IS12_SHIFT (0x0000000C)\r
-\r
- #define HCHIP_ISR_IS12_SET(CrReg,Val) \\r
- HCRREG32_SET(CrReg,HFIELD_SHIFT(HCHIP_ISR_IS12,Val))\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (W) HCHIP_ISR_IS13\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_ISR_IS13_MASK (0x00002000)\r
- #define HCHIP_ISR_IS13_SHIFT (0x0000000D)\r
-\r
- #define HCHIP_ISR_IS13_SET(CrReg,Val) \\r
- HCRREG32_SET(CrReg,HFIELD_SHIFT(HCHIP_ISR_IS13,Val))\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (W) HCHIP_ISR_IS14\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_ISR_IS14_MASK (0x00004000)\r
- #define HCHIP_ISR_IS14_SHIFT (0x0000000E)\r
-\r
- #define HCHIP_ISR_IS14_SET(CrReg,Val) \\r
- HCRREG32_SET(CrReg,HFIELD_SHIFT(HCHIP_ISR_IS14,Val))\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (W) HCHIP_ISR_IS15\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_ISR_IS15_MASK (0x00008000)\r
- #define HCHIP_ISR_IS15_SHIFT (0x0000000F)\r
-\r
- #define HCHIP_ISR_IS15_SET(CrReg,Val) \\r
- HCRREG32_SET(CrReg,HFIELD_SHIFT(HCHIP_ISR_IS15,Val))\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (W) HCHIP_ISR\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_ISR_SET(CrReg,Val) HCRREG32_SET(CrReg,Val)\r
-\r
- #define HCHIP_ISR_CFG(CrReg,is4,is5,is6,is7,is8,is9,is10,is11,is12,is13,is14,\\r
- is15) CrReg=(UINT32)( \\r
- HCRFIELD_SHIFT(HCHIP_ISR_IS4, is4) |\\r
- HCRFIELD_SHIFT(HCHIP_ISR_IS5, is5) |\\r
- HCRFIELD_SHIFT(HCHIP_ISR_IS6, is6) |\\r
- HCRFIELD_SHIFT(HCHIP_ISR_IS7, is7) |\\r
- HCRFIELD_SHIFT(HCHIP_ISR_IS8, is8) |\\r
- HCRFIELD_SHIFT(HCHIP_ISR_IS9, is9) |\\r
- HCRFIELD_SHIFT(HCHIP_ISR_IS10,is10)|\\r
- HCRFIELD_SHIFT(HCHIP_ISR_IS11,is11)|\\r
- HCRFIELD_SHIFT(HCHIP_ISR_IS12,is12)|\\r
- HCRFIELD_SHIFT(HCHIP_ISR_IS13,is13)|\\r
- HCRFIELD_SHIFT(HCHIP_ISR_IS14,is14)|\\r
- HCRFIELD_SHIFT(HCHIP_ISR_IS15,is15) \\r
- ) \r
-\r
-/******************************************************************************\\r
-* HCHIP_ICR - interrupt clear register\r
-*\r
-* Fields:\r
-* (W) HCHIP_ICR_IC4\r
-* (W) HCHIP_ICR_IC5\r
-* (W) HCHIP_ICR_IC6\r
-* (W) HCHIP_ICR_IC7\r
-* (W) HCHIP_ICR_IC8\r
-* (W) HCHIP_ICR_IC9\r
-* (W) HCHIP_ICR_IC10\r
-* (W) HCHIP_ICR_IC11\r
-* (W) HCHIP_ICR_IC12\r
-* (W) HCHIP_ICR_IC13\r
-* (W) HCHIP_ICR_IC14\r
-* (W) HCHIP_ICR_IC15\r
-*\r
-\******************************************************************************/\r
- extern far cregister volatile unsigned int ICR;\r
- #define HCHIP_ICR ICR\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (W) HCHIP_ICR_IC4\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_ICR_IC4_MASK (0x00000010)\r
- #define HCHIP_ICR_IC4_SHIFT (0x00000004)\r
-\r
- #define HCHIP_ICR_IC4_SET(CrReg,Val) \\r
- HCRREG32_SET(CrReg,HFIELD_SHIFT(HCHIP_ICR_IC4,Val))\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (W) HCHIP_ICR_IC5\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_ICR_IC5_MASK (0x00000020)\r
- #define HCHIP_ICR_IC5_SHIFT (0x00000005)\r
-\r
- #define HCHIP_ICR_IC5_SET(CrReg,Val) \\r
- HCRREG32_SET(CrReg,HFIELD_SHIFT(HCHIP_ICR_IC5,Val))\r
- \r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (W) HCHIP_ICR_IC6\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_ICR_IC6_MASK (0x00000040)\r
- #define HCHIP_ICR_IC6_SHIFT (0x00000006)\r
- \r
- #define HCHIP_ICR_IC6_SET(CrReg,Val) \\r
- HCRREG32_SET(CrReg,HFIELD_SHIFT(HCHIP_ICR_IC6,Val))\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (W) HCHIP_ICR_IC7\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_ICR_IC7_MASK (0x00000080)\r
- #define HCHIP_ICR_IC7_SHIFT (0x00000007)\r
-\r
- #define HCHIP_ICR_IC7_SET(CrReg,Val) \\r
- HCRREG32_SET(CrReg,HFIELD_SHIFT(HCHIP_ICR_IC7,Val))\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (W) HCHIP_ICR_IC8\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_ICR_IC8_MASK (0x00000100)\r
- #define HCHIP_ICR_IC8_SHIFT (0x00000008)\r
-\r
- #define HCHIP_ICR_IC8_SET(CrReg,Val) \\r
- HCRREG32_SET(CrReg,HFIELD_SHIFT(HCHIP_ICR_IC8,Val))\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (W) HCHIP_ICR_IC9\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_ICR_IC9_MASK (0x00000200)\r
- #define HCHIP_ICR_IC9_SHIFT (0x00000009)\r
-\r
- #define HCHIP_ICR_IC9_SET(CrReg,Val) \\r
- HCRREG32_SET(CrReg,HFIELD_SHIFT(HCHIP_ICR_IC9,Val))\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (W) HCHIP_ICR_IC10\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_ICR_IC10_MASK (0x00000400)\r
- #define HCHIP_ICR_IC10_SHIFT (0x0000000A)\r
-\r
- #define HCHIP_ICR_IC10_SET(CrReg,Val) \\r
- HCRREG32_SET(CrReg,HFIELD_SHIFT(HCHIP_ICR_IC10,Val))\r
- \r
-/*----------------------------------------------------------------------------*\\r
-* (W) HCHIP_ICR_IC11\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_ICR_IC11_MASK (0x00000800)\r
- #define HCHIP_ICR_IC11_SHIFT (0x0000000B)\r
-\r
- #define HCHIP_ICR_IC11_SET(CrReg,Val) \\r
- HCRREG32_SET(CrReg,HFIELD_SHIFT(HCHIP_ICR_IC11,Val))\r
-/*----------------------------------------------------------------------------*\\r
-* (W) HCHIP_ICR_IC12\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_ICR_IC12_MASK (0x00001000)\r
- #define HCHIP_ICR_IC12_SHIFT (0x0000000C)\r
-\r
- #define HCHIP_ICR_IC12_SET(CrReg,Val) \\r
- HCRREG32_SET(CrReg,HFIELD_SHIFT(HCHIP_ICR_IC12,Val))\r
- \r
-/*----------------------------------------------------------------------------*\\r
-* (W) HCHIP_ICR_IC13\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_ICR_IC13_MASK (0x00002000)\r
- #define HCHIP_ICR_IC13_SHIFT (0x0000000D)\r
-\r
- #define HCHIP_ICR_IC13_SET(CrReg,Val) \\r
- HCRREG32_SET(CrReg,HFIELD_SHIFT(HCHIP_ICR_IC13,Val))\r
- \r
-/*----------------------------------------------------------------------------*\\r
-* (W) HCHIP_ICR_IC14\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_ICR_IC14_MASK (0x00004000)\r
- #define HCHIP_ICR_IC14_SHIFT (0x0000000E)\r
-\r
- #define HCHIP_ICR_IC14_SET(CrReg,Val) \\r
- HCRREG32_SET(CrReg,HFIELD_SHIFT(HCHIP_ICR_IC14,Val))\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (W) HCHIP_ICR_IC15\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_ICR_IC15_MASK (0x00008000)\r
- #define HCHIP_ICR_IC15_SHIFT (0x0000000F)\r
-\r
- #define HCHIP_ICR_IC15_SET(CrReg,Val) \\r
- HCRREG32_SET(CrReg,HFIELD_SHIFT(HCHIP_ICR_IC15,Val))\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (W) HCHIP_ICR\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_ICR_SET(CrReg,Val) HCRREG32_SET(CrReg,Val)\r
-\r
- #define HCHIP_ICR_CFG(CrReg,ic4,ic5,ic6,ic7,ic8,ic9,ic10,ic11,ic12,ic13,ic14,\\r
- ic15) CrReg=(UINT32)( \\r
- HCRFIELD_SHIFT(HCHIP_ICR_IC4, ic4) |\\r
- HCRFIELD_SHIFT(HCHIP_ICR_IC5, ic5) |\\r
- HCRFIELD_SHIFT(HCHIP_ICR_IC6, ic6) |\\r
- HCRFIELD_SHIFT(HCHIP_ICR_IC7, ic7) |\\r
- HCRFIELD_SHIFT(HCHIP_ICR_IC8, ic8) |\\r
- HCRFIELD_SHIFT(HCHIP_ICR_IC9, ic9) |\\r
- HCRFIELD_SHIFT(HCHIP_ICR_IC10,ic10)|\\r
- HCRFIELD_SHIFT(HCHIP_ICR_IC11,ic11)|\\r
- HCRFIELD_SHIFT(HCHIP_ICR_IC12,ic12)|\\r
- HCRFIELD_SHIFT(HCHIP_ICR_IC13,ic13)|\\r
- HCRFIELD_SHIFT(HCHIP_ICR_IC14,ic14)|\\r
- HCRFIELD_SHIFT(HCHIP_ICR_IC15,ic15) \\r
- )\r
-\r
-/******************************************************************************\\r
-* HCHIP_IER - interrupt enable register\r
-*\r
-* Fields: \r
-* (RW) HCHIP_IER_NMIE\r
-* (RW) HCHIP_IER_IE4\r
-* (RW) HCHIP_IER_IE5\r
-* (RW) HCHIP_IER_IE6\r
-* (RW) HCHIP_IER_IE7\r
-* (RW) HCHIP_IER_IE8\r
-* (RW) HCHIP_IER_IE9\r
-* (RW) HCHIP_IER_IE10\r
-* (RW) HCHIP_IER_IE11\r
-* (RW) HCHIP_IER_IE12\r
-* (RW) HCHIP_IER_IE13\r
-* (RW) HCHIP_IER_IE14\r
-* (RW) HCHIP_IER_IE15\r
-*\r
-\******************************************************************************/\r
- extern far cregister volatile unsigned int IER;\r
- #define HCHIP_IER IER\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_IER_NMIE\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_IER_NMIE_MASK (0x00000002)\r
- #define HCHIP_IER_NMIE_SHIFT (0x00000001)\r
- \r
- #define HCHIP_IER_NMIE_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_IER_NMIE)\r
-\r
- #define HCHIP_IER_NMIE_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_IER_NMIE,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_IER_IE4\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_IER_IE4_MASK (0x00000010)\r
- #define HCHIP_IER_IE4_SHIFT (0x00000004)\r
- \r
- #define HCHIP_IER_IE4_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_IER_IE4)\r
-\r
- #define HCHIP_IER_IE4_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_IER_IE4,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_IER_IE5\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_IER_IE5_MASK (0x00000020)\r
- #define HCHIP_IER_IE5_SHIFT (0x00000005)\r
- \r
- #define HCHIP_IER_IE5_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_IER_IE5)\r
-\r
- #define HCHIP_IER_IE5_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_IER_IE5,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_IER_IE6\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_IER_IE6_MASK (0x00000040)\r
- #define HCHIP_IER_IE6_SHIFT (0x00000006)\r
- \r
- #define HCHIP_IER_IE6_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_IER_IE6)\r
-\r
- #define HCHIP_IER_IE6_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_IER_IE6,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_IER_IE7\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_IER_IE7_MASK (0x00000080)\r
- #define HCHIP_IER_IE7_SHIFT (0x00000007)\r
- \r
- #define HCHIP_IER_IE7_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_IER_IE7)\r
-\r
- #define HCHIP_IER_IE7_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_IER_IE7,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_IER_IE8\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_IER_IE8_MASK (0x00000100)\r
- #define HCHIP_IER_IE8_SHIFT (0x00000008)\r
- \r
- #define HCHIP_IER_IE8_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_IER_IE8)\r
-\r
- #define HCHIP_IER_IE8_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_IER_IE8,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_IER_IE9\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_IER_IE9_MASK (0x00000200)\r
- #define HCHIP_IER_IE9_SHIFT (0x00000009)\r
- \r
- #define HCHIP_IER_IE9_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_IER_IE9)\r
-\r
- #define HCHIP_IER_IE9_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_IER_IE9,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_IER_IE10\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_IER_IE10_MASK (0x00000400)\r
- #define HCHIP_IER_IE10_SHIFT (0x0000000A)\r
- \r
- #define HCHIP_IER_IE10_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_IER_IE10)\r
-\r
- #define HCHIP_IER_IE10_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_IER_IE10,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_IER_IE11\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_IER_IE11_MASK (0x00000800)\r
- #define HCHIP_IER_IE11_SHIFT (0x0000000B)\r
- \r
- #define HCHIP_IER_IE11_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_IER_IE11)\r
-\r
- #define HCHIP_IER_IE11_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_IER_IE11,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_IER_IE12\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_IER_IE12_MASK (0x00001000)\r
- #define HCHIP_IER_IE12_SHIFT (0x0000000C)\r
- \r
- #define HCHIP_IER_IE12_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_IER_IE12)\r
-\r
- #define HCHIP_IER_IE12_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_IER_IE12,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_IER_IE13\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_IER_IE13_MASK (0x00002000)\r
- #define HCHIP_IER_IE13_SHIFT (0x0000000D)\r
- \r
- #define HCHIP_IER_IE13_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_IER_IE13)\r
-\r
- #define HCHIP_IER_IE13_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_IER_IE13,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_IER_IE14\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_IER_IE14_MASK (0x00004000)\r
- #define HCHIP_IER_IE14_SHIFT (0x0000000E)\r
- \r
- #define HCHIP_IER_IE14_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_IER_IE14)\r
-\r
- #define HCHIP_IER_IE14_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_IER_IE14,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_IER_IE15\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_IER_IE15_MASK (0x00008000)\r
- #define HCHIP_IER_IE15_SHIFT (0x0000000F)\r
- \r
- #define HCHIP_IER_IE15_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_IER_IE15)\r
-\r
- #define HCHIP_IER_IE15_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_IER_IE15,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_IER\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_IER_GET(CrReg) HCRREG32_GET(CrReg)\r
-\r
- #define HCHIP_IER_SET(CrReg,Val) HCRREG32_SET(CrReg,Val)\r
-\r
- #define HCHIP_IER_CFG(CrReg,nmie,ie4,ie5,ie6,ie7,ie8,ie9,ie10,ie11,ie12,ie13,\\r
- ie14,ie15) CrReg=(UINT32)( \\r
- HCRFIELD_SHIFT(HCHIP_IER_NMIE,nmie)|\\r
- HCRFIELD_SHIFT(HCHIP_IER_IE4, ie4) |\\r
- HCRFIELD_SHIFT(HCHIP_IER_IE5, ie5) |\\r
- HCRFIELD_SHIFT(HCHIP_IER_IE6, ie6) |\\r
- HCRFIELD_SHIFT(HCHIP_IER_IE7, ie7) |\\r
- HCRFIELD_SHIFT(HCHIP_IER_IE8, ie8) |\\r
- HCRFIELD_SHIFT(HCHIP_IER_IE9, ie9) |\\r
- HCRFIELD_SHIFT(HCHIP_IER_IE10,ie10)|\\r
- HCRFIELD_SHIFT(HCHIP_IER_IE11,ie11)|\\r
- HCRFIELD_SHIFT(HCHIP_IER_IE12,ie12)|\\r
- HCRFIELD_SHIFT(HCHIP_IER_IE13,ie13)|\\r
- HCRFIELD_SHIFT(HCHIP_IER_IE14,ie14)|\\r
- HCRFIELD_SHIFT(HCHIP_IER_IE15,ie15) \\r
- )\r
-\r
-/******************************************************************************\\r
-* HCHIP_ISTP - interrupt service table pointer\r
-*\r
-* Fields: \r
-* (R) HCHIP_ISTP_HPEINT\r
-* (RW) HCHIP_ISTP_ISTB\r
-*\r
-\******************************************************************************/\r
- extern far cregister volatile unsigned int ISTP;\r
- #define HCHIP_ISTP ISTP\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (R) HCHIP_ISTP_HPEINT\r
-\*----------------------------------------------------------------------------*/ \r
- #define HCHIP_ISTP_HPEINT_MASK (0x000003E0)\r
- #define HCHIP_ISTP_HPEINT_SHIFT (0x00000005)\r
- \r
- #define HCHIP_ISTP_HPEINT_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_ISTP_HPEINT)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_ISTP_ISTB\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_ISTP_ISTB_MASK (0xFFFFFC00)\r
- #define HCHIP_ISTP_ISTB_SHIFT (0x0000000A)\r
-\r
- #define HCHIP_ISTP_ISTB_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_ISTP_ISTB)\r
-\r
- #define HCHIP_ISTP_ISTB_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_ISTP_ISTB,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_ISTP\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_ISTP_GET(CrReg) HCRREG32_GET(CrReg)\r
-\r
- #define HCHIP_ISTP_SET(CrReg,Val) HCRREG32_SET(CrReg,Val)\r
-\r
- #define HCHIP_ISTP_CFG(CrReg,istb) CrReg=(UINT32)(\\r
- HCRFIELD_SHIFT(HCHIP_ISTP_ISTB,istb) \\r
- )\r
-\r
-/******************************************************************************\\r
-* HCHIP_IRP - interrrupt return pointer\r
-*\r
-* Fields: \r
-* (RW) HCHIP_IRP_IRP\r
-*\r
-\******************************************************************************/\r
- extern far cregister volatile unsigned int IRP;\r
- #define HCHIP_IRP IRP\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_IRP_IRP\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_IRP_IRP_MASK (0xFFFFFFFF)\r
- #define HCHIP_IRP_IRP_SHIFT (0x00000000)\r
-\r
- #define HCHIP_IRP_IRP_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_IRP_IRP)\r
-\r
- #define HCHIP_IRP_IRP_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_IRP_IRP,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_IRP\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_IRP_GET(CrReg) HCRREG32_GET(CrReg)\r
-\r
- #define HCHIP_IRP_SET(CrReg,Val) HCRREG32_SET(CrReg,Val)\r
-\r
- #define HCHIP_IRP_CFG(CrReg,irp) CrReg=(UINT32)( \\r
- HCRFIELD_SHIFT(HCHIP_IRP_IRP,irp) \\r
- )\r
-\r
-/******************************************************************************\\r
-* HCHIP_NRP - nonmaskable interrupt return pointer\r
-*\r
-* Fields: \r
-* (RW) HCHIP_NRP_NRP\r
-*\r
-\******************************************************************************/\r
- extern far cregister volatile unsigned int NRP;\r
- #define HCHIP_NRP NRP\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_NRP_NRP\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_NRP_NRP_MASK (0xFFFFFFFF)\r
- #define HCHIP_NRP_NRP_SHIFT (0x00000000)\r
-\r
- #define HCHIP_NRP_NRP_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_NRP_NRP)\r
-\r
- #define HCHIP_NRP_NRP_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_NRP_NRP,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_NRP\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_NRP_GET(CrReg) HCRREG32_GET(CrReg)\r
-\r
- #define HCHIP_NRP_SET(CrReg,Val) HCRREG32_SET(CrReg,Val)\r
-\r
- #define HCHIP_NRP_CFG(CrReg,nrp) CrReg=(UINT32)( \\r
- HCRFIELD_SHIFT(HCHIP_NRP_NRP,nrp) \\r
- )\r
-\r
-/******************************************************************************\\r
-* HCHIP_AMR - addressing mode register\r
-*\r
-* Fields: \r
-* (RW) HCHIP_AMR_A4MODE\r
-* (RW) HCHIP_AMR_A5MODE\r
-* (RW) HCHIP_AMR_A6MODE\r
-* (RW) HCHIP_AMR_A7MODE\r
-* (RW) HCHIP_AMR_B4MODE\r
-* (RW) HCHIP_AMR_B5MODE\r
-* (RW) HCHIP_AMR_B6MODE\r
-* (RW) HCHIP_AMR_B7MODE\r
-* (RW) HCHIP_AMR_BK0\r
-* (RW) HCHIP_AMR_BK1\r
-*\r
-\******************************************************************************/\r
- extern far cregister volatile unsigned int AMR;\r
- #define HCHIP_AMR AMR\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_AMR_A4MODE\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_AMR_A4MODE_MASK (0x00000003)\r
- #define HCHIP_AMR_A4MODE_SHIFT (0x00000000)\r
-\r
- #define HCHIP_AMR_A4MODE_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_AMR_A4MODE)\r
-\r
- #define HCHIP_AMR_A4MODE_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_AMR_A4MODE,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_AMR_A5MODE\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_AMR_A5MODE_MASK (0x0000000C)\r
- #define HCHIP_AMR_A5MODE_SHIFT (0x00000002)\r
-\r
- #define HCHIP_AMR_A5MODE_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_AMR_A5MODE)\r
-\r
- #define HCHIP_AMR_A5MODE_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_AMR_A5MODE,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_AMR_A6MODE\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_AMR_A6MODE_MASK (0x00000030)\r
- #define HCHIP_AMR_A6MODE_SHIFT (0x00000004)\r
-\r
- #define HCHIP_AMR_A6MODE_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_AMR_A6MODE)\r
-\r
- #define HCHIP_AMR_A6MODE_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_AMR_A6MODE,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_AMR_A7MODE\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_AMR_A7MODE_MASK (0x000000C0)\r
- #define HCHIP_AMR_A7MODE_SHIFT (0x00000006)\r
-\r
- #define HCHIP_AMR_A7MODE_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_AMR_A7MODE)\r
-\r
- #define HCHIP_AMR_A7MODE_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_AMR_A7MODE,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_AMR_B4MODE\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_AMR_B4MODE_MASK (0x00000300)\r
- #define HCHIP_AMR_B4MODE_SHIFT (0x00000008)\r
-\r
- #define HCHIP_AMR_B4MODE_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_AMR_B4MODE)\r
-\r
- #define HCHIP_AMR_B4MODE_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_AMR_B4MODE,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_AMR_B5MODE\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_AMR_B5MODE_MASK (0x00000C00)\r
- #define HCHIP_AMR_B5MODE_SHIFT (0x0000000A)\r
-\r
- #define HCHIP_AMR_B5MODE_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_AMR_B5MODE)\r
-\r
- #define HCHIP_AMR_B5MODE_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_AMR_B5MODE,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_AMR_B6MODE\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_AMR_B6MODE_MASK (0x00003000)\r
- #define HCHIP_AMR_B6MODE_SHIFT (0x0000000C)\r
-\r
- #define HCHIP_AMR_B6MODE_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_AMR_B6MODE)\r
-\r
- #define HCHIP_AMR_B6MODE_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_AMR_B6MODE,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_AMR_B7MODE\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_AMR_B7MODE_MASK (0x0000C000)\r
- #define HCHIP_AMR_B7MODE_SHIFT (0x0000000E)\r
-\r
- #define HCHIP_AMR_B7MODE_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_AMR_B7MODE)\r
-\r
- #define HCHIP_AMR_B7MODE_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_AMR_B7MODE,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_AMR_BK0\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_AMR_BK0_MASK (0x001F0000)\r
- #define HCHIP_AMR_BK0_SHIFT (0x00000010)\r
-\r
- #define HCHIP_AMR_BK0_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_AMR_BK0)\r
-\r
- #define HCHIP_AMR_BK0_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_AMR_BK0,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_AMR_BK1\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_AMR_BK1_MASK (0x001F0000)\r
- #define HCHIP_AMR_BK1_SHIFT (0x00000010)\r
-\r
- #define HCHIP_AMR_BK1_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_AMR_BK1)\r
-\r
- #define HCHIP_AMR_BK1_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_AMR_BK1,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_AMR\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_AMR_GET(CrReg) HCRREG32_GET(CrReg)\r
-\r
- #define HCHIP_AMR_SET(CrReg,Val) HCRREG32_SET(CrReg,Val)\r
-\r
- #define HCHIP_AMR_CFG(CrReg,a4mode,a5mode,a6mode,a7mode,b4mode,b5mode,b6mode,\\r
- b7mode,bk0,bk1) CrReg=(UINT32)( \\r
- HCRFIELD_SHIFT(HCHIP_AMR_A4MODE,a4mode)| \\r
- HCRFIELD_SHIFT(HCHIP_AMR_A5MODE,a5mode)| \\r
- HCRFIELD_SHIFT(HCHIP_AMR_A6MODE,a6mode)| \\r
- HCRFIELD_SHIFT(HCHIP_AMR_A7MODE,a7mode)| \\r
- HCRFIELD_SHIFT(HCHIP_AMR_B4MODE,b4mode)| \\r
- HCRFIELD_SHIFT(HCHIP_AMR_B5MODE,b5mode)| \\r
- HCRFIELD_SHIFT(HCHIP_AMR_B6MODE,b6mode)| \\r
- HCRFIELD_SHIFT(HCHIP_AMR_B7MODE,b7mode)| \\r
- HCRFIELD_SHIFT(HCHIP_AMR_BK0,bk0)| \\r
- HCRFIELD_SHIFT(HCHIP_AMR_BK1,bk1) \\r
- )\r
-\r
-#if (FPU_SUPPORT)\r
-/******************************************************************************\\r
-* HCHIP_FADCR - floating-point adder config register (1)\r
-*\r
-* (1) only supported on devices with floating point unit\r
-*\r
-* Fields: \r
-* (RW) HCHIP_FADCR_L1NAN1\r
-* (RW) HCHIP_FADCR_L1NAN2\r
-* (RW) HCHIP_FADCR_L1DEN1\r
-* (RW) HCHIP_FADCR_L1DEN2\r
-* (RW) HCHIP_FADCR_L1INVAL\r
-* (RW) HCHIP_FADCR_L1INFO\r
-* (RW) HCHIP_FADCR_L1OVER\r
-* (RW) HCHIP_FADCR_L1INEX\r
-* (RW) HCHIP_FADCR_L1UNDER\r
-* (RW) HCHIP_FADCR_L1RMODE\r
-* (RW) HCHIP_FADCR_L2NAN1\r
-* (RW) HCHIP_FADCR_L2NAN2\r
-* (RW) HCHIP_FADCR_L2DEN1\r
-* (RW) HCHIP_FADCR_L2DEN2\r
-* (RW) HCHIP_FADCR_L2INVAL\r
-* (RW) HCHIP_FADCR_L2INFO\r
-* (RW) HCHIP_FADCR_L2OVER\r
-* (RW) HCHIP_FADCR_L2INEX\r
-* (RW) HCHIP_FADCR_L2UNDER\r
-* (RW) HCHIP_FADCR_L2RMODE\r
-*\r
-\******************************************************************************/\r
- extern far cregister volatile unsigned int FADCR;\r
- #define HCHIP_FADCR FADCR\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_FADCR_L1NAN1\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_FADCR_L1NAN1_MASK (0x00000001)\r
- #define HCHIP_FADCR_L1NAN1_SHIFT (0x00000000)\r
-\r
- #define HCHIP_FADCR_L1NAN1_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_FADCR_L1NAN1)\r
-\r
- #define HCHIP_FADCR_L1NAN1_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_FADCR_L1NAN1,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_FADCR_L1NAN2\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_FADCR_L1NAN2_MASK (0x00000002)\r
- #define HCHIP_FADCR_L1NAN2_SHIFT (0x00000001)\r
-\r
- #define HCHIP_FADCR_L1NAN2_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_FADCR_L1NAN2)\r
-\r
- #define HCHIP_FADCR_L1NAN2_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_FADCR_L1NAN2,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_FADCR_L1DEN1\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_FADCR_L1DEN1_MASK (0x00000004)\r
- #define HCHIP_FADCR_L1DEN1_SHIFT (0x00000002)\r
-\r
- #define HCHIP_FADCR_L1DEN1_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_FADCR_L1DEN1)\r
-\r
- #define HCHIP_FADCR_L1DEN1_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_FADCR_L1DEN1,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_FADCR_L1DEN2\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_FADCR_L1DEN2_MASK (0x00000008)\r
- #define HCHIP_FADCR_L1DEN2_SHIFT (0x00000003)\r
-\r
- #define HCHIP_FADCR_L1DEN2_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_FADCR_L1DEN2)\r
-\r
- #define HCHIP_FADCR_L1DEN2_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_FADCR_L1DEN2,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_FADCR_L1INVAL\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_FADCR_L1INVAL_MASK (0x00000010)\r
- #define HCHIP_FADCR_L1INVAL_SHIFT (0x00000004)\r
-\r
- #define HCHIP_FADCR_L1INVAL_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_FADCR_L1INVAL)\r
-\r
- #define HCHIP_FADCR_L1INVAL_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_FADCR_L1INVAL,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_FADCR_L1INFO\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_FADCR_L1INFO_MASK (0x00000020)\r
- #define HCHIP_FADCR_L1INFO_SHIFT (0x00000005)\r
-\r
- #define HCHIP_FADCR_L1INFO_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_FADCR_L1INFO)\r
-\r
- #define HCHIP_FADCR_L1INFO_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_FADCR_L1INFO,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_FADCR_L1OVER\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_FADCR_L1OVER_MASK (0x00000040)\r
- #define HCHIP_FADCR_L1OVER_SHIFT (0x00000006)\r
-\r
- #define HCHIP_FADCR_L1OVER_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_FADCR_L1OVER)\r
-\r
- #define HCHIP_FADCR_L1OVER_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_FADCR_L1OVER,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_FADCR_L1INEX\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_FADCR_L1INEX_MASK (0x00000080)\r
- #define HCHIP_FADCR_L1INEX_SHIFT (0x00000007)\r
-\r
- #define HCHIP_FADCR_L1INEX_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_FADCR_L1INEX)\r
-\r
- #define HCHIP_FADCR_L1INEX_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_FADCR_L1INEX,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_FADCR_L1UNDER\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_FADCR_L1UNDER_MASK (0x00000100)\r
- #define HCHIP_FADCR_L1UNDER_SHIFT (0x00000008)\r
-\r
- #define HCHIP_FADCR_L1UNDER_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_FADCR_L1UNDER)\r
-\r
- #define HCHIP_FADCR_L1UNDER_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_FADCR_L1UNDER,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_FADCR_L1RMODE\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_FADCR_L1RMODE_MASK (0x00000600)\r
- #define HCHIP_FADCR_L1RMODE_SHIFT (0x00000009)\r
-\r
- #define HCHIP_FADCR_L1RMODE_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_FADCR_L1RMODE)\r
-\r
- #define HCHIP_FADCR_L1RMODE_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_FADCR_L1RMODE,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_FADCR_L2NAN1\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_FADCR_L2NAN1_MASK (0x00010000)\r
- #define HCHIP_FADCR_L2NAN1_SHIFT (0x00000010)\r
-\r
- #define HCHIP_FADCR_L2NAN1_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_FADCR_L2NAN1)\r
-\r
- #define HCHIP_FADCR_L2NAN1_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_FADCR_L2NAN1,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_FADCR_L2NAN2\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_FADCR_L2NAN2_MASK (0x00020000)\r
- #define HCHIP_FADCR_L2NAN2_SHIFT (0x00000011)\r
-\r
- #define HCHIP_FADCR_L2NAN2_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_FADCR_L2NAN2)\r
-\r
- #define HCHIP_FADCR_L2NAN2_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_FADCR_L2NAN2,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_FADCR_L2DEN1\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_FADCR_L2DEN1_MASK (0x00040000)\r
- #define HCHIP_FADCR_L2DEN1_SHIFT (0x00000012)\r
-\r
- #define HCHIP_FADCR_L2DEN1_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_FADCR_L2DEN1)\r
-\r
- #define HCHIP_FADCR_L2DEN1_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_FADCR_L2DEN1,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_FADCR_L2DEN2\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_FADCR_L2DEN2_MASK (0x00080000)\r
- #define HCHIP_FADCR_L2DEN2_SHIFT (0x00000013)\r
-\r
- #define HCHIP_FADCR_L2DEN2_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_FADCR_L2DEN2)\r
-\r
- #define HCHIP_FADCR_L2DEN2_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_FADCR_L2DEN2,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_FADCR_L2INVAL\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_FADCR_L2INVAL_MASK (0x00100000)\r
- #define HCHIP_FADCR_L2INVAL_SHIFT (0x00000014)\r
-\r
- #define HCHIP_FADCR_L2INVAL_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_FADCR_L2INVAL)\r
-\r
- #define HCHIP_FADCR_L2INVAL_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_FADCR_L2INVAL,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_FADCR_L2INFO\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_FADCR_L2INFO_MASK (0x00200000)\r
- #define HCHIP_FADCR_L2INFO_SHIFT (0x00000015)\r
-\r
- #define HCHIP_FADCR_L2INFO_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_FADCR_L2INFO)\r
-\r
- #define HCHIP_FADCR_L2INFO_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_FADCR_L2INFO,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_FADCR_L2OVER\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_FADCR_L2OVER_MASK (0x00400000)\r
- #define HCHIP_FADCR_L2OVER_SHIFT (0x00000016)\r
-\r
- #define HCHIP_FADCR_L2OVER_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_FADCR_L2OVER)\r
-\r
- #define HCHIP_FADCR_L2OVER_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_FADCR_L2OVER,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_FADCR_L2INEX\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_FADCR_L2INEX_MASK (0x00800000)\r
- #define HCHIP_FADCR_L2INEX_SHIFT (0x00000017)\r
-\r
- #define HCHIP_FADCR_L2INEX_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_FADCR_L2INEX)\r
-\r
- #define HCHIP_FADCR_L2INEX_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_FADCR_L2INEX,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_FADCR_L2UNDER\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_FADCR_L2UNDER_MASK (0x01000000)\r
- #define HCHIP_FADCR_L2UNDER_SHIFT (0x00000018)\r
-\r
- #define HCHIP_FADCR_L2UNDER_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_FADCR_L2UNDER)\r
-\r
- #define HCHIP_FADCR_L2UNDER_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_FADCR_L2UNDER,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_FADCR_L2RMODE\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_FADCR_L2RMODE_MASK (0x06000000)\r
- #define HCHIP_FADCR_L2RMODE_SHIFT (0x00000019)\r
-\r
- #define HCHIP_FADCR_L2RMODE_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_FADCR_L2RMODE)\r
-\r
- #define HCHIP_FADCR_L2RMODE_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_FADCR_L2RMODE,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_FADCR\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_FADCR_GET(CrReg) HCRREG32_GET(CrReg)\r
-\r
- #define HCHIP_FADCR_SET(CrReg,Val) HCRREG32_SET(CrReg,Val)\r
-\r
- #define HCHIP_FADCR_CFG(CrReg,l1nan1,l1nan2,l1den1,l1den2,l1inval,l1info,\\r
- l1over,l1inex,l1under,l1rmode,l2nan1,l2nan2,l2den1,l2den2,l2inval,l2info,\\r
- l2over,l2inex,l2under,l2rmode) CrReg=(UINT32)( \\r
- HCRFIELD_SHIFT(HCHIP_FADCR_L1NAN1, l1nan1) |\\r
- HCRFIELD_SHIFT(HCHIP_FADCR_L1NAN2, l1nan2) |\\r
- HCRFIELD_SHIFT(HCHIP_FADCR_L1DEN1, l1den1) |\\r
- HCRFIELD_SHIFT(HCHIP_FADCR_L1DEN2, l1den2) |\\r
- HCRFIELD_SHIFT(HCHIP_FADCR_L1INVAL,l1inval)|\\r
- HCRFIELD_SHIFT(HCHIP_FADCR_L1INFO, l1info) |\\r
- HCRFIELD_SHIFT(HCHIP_FADCR_L1OVER, l1over) |\\r
- HCRFIELD_SHIFT(HCHIP_FADCR_L1INEX, l1inex) |\\r
- HCRFIELD_SHIFT(HCHIP_FADCR_L1UNDER,l1under)|\\r
- HCRFIELD_SHIFT(HCHIP_FADCR_L1RMODE,l1rmode)|\\r
- HCRFIELD_SHIFT(HCHIP_FADCR_L2NAN1, l2nan1) |\\r
- HCRFIELD_SHIFT(HCHIP_FADCR_L2NAN2, l2nan2) |\\r
- HCRFIELD_SHIFT(HCHIP_FADCR_L2DEN1, l2den1) |\\r
- HCRFIELD_SHIFT(HCHIP_FADCR_L2DEN2, l2den2) |\\r
- HCRFIELD_SHIFT(HCHIP_FADCR_L2INVAL,l2inval)|\\r
- HCRFIELD_SHIFT(HCHIP_FADCR_L2INFO, l2info) |\\r
- HCRFIELD_SHIFT(HCHIP_FADCR_L2OVER, l2over) |\\r
- HCRFIELD_SHIFT(HCHIP_FADCR_L2INEX, l2inex) |\\r
- HCRFIELD_SHIFT(HCHIP_FADCR_L2UNDER,l2under)|\\r
- HCRFIELD_SHIFT(HCHIP_FADCR_L2RMODE,l2rmode) \\r
- )\r
-#endif /* FPU_SUPPORT */\r
-\r
-#if (FPU_SUPPORT)\r
-/******************************************************************************\\r
-* HCHIP_FAUCR - floating-point auxiliary config register (1)\r
-*\r
-* (1) only supported on devices with floating point unit\r
-*\r
-* Fields: \r
-* (RW) HCHIP_FAUCR_S1NAN1\r
-* (RW) HCHIP_FAUCR_S1NAN2\r
-* (RW) HCHIP_FAUCR_S1DEN1\r
-* (RW) HCHIP_FAUCR_S1DEN2\r
-* (RW) HCHIP_FAUCR_S1INVAL\r
-* (RW) HCHIP_FAUCR_S1INFO\r
-* (RW) HCHIP_FAUCR_S1OVER\r
-* (RW) HCHIP_FAUCR_S1INEX\r
-* (RW) HCHIP_FAUCR_S1UNDER\r
-* (RW) HCHIP_FAUCR_S1UNORD\r
-* (RW) HCHIP_FAUCR_S1DIV0\r
-* (RW) HCHIP_FAUCR_S2NAN1\r
-* (RW) HCHIP_FAUCR_S2NAN2\r
-* (RW) HCHIP_FAUCR_S2DEN1\r
-* (RW) HCHIP_FAUCR_S2DEN2\r
-* (RW) HCHIP_FAUCR_S2INVAL\r
-* (RW) HCHIP_FAUCR_S2INFO\r
-* (RW) HCHIP_FAUCR_S2OVER\r
-* (RW) HCHIP_FAUCR_S2INEX\r
-* (RW) HCHIP_FAUCR_S2UNDER\r
-* (RW) HCHIP_FAUCR_S2UNORD\r
-* (RW) HCHIP_FAUCR_S2DIV0\r
-*\r
-\******************************************************************************/\r
- extern far cregister volatile unsigned int FAUCR;\r
- #define HCHIP_FAUCR FAUCR\r
- \r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_FAUCR_S1NAN1\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_FAUCR_S1NAN1_MASK (0x00000001)\r
- #define HCHIP_FAUCR_S1NAN1_SHIFT (0x00000000)\r
-\r
- #define HCHIP_FAUCR_S1NAN1_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_FAUCR_S1NAN1)\r
-\r
- #define HCHIP_FAUCR_S1NAN1_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_FAUCR_S1NAN1,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_FAUCR_S1NAN2\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_FAUCR_S1NAN2_MASK (0x00000002)\r
- #define HCHIP_FAUCR_S1NAN2_SHIFT (0x00000001)\r
-\r
- #define HCHIP_FAUCR_S1NAN2_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_FAUCR_S1NAN2)\r
-\r
- #define HCHIP_FAUCR_S1NAN2_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_FAUCR_S1NAN2,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_FAUCR_S1DEN1\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_FAUCR_S1DEN1_MASK (0x00000004)\r
- #define HCHIP_FAUCR_S1DEN1_SHIFT (0x00000002)\r
-\r
- #define HCHIP_FAUCR_S1DEN1_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_FAUCR_S1DEN1)\r
-\r
- #define HCHIP_FAUCR_S1DEN1_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_FAUCR_S1DEN1,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_FAUCR_S1DEN2\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_FAUCR_S1DEN2_MASK (0x00000008)\r
- #define HCHIP_FAUCR_S1DEN2_SHIFT (0x00000003)\r
-\r
- #define HCHIP_FAUCR_S1DEN2_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_FAUCR_S1DEN2)\r
-\r
- #define HCHIP_FAUCR_S1DEN2_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_FAUCR_S1DEN2,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_FAUCR_S1INVAL\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_FAUCR_S1INVAL_MASK (0x00000010)\r
- #define HCHIP_FAUCR_S1INVAL_SHIFT (0x00000004)\r
-\r
- #define HCHIP_FAUCR_S1INVAL_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_FAUCR_S1INVAL)\r
-\r
- #define HCHIP_FAUCR_S1INVAL_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_FAUCR_S1INVAL,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_FAUCR_S1INFO\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_FAUCR_S1INFO_MASK (0x00000020)\r
- #define HCHIP_FAUCR_S1INFO_SHIFT (0x00000005)\r
-\r
- #define HCHIP_FAUCR_S1INFO_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_FAUCR_S1INFO)\r
-\r
- #define HCHIP_FAUCR_S1INFO_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_FAUCR_S1INFO,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_FAUCR_S1OVER\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_FAUCR_S1OVER_MASK (0x00000040)\r
- #define HCHIP_FAUCR_S1OVER_SHIFT (0x00000006)\r
-\r
- #define HCHIP_FAUCR_S1OVER_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_FAUCR_S1OVER)\r
-\r
- #define HCHIP_FAUCR_S1OVER_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_FAUCR_S1OVER,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_FAUCR_S1INEX\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_FAUCR_S1INEX_MASK (0x00000080)\r
- #define HCHIP_FAUCR_S1INEX_SHIFT (0x00000007)\r
-\r
- #define HCHIP_FAUCR_S1INEX_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_FAUCR_S1INEX)\r
-\r
- #define HCHIP_FAUCR_S1INEX_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_FAUCR_S1INEX,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_FAUCR_S1UNDER\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_FAUCR_S1UNDER_MASK (0x00000100)\r
- #define HCHIP_FAUCR_S1UNDER_SHIFT (0x00000008)\r
-\r
- #define HCHIP_FAUCR_S1UNDER_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_FAUCR_S1UNDER)\r
-\r
- #define HCHIP_FAUCR_S1UNDER_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_FAUCR_S1UNDER,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_FAUCR_S1UNORD\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_FAUCR_S1UNORD_MASK (0x00000200)\r
- #define HCHIP_FAUCR_S1UNORD_SHIFT (0x00000009)\r
-\r
- #define HCHIP_FAUCR_S1UNORD_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_FAUCR_S1UNORD)\r
-\r
- #define HCHIP_FAUCR_S1UNORD_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_FAUCR_S1UNORD,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_FAUCR_S1DIV0\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_FAUCR_S1DIV0_MASK (0x00000400)\r
- #define HCHIP_FAUCR_S1DIV0_SHIFT (0x0000000A)\r
-\r
- #define HCHIP_FAUCR_S1DIV0_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_FAUCR_S1DIV0)\r
-\r
- #define HCHIP_FAUCR_S1DIV0_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_FAUCR_S1DIV0,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_FAUCR_S2NAN1\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_FAUCR_S2NAN1_MASK (0x00010000)\r
- #define HCHIP_FAUCR_S2NAN1_SHIFT (0x00000010)\r
-\r
- #define HCHIP_FAUCR_S2NAN1_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_FAUCR_S2NAN1)\r
-\r
- #define HCHIP_FAUCR_S2NAN1_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_FAUCR_S2NAN1,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_FAUCR_S2NAN2\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_FAUCR_S2NAN2_MASK (0x00020000)\r
- #define HCHIP_FAUCR_S2NAN2_SHIFT (0x00000011)\r
-\r
- #define HCHIP_FAUCR_S2NAN2_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_FAUCR_S2NAN2)\r
-\r
- #define HCHIP_FAUCR_S2NAN2_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_FAUCR_S2NAN2,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_FAUCR_S2DEN1\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_FAUCR_S2DEN1_MASK (0x00040000)\r
- #define HCHIP_FAUCR_S2DEN1_SHIFT (0x00000012)\r
-\r
- #define HCHIP_FAUCR_S2DEN1_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_FAUCR_S2DEN1)\r
-\r
- #define HCHIP_FAUCR_S2DEN1_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_FAUCR_S2DEN1,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_FAUCR_S2DEN2\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_FAUCR_S2DEN2_MASK (0x00080000)\r
- #define HCHIP_FAUCR_S2DEN2_SHIFT (0x00000013)\r
-\r
- #define HCHIP_FAUCR_S2DEN2_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_FAUCR_S2DEN2)\r
-\r
- #define HCHIP_FAUCR_S2DEN2_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_FAUCR_S2DEN2,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_FAUCR_S2INVAL\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_FAUCR_S2INVAL_MASK (0x00100000)\r
- #define HCHIP_FAUCR_S2INVAL_SHIFT (0x00000014)\r
-\r
- #define HCHIP_FAUCR_S2INVAL_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_FAUCR_S2INVAL)\r
-\r
- #define HCHIP_FAUCR_S2INVAL_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_FAUCR_S2INVAL,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_FAUCR_S2INFO\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_FAUCR_S2INFO_MASK (0x00200000)\r
- #define HCHIP_FAUCR_S2INFO_SHIFT (0x00000015)\r
-\r
- #define HCHIP_FAUCR_S2INFO_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_FAUCR_S2INFO)\r
-\r
- #define HCHIP_FAUCR_S2INFO_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_FAUCR_S2INFO,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_FAUCR_S2OVER\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_FAUCR_S2OVER_MASK (0x00400000)\r
- #define HCHIP_FAUCR_S2OVER_SHIFT (0x00000016)\r
-\r
- #define HCHIP_FAUCR_S2OVER_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_FAUCR_S2OVER)\r
-\r
- #define HCHIP_FAUCR_S2OVER_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_FAUCR_S2OVER,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_FAUCR_S2INEX\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_FAUCR_S2INEX_MASK (0x00800000)\r
- #define HCHIP_FAUCR_S2INEX_SHIFT (0x00000017)\r
-\r
- #define HCHIP_FAUCR_S2INEX_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_FAUCR_S2INEX)\r
-\r
- #define HCHIP_FAUCR_S2INEX_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_FAUCR_S2INEX,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_FAUCR_S2UNDER\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_FAUCR_S2UNDER_MASK (0x01000000)\r
- #define HCHIP_FAUCR_S2UNDER_SHIFT (0x00000018)\r
-\r
- #define HCHIP_FAUCR_S2UNDER_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_FAUCR_S2UNDER)\r
-\r
- #define HCHIP_FAUCR_S2UNDER_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_FAUCR_S2UNDER,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_FAUCR_S2UNORD\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_FAUCR_S2UNORD_MASK (0x02000000)\r
- #define HCHIP_FAUCR_S2UNORD_SHIFT (0x00000019)\r
-\r
- #define HCHIP_FAUCR_S2UNORD_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_FAUCR_S2UNORD)\r
-\r
- #define HCHIP_FAUCR_S2UNORD_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_FAUCR_S2UNORD,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_FAUCR_S2DIV0\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_FAUCR_S2DIV0_MASK (0x04000000)\r
- #define HCHIP_FAUCR_S2DIV0_SHIFT (0x0000001A)\r
-\r
- #define HCHIP_FAUCR_S2DIV0_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_FAUCR_S2DIV0)\r
-\r
- #define HCHIP_FAUCR_S2DIV0_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_FAUCR_S2DIV0,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_FADCR\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_FAUCR_GET(CrReg) HCRREG32_GET(CrReg)\r
-\r
- #define HCHIP_FAUCR_SET(CrReg,Val) HCRREG32_SET(CrReg,Val)\r
-\r
- #define HCHIP_FAUCR_CFG(CrReg,s1nan1,s1nan2,s1den1,s1den2,s1inval,s1info,\\r
- s1over,s1inex,s1under,s1unord,s1div0,s2nan1,s2nan2,s2den1,s2den2,s2inval,\\r
- s2info,s2over,s2inex,s2under,s2unord,s2div0) CrReg=(UINT32)( \\r
- HCRFIELD_SHIFT(HCHIP_FAUCR_S1NAN1, s1nan1) |\\r
- HCRFIELD_SHIFT(HCHIP_FAUCR_S1NAN2, s1nan2) |\\r
- HCRFIELD_SHIFT(HCHIP_FAUCR_S1DEN1, s1den1) |\\r
- HCRFIELD_SHIFT(HCHIP_FAUCR_S1DEN2, s1den2) |\\r
- HCRFIELD_SHIFT(HCHIP_FAUCR_S1INVAL,s1inval)|\\r
- HCRFIELD_SHIFT(HCHIP_FAUCR_S1INFO, s1info) |\\r
- HCRFIELD_SHIFT(HCHIP_FAUCR_S1OVER, s1over) |\\r
- HCRFIELD_SHIFT(HCHIP_FAUCR_S1INEX, s1inex) |\\r
- HCRFIELD_SHIFT(HCHIP_FAUCR_S1UNDER,s1under)|\\r
- HCRFIELD_SHIFT(HCHIP_FAUCR_S1UNORD,s1unord)|\\r
- HCRFIELD_SHIFT(HCHIP_FAUCR_S1DIV0, s1div0) |\\r
- HCRFIELD_SHIFT(HCHIP_FAUCR_S2NAN1, s2nan1) |\\r
- HCRFIELD_SHIFT(HCHIP_FAUCR_S2NAN2, s2nan2) |\\r
- HCRFIELD_SHIFT(HCHIP_FAUCR_S2DEN1, s2den1) |\\r
- HCRFIELD_SHIFT(HCHIP_FAUCR_S2DEN2, s2den2) |\\r
- HCRFIELD_SHIFT(HCHIP_FAUCR_S2INVAL,s2inval)|\\r
- HCRFIELD_SHIFT(HCHIP_FAUCR_S2INFO, s2info) |\\r
- HCRFIELD_SHIFT(HCHIP_FAUCR_S2OVER, s2over) |\\r
- HCRFIELD_SHIFT(HCHIP_FAUCR_S2INEX, s2inex) |\\r
- HCRFIELD_SHIFT(HCHIP_FAUCR_S2UNDER,s2under)|\\r
- HCRFIELD_SHIFT(HCHIP_FAUCR_S2UNORD,s2unord)|\\r
- HCRFIELD_SHIFT(HCHIP_FAUCR_S2DIV0, s2div0) \\r
- )\r
-#endif /* FPU_SUPPORT */\r
-\r
-#if (FPU_SUPPORT)\r
-/******************************************************************************\\r
-* HCHIP_FMCR - floating-point multiplier config register (1)\r
-*\r
-* (1) only supported on devices with floating point unit\r
-*\r
-* Fields: \r
-* (RW) HCHIP_FMCR_M1NAN1\r
-* (RW) HCHIP_FMCR_M1NAN2\r
-* (RW) HCHIP_FMCR_M1DEN1\r
-* (RW) HCHIP_FMCR_M1DEN2\r
-* (RW) HCHIP_FMCR_M1INVAL\r
-* (RW) HCHIP_FMCR_M1INFO\r
-* (RW) HCHIP_FMCR_M1OVER\r
-* (RW) HCHIP_FMCR_M1INEX\r
-* (RW) HCHIP_FMCR_M1UNDER\r
-* (RW) HCHIP_FMCR_M1RMODE\r
-* (RW) HCHIP_FMCR_M2NAN1\r
-* (RW) HCHIP_FMCR_M2NAN2\r
-* (RW) HCHIP_FMCR_M2DEN1\r
-* (RW) HCHIP_FMCR_M2DEN2\r
-* (RW) HCHIP_FMCR_M2INVAL\r
-* (RW) HCHIP_FMCR_M2INFO\r
-* (RW) HCHIP_FMCR_M2OVER\r
-* (RW) HCHIP_FMCR_M2INEX\r
-* (RW) HCHIP_FMCR_M2UNDER\r
-* (RW) HCHIP_FMCR_M2RMODE\r
-*\r
-\******************************************************************************/\r
- extern far cregister volatile unsigned int FMCR;\r
- #define HCHIP_FMCR FMCR\r
- \r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_FMCR_M1NAN1\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_FMCR_M1NAN1_MASK (0x00000001)\r
- #define HCHIP_FMCR_M1NAN1_SHIFT (0x00000000)\r
-\r
- #define HCHIP_FMCR_M1NAN1_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_FMCR_M1NAN1)\r
-\r
- #define HCHIP_FMCR_M1NAN1_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_FMCR_M1NAN1,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_FMCR_M1NAN2\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_FMCR_M1NAN2_MASK (0x00000002)\r
- #define HCHIP_FMCR_M1NAN2_SHIFT (0x00000001)\r
-\r
- #define HCHIP_FMCR_M1NAN2_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_FMCR_M1NAN2)\r
-\r
- #define HCHIP_FMCR_M1NAN2_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_FMCR_M1NAN2,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_FMCR_M1DEN1\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_FMCR_M1DEN1_MASK (0x00000004)\r
- #define HCHIP_FMCR_M1DEN1_SHIFT (0x00000002)\r
-\r
- #define HCHIP_FMCR_M1DEN1_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_FMCR_M1DEN1)\r
-\r
- #define HCHIP_FMCR_M1DEN1_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_FMCR_M1DEN1,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_FMCR_M1DEN2\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_FMCR_M1DEN2_MASK (0x00000008)\r
- #define HCHIP_FMCR_M1DEN2_SHIFT (0x00000003)\r
-\r
- #define HCHIP_FMCR_M1DEN2_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_FMCR_M1DEN2)\r
-\r
- #define HCHIP_FMCR_M1DEN2_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_FMCR_M1DEN2,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_FMCR_M1INVAL\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_FMCR_M1INVAL_MASK (0x00000010)\r
- #define HCHIP_FMCR_M1INVAL_SHIFT (0x00000004)\r
-\r
- #define HCHIP_FMCR_M1INVAL_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_FMCR_M1INVAL)\r
-\r
- #define HCHIP_FMCR_M1INVAL_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_FMCR_M1INVAL,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_FMCR_M1INFO\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_FMCR_M1INFO_MASK (0x00000020)\r
- #define HCHIP_FMCR_M1INFO_SHIFT (0x00000005)\r
-\r
- #define HCHIP_FMCR_M1INFO_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_FMCR_M1INFO)\r
-\r
- #define HCHIP_FMCR_M1INFO_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_FMCR_M1INFO,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_FMCR_M1OVER\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_FMCR_M1OVER_MASK (0x00000040)\r
- #define HCHIP_FMCR_M1OVER_SHIFT (0x00000006)\r
-\r
- #define HCHIP_FMCR_M1OVER_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_FMCR_M1OVER)\r
-\r
- #define HCHIP_FMCR_M1OVER_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_FMCR_M1OVER,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_FMCR_M1INEX\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_FMCR_M1INEX_MASK (0x00000080)\r
- #define HCHIP_FMCR_M1INEX_SHIFT (0x00000007)\r
-\r
- #define HCHIP_FMCR_M1INEX_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_FMCR_M1INEX)\r
-\r
- #define HCHIP_FMCR_M1INEX_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_FMCR_M1INEX,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_FMCR_M1UNDER\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_FMCR_M1UNDER_MASK (0x00000100)\r
- #define HCHIP_FMCR_M1UNDER_SHIFT (0x00000008)\r
-\r
- #define HCHIP_FMCR_M1UNDER_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_FMCR_M1UNDER)\r
-\r
- #define HCHIP_FMCR_M1UNDER_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_FMCR_M1UNDER,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_FMCR_M1RMODE\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_FMCR_M1RMODE_MASK (0x00000600)\r
- #define HCHIP_FMCR_M1RMODE_SHIFT (0x00000009)\r
-\r
- #define HCHIP_FMCR_M1RMODE_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_FMCR_M1RMODE)\r
-\r
- #define HCHIP_FMCR_M1RMODE_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_FMCR_M1RMODE,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_FMCR_M2NAN1\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_FMCR_M2NAN1_MASK (0x00010000)\r
- #define HCHIP_FMCR_M2NAN1_SHIFT (0x00000010)\r
-\r
- #define HCHIP_FMCR_M2NAN1_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_FMCR_M2NAN1)\r
-\r
- #define HCHIP_FMCR_M2NAN1_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_FMCR_M2NAN1,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_FMCR_M2NAN2\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_FMCR_M2NAN2_MASK (0x00020000)\r
- #define HCHIP_FMCR_M2NAN2_SHIFT (0x00000011)\r
-\r
- #define HCHIP_FMCR_M2NAN2_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_FMCR_M2NAN2)\r
-\r
- #define HCHIP_FMCR_M2NAN2_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_FMCR_M2NAN2,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_FMCR_M2DEN1\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_FMCR_M2DEN1_MASK (0x00040000)\r
- #define HCHIP_FMCR_M2DEN1_SHIFT (0x00000012)\r
-\r
- #define HCHIP_FMCR_M2DEN1_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_FMCR_M2DEN1)\r
-\r
- #define HCHIP_FMCR_M2DEN1_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_FMCR_M2DEN1,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_FMCR_M2DEN2\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_FMCR_M2DEN2_MASK (0x00080000)\r
- #define HCHIP_FMCR_M2DEN2_SHIFT (0x00000013)\r
-\r
- #define HCHIP_FMCR_M2DEN2_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_FMCR_M2DEN2)\r
-\r
- #define HCHIP_FMCR_M2DEN2_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_FMCR_M2DEN2,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_FMCR_M2INVAL\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_FMCR_M2INVAL_MASK (0x00100000)\r
- #define HCHIP_FMCR_M2INVAL_SHIFT (0x00000014)\r
-\r
- #define HCHIP_FMCR_M2INVAL_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_FMCR_M2INVAL)\r
-\r
- #define HCHIP_FMCR_M2INVAL_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_FMCR_M2INVAL,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_FMCR_M2INFO\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_FMCR_M2INFO_MASK (0x00200000)\r
- #define HCHIP_FMCR_M2INFO_SHIFT (0x00000015)\r
-\r
- #define HCHIP_FMCR_M2INFO_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_FMCR_M2INFO)\r
-\r
- #define HCHIP_FMCR_M2INFO_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_FMCR_M2INFO,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_FMCR_M2OVER\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_FMCR_M2OVER_MASK (0x00400000)\r
- #define HCHIP_FMCR_M2OVER_SHIFT (0x00000016)\r
-\r
- #define HCHIP_FMCR_M2OVER_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_FMCR_M2OVER)\r
-\r
- #define HCHIP_FMCR_M2OVER_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_FMCR_M2OVER,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_FMCR_M2INEX\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_FMCR_M2INEX_MASK (0x00800000)\r
- #define HCHIP_FMCR_M2INEX_SHIFT (0x00000017)\r
-\r
- #define HCHIP_FMCR_M2INEX_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_FMCR_M2INEX)\r
-\r
- #define HCHIP_FMCR_M2INEX_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_FMCR_M2INEX,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_FMCR_M2UNDER\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_FMCR_M2UNDER_MASK (0x01000000)\r
- #define HCHIP_FMCR_M2UNDER_SHIFT (0x00000018)\r
-\r
- #define HCHIP_FMCR_M2UNDER_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_FMCR_M2UNDER)\r
-\r
- #define HCHIP_FMCR_M2UNDER_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_FMCR_M2UNDER,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_FMCR_M2RMODE\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_FMCR_M2RMODE_MASK (0x06000000)\r
- #define HCHIP_FMCR_M2RMODE_SHIFT (0x00000019)\r
-\r
- #define HCHIP_FMCR_M2RMODE_GET(CrReg) \\r
- HCRFIELD_GET(CrReg,HCHIP_FMCR_M2RMODE)\r
-\r
- #define HCHIP_FMCR_M2RMODE_SET(CrReg,Val) \\r
- HCRFIELD_SET(CrReg,HCHIP_FMCR_M2RMODE,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCHIP_FMCR\r
-\*----------------------------------------------------------------------------*/\r
- #define HCHIP_FMCR_GET(CrReg) HCRREG32_GET(CrReg)\r
-\r
- #define HCHIP_FMCR_SET(CrReg,Val) HCRREG32_SET(CrReg,Val)\r
-\r
- #define HCHIP_FMCR_CFG(CrReg,m1nan1,m1nan2,m1den1,m1den2,m1inval,m1info,\\r
- m1over,m1inex,m1under,m1rmode,m2nan1,m2nan2,m2den1,m2den2,m2inval,m2info,\\r
- m2over,m2inex,m2under,m2rmode) CrReg=(UINT32)( \\r
- HSHIFT_FDIELD(HCHIP_FMCR_M1NAN1, m1nan1) |\\r
- HSHIFT_FDIELD(HCHIP_FMCR_M1NAN2, m1nan2) |\\r
- HSHIFT_FDIELD(HCHIP_FMCR_M1DEN1, m1den1) |\\r
- HSHIFT_FDIELD(HCHIP_FMCR_M1DEN2, m1den2) |\\r
- HSHIFT_FDIELD(HCHIP_FMCR_M1INVAL,m1inval)|\\r
- HSHIFT_FDIELD(HCHIP_FMCR_M1INFO, m1info) |\\r
- HSHIFT_FDIELD(HCHIP_FMCR_M1OVER, m1over) |\\r
- HSHIFT_FDIELD(HCHIP_FMCR_M1INEX, m1inex) |\\r
- HSHIFT_FDIELD(HCHIP_FMCR_M1UNDER,m1under)|\\r
- HSHIFT_FDIELD(HCHIP_FMCR_M1RMODE,m1rmode)|\\r
- HSHIFT_FDIELD(HCHIP_FMCR_M2NAN1, m2nan1) |\\r
- HSHIFT_FDIELD(HCHIP_FMCR_M2NAN2, m2nan2) |\\r
- HSHIFT_FDIELD(HCHIP_FMCR_M2DEN1, m2den1) |\\r
- HSHIFT_FDIELD(HCHIP_FMCR_M2DEN2, m2den2) |\\r
- HSHIFT_FDIELD(HCHIP_FMCR_M2INVAL,m2inval)|\\r
- HSHIFT_FDIELD(HCHIP_FMCR_M2INFO, m2info) |\\r
- HSHIFT_FDIELD(HCHIP_FMCR_M2OVER, m2over) |\\r
- HSHIFT_FDIELD(HCHIP_FMCR_M2INEX, m2inex) |\\r
- HSHIFT_FDIELD(HCHIP_FMCR_M2UNDER,m2under)|\\r
- HSHIFT_FDIELD(HCHIP_FMCR_M2RMODE,m2rmode) \\r
- )\r
-#endif /* FPU_SUPPORT */\r
-\r
-/******************************************************************************/\r
-\r
-#endif /* _CHIPHAL_H_ */\r
-/******************************************************************************\\r
-* End of chiphal.h\r
-\******************************************************************************/\r
-\r
-\r
-\r
-/******************************************************************************\\r
-* Copyright (C) 1999-2000 Texas Instruments Incorporated.\r
-* All Rights Reserved\r
-*------------------------------------------------------------------------------\r
-* FILENAME...... cachehal.h\r
-* DATE CREATED.. 06/12/1999 \r
-* LAST MODIFIED. 03/08/2000\r
-* \r
-*------------------------------------------------------------------------------\r
-* DESCRIPTION: (HAL interface file for the CACHE module)\r
-*\r
-* Registers Covered:\r
-* HCACHE_CCFG - cache configuration register\r
-* HCACHE_L2FBAR - L2 flush base address register\r
-* HCACHE_L2FWC - L2 flush word count register\r
-* HCACHE_L2CBAR - L2 clean base register\r
-* HCACHE_L2CWC - L2 clean word count register\r
-* HCACHE_L1PFBAR - L1P flush base address register\r
-* HCACHE_L1PFWC - L1P flush word count register\r
-* HCACHE_L1DFBAR - L1D flush base address register\r
-* HCACHE_L1DFWC - L1D flush word count register\r
-* HCACHE_L2FLUSH - L2 flush register\r
-* HCACHE_L2CLEAN - L2 clean register\r
-* HCACHE_MAR0 - memory attribute register, region 0\r
-* HCACHE_MAR1 - memory attribute register, region 1\r
-* HCACHE_MAR2 - memory attribute register, region 2\r
-* HCACHE_MAR3 - memory attribute register, region 3\r
-* HCACHE_MAR4 - memory attribute register, region 4\r
-* HCACHE_MAR5 - memory attribute register, region 5\r
-* HCACHE_MAR6 - memory attribute register, region 6\r
-* HCACHE_MAR7 - memory attribute register, region 7\r
-* HCACHE_MAR8 - memory attribute register, region 8\r
-* HCACHE_MAR9 - memory attribute register, region 9\r
-* HCACHE_MAR10 - memory attribute register, region 10\r
-* HCACHE_MAR11 - memory attribute register, region 11\r
-* HCACHE_MAR12 - memory attribute register, region 12\r
-* HCACHE_MAR13 - memory attribute register, region 13\r
-* HCACHE_MAR14 - memory attribute register, region 14\r
-* HCACHE_MAR15 - memory attribute register, region 15\r
-*\r
-\******************************************************************************/\r
-#ifndef _CACHEHAL_H_\r
-#define _CACHEHAL_H_\r
-\r
-#if (CACHE_SUPPORT)\r
-/*============================================================================*\\r
-* misc declarations\r
-\*============================================================================*/\r
- #define HCACHE_BASE_ADDR (HCHIP_PERBASE_ADDR+0x00040000)\r
-\r
-/******************************************************************************\\r
-* HCACHE_CCFG - cache configuration register\r
-*\r
-* Fields:\r
-* (RW) HCACHE_CCFG_L2MODE\r
-* (RW) HCACHE_CCFG_ID\r
-* (RW) HCACHE_CCFG_IP\r
-* (RW) HCACHE_CCFG_P\r
-*\r
-\******************************************************************************/\r
- #define HCACHE_CCFG_ADDR (HCACHE_BASE_ADDR+0x0000)\r
- #define HCACHE_CCFG REG32(HCACHE_CCFG_ADDR)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCACHE_CCFG_L2MODE\r
-\*----------------------------------------------------------------------------*/\r
- #define HCACHE_CCFG_L2MODE_MASK (0x00000007)\r
- #define HCACHE_CCFG_L2MODE_SHIFT (0x00000000)\r
-\r
- #define HCACHE_CCFG_L2MODE_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HCACHE_CCFG_L2MODE)\r
-\r
- #define HCACHE_CCFG_L2MODE_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HCACHE_CCFG_L2MODE,Val)\r
- \r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCACHE_CCFG_ID\r
-\*----------------------------------------------------------------------------*/\r
- #define HCACHE_CCFG_ID_MASK (0x00000100)\r
- #define HCACHE_CCFG_ID_SHIFT (0x00000008)\r
-\r
- #define HCACHE_CCFG_ID_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HCACHE_CCFG_ID)\r
-\r
- #define HCACHE_CCFG_ID_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HCACHE_CCFG_ID,Val)\r
- \r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCACHE_CCFG_IP\r
-\*----------------------------------------------------------------------------*/\r
- #define HCACHE_CCFG_IP_MASK (0x00000200)\r
- #define HCACHE_CCFG_IP_SHIFT (0x00000009)\r
-\r
- #define HCACHE_CCFG_IP_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HCACHE_CCFG_IP)\r
-\r
- #define HCACHE_CCFG_IP_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HCACHE_CCFG_IP,Val)\r
- \r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCACHE_CCFG_P\r
-\*----------------------------------------------------------------------------*/\r
- #define HCACHE_CCFG_P_MASK (0x80000000)\r
- #define HCACHE_CCFG_P_SHIFT (0x0000001F)\r
-\r
- #define HCACHE_CCFG_P_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HCACHE_CCFG_P)\r
-\r
- #define HCACHE_CCFG_P_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HCACHE_CCFG_P,Val)\r
- \r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCACHE_CCFG\r
-\*----------------------------------------------------------------------------*/\r
- #define HCACHE_CCFG_GET(RegAddr) HREG32_GET(RegAddr)\r
- #define HCACHE_CCFG_SET(RegAddr,Val) HREG32_SET(RegAddr,Val)\r
-\r
- #define HCACHE_CCFG_CFG(RegAddr,l2mode,id,ip,p) REG32(RegAddr) = (UINT32)( \\r
- HFIELD_SHIFT(HCACHE_CCFG_L2MODE,l2mode)| \\r
- HFIELD_SHIFT(HCACHE_CCFG_ID,id)| \\r
- HFIELD_SHIFT(HCACHE_CCFG_IP,ip)| \\r
- HFIELD_SHIFT(HCACHE_CCFG_P,p) \\r
- )\r
-\r
-/******************************************************************************\\r
-* HCACHE_L2FBAR - L2 flush base address register\r
-*\r
-* Fields:\r
-* (RW) HCACHE_L2FBAR_L2FBAR\r
-*\r
-\******************************************************************************/\r
- #define HCACHE_L2FBAR_ADDR (HCACHE_BASE_ADDR+0x4000)\r
- #define HCACHE_L2FBAR REG32(HCACHE_L2FBAR_ADDR)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCACHE_L2FBAR_L2FBAR\r
-\*----------------------------------------------------------------------------*/\r
- #define HCACHE_L2FBAR_L2FBAR_MASK (0xFFFFFFFF)\r
- #define HCACHE_L2FBAR_L2FBAR_SHIFT (0x00000000)\r
-\r
- #define HCACHE_L2FBAR_L2FBAR_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HCACHE_L2FBAR_L2FBAR)\r
-\r
- #define HCACHE_L2FBAR_L2FBAR_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HCACHE_L2FBAR_L2FBAR,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCACHE_L2FBAR\r
-\*----------------------------------------------------------------------------*/\r
- #define HCACHE_L2FBAR_GET(RegAddr) HREG32_GET(RegAddr)\r
- #define HCACHE_L2FBAR_SET(RegAddr,Val) HREG32_SET(RegAddr,Val)\r
-\r
- #define HCACHE_L2FBAR_CFG(RegAddr,l2fbar) REG32(RegAddr) = (UINT32)( \\r
- HFIELD_SHIFT(HCACHE_L2FBAR_L2FBAR,l2fbar) \\r
- )\r
-\r
-/******************************************************************************\\r
-* HCACHE_L2FWC - L2 flush word count register\r
-*\r
-* Fields:\r
-* (RW) HCACHE_L2FWC_L2FWC\r
-*\r
-\******************************************************************************/\r
- #define HCACHE_L2FWC_ADDR (HCACHE_BASE_ADDR+0x4004)\r
- #define HCACHE_L2FWC REG32(HCACHE_L2FWC_ADDR)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCACHE_L2FWC_L2FWC\r
-\*----------------------------------------------------------------------------*/\r
- #define HCACHE_L2FWC_L2FWC_MASK (0x0000FFFF)\r
- #define HCACHE_L2FWC_L2FWC_SHIFT (0x00000000)\r
-\r
- #define HCACHE_L2FWC_L2FWC_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HCACHE_L2FWC_L2FWC)\r
-\r
- #define HCACHE_L2FWC_L2FWC_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HCACHE_L2FWC_L2FWC,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCACHE_L2FWC\r
-\*----------------------------------------------------------------------------*/\r
- #define HCACHE_L2FWC_GET(RegAddr) HREG32_GET(RegAddr)\r
- #define HCACHE_L2FWC_SET(RegAddr,Val) HREG32_SET(RegAddr,Val)\r
-\r
- #define HCACHE_L2FWC_CFG(RegAddr,l2fwc) REG32(RegAddr) = (UINT32)( \\r
- HFIELD_SHIFT(HCACHE_L2FWC_L2FWC,l2fwc) \\r
- )\r
-\r
-/******************************************************************************\\r
-* HCACHE_L2CBAR - L2 clean base register\r
-*\r
-* Fields:\r
-* (RW) HCACHE_L2CBAR_L2CBAR\r
-*\r
-\******************************************************************************/\r
- #define HCACHE_L2CBAR_ADDR (HCACHE_BASE_ADDR+0x4010)\r
- #define HCACHE_L2CBAR REG32(HCACHE_L2CBAR_ADDR)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCACHE_L2CBAR_L2CBAR\r
-\*----------------------------------------------------------------------------*/\r
- #define HCACHE_L2CBAR_L2CBAR_MASK (0xFFFFFFFF)\r
- #define HCACHE_L2CBAR_L2CBAR_SHIFT (0x00000000)\r
-\r
- #define HCACHE_L2CBAR_L2CBAR_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HCACHE_L2CBAR_L2CBAR)\r
-\r
- #define HCACHE_L2CBAR_L2CBAR_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HCACHE_L2CBAR_L2CBAR,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCACHE_L2CBAR\r
-\*----------------------------------------------------------------------------*/\r
- #define HCACHE_L2CBAR_GET(RegAddr) HREG32_GET(RegAddr)\r
- #define HCACHE_L2CBAR_SET(RegAddr,Val) HREG32_SET(RegAddr,Val)\r
-\r
- #define HCACHE_L2CBAR_CFG(RegAddr,l2cbar) REG32(RegAddr) = (UINT32)( \\r
- HFIELD_SHIFT(HCACHE_L2CBAR_L2CBAR,l2cbar) \\r
- )\r
-\r
-/******************************************************************************\\r
-* HCACHE_L2CWC - L2 clean word count register\r
-*\r
-* Fields:\r
-* (RW) HCACHE_L2CWC_L2CWC\r
-*\r
-\******************************************************************************/\r
- #define HCACHE_L2CWC_ADDR (HCACHE_BASE_ADDR+0x4014)\r
- #define HCACHE_L2CWC REG32(HCACHE_L2CWC_ADDR)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCACHE_L2CWC_L2CWC\r
-\*----------------------------------------------------------------------------*/\r
- #define HCACHE_L2CWC_L2CWC_MASK (0x0000FFFF)\r
- #define HCACHE_L2CWC_L2CWC_SHIFT (0x00000000)\r
-\r
- #define HCACHE_L2CWC_L2CWC_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HCACHE_L2CWC_L2CWC)\r
-\r
- #define HCACHE_L2CWC_L2CWC_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HCACHE_L2CWC_L2CWC,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCACHE_L2CWC\r
-\*----------------------------------------------------------------------------*/\r
- #define HCACHE_L2CWC_GET(RegAddr) HREG32_GET(RegAddr)\r
- #define HCACHE_L2CWC_SET(RegAddr,Val) HREG32_SET(RegAddr,Val)\r
-\r
- #define HCACHE_L2CWC_CFG(RegAddr,l2cwc) REG32(RegAddr) = (UINT32)( \\r
- HFIELD_SHIFT(HCACHE_L2CWC_L2CWC,l2cwc) \\r
- )\r
-\r
-/******************************************************************************\\r
-* HCACHE_L1PFBAR - L1P flush base address register\r
-*\r
-* Fields:\r
-* (RW) HCACHE_L1PFBAR_L1PFBAR\r
-*\r
-\******************************************************************************/\r
- #define HCACHE_L1PFBAR_ADDR (HCACHE_BASE_ADDR+0x4020)\r
- #define HCACHE_L1PFBAR REG32(HCACHE_L1PFBAR_ADDR)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCACHE_L1PFBAR_L1PFBAR\r
-\*----------------------------------------------------------------------------*/\r
- #define HCACHE_L1PFBAR_L1PFBAR_MASK (0xFFFFFFFF)\r
- #define HCACHE_L1PFBAR_L1PFBAR_SHIFT (0x00000000)\r
-\r
- #define HCACHE_L1PFBAR_L1PFBAR_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HCACHE_L1PFBAR_L1PFBAR)\r
-\r
- #define HCACHE_L1PFBAR_L1PFBAR_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HCACHE_L1PFBAR_L1PFBAR,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCACHE_L1PFBAR\r
-\*----------------------------------------------------------------------------*/\r
- #define HCACHE_L1PFBAR_GET(RegAddr) HREG32_GET(RegAddr)\r
- #define HCACHE_L1PFBAR_SET(RegAddr,Val) HREG32_SET(RegAddr,Val)\r
-\r
- #define HCACHE_L1PFBAR_CFG(RegAddr,l1pfbar) REG32(RegAddr) = (UINT32)( \\r
- HFIELD_SHIFT(HCACHE_L1PFBAR_L1PFBAR,l1pfbar) \\r
- )\r
-\r
-/******************************************************************************\\r
-* HCACHE_L1PFWC - L1P flush word count register\r
-*\r
-* Fields:\r
-* (RW) HCACHE_L1PFWC_L1PFWC\r
-*\r
-\******************************************************************************/\r
- #define HCACHE_L1PFWC_ADDR (HCACHE_BASE_ADDR+0x4024)\r
- #define HCACHE_L1PFWC REG32(HCACHE_L1PFWC_ADDR)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCACHE_L1PFWC_L1PFWC\r
-\*----------------------------------------------------------------------------*/\r
- #define HCACHE_L1PFWC_L1PFWC_MASK (0x0000FFFF)\r
- #define HCACHE_L1PFWC_L1PFWC_SHIFT (0x00000000)\r
-\r
- #define HCACHE_L1PFWC_L1PFWC_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HCACHE_L1PFWC_L1PFWC)\r
-\r
- #define HCACHE_L1PFWC_L1PFWC_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HCACHE_L1PFWC_L1PFWC,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCACHE_L1PFWC\r
-\*----------------------------------------------------------------------------*/\r
- #define HCACHE_L1PFWC_GET(RegAddr) HREG32_GET(RegAddr)\r
- #define HCACHE_L1PFWC_SET(RegAddr,Val) HREG32_SET(RegAddr,Val)\r
-\r
- #define HCACHE_L1PFWC_CFG(RegAddr,l1pfwc) REG32(RegAddr) = (UINT32)( \\r
- HFIELD_SHIFT(HCACHE_L1PFWC_L1PFWC,l1pfwc) \\r
- )\r
-\r
-/******************************************************************************\\r
-* HCACHE_L1DFBAR - L1D flush base address register\r
-*\r
-* Fields:\r
-* (RW) HCACHE_L1DFBAR_L1DFBAR\r
-*\r
-\******************************************************************************/\r
- #define HCACHE_L1DFBAR_ADDR (HCACHE_BASE_ADDR+0x4030)\r
- #define HCACHE_L1DFBAR REG32(HCACHE_L1DFBAR_ADDR)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCACHE_L1DFBAR_L1DFBAR\r
-\*----------------------------------------------------------------------------*/\r
- #define HCACHE_L1DFBAR_L1DFBAR_MASK (0xFFFFFFFF)\r
- #define HCACHE_L1DFBAR_L1DFBAR_SHIFT (0x00000000)\r
-\r
- #define HCACHE_L1DFBAR_L1DFBAR_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HCACHE_L1DFBAR_L1DFBAR)\r
-\r
- #define HCACHE_L1DFBAR_L1DFBAR_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HCACHE_L1DFBAR_L1DFBAR,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCACHE_L1DFBAR\r
-\*----------------------------------------------------------------------------*/\r
- #define HCACHE_L1DFBAR_GET(RegAddr) HREG32_GET(RegAddr)\r
- #define HCACHE_L1DFBAR_SET(RegAddr,Val) HREG32_SET(RegAddr,Val)\r
-\r
- #define HCACHE_L1DFBAR_CFG(RegAddr,l1dfbar) REG32(RegAddr) = (UINT32)( \\r
- HFIELD_SHIFT(HCACHE_L1DFBAR_L1DFBAR,l1dfbar) \\r
- )\r
-\r
-/******************************************************************************\\r
-* HCACHE_L1DFWC - L1D flush word count register\r
-*\r
-* Fields:\r
-* (RW) HCACHE_L1DFWC_L1DFWC\r
-*\r
-\******************************************************************************/\r
- #define HCACHE_L1DFWC_ADDR (HCACHE_BASE_ADDR+0x4034)\r
- #define HCACHE_L1DFWC REG32(HCACHE_L1DFWC_ADDR)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCACHE_L1DFWC_L1DFWC\r
-\*----------------------------------------------------------------------------*/\r
- #define HCACHE_L1DFWC_L1DFWC_MASK (0x0000FFFF)\r
- #define HCACHE_L1DFWC_L1DFWC_SHIFT (0x00000000)\r
-\r
- #define HCACHE_L1DFWC_L1DFWC_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HCACHE_L1DFWC_L1DFWC)\r
-\r
- #define HCACHE_L1DFWC_L1DFWC_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HCACHE_L1DFWC_L1DFWC,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCACHE_L1DFWC\r
-\*----------------------------------------------------------------------------*/\r
- #define HCACHE_L1DFWC_GET(RegAddr) HREG32_GET(RegAddr)\r
- #define HCACHE_L1DFWC_SET(RegAddr,Val) HREG32_SET(RegAddr,Val)\r
- \r
- #define HCACHE_L1DFWC_CFG(RegAddr,l1dfwc) REG32(RegAddr) = (UINT32)( \\r
- HFIELD_SHIFT(HCACHE_L1DFWC_L1DFWC,l1dfwc) \\r
- )\r
-\r
-/******************************************************************************\\r
-* HCACHE_L2FLUSH - L2 flush register\r
-*\r
-* Fields:\r
-* (RW) HCACHE_L2FLUSH_F\r
-*\r
-\******************************************************************************/\r
- #define HCACHE_L2FLUSH_ADDR (HCACHE_BASE_ADDR+0x5000)\r
- #define HCACHE_L2FLUSH REG32(HCACHE_L2FLUSH_ADDR)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCACHE_L2FLUSH_F\r
-\*----------------------------------------------------------------------------*/\r
- #define HCACHE_L2FLUSH_F_MASK (0x00000001)\r
- #define HCACHE_L2FLUSH_F_SHIFT (0x00000000)\r
-\r
- #define HCACHE_L2FLUSH_F_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HCACHE_L2FLUSH_F)\r
-\r
- #define HCACHE_L2FLUSH_F_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HCACHE_L2FLUSH_F,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCACHE_L2FLUSH\r
-\*----------------------------------------------------------------------------*/\r
- #define HCACHE_L2FLUSH_GET(RegAddr) HREG32_GET(RegAddr)\r
- #define HCACHE_L2FLUSH_SET(RegAddr,Val) HREG32_SET(RegAddr,Val)\r
-\r
- #define HCACHE_L2FLUSH_CFG(RegAddr,f) REG32(RegAddr) = (UINT32)( \\r
- HFIELD_SHIFT(HCACHE_L2FLUSH_F,f) \\r
- )\r
-\r
-/******************************************************************************\\r
-* HCACHE_L2CLEAN - L2 clean register\r
-*\r
-* Fields:\r
-* (RW) HCACHE_L2CLEAN_C\r
-*\r
-\******************************************************************************/\r
- #define HCACHE_L2CLEAN_ADDR (HCACHE_BASE_ADDR+0x5004)\r
- #define HCACHE_L2CLEAN REG32(HCACHE_L2CLEAN_ADDR)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCACHE_L2CLEAN_C\r
-\*----------------------------------------------------------------------------*/\r
- #define HCACHE_L2CLEAN_C_MASK (0x00000001)\r
- #define HCACHE_L2CLEAN_C_SHIFT (0x00000000)\r
-\r
- #define HCACHE_L2CLEAN_C_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HCACHE_L2CLEAN_C)\r
-\r
- #define HCACHE_L2CLEAN_C_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HCACHE_L2CLEAN_C,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCACHE_L2CLEAN\r
-\*----------------------------------------------------------------------------*/\r
- #define HCACHE_L2CLEAN_GET(RegAddr) HREG32_GET(RegAddr)\r
- #define HCACHE_L2CLEAN_SET(RegAddr,Val) HREG32_SET(RegAddr,Val)\r
-\r
- #define HCACHE_L2CLEAN_CFG(RegAddr,c) REG32(RegAddr) = (UINT32)( \\r
- HFIELD_SHIFT(HCACHE_L2CLEAN_C,c) \\r
- )\r
-\r
-/******************************************************************************\\r
-* HCACHE_MAR0 - memory attribute register 0 (16M) 0x80000000->0x80FFFFFF\r
-* HCACHE_MAR1 - memory attribute register 1 (16M) 0x81000000->0x81FFFFFF\r
-* HCACHE_MAR2 - memory attribute register 2 (16M) 0x82000000->0x82FFFFFF\r
-* HCACHE_MAR3 - memory attribute register 3 (16M) 0x83000000->0x83FFFFFF\r
-* HCACHE_MAR4 - memory attribute register 4 (16M) 0x90000000->0x90FFFFFF\r
-* HCACHE_MAR5 - memory attribute register 5 (16M) 0x91000000->0x91FFFFFF\r
-* HCACHE_MAR6 - memory attribute register 6 (16M) 0x92000000->0x92FFFFFF\r
-* HCACHE_MAR7 - memory attribute register 7 (16M) 0x93000000->0x93FFFFFF\r
-* HCACHE_MAR8 - memory attribute register 8 (16M) 0xA0000000->0xA0FFFFFF\r
-* HCACHE_MAR9 - memory attribute register 9 (16M) 0xA1000000->0xA1FFFFFF\r
-* HCACHE_MAR10 - memory attribute register 10 (16M) 0xA2000000->0xA2FFFFFF\r
-* HCACHE_MAR11 - memory attribute register 11 (16M) 0xA3000000->0xA3FFFFFF\r
-* HCACHE_MAR12 - memory attribute register 12 (16M) 0xB0000000->0xB0FFFFFF\r
-* HCACHE_MAR13 - memory attribute register 13 (16M) 0xB1000000->0xB1FFFFFF\r
-* HCACHE_MAR14 - memory attribute register 14 (16M) 0xB2000000->0xB2FFFFFF\r
-* HCACHE_MAR15 - memory attribute register 15 (16M) 0xB3000000->0xB3FFFFFF\r
-*\r
-* Fields:\r
-* (RW) HCACHE_MAR_CE\r
-*\r
-\******************************************************************************/\r
- #define HCACHE_MAR0_ADDR (HCACHE_BASE_ADDR+0x8200)\r
- #define HCACHE_MAR1_ADDR (HCACHE_BASE_ADDR+0x8204)\r
- #define HCACHE_MAR2_ADDR (HCACHE_BASE_ADDR+0x8208)\r
- #define HCACHE_MAR3_ADDR (HCACHE_BASE_ADDR+0x820C)\r
- #define HCACHE_MAR4_ADDR (HCACHE_BASE_ADDR+0x8240)\r
- #define HCACHE_MAR5_ADDR (HCACHE_BASE_ADDR+0x8244)\r
- #define HCACHE_MAR6_ADDR (HCACHE_BASE_ADDR+0x8248)\r
- #define HCACHE_MAR7_ADDR (HCACHE_BASE_ADDR+0x824C)\r
- #define HCACHE_MAR8_ADDR (HCACHE_BASE_ADDR+0x8280)\r
- #define HCACHE_MAR9_ADDR (HCACHE_BASE_ADDR+0x8284)\r
- #define HCACHE_MAR10_ADDR (HCACHE_BASE_ADDR+0x8288)\r
- #define HCACHE_MAR11_ADDR (HCACHE_BASE_ADDR+0x828C)\r
- #define HCACHE_MAR12_ADDR (HCACHE_BASE_ADDR+0x82C0)\r
- #define HCACHE_MAR13_ADDR (HCACHE_BASE_ADDR+0x82C4)\r
- #define HCACHE_MAR14_ADDR (HCACHE_BASE_ADDR+0x82C8)\r
- #define HCACHE_MAR15_ADDR (HCACHE_BASE_ADDR+0x82CC)\r
- \r
- #define HCACHE_MAR0 REG32(HCACHE_MAR0_ADDR)\r
- #define HCACHE_MAR1 REG32(HCACHE_MAR1_ADDR)\r
- #define HCACHE_MAR2 REG32(HCACHE_MAR2_ADDR)\r
- #define HCACHE_MAR3 REG32(HCACHE_MAR3_ADDR)\r
- #define HCACHE_MAR4 REG32(HCACHE_MAR4_ADDR)\r
- #define HCACHE_MAR5 REG32(HCACHE_MAR5_ADDR)\r
- #define HCACHE_MAR6 REG32(HCACHE_MAR6_ADDR)\r
- #define HCACHE_MAR7 REG32(HCACHE_MAR7_ADDR)\r
- #define HCACHE_MAR8 REG32(HCACHE_MAR8_ADDR)\r
- #define HCACHE_MAR9 REG32(HCACHE_MAR9_ADDR)\r
- #define HCACHE_MAR10 REG32(HCACHE_MAR10_ADDR)\r
- #define HCACHE_MAR11 REG32(HCACHE_MAR11_ADDR)\r
- #define HCACHE_MAR12 REG32(HCACHE_MAR12_ADDR)\r
- #define HCACHE_MAR13 REG32(HCACHE_MAR13_ADDR)\r
- #define HCACHE_MAR14 REG32(HCACHE_MAR14_ADDR)\r
- #define HCACHE_MAR15 REG32(HCACHE_MAR15_ADDR)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCACHE_MAR_CE\r
-\*----------------------------------------------------------------------------*/\r
- #define HCACHE_MAR_CE_MASK (0x00000001)\r
- #define HCACHE_MAR_CE_SHIFT (0x00000000) \r
-\r
- #define HCACHE_MAR_CE_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HCACHE_MAR_CE)\r
-\r
- #define HCACHE_MAR_CE_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HCACHE_MAR_CE,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HCACHE_MAR\r
-\*----------------------------------------------------------------------------*/\r
- #define HCACHE_MAR_GET(RegAddr) HREG32_GET(RegAddr)\r
- #define HCACHE_MAR_SET(RegAddr,Val) HREG32_SET(RegAddr,Val)\r
-\r
- #define HCACHE_MAR_CFG(RegAddr,ce) REG32(RegAddr) = (UINT32)( \\r
- HFIELD_SHIFT(HCACHE_MAR_CE,ce) \\r
- )\r
-\r
-/******************************************************************************/\r
-\r
-#endif /* CACHE_SUPPORT */\r
-#endif /* _CACHEHAL_H_ */\r
-/******************************************************************************\\r
-* End of cachehal.h\r
-\******************************************************************************/\r
-\r
-/******************************************************************************\\r
-* Copyright (C) 1999-2000 Texas Instruments Incorporated.\r
-* All Rights Reserved\r
-*------------------------------------------------------------------------------\r
-* FILENAME...... dmahal.h\r
-* DATE CREATED.. 03/12/1999 \r
-* LAST MODIFIED. 03/08/2000\r
-* \r
-*------------------------------------------------------------------------------\r
-* DESCRIPTION: (HAL interface file for the DMA module)\r
-*\r
-* Registers Covered:\r
-* HDMA_AUXCTL_ADDR - auxiliary control register\r
-* HDMA_PRICTL0_ADDR - primary control register\r
-* HDMA_PRICTL1_ADDR - primary control register\r
-* HDMA_PRICTL2_ADDR - primary control register\r
-* HDMA_PRICTL3_ADDR - primary control register\r
-* HDMA_SECCTL0_ADDR - seconday control register\r
-* HDMA_SECCTL1_ADDR - seconday control register\r
-* HDMA_SECCTL2_ADDR - seconday control register\r
-* HDMA_SECCTL3_ADDR - seconday control register\r
-* HDMA_SRC0_ADDR - source address register\r
-* HDMA_SRC1_ADDR - source address register\r
-* HDMA_SRC2_ADDR - source address register\r
-* HDMA_SRC3_ADDR - source address register\r
-* HDMA_DST0_ADDR - destination address register\r
-* HDMA_DST1_ADDR - destination address register\r
-* HDMA_DST2_ADDR - destination address register\r
-* HDMA_DST3_ADDR - destination address register\r
-* HDMA_XFRCNT0_ADDR - transfer count register\r
-* HDMA_XFRCNT1_ADDR - transfer count register\r
-* HDMA_XFRCNT2_ADDR - transfer count register\r
-* HDMA_XFRCNT3_ADDR - transfer count register\r
-* HDMA_GBLCNTA_ADDR - global count reload register\r
-* HDMA_GBLCNTB_ADDR - global count reload register\r
-* HDMA_GBLIDXA_ADDR - global index register\r
-* HDMA_GBLIDXB_ADDR - global index register\r
-* HDMA_GBLADDRA_ADDR - global address register\r
-* HDMA_GBLADDRB_ADDR - global address register\r
-* HDMA_GBLADDRC_ADDR - global address register\r
-* HDMA_GBLADDRD_ADDR - global address register\r
-*\r
-*\r
-\******************************************************************************/\r
-#ifndef _DMAHAL_H_\r
-#define _DMAHAL_H_\r
-\r
-#if (DMA_SUPPORT)\r
-/*============================================================================*\\r
-* misc declarations\r
-\*============================================================================*/\r
- #define HDMA_BASE_ADDR (HCHIP_PERBASE_ADDR+0x00040000)\r
-\r
- #define HDMA_CHA_CNT (4)\r
- #define HDMA_GBLADDR_CNT (4)\r
- #define HDMA_GBLIDX_CNT (2)\r
- #define HDMA_GBLCNT_CNT (2)\r
-\r
-/******************************************************************************\\r
-* HDMA_AUXCTL_ADDR - auxiliary control register\r
-*\r
-* Fields:\r
-* (RW) HDMA_AUXCTL_CHPRI\r
-* (RW) HDMA_AUXCTL_AUXPRI\r
-*\r
-\******************************************************************************/\r
- #define HDMA_AUXCTL_ADDR (HDMA_BASE_ADDR+0x0070)\r
- #define HDMA_AUXCTL REG32(HDMA_AUXCTL_ADDR)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HDMA_AUXCTL_CHPRI\r
-\*----------------------------------------------------------------------------*/\r
- #define HDMA_AUXCTL_CHPRI_MASK (0x0000000F)\r
- #define HDMA_AUXCTL_CHPRI_SHIFT (0x00000000)\r
-\r
- #define HDMA_AUXCTL_CHPRI_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HDMA_AUXCTL_CHPRI)\r
-\r
- #define HDMA_AUXCTL_CHPRI_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HDMA_AUXCTL_CHPRI,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HDMA_AUXCTL_AUXPRI\r
-\*----------------------------------------------------------------------------*/\r
- #define HDMA_AUXCTL_AUXPRI_MASK (0x00000010)\r
- #define HDMA_AUXCTL_AUXPRI_SHIFT (0x00000004)\r
-\r
- #define HDMA_AUXCTL_AUXPRI_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HDMA_AUXCTL_AUXPRI)\r
-\r
- #define HDMA_AUXCTL_AUXPRI_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HDMA_AUXCTL_AUXPRI,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HDMA_AUXCTL\r
-\*----------------------------------------------------------------------------*/\r
- #define HDMA_AUXCTL_GET(RegAddr) HREG32_GET(RegAddr)\r
- #define HDMA_AUXCTL_SET(RegAddr,Val) HREG32_SET(RegAddr,Val)\r
-\r
- #define HDMA_AUXCTL_CFG(RegAddr,chpri,auxpri) REG32(RegAddr)=(UINT32)(\\r
- HFIELD_SHIFT(HDMA_AUXCTL_CHPRI,chpri)|\\r
- HFIELD_SHIFT(HDMA_AUXCTL_AUXPRI,auxpri)\\r
- )\r
-\r
-/******************************************************************************\\r
-* HDMA_PRICTL0_ADDR - primary control register\r
-* HDMA_PRICTL1_ADDR - primary control register\r
-* HDMA_PRICTL2_ADDR - primary control register\r
-* HDMA_PRICTL3_ADDR - primary control register\r
-*\r
-* Fields:\r
-* (RW) HDMA_PRICTL_START\r
-* (R) HDMA_PRICTL_STATUS\r
-* (RW) HDMA_PRICTL_SRCDIR\r
-* (RW) HDMA_PRICTL_DSTDIR\r
-* (RW) HDMA_PRICTL_ESIZE\r
-* (RW) HDMA_PRICTL_SPLIT\r
-* (RW) HDMA_PRICTL_CNTRLD\r
-* (RW) HDMA_PRICTL_INDEX\r
-* (RW) HDMA_PRICTL_RSYNC\r
-* (RW) HDMA_PRICTL_WSYNC\r
-* (RW) HDMA_PRICTL_PRI\r
-* (RW) HDMA_PRICTL_TCINT\r
-* (RW) HDMA_PRICTL_FS\r
-* (RW) HDMA_PRICTL_EMOD\r
-* (RW) HDMA_PRICTL_SRCRLD\r
-* (RW) HDMA_PRICTL_DSTRLD\r
-*\r
-\******************************************************************************/\r
- #define HDMA_PRICTL0_ADDR (HDMA_BASE_ADDR+0x0000)\r
- #define HDMA_PRICTL1_ADDR (HDMA_BASE_ADDR+0x0040)\r
- #define HDMA_PRICTL2_ADDR (HDMA_BASE_ADDR+0x0004)\r
- #define HDMA_PRICTL3_ADDR (HDMA_BASE_ADDR+0x0044)\r
-\r
- #define HDMA_PRICTL0 REG32(HDMA_PRICTL0_ADDR)\r
- #define HDMA_PRICTL1 REG32(HDMA_PRICTL1_ADDR)\r
- #define HDMA_PRICTL2 REG32(HDMA_PRICTL2_ADDR)\r
- #define HDMA_PRICTL3 REG32(HDMA_PRICTL3_ADDR)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HDMA_PRICTL_START\r
-\*----------------------------------------------------------------------------*/\r
- #define HDMA_PRICTL_START_MASK (0x00000003)\r
- #define HDMA_PRICTL_START_SHIFT (0x00000000)\r
-\r
- #define HDMA_PRICTL_START_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HDMA_PRICTL_START)\r
-\r
- #define HDMA_PRICTL_START_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HDMA_PRICTL_START,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (R) HDMA_PRICTL_STATUS\r
-\*----------------------------------------------------------------------------*/\r
- #define HDMA_PRICTL_STATUS_MASK (0x0000000C)\r
- #define HDMA_PRICTL_STATUS_SHIFT (0x00000002)\r
-\r
- #define HDMA_PRICTL_STATUS_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HDMA_PRICTL_STATUS)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HDMA_PRICTL_SRCDIR\r
-\*----------------------------------------------------------------------------*/\r
- #define HDMA_PRICTL_SRCDIR_MASK (0x00000030)\r
- #define HDMA_PRICTL_SRCDIR_SHIFT (0x00000004)\r
-\r
- #define HDMA_PRICTL_SRCDIR_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HDMA_PRICTL_SRCDIR)\r
-\r
- #define HDMA_PRICTL_SRCDIR_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HDMA_PRICTL_SRCDIR,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HDMA_PRICTL_DSTDIR\r
-\*----------------------------------------------------------------------------*/\r
- #define HDMA_PRICTL_DSTDIR_MASK (0x000000C0)\r
- #define HDMA_PRICTL_DSTDIR_SHIFT (0x00000006)\r
-\r
- #define HDMA_PRICTL_DSTDIR_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HDMA_PRICTL_DSTDIR)\r
-\r
- #define HDMA_PRICTL_DSTDIR_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HDMA_PRICTL_DSTDIR,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HDMA_PRICTL_ESIZE\r
-\*----------------------------------------------------------------------------*/\r
- #define HDMA_PRICTL_ESIZE_MASK (0x00000300)\r
- #define HDMA_PRICTL_ESIZE_SHIFT (0x00000008)\r
-\r
- #define HDMA_PRICTL_ESIZE_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HDMA_PRICTL_ESIZE)\r
-\r
- #define HDMA_PRICTL_ESIZE_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HDMA_PRICTL_ESIZE,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HDMA_PRICTL_SPLIT\r
-\*----------------------------------------------------------------------------*/\r
- #define HDMA_PRICTL_SPLIT_MASK (0x00000C00)\r
- #define HDMA_PRICTL_SPLIT_SHIFT (0x0000000A)\r
-\r
- #define HDMA_PRICTL_SPLIT_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HDMA_PRICTL_SPLIT)\r
-\r
- #define HDMA_PRICTL_SPLIT_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HDMA_PRICTL_SPLIT,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HDMA_PRICTL_CNTRLD\r
-\*----------------------------------------------------------------------------*/\r
- #define HDMA_PRICTL_CNTRLD_MASK (0x00001000)\r
- #define HDMA_PRICTL_CNTRLD_SHIFT (0x0000000C)\r
-\r
- #define HDMA_PRICTL_CNTRLD_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HDMA_PRICTL_CNTRLD)\r
-\r
- #define HDMA_PRICTL_CNTRLD_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HDMA_PRICTL_CNTRLD,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HDMA_PRICTL_INDEX\r
-\*----------------------------------------------------------------------------*/\r
- #define HDMA_PRICTL_INDEX_MASK (0x00002000)\r
- #define HDMA_PRICTL_INDEX_SHIFT (0x0000000D)\r
-\r
- #define HDMA_PRICTL_INDEX_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HDMA_PRICTL_INDEX)\r
-\r
- #define HDMA_PRICTL_INDEX_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HDMA_PRICTL_INDEX,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HDMA_PRICTL_RSYNC\r
-\*----------------------------------------------------------------------------*/\r
- #define HDMA_PRICTL_RSYNC_MASK (0x0007C000)\r
- #define HDMA_PRICTL_RSYNC_SHIFT (0x0000000E)\r
-\r
- #define HDMA_PRICTL_RSYNC_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HDMA_PRICTL_RSYNC)\r
-\r
- #define HDMA_PRICTL_RSYNC_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HDMA_PRICTL_RSYNC,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HDMA_PRICTL_WSYNC\r
-\*----------------------------------------------------------------------------*/\r
- #define HDMA_PRICTL_WSYNC_MASK (0x00F10000)\r
- #define HDMA_PRICTL_WSYNC_SHIFT (0x00000013)\r
-\r
- #define HDMA_PRICTL_WSYNC_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HDMA_PRICTL_WSYNC)\r
-\r
- #define HDMA_PRICTL_WSYNC_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HDMA_PRICTL_WSYNC,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HDMA_PRICTL_PRI\r
-\*----------------------------------------------------------------------------*/\r
- #define HDMA_PRICTL_PRI_MASK (0x01000000)\r
- #define HDMA_PRICTL_PRI_SHIFT (0x00000018)\r
-\r
- #define HDMA_PRICTL_PRI_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HDMA_PRICTL_PRI)\r
-\r
- #define HDMA_PRICTL_PRI_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HDMA_PRICTL_PRI,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HDMA_PRICTL_TCINT\r
-\*----------------------------------------------------------------------------*/\r
- #define HDMA_PRICTL_TCINT_MASK (0x02000000)\r
- #define HDMA_PRICTL_TCINT_SHIFT (0x00000019)\r
-\r
- #define HDMA_PRICTL_TCINT_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HDMA_PRICTL_TCINT)\r
-\r
- #define HDMA_PRICTL_TCINT_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HDMA_PRICTL_TCINT,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HDMA_PRICTL_FS\r
-\*----------------------------------------------------------------------------*/\r
- #define HDMA_PRICTL_FS_MASK (0x04000000)\r
- #define HDMA_PRICTL_FS_SHIFT (0x0000001A)\r
-\r
- #define HDMA_PRICTL_FS_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HDMA_PRICTL_FS)\r
-\r
- #define HDMA_PRICTL_FS_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HDMA_PRICTL_FS,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HDMA_PRICTL_EMOD\r
-\*----------------------------------------------------------------------------*/\r
- #define HDMA_PRICTL_EMOD_MASK (0x08000000)\r
- #define HDMA_PRICTL_EMOD_SHIFT (0x0000001B)\r
-\r
- #define HDMA_PRICTL_EMOD_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HDMA_PRICTL_EMOD)\r
-\r
- #define HDMA_PRICTL_EMOD_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HDMA_PRICTL_EMOD,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HDMA_PRICTL_SRCRLD\r
-\*----------------------------------------------------------------------------*/\r
- #define HDMA_PRICTL_SRCRLD_MASK (0x30000000)\r
- #define HDMA_PRICTL_SRCRLD_SHIFT (0x0000001C)\r
-\r
- #define HDMA_PRICTL_SRCRLD_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HDMA_PRICTL_SRCRLD)\r
-\r
- #define HDMA_PRICTL_SRCRLD_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HDMA_PRICTL_SRCRLD,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HDMA_PRICTL_DSTRLD\r
-\*----------------------------------------------------------------------------*/\r
- #define HDMA_PRICTL_DSTRLD_MASK (0xC0000000)\r
- #define HDMA_PRICTL_DSTRLD_SHIFT (0x0000001E)\r
-\r
- #define HDMA_PRICTL_DSTRLD_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HDMA_PRICTL_DSTRLD)\r
-\r
- #define HDMA_PRICTL_DSTRLD_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HDMA_PRICTL_DSTRLD,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HDMA_PRICTL\r
-\*----------------------------------------------------------------------------*/\r
- #define HDMA_PRICTL_GET(RegAddr) HREG32_GET(RegAddr)\r
- #define HDMA_PRICTL_SET(RegAddr,Val) HREG32_SET(RegAddr,Val)\r
-\r
- #define HDMA_PRICTL_CFG(RegAddr,start,srcdir,dstdir,esize,split,cntrld,\\r
- index,rsync,wsync,pri,tcint,fs,emod,srcrld,dstrld) \\r
- REG32(RegAddr)=(UINT32)(\\r
- HFIELD_SHIFT(HDMA_PRICTL_START,start)|\\r
- HFIELD_SHIFT(HDMA_PRICTL_SRCDIR,srcdir)|\\r
- HFIELD_SHIFT(HDMA_PRICTL_DSTDIR,dstdir)|\\r
- HFIELD_SHIFT(HDMA_PRICTL_ESIZE,esize)|\\r
- HFIELD_SHIFT(HDMA_PRICTL_SPLIT,split)|\\r
- HFIELD_SHIFT(HDMA_PRICTL_CNTRLD,cntrld)|\\r
- HFIELD_SHIFT(HDMA_PRICTL_INDEX,index)|\\r
- HFIELD_SHIFT(HDMA_PRICTL_RSYNC,rsync)|\\r
- HFIELD_SHIFT(HDMA_PRICTL_WSYNC,wsync)|\\r
- HFIELD_SHIFT(HDMA_PRICTL_PRI,pri)|\\r
- HFIELD_SHIFT(HDMA_PRICTL_TCINT,tcint)|\\r
- HFIELD_SHIFT(HDMA_PRICTL_FS,fs)|\\r
- HFIELD_SHIFT(HDMA_PRICTL_EMOD,emod)|\\r
- HFIELD_SHIFT(HDMA_PRICTL_SRCRLD,srcrld)|\\r
- HFIELD_SHIFT(HDMA_PRICTL_DSTRLD,dstrld)\\r
- )\r
-\r
-/******************************************************************************\\r
-* HDMA_SECCTL0_ADDR - seconday control register\r
-* HDMA_SECCTL1_ADDR - seconday control register\r
-* HDMA_SECCTL2_ADDR - seconday control register\r
-* HDMA_SECCTL3_ADDR - seconday control register\r
-*\r
-* Fields:\r
-* (RW) HDMA_SECCTL_SXCOND\r
-* (RW) HDMA_SECCTL_SXIE\r
-* (RW) HDMA_SECCTL_FRAMECOND\r
-* (RW) HDMA_SECCTL_FRAMEIE\r
-* (RW) HDMA_SECCTL_LASTCOND\r
-* (RW) HDMA_SECCTL_LASTIE\r
-* (RW) HDMA_SECCTL_BLOCKCOND\r
-* (RW) HDMA_SECCTL_BLOCKIE\r
-* (RW) HDMA_SECCTL_RDROPCOND\r
-* (RW) HDMA_SECCTL_RDROPIE\r
-* (RW) HDMA_SECCTL_WDROPCOND\r
-* (RW) HDMA_SECCTL_WDROPIE\r
-* (RW) HDMA_SECCTL_RSYNCSTAT\r
-* (RW) HDMA_SECCTL_RSYNCCLR\r
-* (RW) HDMA_SECCTL_WSYNCSTAT\r
-* (RW) HDMA_SECCTL_WSYNCCLR\r
-* (RW) HDMA_SECCTL_DMACEN\r
-* (RW) HDMA_SECCTL_FSIG (1)\r
-* (RW) HDMA_SECCTL_RSPOL (1)\r
-* (RW) HDMA_SECCTL_WSPOL (1)\r
-*\r
-* (1) only on 6202 or 6203 devices\r
-*\r
-\******************************************************************************/\r
- #define HDMA_SECCTL0_ADDR (HDMA_BASE_ADDR+0x0008)\r
- #define HDMA_SECCTL1_ADDR (HDMA_BASE_ADDR+0x0048)\r
- #define HDMA_SECCTL2_ADDR (HDMA_BASE_ADDR+0x000C)\r
- #define HDMA_SECCTL3_ADDR (HDMA_BASE_ADDR+0x004C)\r
-\r
- #define HDMA_SECCTL0 REG32(HDMA_SECCTL0_ADDR)\r
- #define HDMA_SECCTL1 REG32(HDMA_SECCTL1_ADDR)\r
- #define HDMA_SECCTL2 REG32(HDMA_SECCTL2_ADDR)\r
- #define HDMA_SECCTL3 REG32(HDMA_SECCTL3_ADDR)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HDMA_SECCTL_SXCOND\r
-\*----------------------------------------------------------------------------*/\r
- #define HDMA_SECCTL_SXCOND_MASK (0x00000001)\r
- #define HDMA_SECCTL_SXCOND_SHIFT (0x00000000)\r
-\r
- #define HDMA_SECCTL_SXCOND_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HDMA_SECCTL_SXCOND)\r
-\r
- #define HDMA_SECCTL_SXCOND_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HDMA_SECCTL_SXCOND,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HDMA_SECCTL_SXIE\r
-\*----------------------------------------------------------------------------*/\r
- #define HDMA_SECCTL_SXIE_MASK (0x00000002)\r
- #define HDMA_SECCTL_SXIE_SHIFT (0x00000001)\r
-\r
- #define HDMA_SECCTL_SXIE_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HDMA_SECCTL_SXIE)\r
-\r
- #define HDMA_SECCTL_SXIE_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HDMA_SECCTL_SXIE,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HDMA_SECCTL_FRAMECOND\r
-\*----------------------------------------------------------------------------*/\r
- #define HDMA_SECCTL_FRAMECOND_MASK (0x00000004)\r
- #define HDMA_SECCTL_FRAMECOND_SHIFT (0x00000002)\r
-\r
- #define HDMA_SECCTL_FRAMECOND_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HDMA_SECCTL_FRAMECOND)\r
-\r
- #define HDMA_SECCTL_FRAMECOND_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HDMA_SECCTL_FRAMECOND,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HDMA_SECCTL_FRAMEIE\r
-\*----------------------------------------------------------------------------*/\r
- #define HDMA_SECCTL_FRAMEIE_MASK (0x00000008)\r
- #define HDMA_SECCTL_FRAMEIE_SHIFT (0x00000003)\r
-\r
- #define HDMA_SECCTL_FRAMEIE_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HDMA_SECCTL_FRAMEIE)\r
-\r
- #define HDMA_SECCTL_FRAMEIE_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HDMA_SECCTL_FRAMEIE,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HDMA_SECCTL_LASTCOND\r
-\*----------------------------------------------------------------------------*/\r
- #define HDMA_SECCTL_LASTCOND_MASK (0x00000010)\r
- #define HDMA_SECCTL_LASTCOND_SHIFT (0x00000004)\r
-\r
- #define HDMA_SECCTL_LASTCOND_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HDMA_SECCTL_LASTCOND)\r
-\r
- #define HDMA_SECCTL_LASTCOND_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HDMA_SECCTL_LASTCOND,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HDMA_SECCTL_LASTIE\r
-\*----------------------------------------------------------------------------*/\r
- #define HDMA_SECCTL_LASTIE_MASK (0x00000020)\r
- #define HDMA_SECCTL_LASTIE_SHIFT (0x00000005)\r
-\r
- #define HDMA_SECCTL_LASTIE_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HDMA_SECCTL_LASTIE)\r
-\r
- #define HDMA_SECCTL_LASTIE_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HDMA_SECCTL_LASTIE,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HDMA_SECCTL_BLOCKCOND\r
-\*----------------------------------------------------------------------------*/\r
- #define HDMA_SECCTL_BLOCKCOND_MASK (0x00000040)\r
- #define HDMA_SECCTL_BLOCKCOND_SHIFT (0x00000006)\r
-\r
- #define HDMA_SECCTL_BLOCKCOND_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HDMA_SECCTL_BLOCKCOND)\r
-\r
- #define HDMA_SECCTL_BLOCKCOND_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HDMA_SECCTL_BLOCKCOND,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HDMA_SECCTL_BLOCKIE\r
-\*----------------------------------------------------------------------------*/\r
- #define HDMA_SECCTL_BLOCKIE_MASK (0x00000080)\r
- #define HDMA_SECCTL_BLOCKIE_SHIFT (0x00000007)\r
-\r
- #define HDMA_SECCTL_BLOCKIE_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HDMA_SECCTL_BLOCKIE)\r
-\r
- #define HDMA_SECCTL_BLOCKIE_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HDMA_SECCTL_BLOCKIE,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HDMA_SECCTL_RDROPCOND\r
-\*----------------------------------------------------------------------------*/\r
- #define HDMA_SECCTL_RDROPCOND_MASK (0x00000100)\r
- #define HDMA_SECCTL_RDROPCOND_SHIFT (0x00000008)\r
-\r
- #define HDMA_SECCTL_RDROPCOND_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HDMA_SECCTL_RDROPCOND)\r
-\r
- #define HDMA_SECCTL_RDROPCOND_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HDMA_SECCTL_RDROPCOND,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HDMA_SECCTL_RDROPIE\r
-\*----------------------------------------------------------------------------*/\r
- #define HDMA_SECCTL_RDROPIE_MASK (0x00000200)\r
- #define HDMA_SECCTL_RDROPIE_SHIFT (0x00000009)\r
-\r
- #define HDMA_SECCTL_RDROPIE_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HDMA_SECCTL_RDROPIE)\r
-\r
- #define HDMA_SECCTL_RDROPIE_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HDMA_SECCTL_RDROPIE,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HDMA_SECCTL_WDROPCOND\r
-\*----------------------------------------------------------------------------*/\r
- #define HDMA_SECCTL_WDROPCOND_MASK (0x00000400)\r
- #define HDMA_SECCTL_WDROPCOND_SHIFT (0x0000000A)\r
-\r
- #define HDMA_SECCTL_WDROPCOND_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HDMA_SECCTL_WDROPCOND)\r
-\r
- #define HDMA_SECCTL_WDROPCOND_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HDMA_SECCTL_WDROPCOND,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HDMA_SECCTL_WDROPIE\r
-\*----------------------------------------------------------------------------*/\r
- #define HDMA_SECCTL_WDROPIE_MASK (0x00000800)\r
- #define HDMA_SECCTL_WDROPIE_SHIFT (0x0000000B)\r
-\r
- #define HDMA_SECCTL_WDROPIE_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HDMA_SECCTL_WDROPIE)\r
-\r
- #define HDMA_SECCTL_WDROPIE_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HDMA_SECCTL_WDROPIE,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HDMA_SECCTL_RSYNCSTAT\r
-\*----------------------------------------------------------------------------*/\r
- #define HDMA_SECCTL_RSYNCSTAT_MASK (0x00001000)\r
- #define HDMA_SECCTL_RSYNCSTAT_SHIFT (0x0000000C)\r
-\r
- #define HDMA_SECCTL_RSYNCSTAT_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HDMA_SECCTL_RSYNCSTAT)\r
-\r
- #define HDMA_SECCTL_RSYNCSTAT_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HDMA_SECCTL_RSYNCSTAT,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HDMA_SECCTL_RSYNCCLR\r
-\*----------------------------------------------------------------------------*/\r
- #define HDMA_SECCTL_RSYNCCLR_MASK (0x00002000)\r
- #define HDMA_SECCTL_RSYNCCLR_SHIFT (0x0000000D)\r
-\r
- #define HDMA_SECCTL_RSYNCCLR_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HDMA_SECCTL_RSYNCCLR)\r
-\r
- #define HDMA_SECCTL_RSYNCCLR_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HDMA_SECCTL_RSYNCCLR,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HDMA_SECCTL_WSYNCSTAT\r
-\*----------------------------------------------------------------------------*/\r
- #define HDMA_SECCTL_WSYNCSTAT_MASK (0x00004000)\r
- #define HDMA_SECCTL_WSYNCSTAT_SHIFT (0x0000000E)\r
-\r
- #define HDMA_SECCTL_WSYNCSTAT_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HDMA_SECCTL_WSYNCSTAT)\r
-\r
- #define HDMA_SECCTL_WSYNCSTAT_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HDMA_SECCTL_WSYNCSTAT,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HDMA_SECCTL_WSYNCCLR\r
-\*----------------------------------------------------------------------------*/\r
- #define HDMA_SECCTL_WSYNCCLR_MASK (0x00008000)\r
- #define HDMA_SECCTL_WSYNCCLR_SHIFT (0x0000000F)\r
-\r
- #define HDMA_SECCTL_WSYNCCLR_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HDMA_SECCTL_WSYNCCLR)\r
-\r
- #define HDMA_SECCTL_WSYNCCLR_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HDMA_SECCTL_WSYNCCLR,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HDMA_SECCTL_DMACEN\r
-\*----------------------------------------------------------------------------*/\r
- #define HDMA_SECCTL_DMACEN_MASK (0x00070000)\r
- #define HDMA_SECCTL_DMACEN_SHIFT (0x00000010)\r
-\r
- #define HDMA_SECCTL_DMACEN_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HDMA_SECCTL_DMACEN)\r
-\r
- #define HDMA_SECCTL_DMACEN_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HDMA_SECCTL_DMACEN,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HDMA_SECCTL_FSIG\r
-\*----------------------------------------------------------------------------*/\r
-#if (CHIP_6201|CHIP_6203)\r
- #define HDMA_SECCTL_FSIG_MASK (0x00080000)\r
- #define HDMA_SECCTL_FSIG_SHIFT (0x00000013)\r
-#else\r
- #define HDMA_SECCTL_FSIG_MASK (0x00000000)\r
- #define HDMA_SECCTL_FSIG_SHIFT (0x00000000)\r
-#endif\r
-\r
- #define HDMA_SECCTL_FSIG_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HDMA_SECCTL_FSIG)\r
-\r
- #define HDMA_SECCTL_FSIG_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HDMA_SECCTL_FSIG,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HDMA_SECCTL_RSPOL\r
-\*----------------------------------------------------------------------------*/\r
-#if (CHIP_6201|CHIP_6203)\r
- #define HDMA_SECCTL_RSPOL_MASK (0x00100000)\r
- #define HDMA_SECCTL_RSPOL_SHIFT (0x00000014)\r
-#else\r
- #define HDMA_SECCTL_RSPOL_MASK (0x00000000)\r
- #define HDMA_SECCTL_RSPOL_SHIFT (0x00000000)\r
-#endif\r
-\r
- #define HDMA_SECCTL_RSPOL_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HDMA_SECCTL_RSPOL)\r
-\r
- #define HDMA_SECCTL_RSPOL_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HDMA_SECCTL_RSPOL,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HDMA_SECCTL_WSPOL\r
-\*----------------------------------------------------------------------------*/\r
-#if (CHIP_6201|CHIP_6203)\r
- #define HDMA_SECCTL_WSPOL_MASK (0x00200000)\r
- #define HDMA_SECCTL_WSPOL_SHIFT (0x00000015)\r
-#else\r
- #define HDMA_SECCTL_WSPOL_MASK (0x00000000)\r
- #define HDMA_SECCTL_WSPOL_SHIFT (0x00000000)\r
-#endif\r
-\r
- #define HDMA_SECCTL_WSPOL_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HDMA_SECCTL_WSPOL)\r
-\r
- #define HDMA_SECCTL_WSPOL_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HDMA_SECCTL_WSPOL,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HDMA_SECCTL\r
-\*----------------------------------------------------------------------------*/\r
- #define HDMA_SECCTL_GET(RegAddr) HREG32_GET(RegAddr)\r
- #define HDMA_SECCTL_SET(RegAddr,Val) HREG32_SET(RegAddr,Val)\r
-\r
- #define HDMA_SECCTL_CFG(RegAddr,sxcond,sxie,framecond,frameie,lastcond,\\r
- lastie,blockcond,blockie,rdropcond,rdropie,wdropcond,wdropie,rsyncstat,\\r
- rsyncclr,wsyncstat,wsyncclr,dmacen,fsig,rspol,wspol) \\r
- REG32(RegAddr)=(UINT32)(\\r
- HFIELD_SHIFT(HDMA_SECCTL_SXCOND,sxcond)|\\r
- HFIELD_SHIFT(HDMA_SECCTL_SXIE,sxie)|\\r
- HFIELD_SHIFT(HDMA_SECCTL_FRAMECOND,framecond)|\\r
- HFIELD_SHIFT(HDMA_SECCTL_FRAMEIE,frameie)|\\r
- HFIELD_SHIFT(HDMA_SECCTL_LASTCOND,lastcond)|\\r
- HFIELD_SHIFT(HDMA_SECCTL_LASTIE,lastie)|\\r
- HFIELD_SHIFT(HDMA_SECCTL_BLOCKCOND,blockcond)|\\r
- HFIELD_SHIFT(HDMA_SECCTL_BLOCKIE,blockie)|\\r
- HFIELD_SHIFT(HDMA_SECCTL_RDROPCOND,rdropcond)|\\r
- HFIELD_SHIFT(HDMA_SECCTL_RDROPIE,rdropie)|\\r
- HFIELD_SHIFT(HDMA_SECCTL_WDROPCOND,wdropcond)|\\r
- HFIELD_SHIFT(HDMA_SECCTL_WDROPIE,wdropie)|\\r
- HFIELD_SHIFT(HDMA_SECCTL_RSYNCSTAT,rsyncstat)|\\r
- HFIELD_SHIFT(HDMA_SECCTL_RSYNCCLR,rsyncclr)|\\r
- HFIELD_SHIFT(HDMA_SECCTL_WSYNCSTAT,wsyncstat)|\\r
- HFIELD_SHIFT(HDMA_SECCTL_WSYNCCLR,wsyncclr)|\\r
- HFIELD_SHIFT(HDMA_SECCTL_DMACEN,dmacen)|\\r
- HFIELD_SHIFT(HDMA_SECCTL_FSIG,fsig)|\\r
- HFIELD_SHIFT(HDMA_SECCTL_RSPOL,rspol)|\\r
- HFIELD_SHIFT(HDMA_SECCTL_WSPOL,wspol)\\r
- )\r
-\r
-/******************************************************************************\\r
-* HDMA_SRC0_ADDR - source address register\r
-* HDMA_SRC1_ADDR - source address register\r
-* HDMA_SRC2_ADDR - source address register\r
-* HDMA_SRC3_ADDR - source address register\r
-*\r
-* Fields:\r
-* (RW) HDMA_SRC_SRC\r
-*\r
-\******************************************************************************/\r
- #define HDMA_SRC0_ADDR (HDMA_BASE_ADDR+0x0010)\r
- #define HDMA_SRC1_ADDR (HDMA_BASE_ADDR+0x0050)\r
- #define HDMA_SRC2_ADDR (HDMA_BASE_ADDR+0x0014)\r
- #define HDMA_SRC3_ADDR (HDMA_BASE_ADDR+0x0054)\r
-\r
- #define HDMA_SRC0 REG32(HDMA_SRC0_ADDR)\r
- #define HDMA_SRC1 REG32(HDMA_SRC1_ADDR)\r
- #define HDMA_SRC2 REG32(HDMA_SRC2_ADDR)\r
- #define HDMA_SRC3 REG32(HDMA_SRC3_ADDR)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HDMA_SRC_SRC\r
-\*----------------------------------------------------------------------------*/\r
- #define HDMA_SRC_SRC_MASK (0xFFFFFFFF)\r
- #define HDMA_SRC_SRC_SHIFT (0x00000000)\r
-\r
- #define HDMA_SRC_SRC_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HDMA_SRC_SRC)\r
-\r
- #define HDMA_SRC_SRC_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HDMA_SRC_SRC,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HDMA_SRC\r
-\*----------------------------------------------------------------------------*/\r
- #define HDMA_SRC_GET(RegAddr) HREG32_GET(RegAddr)\r
- #define HDMA_SRC_SET(RegAddr,Val) HREG32_SET(RegAddr,Val)\r
-\r
- #define HDMA_SRC_CFG(RegAddr,src) \\r
- REG32(RegAddr)=(UINT32)(\\r
- HFIELD_SHIFT(HDMA_SRC_SRC,src)\\r
- )\r
-\r
-/******************************************************************************\\r
-* HDMA_DST0_ADDR - destination address register\r
-* HDMA_DST1_ADDR - destination address register\r
-* HDMA_DST2_ADDR - destination address register\r
-* HDMA_DST3_ADDR - destination address register\r
-*\r
-* Fields:\r
-* (RW) HDMA_DST_DST\r
-*\r
-\******************************************************************************/\r
- #define HDMA_DST0_ADDR (HDMA_BASE_ADDR+0x0018)\r
- #define HDMA_DST1_ADDR (HDMA_BASE_ADDR+0x0058)\r
- #define HDMA_DST2_ADDR (HDMA_BASE_ADDR+0x001C)\r
- #define HDMA_DST3_ADDR (HDMA_BASE_ADDR+0x005C)\r
-\r
- #define HDMA_DST0 REG32(HDMA_DST0_ADDR)\r
- #define HDMA_DST1 REG32(HDMA_DST1_ADDR)\r
- #define HDMA_DST2 REG32(HDMA_DST2_ADDR)\r
- #define HDMA_DST3 REG32(HDMA_DST3_ADDR)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HDMA_DST_DST\r
-\*----------------------------------------------------------------------------*/\r
- #define HDMA_DST_DST_MASK (0xFFFFFFFF)\r
- #define HDMA_DST_DST_SHIFT (0x00000000)\r
-\r
- #define HDMA_DST_DST_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HDMA_DST_DST)\r
-\r
- #define HDMA_DST_DST_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HDMA_DST_DST,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HDMA_DST\r
-\*----------------------------------------------------------------------------*/\r
- #define HDMA_DST_GET(RegAddr) HREG32_GET(RegAddr)\r
- #define HDMA_DST_SET(RegAddr,Val) HREG32_SET(RegAddr,Val)\r
-\r
- #define HDMA_DST_CFG(RegAddr,dst) \\r
- REG32(RegAddr)=(UINT32)(\\r
- HFIELD_SHIFT(HDMA_DST_DST,dst)\\r
- )\r
-\r
-/******************************************************************************\\r
-* HDMA_XFRCNT0_ADDR - transfer count register\r
-* HDMA_XFRCNT1_ADDR - transfer count register\r
-* HDMA_XFRCNT2_ADDR - transfer count register\r
-* HDMA_XFRCNT3_ADDR - transfer count register\r
-*\r
-* Fields:\r
-* (RW) HDMA_XFRCNT_ELECNT\r
-* (RW) HDMA_XFRCNT_FRMCNT\r
-*\r
-\******************************************************************************/\r
- #define HDMA_XFRCNT0_ADDR (HDMA_BASE_ADDR+0x0020)\r
- #define HDMA_XFRCNT1_ADDR (HDMA_BASE_ADDR+0x0060)\r
- #define HDMA_XFRCNT2_ADDR (HDMA_BASE_ADDR+0x0024)\r
- #define HDMA_XFRCNT3_ADDR (HDMA_BASE_ADDR+0x0064)\r
-\r
- #define HDMA_XFRCNT0 REG32(HDMA_XFRCNT0_ADDR)\r
- #define HDMA_XFRCNT1 REG32(HDMA_XFRCNT1_ADDR)\r
- #define HDMA_XFRCNT2 REG32(HDMA_XFRCNT2_ADDR)\r
- #define HDMA_XFRCNT3 REG32(HDMA_XFRCNT3_ADDR)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HDMA_XFRCNT_ELECNT\r
-\*----------------------------------------------------------------------------*/\r
- #define HDMA_XFRCNT_ELECNT_MASK (0x0000FFFF)\r
- #define HDMA_XFRCNT_ELECNT_SHIFT (0x00000000)\r
-\r
- #define HDMA_XFRCNT_ELECNT_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HDMA_XFRCNT_ELECNT)\r
-\r
- #define HDMA_XFRCNT_ELECNT_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HDMA_XFRCNT_ELECNT,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HDMA_XFRCNT_FRMCNT\r
-\*----------------------------------------------------------------------------*/\r
- #define HDMA_XFRCNT_FRMCNT_MASK (0xFFFF0000)\r
- #define HDMA_XFRCNT_FRMCNT_SHIFT (0x00000010)\r
-\r
- #define HDMA_XFRCNT_FRMCNT_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HDMA_XFRCNT_FRMCNT)\r
-\r
- #define HDMA_XFRCNT_FRMCNT_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HDMA_XFRCNT_FRMCNT,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HDMA_XFRCNT\r
-\*----------------------------------------------------------------------------*/\r
- #define HDMA_XFRCNT_GET(RegAddr) HREG32_GET(RegAddr)\r
- #define HDMA_XFRCNT_SET(RegAddr,Val) HREG32_SET(RegAddr,Val)\r
-\r
- #define HDMA_XFRCNT_CFG(RegAddr,elecnt,frmcnt) \\r
- REG32(RegAddr)=(UINT32)(\\r
- HFIELD_SHIFT(HDMA_XFRCNT_ELECNT,elecnt)|\\r
- HFIELD_SHIFT(HDMA_XFRCNT_FRMCNT,frmcnt)\\r
- )\r
-\r
-/******************************************************************************\\r
-* HDMA_GBLCNTA_ADDR - global count reload register\r
-* HDMA_GBLCNTB_ADDR - global count reload register\r
-*\r
-* Fields:\r
-* (RW) HDMA_GBLCNT_ELECNT\r
-* (RW) HDMA_GBLCNT_FRMCNT\r
-*\r
-\******************************************************************************/\r
- #define HDMA_GBLCNTA_ADDR (HDMA_BASE_ADDR+0x0028)\r
- #define HDMA_GBLCNTB_ADDR (HDMA_BASE_ADDR+0x002C)\r
-\r
- #define HDMA_GBLCNTA REG32(HDMA_GBLCNTA_ADDR)\r
- #define HDMA_GBLCNTB REG32(HDMA_GBLCNTB_ADDR)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HDMA_GBLCNT_ELECNT\r
-\*----------------------------------------------------------------------------*/\r
- #define HDMA_GBLCNT_ELECNT_MASK (0x0000FFFF)\r
- #define HDMA_GBLCNT_ELECNT_SHIFT (0x00000000)\r
-\r
- #define HDMA_GBLCNT_ELECNT_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HDMA_GBLCNT_ELECNT)\r
-\r
- #define HDMA_GBLCNT_ELECNT_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HDMA_GBLCNT_ELECNT,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HDMA_GBLCNT_FRMCNT\r
-\*----------------------------------------------------------------------------*/\r
- #define HDMA_GBLCNT_FRMCNT_MASK (0xFFFF0000)\r
- #define HDMA_GBLCNT_FRMCNT_SHIFT (0x00000010)\r
-\r
- #define HDMA_GBLCNT_FRMCNT_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HDMA_GBLCNT_FRMCNT)\r
-\r
- #define HDMA_GBLCNT_FRMCNT_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HDMA_GBLCNT_FRMCNT,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HDMA_GBLCNT\r
-\*----------------------------------------------------------------------------*/\r
- #define HDMA_GBLCNT_GET(RegAddr) HREG32_GET(RegAddr)\r
- #define HDMA_GBLCNT_SET(RegAddr,Val) HREG32_SET(RegAddr,Val)\r
-\r
- #define HDMA_GBLCNT_CFG(RegAddr,elecnt,frmcnt) \\r
- REG32(RegAddr)=(UINT32)(\\r
- HFIELD_SHIFT(HDMA_GBLCNT_ELECNT,elecnt)|\\r
- HFIELD_SHIFT(HDMA_GBLCNT_FRMCNT,frmcnt)\\r
- )\r
-\r
-/******************************************************************************\\r
-* HDMA_GBLIDXA_ADDR - global index register\r
-* HDMA_GBLIDXB_ADDR - global index register\r
-*\r
-* Fields:\r
-* (RW) HDMA_GBLIDX_ELEIDX\r
-* (RW) HDMA_GBLIDX_FRMIDX\r
-*\r
-\******************************************************************************/\r
- #define HDMA_GBLIDXA_ADDR (HDMA_BASE_ADDR+0x0030)\r
- #define HDMA_GBLIDXB_ADDR (HDMA_BASE_ADDR+0x0034)\r
-\r
- #define HDMA_GBLIDXA REG32(HDMA_GBLIDXA_ADDR)\r
- #define HDMA_GBLIDXB REG32(HDMA_GBLIDXB_ADDR)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HDMA_GBLIDX_ELEIDX\r
-\*----------------------------------------------------------------------------*/\r
- #define HDMA_GBLIDX_ELEIDX_MASK (0x0000FFFF)\r
- #define HDMA_GBLIDX_ELEIDX_SHIFT (0x00000000)\r
-\r
- #define HDMA_GBLIDX_ELEIDX_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HDMA_GBLIDX_ELEIDX)\r
-\r
- #define HDMA_GBLIDX_ELEIDX_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HDMA_GBLIDX_ELEIDX,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HDMA_GBLIDX_FRMIDX\r
-\*----------------------------------------------------------------------------*/\r
- #define HDMA_GBLIDX_FRMIDX_MASK (0xFFFF0000)\r
- #define HDMA_GBLIDX_FRMIDX_SHIFT (0x00000010)\r
-\r
- #define HDMA_GBLIDX_FRMIDX_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HDMA_GBLIDX_FRMIDX)\r
-\r
- #define HDMA_GBLIDX_FRMIDX_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HDMA_GBLIDX_FRMIDX,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HDMA_GBLIDX\r
-\*----------------------------------------------------------------------------*/\r
- #define HDMA_GBLIDX_GET(RegAddr) HREG32_GET(RegAddr)\r
- #define HDMA_GBLIDX_SET(RegAddr,Val) HREG32_SET(RegAddr,Val)\r
-\r
- #define HDMA_GBLIDX_CFG(RegAddr,eleidx, frmidx) \\r
- REG32(RegAddr)=(UINT32)(\\r
- HFIELD_SHIFT(HDMA_GBLIDX_ELEIDX,eleidx)|\\r
- HFIELD_SHIFT(HDMA_GBLIDX_FRMIDX,frmidx)\\r
- )\r
-\r
-/******************************************************************************\\r
-* HDMA_GBLADDRA_ADDR - global address register\r
-* HDMA_GBLADDRB_ADDR - global address register\r
-* HDMA_GBLADDRC_ADDR - global address register\r
-* HDMA_GBLADDRD_ADDR - global address register\r
-*\r
-* Fields:\r
-* (RW) HDMA_GBLADDR_GBLADDR\r
-*\r
-\******************************************************************************/\r
- #define HDMA_GBLADDRA_ADDR (HDMA_BASE_ADDR+0x0038)\r
- #define HDMA_GBLADDRB_ADDR (HDMA_BASE_ADDR+0x003C)\r
- #define HDMA_GBLADDRC_ADDR (HDMA_BASE_ADDR+0x0068)\r
- #define HDMA_GBLADDRD_ADDR (HDMA_BASE_ADDR+0x006C)\r
-\r
- #define HDMA_GBLADDRA REG32(HDMA_GBLADDRA_ADDR)\r
- #define HDMA_GBLADDRB REG32(HDMA_GBLADDRB_ADDR)\r
- #define HDMA_GBLADDRC REG32(HDMA_GBLADDRC_ADDR)\r
- #define HDMA_GBLADDRD REG32(HDMA_GBLADDRD_ADDR)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HDMA_GBLADDR_GBLADDR\r
-\*----------------------------------------------------------------------------*/\r
- #define HDMA_GBLADDR_ADDR_MASK (0xFFFFFFFF)\r
- #define HDMA_GBLADDR_ADDR_SHIFT (0x00000000)\r
-\r
- #define HDMA_GBLADDR_GBLADDR_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HDMA_GBLADDR_GBLADDR)\r
-\r
- #define HDMA_GBLADDR_GBLADDR_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HDMA_GBLADDR_GBLADDR,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HDMA_GBLADDR\r
-\*----------------------------------------------------------------------------*/\r
- #define HDMA_GBLADDR_GET(RegAddr) HREG32_GET(RegAddr)\r
- #define HDMA_GBLADDR_SET(RegAddr,Val) HREG32_SET(RegAddr,Val)\r
-\r
- #define HDMA_GBLADDR_CFG(RegAddr,gbladdr) \\r
- REG32(RegAddr)=(UINT32)(\\r
- HFIELD_SHIFT(HDMA_GBLADDR_GBLADDR,gbladdr)\\r
- )\r
-\r
-/******************************************************************************/\r
-\r
-#endif /* DMA_SUPPORT */\r
-#endif /* _DMAHAL_H_ */\r
-/******************************************************************************\\r
-* End of dmahal.h\r
-\******************************************************************************/\r
-/******************************************************************************\\r
-* Copyright (C) 1999-2000 Texas Instruments Incorporated.\r
-* All Rights Reserved\r
-*------------------------------------------------------------------------------\r
-* FILENAME...... edmahal.h\r
-* DATE CREATED.. 06/12/1999 \r
-* LAST MODIFIED. 03/08/2000\r
-* \r
-*------------------------------------------------------------------------------\r
-* DESCRIPTION: (HAL interface file for the EDMA module)\r
-*\r
-* Registers Covered:\r
-* HEDMA_OPT - options (for both QDMA and PRAM entries)\r
-* HEDMA_SRC - source address (for both QDMA and PRAM entries)\r
-* HEDMA_CNT - transfer count (for both QDMA and PRAM entries)\r
-* HEDMA_DST - destination address (for both QDMA and PRAM entries)\r
-* HEDMA_IDX - index (for both QDMA and PRAM entries)\r
-* HEDMA_RLD - reload/link (for PRAM entries)\r
-* HEDMA_PQSR - priority queue status register\r
-* HEDMA_CIPR - channel interrupt pending register\r
-* HEDMA_CIER - channel interrupt enable register\r
-* HEDMA_CCER - channel chain enable register\r
-* HEDMA_ER - event register\r
-* HEDMA_EER - event enable register\r
-* HEDMA_ECR - event clear register\r
-* HEDMA_ESR - event set register\r
-*\r
-\******************************************************************************/\r
-#ifndef _EDMAHAL_H_\r
-#define _EDMAHAL_H_\r
-\r
-#if (EDMA_SUPPORT)\r
-/*============================================================================*\\r
-* misc declarations\r
-\*============================================================================*/\r
- #define HEDMA_BASE0_ADDR (HCHIP_PERBASE_ADDR+0x00200000)\r
- #define HEDMA_BASE1_ADDR (HCHIP_PERBASE_ADDR+0x00800000)\r
-\r
- #define HEDMA_CHA_CNT (16)\r
-\r
- #define HEDMA_PRAM_START (HEDMA_BASE0_ADDR)\r
- #define HEDMA_PRAM_SIZE (0x00000800) \r
- #define HEDMA_PRAM_END (HEDMA_PRAM_START+HEDMA_PRAM_SIZE-1)\r
- #define HEDMA_ENTRY_SIZE (24)\r
- #define HEDMA_ENTRY_CNT (HEDMA_PRAM_SIZE / HEDMA_ENTRY_SIZE)\r
- \r
- #define HEDMA_MK_ENTRY_ADDR(cha) (HEDMA_PRAM_START+(cha)*HEDMA_ENTRY_SIZE)\r
-\r
- #define HEDMA_ENTRY0_ADDR HEDMA_MK_ENTRY_ADDR(0)\r
- #define HEDMA_ENTRY1_ADDR HEDMA_MK_ENTRY_ADDR(1)\r
- #define HEDMA_ENTRY2_ADDR HEDMA_MK_ENTRY_ADDR(2)\r
- #define HEDMA_ENTRY3_ADDR HEDMA_MK_ENTRY_ADDR(3)\r
- #define HEDMA_ENTRY4_ADDR HEDMA_MK_ENTRY_ADDR(4)\r
- #define HEDMA_ENTRY5_ADDR HEDMA_MK_ENTRY_ADDR(5)\r
- #define HEDMA_ENTRY6_ADDR HEDMA_MK_ENTRY_ADDR(6)\r
- #define HEDMA_ENTRY7_ADDR HEDMA_MK_ENTRY_ADDR(7)\r
- #define HEDMA_ENTRY8_ADDR HEDMA_MK_ENTRY_ADDR(8)\r
- #define HEDMA_ENTRY9_ADDR HEDMA_MK_ENTRY_ADDR(9)\r
- #define HEDMA_ENTRY10_ADDR HEDMA_MK_ENTRY_ADDR(10)\r
- #define HEDMA_ENTRY11_ADDR HEDMA_MK_ENTRY_ADDR(11)\r
- #define HEDMA_ENTRY12_ADDR HEDMA_MK_ENTRY_ADDR(12)\r
- #define HEDMA_ENTRY13_ADDR HEDMA_MK_ENTRY_ADDR(13)\r
- #define HEDMA_ENTRY14_ADDR HEDMA_MK_ENTRY_ADDR(14)\r
- #define HEDMA_ENTRY15_ADDR HEDMA_MK_ENTRY_ADDR(15)\r
-\r
- #define HEDMA_LINK_START HEDMA_MK_ENTRY_ADDR(16)\r
-\r
- #define HEDMA_LINK_CNT ((HEDMA_PRAM_END-HEDMA_LINK_START+1)\\r
- /HEDMA_ENTRY_SIZE)\r
- \r
- #define HEDMA_MK_LINK_ADDR(l) (HEDMA_LINK_START+(l)*HEDMA_ENTRY_SIZE)\r
-\r
- #define HEDMA_SCRATCH_START (HEDMA_LINK_START+\\r
- (HEDMA_ENTRY_SIZE*HEDMA_LINK_CNT))\r
- \r
- #define HEDMA_SCRATCH_SIZE (HEDMA_PRAM_END-HEDMA_SCRATCH_START+1) \r
-\r
-\r
- #define HEDMA_OPT_OFFSET (0x00000000)\r
- #define HEDMA_SRC_OFFSET (0x00000004)\r
- #define HEDMA_CNT_OFFSET (0x00000008)\r
- #define HEDMA_DST_OFFSET (0x0000000C)\r
- #define HEDMA_IDX_OFFSET (0x00000010)\r
- #define HEDMA_RLD_OFFSET (0x00000014)\r
-\r
-/******************************************************************************\\r
-* HEDMA_OPT - transfer options\r
-*\r
-* Fields:\r
-* (RW) HEDMA_OPT_FS\r
-* (RW) HEDMA_OPT_LINK\r
-* (RW) HEDMA_OPT_TCC\r
-* (RW) HEDMA_OPT_TCINT\r
-* (RW) HEDMA_OPT_DUM\r
-* (RW) HEDMA_OPT_2DD\r
-* (RW) HEDMA_OPT_SUM\r
-* (RW) HEDMA_OPT_2DS\r
-* (RW) HEDMA_OPT_ESIZE\r
-* (RW) HEDMA_OPT_PRI\r
-*\r
-\******************************************************************************/\r
- #define HEDMA_QOPT_ADDR (HEDMA_BASE1_ADDR+0x0000)\r
- #define HEDMA_QSOPT_ADDR (HEDMA_BASE1_ADDR+0x0020)\r
- #define HEDMA_QOPT REG32(HEDMA_QOPT_ADDR)\r
- #define HEDMA_QSOPT REG32(HEDMA_QSOPT_ADDR)\r
-\r
- #define HEDMA_OPT0_ADDR (HEDMA_ENTRY0_ADDR+HEDMA_OPT_OFFSET)\r
- #define HEDMA_OPT1_ADDR (HEDMA_ENTRY1_ADDR+HEDMA_OPT_OFFSET)\r
- #define HEDMA_OPT2_ADDR (HEDMA_ENTRY2_ADDR+HEDMA_OPT_OFFSET)\r
- #define HEDMA_OPT3_ADDR (HEDMA_ENTRY3_ADDR+HEDMA_OPT_OFFSET)\r
- #define HEDMA_OPT4_ADDR (HEDMA_ENTRY4_ADDR+HEDMA_OPT_OFFSET)\r
- #define HEDMA_OPT5_ADDR (HEDMA_ENTRY5_ADDR+HEDMA_OPT_OFFSET)\r
- #define HEDMA_OPT6_ADDR (HEDMA_ENTRY6_ADDR+HEDMA_OPT_OFFSET)\r
- #define HEDMA_OPT7_ADDR (HEDMA_ENTRY7_ADDR+HEDMA_OPT_OFFSET)\r
- #define HEDMA_OPT8_ADDR (HEDMA_ENTRY8_ADDR+HEDMA_OPT_OFFSET)\r
- #define HEDMA_OPT9_ADDR (HEDMA_ENTRY9_ADDR+HEDMA_OPT_OFFSET)\r
- #define HEDMA_OPT10_ADDR (HEDMA_ENTRY10_ADDR+HEDMA_OPT_OFFSET)\r
- #define HEDMA_OPT11_ADDR (HEDMA_ENTRY11_ADDR+HEDMA_OPT_OFFSET)\r
- #define HEDMA_OPT12_ADDR (HEDMA_ENTRY12_ADDR+HEDMA_OPT_OFFSET)\r
- #define HEDMA_OPT13_ADDR (HEDMA_ENTRY13_ADDR+HEDMA_OPT_OFFSET)\r
- #define HEDMA_OPT14_ADDR (HEDMA_ENTRY14_ADDR+HEDMA_OPT_OFFSET)\r
- #define HEDMA_OPT15_ADDR (HEDMA_ENTRY15_ADDR+HEDMA_OPT_OFFSET)\r
-\r
- #define HEDMA_OPT0 REG32(HEDMA_OPT0_ADDR)\r
- #define HEDMA_OPT1 REG32(HEDMA_OPT1_ADDR)\r
- #define HEDMA_OPT2 REG32(HEDMA_OPT2_ADDR)\r
- #define HEDMA_OPT3 REG32(HEDMA_OPT3_ADDR)\r
- #define HEDMA_OPT4 REG32(HEDMA_OPT4_ADDR)\r
- #define HEDMA_OPT5 REG32(HEDMA_OPT5_ADDR)\r
- #define HEDMA_OPT6 REG32(HEDMA_OPT6_ADDR)\r
- #define HEDMA_OPT7 REG32(HEDMA_OPT7_ADDR)\r
- #define HEDMA_OPT8 REG32(HEDMA_OPT8_ADDR)\r
- #define HEDMA_OPT9 REG32(HEDMA_OPT9_ADDR)\r
- #define HEDMA_OPT10 REG32(HEDMA_OPT10_ADDR)\r
- #define HEDMA_OPT11 REG32(HEDMA_OPT11_ADDR)\r
- #define HEDMA_OPT12 REG32(HEDMA_OPT12_ADDR)\r
- #define HEDMA_OPT13 REG32(HEDMA_OPT13_ADDR)\r
- #define HEDMA_OPT14 REG32(HEDMA_OPT14_ADDR)\r
- #define HEDMA_OPT15 REG32(HEDMA_OPT15_ADDR)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_OPT_FS\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_OPT_FS_MASK (0x00000001)\r
- #define HEDMA_OPT_FS_SHIFT (0x00000000)\r
-\r
- #define HEDMA_OPT_FS_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_OPT_FS)\r
-\r
- #define HEDMA_OPT_FS_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_OPT_FS,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_OPT_LINK\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_OPT_LINK_MASK (0x00000002)\r
- #define HEDMA_OPT_LINK_SHIFT (0x00000001)\r
-\r
- #define HEDMA_OPT_LINK_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_OPT_LINK)\r
-\r
- #define HEDMA_OPT_LINK_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_OPT_LINK,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_OPT_TCC\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_OPT_TCC_MASK (0x000F0000)\r
- #define HEDMA_OPT_TCC_SHIFT (0x00000010)\r
-\r
- #define HEDMA_OPT_TCC_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_OPT_TCC)\r
-\r
- #define HEDMA_OPT_TCC_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_OPT_TCC,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_OPT_TCINT\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_OPT_TCINT_MASK (0x00100000)\r
- #define HEDMA_OPT_TCINT_SHIFT (0x00000014)\r
-\r
- #define HEDMA_OPT_TCINT_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_OPT_TCINT)\r
-\r
- #define HEDMA_OPT_TCINT_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_OPT_TCINT,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_OPT_DUM\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_OPT_DUM_MASK (0x00600000)\r
- #define HEDMA_OPT_DUM_SHIFT (0x00000015)\r
-\r
- #define HEDMA_OPT_DUM_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_OPT_DUM)\r
-\r
- #define HEDMA_OPT_DUM_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_OPT_DUM,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_OPT_2DD\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_OPT_2DD_MASK (0x00800000)\r
- #define HEDMA_OPT_2DD_SHIFT (0x00000017)\r
-\r
- #define HEDMA_OPT_2DD_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_OPT_2DD)\r
-\r
- #define HEDMA_OPT_2DD_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_OPT_2DD,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_OPT_SUM\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_OPT_SUM_MASK (0x03000000)\r
- #define HEDMA_OPT_SUM_SHIFT (0x00000018)\r
-\r
- #define HEDMA_OPT_SUM_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_OPT_SUM)\r
-\r
- #define HEDMA_OPT_SUM_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_OPT_SUM,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_OPT_2DS\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_OPT_2DS_MASK (0x04000000)\r
- #define HEDMA_OPT_2DS_SHIFT (0x0000001A)\r
-\r
- #define HEDMA_OPT_2DS_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_OPT_2DS)\r
-\r
- #define HEDMA_OPT_2DS_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_OPT_2DS,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_OPT_ESIZE\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_OPT_ESIZE_MASK (0x18000000)\r
- #define HEDMA_OPT_ESIZE_SHIFT (0x0000001B)\r
-\r
- #define HEDMA_OPT_ESIZE_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_OPT_ESIZE)\r
-\r
- #define HEDMA_OPT_ESIZE_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_OPT_ESIZE,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_OPT_PRI\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_OPT_PRI_MASK (0xE0000000)\r
- #define HEDMA_OPT_PRI_SHIFT (0x0000001D)\r
-\r
- #define HEDMA_OPT_PRI_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_OPT_PRI)\r
-\r
- #define HEDMA_OPT_PRI_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_OPT_PRI,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_OPT\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_OPT_GET(RegAddr) HREG32_GET(RegAddr)\r
- #define HEDMA_OPT_SET(RegAddr,Val) HREG32_SET(RegAddr,Val)\r
-\r
- #define HEDMA_OPT_CFG(RegAddr,fs,link,tcc,tcint,dum,d2d,sum,s2d,esize,pri)\\r
- REG32(RegAddr)=(UINT32)(\\r
- HFIELD_SHIFT(HEDMA_OPT_FS,fs)|\\r
- HFIELD_SHIFT(HEDMA_OPT_LINK,link)|\\r
- HFIELD_SHIFT(HEDMA_OPT_TCC,tcc)|\\r
- HFIELD_SHIFT(HEDMA_OPT_TCINT,tcint)|\\r
- HFIELD_SHIFT(HEDMA_OPT_DUM,dum)|\\r
- HFIELD_SHIFT(HEDMA_OPT_2DD,d2d)|\\r
- HFIELD_SHIFT(HEDMA_OPT_SUM,sum)|\\r
- HFIELD_SHIFT(HEDMA_OPT_2DS,s2d)|\\r
- HFIELD_SHIFT(HEDMA_OPT_ESIZE,esize)|\\r
- HFIELD_SHIFT(HEDMA_OPT_PRI,pri)\\r
- )\r
-\r
-/******************************************************************************\\r
-* HEDMA_SRC - source address\r
-*\r
-* Fields:\r
-* (RW) HEDMA_SRC_SRC\r
-*\r
-\******************************************************************************/\r
- #define HEDMA_QSRC_ADDR (HEDMA_BASE1_ADDR+0x0004)\r
- #define HEDMA_QSSRC_ADDR (HEDMA_BASE1_ADDR+0x0024)\r
- #define HEDMA_QSRC REG32(HEDMA_QSRC_ADDR)\r
- #define HEDMA_QSSRC REG32(HEDMA_QSSRC_ADDR)\r
-\r
- #define HEDMA_SRC0_ADDR (HEDMA_ENTRY0_ADDR+HEDMA_SRC_OFFSET)\r
- #define HEDMA_SRC1_ADDR (HEDMA_ENTRY1_ADDR+HEDMA_SRC_OFFSET)\r
- #define HEDMA_SRC2_ADDR (HEDMA_ENTRY2_ADDR+HEDMA_SRC_OFFSET)\r
- #define HEDMA_SRC3_ADDR (HEDMA_ENTRY3_ADDR+HEDMA_SRC_OFFSET)\r
- #define HEDMA_SRC4_ADDR (HEDMA_ENTRY4_ADDR+HEDMA_SRC_OFFSET)\r
- #define HEDMA_SRC5_ADDR (HEDMA_ENTRY5_ADDR+HEDMA_SRC_OFFSET)\r
- #define HEDMA_SRC6_ADDR (HEDMA_ENTRY6_ADDR+HEDMA_SRC_OFFSET)\r
- #define HEDMA_SRC7_ADDR (HEDMA_ENTRY7_ADDR+HEDMA_SRC_OFFSET)\r
- #define HEDMA_SRC8_ADDR (HEDMA_ENTRY8_ADDR+HEDMA_SRC_OFFSET)\r
- #define HEDMA_SRC9_ADDR (HEDMA_ENTRY9_ADDR+HEDMA_SRC_OFFSET)\r
- #define HEDMA_SRC10_ADDR (HEDMA_ENTRY10_ADDR+HEDMA_SRC_OFFSET)\r
- #define HEDMA_SRC11_ADDR (HEDMA_ENTRY11_ADDR+HEDMA_SRC_OFFSET)\r
- #define HEDMA_SRC12_ADDR (HEDMA_ENTRY12_ADDR+HEDMA_SRC_OFFSET)\r
- #define HEDMA_SRC13_ADDR (HEDMA_ENTRY13_ADDR+HEDMA_SRC_OFFSET)\r
- #define HEDMA_SRC14_ADDR (HEDMA_ENTRY14_ADDR+HEDMA_SRC_OFFSET)\r
- #define HEDMA_SRC15_ADDR (HEDMA_ENTRY15_ADDR+HEDMA_SRC_OFFSET)\r
-\r
- #define HEDMA_SRC0 REG32(HEDMA_SRC0_ADDR)\r
- #define HEDMA_SRC1 REG32(HEDMA_SRC1_ADDR)\r
- #define HEDMA_SRC2 REG32(HEDMA_SRC2_ADDR)\r
- #define HEDMA_SRC3 REG32(HEDMA_SRC3_ADDR)\r
- #define HEDMA_SRC4 REG32(HEDMA_SRC4_ADDR)\r
- #define HEDMA_SRC5 REG32(HEDMA_SRC5_ADDR)\r
- #define HEDMA_SRC6 REG32(HEDMA_SRC6_ADDR)\r
- #define HEDMA_SRC7 REG32(HEDMA_SRC7_ADDR)\r
- #define HEDMA_SRC8 REG32(HEDMA_SRC8_ADDR)\r
- #define HEDMA_SRC9 REG32(HEDMA_SRC9_ADDR)\r
- #define HEDMA_SRC10 REG32(HEDMA_SRC10_ADDR)\r
- #define HEDMA_SRC11 REG32(HEDMA_SRC11_ADDR)\r
- #define HEDMA_SRC12 REG32(HEDMA_SRC12_ADDR)\r
- #define HEDMA_SRC13 REG32(HEDMA_SRC13_ADDR)\r
- #define HEDMA_SRC14 REG32(HEDMA_SRC14_ADDR)\r
- #define HEDMA_SRC15 REG32(HEDMA_SRC15_ADDR)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_SRC_SRC\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_SRC_SRC_MASK (0xFFFFFFFF)\r
- #define HEDMA_SRC_SRC_SHIFT (0x00000000)\r
- \r
- #define HEDMA_SRC_SRC_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_SRC_SRC)\r
-\r
- #define HEDMA_SRC_SRC_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_SRC_SRC,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_SRC\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_SRC_GET(RegAddr) HREG32_GET(RegAddr)\r
- #define HEDMA_SRC_SET(RegAddr,Val) HREG32_SET(RegAddr,Val)\r
-\r
- #define HEDMA_SRC_CFG(RegAddr,src)\\r
- REG32(RegAddr)=(UINT32)(\\r
- HFIELD_SHIFT(HEDMA_SRC_SRC,src)\\r
- )\r
-\r
-/******************************************************************************\\r
-* HEDMA_CNT - transfer count\r
-*\r
-* Fields:\r
-* (RW) HEDMA_CNT_ELECNT\r
-* (RW) HEDMA_CNT_FRMCNT\r
-*\r
-\******************************************************************************/\r
- #define HEDMA_QCNT_ADDR (HEDMA_BASE1_ADDR+0x0008)\r
- #define HEDMA_QSCNT_ADDR (HEDMA_BASE1_ADDR+0x0028) \r
- #define HEDMA_QCNT REG32(HEDMA_QCNT_ADDR)\r
- #define HEDMA_QSCNT REG32(HEDMA_QSCNT_ADDR)\r
- \r
- #define HEDMA_CNT0_ADDR (HEDMA_ENTRY0_ADDR+HEDMA_CNT_OFFSET)\r
- #define HEDMA_CNT1_ADDR (HEDMA_ENTRY1_ADDR+HEDMA_CNT_OFFSET)\r
- #define HEDMA_CNT2_ADDR (HEDMA_ENTRY2_ADDR+HEDMA_CNT_OFFSET)\r
- #define HEDMA_CNT3_ADDR (HEDMA_ENTRY3_ADDR+HEDMA_CNT_OFFSET)\r
- #define HEDMA_CNT4_ADDR (HEDMA_ENTRY4_ADDR+HEDMA_CNT_OFFSET)\r
- #define HEDMA_CNT5_ADDR (HEDMA_ENTRY5_ADDR+HEDMA_CNT_OFFSET)\r
- #define HEDMA_CNT6_ADDR (HEDMA_ENTRY6_ADDR+HEDMA_CNT_OFFSET)\r
- #define HEDMA_CNT7_ADDR (HEDMA_ENTRY7_ADDR+HEDMA_CNT_OFFSET)\r
- #define HEDMA_CNT8_ADDR (HEDMA_ENTRY8_ADDR+HEDMA_CNT_OFFSET)\r
- #define HEDMA_CNT9_ADDR (HEDMA_ENTRY9_ADDR+HEDMA_CNT_OFFSET)\r
- #define HEDMA_CNT10_ADDR (HEDMA_ENTRY10_ADDR+HEDMA_CNT_OFFSET)\r
- #define HEDMA_CNT11_ADDR (HEDMA_ENTRY11_ADDR+HEDMA_CNT_OFFSET)\r
- #define HEDMA_CNT12_ADDR (HEDMA_ENTRY12_ADDR+HEDMA_CNT_OFFSET)\r
- #define HEDMA_CNT13_ADDR (HEDMA_ENTRY13_ADDR+HEDMA_CNT_OFFSET)\r
- #define HEDMA_CNT14_ADDR (HEDMA_ENTRY14_ADDR+HEDMA_CNT_OFFSET)\r
- #define HEDMA_CNT15_ADDR (HEDMA_ENTRY15_ADDR+HEDMA_CNT_OFFSET)\r
-\r
- #define HEDMA_CNT0 REG32(HEDMA_CNT0_ADDR)\r
- #define HEDMA_CNT1 REG32(HEDMA_CNT1_ADDR)\r
- #define HEDMA_CNT2 REG32(HEDMA_CNT2_ADDR)\r
- #define HEDMA_CNT3 REG32(HEDMA_CNT3_ADDR)\r
- #define HEDMA_CNT4 REG32(HEDMA_CNT4_ADDR)\r
- #define HEDMA_CNT5 REG32(HEDMA_CNT5_ADDR)\r
- #define HEDMA_CNT6 REG32(HEDMA_CNT6_ADDR)\r
- #define HEDMA_CNT7 REG32(HEDMA_CNT7_ADDR)\r
- #define HEDMA_CNT8 REG32(HEDMA_CNT8_ADDR)\r
- #define HEDMA_CNT9 REG32(HEDMA_CNT9_ADDR)\r
- #define HEDMA_CNT10 REG32(HEDMA_CNT10_ADDR)\r
- #define HEDMA_CNT11 REG32(HEDMA_CNT11_ADDR)\r
- #define HEDMA_CNT12 REG32(HEDMA_CNT12_ADDR)\r
- #define HEDMA_CNT13 REG32(HEDMA_CNT13_ADDR)\r
- #define HEDMA_CNT14 REG32(HEDMA_CNT14_ADDR)\r
- #define HEDMA_CNT15 REG32(HEDMA_CNT15_ADDR)\r
- \r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_CNT_ELECNT\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_CNT_ELECNT_MASK (0x0000FFFF)\r
- #define HEDMA_CNT_ELECNT_SHIFT (0x00000000)\r
- \r
- #define HEDMA_CNT_ELECNT_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_CNT_ELECNT)\r
-\r
- #define HEDMA_CNT_ELECNT_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_CNT_ELECNT,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_CNT_FRMCNT\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_CNT_FRMCNT_MASK (0xFFFF0000)\r
- #define HEDMA_CNT_FRMCNT_SHIFT (0x00000010)\r
- \r
- #define HEDMA_CNT_FRMCNT_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_CNT_FRMCNT)\r
-\r
- #define HEDMA_CNT_FRMCNT_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_CNT_FRMCNT,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_CNT\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_CNT_GET(RegAddr) HREG32_GET(RegAddr)\r
- #define HEDMA_CNT_SET(RegAddr,Val) HREG32_SET(RegAddr,Val)\r
-\r
- #define HEDMA_CNT_CFG(RegAddr,elecnt,frmcnt)\\r
- REG32(RegAddr)=(UINT32)(\\r
- HFIELD_SHIFT(HEDMA_CNT_ELECNT,elecnt)|\\r
- HFIELD_SHIFT(HEDMA_CNT_FRMCNT,frmcnt)\\r
- )\r
-\r
-/******************************************************************************\\r
-* HEDMA_DST - destination address\r
-*\r
-* Fields:\r
-* (RW) HEDMA_DST_DST\r
-*\r
-\******************************************************************************/\r
- #define HEDMA_QDST_ADDR (HEDMA_BASE1_ADDR+0x000C)\r
- #define HEDMA_QSDST_ADDR (HEDMA_BASE1_ADDR+0x002C)\r
- #define HEDMA_QDST REG32(HEDMA_QDST_ADDR)\r
- #define HEDMA_QSDST REG32(HEDMA_QSDST_ADDR)\r
-\r
- #define HEDMA_DST0_ADDR (HEDMA_ENTRY0_ADDR+HEDMA_DST_OFFSET)\r
- #define HEDMA_DST1_ADDR (HEDMA_ENTRY1_ADDR+HEDMA_DST_OFFSET)\r
- #define HEDMA_DST2_ADDR (HEDMA_ENTRY2_ADDR+HEDMA_DST_OFFSET)\r
- #define HEDMA_DST3_ADDR (HEDMA_ENTRY3_ADDR+HEDMA_DST_OFFSET)\r
- #define HEDMA_DST4_ADDR (HEDMA_ENTRY4_ADDR+HEDMA_DST_OFFSET)\r
- #define HEDMA_DST5_ADDR (HEDMA_ENTRY5_ADDR+HEDMA_DST_OFFSET)\r
- #define HEDMA_DST6_ADDR (HEDMA_ENTRY6_ADDR+HEDMA_DST_OFFSET)\r
- #define HEDMA_DST7_ADDR (HEDMA_ENTRY7_ADDR+HEDMA_DST_OFFSET)\r
- #define HEDMA_DST8_ADDR (HEDMA_ENTRY8_ADDR+HEDMA_DST_OFFSET)\r
- #define HEDMA_DST9_ADDR (HEDMA_ENTRY9_ADDR+HEDMA_DST_OFFSET)\r
- #define HEDMA_DST10_ADDR (HEDMA_ENTRY10_ADDR+HEDMA_DST_OFFSET)\r
- #define HEDMA_DST11_ADDR (HEDMA_ENTRY11_ADDR+HEDMA_DST_OFFSET)\r
- #define HEDMA_DST12_ADDR (HEDMA_ENTRY12_ADDR+HEDMA_DST_OFFSET)\r
- #define HEDMA_DST13_ADDR (HEDMA_ENTRY13_ADDR+HEDMA_DST_OFFSET)\r
- #define HEDMA_DST14_ADDR (HEDMA_ENTRY14_ADDR+HEDMA_DST_OFFSET)\r
- #define HEDMA_DST15_ADDR (HEDMA_ENTRY15_ADDR+HEDMA_DST_OFFSET)\r
-\r
- #define HEDMA_DST0 REG32(HEDMA_DST0_ADDR)\r
- #define HEDMA_DST1 REG32(HEDMA_DST1_ADDR)\r
- #define HEDMA_DST2 REG32(HEDMA_DST2_ADDR)\r
- #define HEDMA_DST3 REG32(HEDMA_DST3_ADDR)\r
- #define HEDMA_DST4 REG32(HEDMA_DST4_ADDR)\r
- #define HEDMA_DST5 REG32(HEDMA_DST5_ADDR)\r
- #define HEDMA_DST6 REG32(HEDMA_DST6_ADDR)\r
- #define HEDMA_DST7 REG32(HEDMA_DST7_ADDR)\r
- #define HEDMA_DST8 REG32(HEDMA_DST8_ADDR)\r
- #define HEDMA_DST9 REG32(HEDMA_DST9_ADDR)\r
- #define HEDMA_DST10 REG32(HEDMA_DST10_ADDR)\r
- #define HEDMA_DST11 REG32(HEDMA_DST11_ADDR)\r
- #define HEDMA_DST12 REG32(HEDMA_DST12_ADDR)\r
- #define HEDMA_DST13 REG32(HEDMA_DST13_ADDR)\r
- #define HEDMA_DST14 REG32(HEDMA_DST14_ADDR)\r
- #define HEDMA_DST15 REG32(HEDMA_DST15_ADDR)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_DST_DST\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_DST_DST_MASK (0xFFFFFFFF)\r
- #define HEDMA_DST_DST_SHIFT (0x00000000)\r
- \r
- #define HEDMA_DST_DST_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_DST_DST)\r
-\r
- #define HEDMA_DST_DST_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_DST_DST,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_DST\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_DST_GET(RegAddr) HREG32_GET(RegAddr)\r
- #define HEDMA_DST_SET(RegAddr,Val) HREG32_SET(RegAddr,Val)\r
-\r
- #define HEDMA_DST_CFG(RegAddr,src)\\r
- REG32(RegAddr)=(UINT32)(\\r
- HFIELD_SHIFT(HEDMA_DST_DST,src)\\r
- )\r
-\r
-/******************************************************************************\\r
-* HEDMA_IDX - transfer count\r
-*\r
-* Fields:\r
-* (RW) HEDMA_IDX_ELEIDX\r
-* (RW) HEDMA_IDX_FRMIDX\r
-*\r
-\******************************************************************************/\r
- #define HEDMA_QIDX_ADDR (HEDMA_BASE1_ADDR+0x0010)\r
- #define HEDMA_QSIDX_ADDR (HEDMA_BASE1_ADDR+0x0030)\r
- #define HEDMA_QIDX REG32(HEDMA_QIDX_ADDR)\r
- #define HEDMA_QSIDX REG32(HEDMA_QSIDX_ADDR)\r
- \r
- #define HEDMA_IDX0_ADDR (HEDMA_ENTRY0_ADDR+HEDMA_IDX_OFFSET)\r
- #define HEDMA_IDX1_ADDR (HEDMA_ENTRY1_ADDR+HEDMA_IDX_OFFSET)\r
- #define HEDMA_IDX2_ADDR (HEDMA_ENTRY2_ADDR+HEDMA_IDX_OFFSET)\r
- #define HEDMA_IDX3_ADDR (HEDMA_ENTRY3_ADDR+HEDMA_IDX_OFFSET)\r
- #define HEDMA_IDX4_ADDR (HEDMA_ENTRY4_ADDR+HEDMA_IDX_OFFSET)\r
- #define HEDMA_IDX5_ADDR (HEDMA_ENTRY5_ADDR+HEDMA_IDX_OFFSET)\r
- #define HEDMA_IDX6_ADDR (HEDMA_ENTRY6_ADDR+HEDMA_IDX_OFFSET)\r
- #define HEDMA_IDX7_ADDR (HEDMA_ENTRY7_ADDR+HEDMA_IDX_OFFSET)\r
- #define HEDMA_IDX8_ADDR (HEDMA_ENTRY8_ADDR+HEDMA_IDX_OFFSET)\r
- #define HEDMA_IDX9_ADDR (HEDMA_ENTRY9_ADDR+HEDMA_IDX_OFFSET)\r
- #define HEDMA_IDX10_ADDR (HEDMA_ENTRY10_ADDR+HEDMA_IDX_OFFSET)\r
- #define HEDMA_IDX11_ADDR (HEDMA_ENTRY11_ADDR+HEDMA_IDX_OFFSET)\r
- #define HEDMA_IDX12_ADDR (HEDMA_ENTRY12_ADDR+HEDMA_IDX_OFFSET)\r
- #define HEDMA_IDX13_ADDR (HEDMA_ENTRY13_ADDR+HEDMA_IDX_OFFSET)\r
- #define HEDMA_IDX14_ADDR (HEDMA_ENTRY14_ADDR+HEDMA_IDX_OFFSET)\r
- #define HEDMA_IDX15_ADDR (HEDMA_ENTRY15_ADDR+HEDMA_IDX_OFFSET)\r
-\r
- #define HEDMA_IDX0 REG32(HEDMA_IDX0_ADDR)\r
- #define HEDMA_IDX1 REG32(HEDMA_IDX1_ADDR)\r
- #define HEDMA_IDX2 REG32(HEDMA_IDX2_ADDR)\r
- #define HEDMA_IDX3 REG32(HEDMA_IDX3_ADDR)\r
- #define HEDMA_IDX4 REG32(HEDMA_IDX4_ADDR)\r
- #define HEDMA_IDX5 REG32(HEDMA_IDX5_ADDR)\r
- #define HEDMA_IDX6 REG32(HEDMA_IDX6_ADDR)\r
- #define HEDMA_IDX7 REG32(HEDMA_IDX7_ADDR)\r
- #define HEDMA_IDX8 REG32(HEDMA_IDX8_ADDR)\r
- #define HEDMA_IDX9 REG32(HEDMA_IDX9_ADDR)\r
- #define HEDMA_IDX10 REG32(HEDMA_IDX10_ADDR)\r
- #define HEDMA_IDX11 REG32(HEDMA_IDX11_ADDR)\r
- #define HEDMA_IDX12 REG32(HEDMA_IDX12_ADDR)\r
- #define HEDMA_IDX13 REG32(HEDMA_IDX13_ADDR)\r
- #define HEDMA_IDX14 REG32(HEDMA_IDX14_ADDR)\r
- #define HEDMA_IDX15 REG32(HEDMA_IDX15_ADDR)\r
- \r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_IDX_ELEIDX\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_IDX_ELEIDX_MASK (0x0000FFFF)\r
- #define HEDMA_IDX_ELEIDX_SHIFT (0x00000000)\r
- \r
- #define HEDMA_IDX_ELEIDX_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_IDX_ELEIDX)\r
-\r
- #define HEDMA_IDX_ELEIDX_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_IDX_ELEIDX,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_IDX_FRMIDX\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_IDX_FRMIDX_MASK (0xFFFF0000)\r
- #define HEDMA_IDX_FRMIDX_SHIFT (0x00000010)\r
- \r
- #define HEDMA_IDX_FRMIDX_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_IDX_FRMIDX)\r
-\r
- #define HEDMA_IDX_FRMIDX_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_IDX_FRMIDX,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_IDX\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_IDX_GET(RegAddr) HREG32_GET(RegAddr)\r
- #define HEDMA_IDX_SET(RegAddr,Val) HREG32_SET(RegAddr,Val)\r
-\r
- #define HEDMA_IDX_CFG(RegAddr,eleidx,frmidx)\\r
- REG32(RegAddr)=(UINT32)(\\r
- HFIELD_SHIFT(HEDMA_IDX_ELEIDX,eleidx)|\\r
- HFIELD_SHIFT(HEDMA_IDX_FRMIDX,frmidx)\\r
- )\r
-\r
-/******************************************************************************\\r
-* HEDMA_RLD - element reload/link address\r
-*\r
-* Fields:\r
-* (RW) HEDMA_RLD_LINK\r
-* (RW) HEDMA_RLD_ELERLD\r
-*\r
-\******************************************************************************/\r
- #define HEDMA_RLD0_ADDR (HEDMA_ENTRY0_ADDR+HEDMA_RLD_OFFSET)\r
- #define HEDMA_RLD1_ADDR (HEDMA_ENTRY1_ADDR+HEDMA_RLD_OFFSET)\r
- #define HEDMA_RLD2_ADDR (HEDMA_ENTRY2_ADDR+HEDMA_RLD_OFFSET)\r
- #define HEDMA_RLD3_ADDR (HEDMA_ENTRY3_ADDR+HEDMA_RLD_OFFSET)\r
- #define HEDMA_RLD4_ADDR (HEDMA_ENTRY4_ADDR+HEDMA_RLD_OFFSET)\r
- #define HEDMA_RLD5_ADDR (HEDMA_ENTRY5_ADDR+HEDMA_RLD_OFFSET)\r
- #define HEDMA_RLD6_ADDR (HEDMA_ENTRY6_ADDR+HEDMA_RLD_OFFSET)\r
- #define HEDMA_RLD7_ADDR (HEDMA_ENTRY7_ADDR+HEDMA_RLD_OFFSET)\r
- #define HEDMA_RLD8_ADDR (HEDMA_ENTRY8_ADDR+HEDMA_RLD_OFFSET)\r
- #define HEDMA_RLD9_ADDR (HEDMA_ENTRY9_ADDR+HEDMA_RLD_OFFSET)\r
- #define HEDMA_RLD10_ADDR (HEDMA_ENTRY10_ADDR+HEDMA_RLD_OFFSET)\r
- #define HEDMA_RLD11_ADDR (HEDMA_ENTRY11_ADDR+HEDMA_RLD_OFFSET)\r
- #define HEDMA_RLD12_ADDR (HEDMA_ENTRY12_ADDR+HEDMA_RLD_OFFSET)\r
- #define HEDMA_RLD13_ADDR (HEDMA_ENTRY13_ADDR+HEDMA_RLD_OFFSET)\r
- #define HEDMA_RLD14_ADDR (HEDMA_ENTRY14_ADDR+HEDMA_RLD_OFFSET)\r
- #define HEDMA_RLD15_ADDR (HEDMA_ENTRY15_ADDR+HEDMA_RLD_OFFSET)\r
-\r
- #define HEDMA_RLD0 REG32(HEDMA_RLD0_ADDR)\r
- #define HEDMA_RLD1 REG32(HEDMA_RLD1_ADDR)\r
- #define HEDMA_RLD2 REG32(HEDMA_RLD2_ADDR)\r
- #define HEDMA_RLD3 REG32(HEDMA_RLD3_ADDR)\r
- #define HEDMA_RLD4 REG32(HEDMA_RLD4_ADDR)\r
- #define HEDMA_RLD5 REG32(HEDMA_RLD5_ADDR)\r
- #define HEDMA_RLD6 REG32(HEDMA_RLD6_ADDR)\r
- #define HEDMA_RLD7 REG32(HEDMA_RLD7_ADDR)\r
- #define HEDMA_RLD8 REG32(HEDMA_RLD8_ADDR)\r
- #define HEDMA_RLD9 REG32(HEDMA_RLD9_ADDR)\r
- #define HEDMA_RLD10 REG32(HEDMA_RLD10_ADDR)\r
- #define HEDMA_RLD11 REG32(HEDMA_RLD11_ADDR)\r
- #define HEDMA_RLD12 REG32(HEDMA_RLD12_ADDR)\r
- #define HEDMA_RLD13 REG32(HEDMA_RLD13_ADDR)\r
- #define HEDMA_RLD14 REG32(HEDMA_RLD14_ADDR)\r
- #define HEDMA_RLD15 REG32(HEDMA_RLD15_ADDR)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_RLD_LINK\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_RLD_LINK_MASK (0x0000FFFF)\r
- #define HEDMA_RLD_LINK_SHIFT (0x00000000)\r
- \r
- #define HEDMA_RLD_LINK_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_RLD_LINK)\r
-\r
- #define HEDMA_RLD_LINK_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_RLD_LINK,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_RLD_ELERLD\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_RLD_ELERLD_MASK (0xFFFF0000)\r
- #define HEDMA_RLD_ELERLD_SHIFT (0x00000010)\r
- \r
- #define HEDMA_RLD_ELERLD_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_RLD_ELERLD)\r
-\r
- #define HEDMA_RLD_ELERLD_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_RLD_ELERLD,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_RLD\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_RLD_GET(RegAddr) HREG32_GET(RegAddr)\r
- #define HEDMA_RLD_SET(RegAddr,Val) HREG32_SET(RegAddr,Val)\r
-\r
- #define HEDMA_RLD_CFG(RegAddr,link,elerld)\\r
- REG32(RegAddr)=(UINT32)(\\r
- HFIELD_SHIFT(HEDMA_RLD_LINK,link)|\\r
- HFIELD_SHIFT(HEDMA_RLD_ELERLD,elerld)\\r
- )\r
-\r
-/******************************************************************************\\r
-* HEDMA_PQSR - priority queue status register\r
-*\r
-* Fields:\r
-* (R) HEDMA_PQSR_PQ0\r
-* (R) HEDMA_PQSR_PQ1\r
-* (R) HEDMA_PQSR_PQ2\r
-*\r
-\******************************************************************************/\r
- #define HEDMA_PQSR_ADDR (HEDMA_BASE0_ADDR+0xFFE0)\r
- #define HEDMA_PQSR REG32(HEDMA_PQSR_ADDR)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (R) HEDMA_PQSR_PQ0\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_PQSR_PQ0_MASK (0x00000001)\r
- #define HEDMA_PQSR_PQ0_SHIFT (0x00000000)\r
- \r
- #define HEDMA_PQSR_PQ0_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_PQSR_PQ0)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (R) HEDMA_PQSR_PQ1\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_PQSR_PQ1_MASK (0x00000002)\r
- #define HEDMA_PQSR_PQ1_SHIFT (0x00000001)\r
- \r
- #define HEDMA_PQSR_PQ1_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_PQSR_PQ1)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (R) HEDMA_PQSR_PQ2\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_PQSR_PQ2_MASK (0x00000004)\r
- #define HEDMA_PQSR_PQ2_SHIFT (0x00000002)\r
-\r
- #define HEDMA_PQSR_PQ2_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_PQSR_PQ2)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (R) HEDMA_PQSR\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_PQSR_GET(RegAddr) HREG32_GET(RegAddr)\r
-\r
-/******************************************************************************\\r
-* HEDMA_CIPR - channel interrupt pending register\r
-*\r
-* Fields:\r
-* (RW) HEDMA_CIPR_CIP0\r
-* (RW) HEDMA_CIPR_CIP1\r
-* (RW) HEDMA_CIPR_CIP2\r
-* (RW) HEDMA_CIPR_CIP3\r
-* (RW) HEDMA_CIPR_CIP4\r
-* (RW) HEDMA_CIPR_CIP5\r
-* (RW) HEDMA_CIPR_CIP6\r
-* (RW) HEDMA_CIPR_CIP7\r
-* (RW) HEDMA_CIPR_CIP8\r
-* (RW) HEDMA_CIPR_CIP9\r
-* (RW) HEDMA_CIPR_CIP10\r
-* (RW) HEDMA_CIPR_CIP11\r
-* (RW) HEDMA_CIPR_CIP12\r
-* (RW) HEDMA_CIPR_CIP13\r
-* (RW) HEDMA_CIPR_CIP14\r
-* (RW) HEDMA_CIPR_CIP15\r
-*\r
-\******************************************************************************/\r
- #define HEDMA_CIPR_ADDR (HEDMA_BASE0_ADDR+0xFFE4)\r
- #define HEDMA_CIPR REG32(HEDMA_CIPR_ADDR)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_CIPR_CIP0\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_CIPR_CIP0_MASK (0x00000001)\r
- #define HEDMA_CIPR_CIP0_SHIFT (0x00000000)\r
- \r
- #define HEDMA_CIPR_CIP0_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_CIPR_CIP0)\r
-\r
- #define HEDMA_CIPR_CIP0_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_CIPR_CIP0,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_CIPR_CIP1\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_CIPR_CIP1_MASK (0x00000002)\r
- #define HEDMA_CIPR_CIP1_SHIFT (0x00000001)\r
- \r
- #define HEDMA_CIPR_CIP1_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_CIPR_CIP1)\r
-\r
- #define HEDMA_CIPR_CIP1_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_CIPR_CIP1,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_CIPR_CIP2\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_CIPR_CIP2_MASK (0x00000004)\r
- #define HEDMA_CIPR_CIP2_SHIFT (0x00000002)\r
- \r
- #define HEDMA_CIPR_CIP2_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_CIPR_CIP2)\r
-\r
- #define HEDMA_CIPR_CIP2_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_CIPR_CIP2,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_CIPR_CIP3\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_CIPR_CIP3_MASK (0x00000008)\r
- #define HEDMA_CIPR_CIP3_SHIFT (0x00000003)\r
- \r
- #define HEDMA_CIPR_CIP3_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_CIPR_CIP3)\r
-\r
- #define HEDMA_CIPR_CIP3_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_CIPR_CIP3,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_CIPR_CIP4\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_CIPR_CIP4_MASK (0x00000010)\r
- #define HEDMA_CIPR_CIP4_SHIFT (0x00000004)\r
- \r
- #define HEDMA_CIPR_CIP4_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_CIPR_CIP4)\r
-\r
- #define HEDMA_CIPR_CIP4_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_CIPR_CIP4,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_CIPR_CIP5\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_CIPR_CIP5_MASK (0x00000020)\r
- #define HEDMA_CIPR_CIP5_SHIFT (0x00000005)\r
- \r
- #define HEDMA_CIPR_CIP5_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_CIPR_CIP5)\r
-\r
- #define HEDMA_CIPR_CIP5_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_CIPR_CIP5,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_CIPR_CIP6\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_CIPR_CIP6_MASK (0x00000040)\r
- #define HEDMA_CIPR_CIP6_SHIFT (0x00000006)\r
- \r
- #define HEDMA_CIPR_CIP6_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_CIPR_CIP6)\r
-\r
- #define HEDMA_CIPR_CIP6_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_CIPR_CIP6,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_CIPR_CIP7\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_CIPR_CIP7_MASK (0x00000080)\r
- #define HEDMA_CIPR_CIP7_SHIFT (0x00000007)\r
- \r
- #define HEDMA_CIPR_CIP7_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_CIPR_CIP7)\r
-\r
- #define HEDMA_CIPR_CIP7_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_CIPR_CIP7,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_CIPR_CIP8\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_CIPR_CIP8_MASK (0x00000100)\r
- #define HEDMA_CIPR_CIP8_SHIFT (0x00000008)\r
- \r
- #define HEDMA_CIPR_CIP8_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_CIPR_CIP8)\r
-\r
- #define HEDMA_CIPR_CIP8_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_CIPR_CIP8,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_CIPR_CIP9\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_CIPR_CIP9_MASK (0x00000200)\r
- #define HEDMA_CIPR_CIP9_SHIFT (0x00000009)\r
- \r
- #define HEDMA_CIPR_CIP9_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_CIPR_CIP9)\r
-\r
- #define HEDMA_CIPR_CIP9_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_CIPR_CIP9,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_CIPR_CIP10\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_CIPR_CIP10_MASK (0x00000400)\r
- #define HEDMA_CIPR_CIP10_SHIFT (0x0000000A)\r
- \r
- #define HEDMA_CIPR_CIP10_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_CIPR_CIP10)\r
-\r
- #define HEDMA_CIPR_CIP10_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_CIPR_CIP10,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_CIPR_CIP11\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_CIPR_CIP11_MASK (0x00000800)\r
- #define HEDMA_CIPR_CIP11_SHIFT (0x0000000B)\r
- \r
- #define HEDMA_CIPR_CIP11_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_CIPR_CIP11)\r
-\r
- #define HEDMA_CIPR_CIP11_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_CIPR_CIP11,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_CIPR_CIP12\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_CIPR_CIP12_MASK (0x00001000)\r
- #define HEDMA_CIPR_CIP12_SHIFT (0x0000000C)\r
- \r
- #define HEDMA_CIPR_CIP12_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_CIPR_CIP12)\r
-\r
- #define HEDMA_CIPR_CIP12_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_CIPR_CIP12,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_CIPR_CIP13\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_CIPR_CIP13_MASK (0x00002000)\r
- #define HEDMA_CIPR_CIP13_SHIFT (0x0000000D)\r
- \r
- #define HEDMA_CIPR_CIP13_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_CIPR_CIP13)\r
-\r
- #define HEDMA_CIPR_CIP13_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_CIPR_CIP13,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_CIPR_CIP14\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_CIPR_CIP14_MASK (0x00004000)\r
- #define HEDMA_CIPR_CIP14_SHIFT (0x0000000E)\r
- \r
- #define HEDMA_CIPR_CIP14_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_CIPR_CIP14)\r
-\r
- #define HEDMA_CIPR_CIP14_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_CIPR_CIP14,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_CIPR_CIP15\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_CIPR_CIP15_MASK (0x00008000)\r
- #define HEDMA_CIPR_CIP15_SHIFT (0x0000000F)\r
- \r
- #define HEDMA_CIPR_CIP15_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_CIPR_CIP15)\r
-\r
- #define HEDMA_CIPR_CIP15_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_CIPR_CIP15,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_CIPR\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_CIPR_GET(RegAddr) HREG32_GET(RegAddr)\r
- #define HEDMA_CIPR_SET(RegAddr,Val) HREG32_SET(RegAddr,Val)\r
-\r
- #define HEDMA_CIPR_CFG(RegAddr,cip0,cip1,cip2,cip3,cip4,cip5,cip6,cip7,\\r
- cip8,cip9,cip10,cip11,cip12,cip13,cip14,cip15) REG32(RegAddr)=(UINT32)(\\r
- HFIELD_SHIFT(HEDMA_CIPR_CIP0,cip0)|\\r
- HFIELD_SHIFT(HEDMA_CIPR_CIP1,cip1)|\\r
- HFIELD_SHIFT(HEDMA_CIPR_CIP2,cip2)|\\r
- HFIELD_SHIFT(HEDMA_CIPR_CIP3,cip3)|\\r
- HFIELD_SHIFT(HEDMA_CIPR_CIP4,cip4)|\\r
- HFIELD_SHIFT(HEDMA_CIPR_CIP5,cip5)|\\r
- HFIELD_SHIFT(HEDMA_CIPR_CIP6,cip6)|\\r
- HFIELD_SHIFT(HEDMA_CIPR_CIP7,cip7)|\\r
- HFIELD_SHIFT(HEDMA_CIPR_CIP8,cip8)|\\r
- HFIELD_SHIFT(HEDMA_CIPR_CIP9,cip9)|\\r
- HFIELD_SHIFT(HEDMA_CIPR_CIP10,cip10)|\\r
- HFIELD_SHIFT(HEDMA_CIPR_CIP11,cip11)|\\r
- HFIELD_SHIFT(HEDMA_CIPR_CIP12,cip12)|\\r
- HFIELD_SHIFT(HEDMA_CIPR_CIP13,cip13)|\\r
- HFIELD_SHIFT(HEDMA_CIPR_CIP14,cip14)|\\r
- HFIELD_SHIFT(HEDMA_CIPR_CIP15,cip15)\\r
- )\r
-\r
-/******************************************************************************\\r
-* HEDMA_CIER - channel interrupt enable register\r
-*\r
-* Fields:\r
-* (RW) HEDMA_CIER_CIE0\r
-* (RW) HEDMA_CIER_CIE1\r
-* (RW) HEDMA_CIER_CIE2\r
-* (RW) HEDMA_CIER_CIE3\r
-* (RW) HEDMA_CIER_CIE4\r
-* (RW) HEDMA_CIER_CIE5\r
-* (RW) HEDMA_CIER_CIE6\r
-* (RW) HEDMA_CIER_CIE7\r
-* (RW) HEDMA_CIER_CIE8\r
-* (RW) HEDMA_CIER_CIE9\r
-* (RW) HEDMA_CIER_CIE10\r
-* (RW) HEDMA_CIER_CIE11\r
-* (RW) HEDMA_CIER_CIE12\r
-* (RW) HEDMA_CIER_CIE13\r
-* (RW) HEDMA_CIER_CIE14\r
-* (RW) HEDMA_CIER_CIE15\r
-*\r
-\******************************************************************************/\r
- #define HEDMA_CIER_ADDR (HEDMA_BASE0_ADDR+0xFFE8)\r
- #define HEDMA_CIER REG32(HEDMA_CIER_ADDR)\r
- \r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_CIER_CIE0\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_CIER_CIE0_MASK (0x00000001)\r
- #define HEDMA_CIER_CIE0_SHIFT (0x00000000)\r
- \r
- #define HEDMA_CIER_CIE0_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_CIER_CIE0)\r
-\r
- #define HEDMA_CIER_CIE0_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_CIER_CIE0,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_CIER_CIE1\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_CIER_CIE1_MASK (0x00000002)\r
- #define HEDMA_CIER_CIE1_SHIFT (0x00000001)\r
- \r
- #define HEDMA_CIER_CIE1_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_CIER_CIE1)\r
-\r
- #define HEDMA_CIER_CIE1_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_CIER_CIE1,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_CIER_CIE2\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_CIER_CIE2_MASK (0x00000004)\r
- #define HEDMA_CIER_CIE2_SHIFT (0x00000002)\r
- \r
- #define HEDMA_CIER_CIE2_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_CIER_CIE2)\r
-\r
- #define HEDMA_CIER_CIE2_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_CIER_CIE2,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_CIER_CIE3\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_CIER_CIE3_MASK (0x00000008)\r
- #define HEDMA_CIER_CIE3_SHIFT (0x00000003)\r
- \r
- #define HEDMA_CIER_CIE3_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_CIER_CIE3)\r
-\r
- #define HEDMA_CIER_CIE3_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_CIER_CIE3,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_CIER_CIE4\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_CIER_CIE4_MASK (0x00000010)\r
- #define HEDMA_CIER_CIE4_SHIFT (0x00000004)\r
- \r
- #define HEDMA_CIER_CIE4_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_CIER_CIE4)\r
-\r
- #define HEDMA_CIER_CIE4_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_CIER_CIE4,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_CIER_CIE5\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_CIER_CIE5_MASK (0x00000020)\r
- #define HEDMA_CIER_CIE5_SHIFT (0x00000005)\r
- \r
- #define HEDMA_CIER_CIE5_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_CIER_CIE5)\r
-\r
- #define HEDMA_CIER_CIE5_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_CIER_CIE5,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_CIER_CIE6\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_CIER_CIE6_MASK (0x00000040)\r
- #define HEDMA_CIER_CIE6_SHIFT (0x00000006)\r
- \r
- #define HEDMA_CIER_CIE6_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_CIER_CIE6)\r
-\r
- #define HEDMA_CIER_CIE6_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_CIER_CIE6,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_CIER_CIE7\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_CIER_CIE7_MASK (0x00000080)\r
- #define HEDMA_CIER_CIE7_SHIFT (0x00000007)\r
- \r
- #define HEDMA_CIER_CIE7_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_CIER_CIE7)\r
-\r
- #define HEDMA_CIER_CIE7_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_CIER_CIE7,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_CIER_CIE8\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_CIER_CIE8_MASK (0x00000100)\r
- #define HEDMA_CIER_CIE8_SHIFT (0x00000008)\r
- \r
- #define HEDMA_CIER_CIE8_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_CIER_CIE8)\r
-\r
- #define HEDMA_CIER_CIE8_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_CIER_CIE8,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_CIER_CIE9\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_CIER_CIE9_MASK (0x00000200)\r
- #define HEDMA_CIER_CIE9_SHIFT (0x00000009)\r
- \r
- #define HEDMA_CIER_CIE9_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_CIER_CIE9)\r
-\r
- #define HEDMA_CIER_CIE9_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_CIER_CIE9,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_CIER_CIE10\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_CIER_CIE10_MASK (0x00000400)\r
- #define HEDMA_CIER_CIE10_SHIFT (0x0000000A)\r
- \r
- #define HEDMA_CIER_CIE10_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_CIER_CIE10)\r
-\r
- #define HEDMA_CIER_CIE10_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_CIER_CIE10,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_CIER_CIE11\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_CIER_CIE11_MASK (0x00000800)\r
- #define HEDMA_CIER_CIE11_SHIFT (0x0000000B)\r
- \r
- #define HEDMA_CIER_CIE11_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_CIER_CIE11)\r
-\r
- #define HEDMA_CIER_CIE11_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_CIER_CIE11,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_CIER_CIE12\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_CIER_CIE12_MASK (0x00001000)\r
- #define HEDMA_CIER_CIE12_SHIFT (0x0000000C)\r
- \r
- #define HEDMA_CIER_CIE12_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_CIER_CIE12)\r
-\r
- #define HEDMA_CIER_CIE12_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_CIER_CIE12,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_CIER_CIE13\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_CIER_CIE13_MASK (0x00002000)\r
- #define HEDMA_CIER_CIE13_SHIFT (0x0000000D)\r
- \r
- #define HEDMA_CIER_CIE13_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_CIER_CIE13)\r
-\r
- #define HEDMA_CIER_CIE13_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_CIER_CIE13,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_CIER_CIE14\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_CIER_CIE14_MASK (0x00004000)\r
- #define HEDMA_CIER_CIE14_SHIFT (0x0000000E)\r
- \r
- #define HEDMA_CIER_CIE14_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_CIER_CIE14)\r
-\r
- #define HEDMA_CIER_CIE14_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_CIER_CIE14,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_CIER_CIE15\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_CIER_CIE15_MASK (0x00008000)\r
- #define HEDMA_CIER_CIE15_SHIFT (0x0000000F)\r
- \r
- #define HEDMA_CIER_CIE15_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_CIER_CIE15)\r
-\r
- #define HEDMA_CIER_CIE15_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_CIER_CIE15,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_CIER\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_CIER_GET(RegAddr) HREG32_GET(RegAddr)\r
- #define HEDMA_CIER_SET(RegAddr,Val) HREG32_SET(RegAddr,Val)\r
-\r
- #define HEDMA_CIER_CFG(RegAddr,cie0,cie1,cie2,cie3,cie4,cie5,cie6,cie7,\\r
- cie8,cie9,cie10,cie11,cie12,cie13,cie14,cie15) REG32(RegAddr)=(UINT32)(\\r
- HFIELD_SHIFT(HEDMA_CIER_CIE0,cie0)|\\r
- HFIELD_SHIFT(HEDMA_CIER_CIE1,cie1)|\\r
- HFIELD_SHIFT(HEDMA_CIER_CIE2,cie2)|\\r
- HFIELD_SHIFT(HEDMA_CIER_CIE3,cie3)|\\r
- HFIELD_SHIFT(HEDMA_CIER_CIE4,cie4)|\\r
- HFIELD_SHIFT(HEDMA_CIER_CIE5,cie5)|\\r
- HFIELD_SHIFT(HEDMA_CIER_CIE6,cie6)|\\r
- HFIELD_SHIFT(HEDMA_CIER_CIE7,cie7)|\\r
- HFIELD_SHIFT(HEDMA_CIER_CIE8,cie8)|\\r
- HFIELD_SHIFT(HEDMA_CIER_CIE9,cie9)|\\r
- HFIELD_SHIFT(HEDMA_CIER_CIE10,cie10)|\\r
- HFIELD_SHIFT(HEDMA_CIER_CIE11,cie11)|\\r
- HFIELD_SHIFT(HEDMA_CIER_CIE12,cie12)|\\r
- HFIELD_SHIFT(HEDMA_CIER_CIE13,cie13)|\\r
- HFIELD_SHIFT(HEDMA_CIER_CIE14,cie14)|\\r
- HFIELD_SHIFT(HEDMA_CIER_CIE15,cie15)\\r
- )\r
-\r
-/******************************************************************************\\r
-* HEDMA_CCER - channel chain enable register\r
-*\r
-* Fields:\r
-* (RW) HEDMA_CCER_CCE8\r
-* (RW) HEDMA_CCER_CCE9\r
-* (RW) HEDMA_CCER_CCE10\r
-* (RW) HEDMA_CCER_CCE11\r
-*\r
-\******************************************************************************/\r
- #define HEDMA_CCER_ADDR (HEDMA_BASE0_ADDR+0xFFEC)\r
- #define HEDMA_CCER REG32(HEDMA_CCER_ADDR)\r
- \r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_CCER_CCE8\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_CCER_CCE8_MASK (0x00000100)\r
- #define HEDMA_CCER_CCE8_SHIFT (0x00000008)\r
- \r
- #define HEDMA_CCER_CCE8_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_CCER_CCE8)\r
-\r
- #define HEDMA_CCER_CCE8_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_CCER_CCE8,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_CCER_CCE9\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_CCER_CCE9_MASK (0x00000200)\r
- #define HEDMA_CCER_CCE9_SHIFT (0x00000009)\r
- \r
- #define HEDMA_CCER_CCE9_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_CCER_CCE9)\r
-\r
- #define HEDMA_CCER_CCE9_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_CCER_CCE9,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_CCER_CCE10\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_CCER_CCE10_MASK (0x00000400)\r
- #define HEDMA_CCER_CCE10_SHIFT (0x0000000A)\r
- \r
- #define HEDMA_CCER_CCE10_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_CCER_CCE10)\r
-\r
- #define HEDMA_CCER_CCE10_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_CCER_CCE10,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_CCER_CCE11\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_CCER_CCE11_MASK (0x00000800)\r
- #define HEDMA_CCER_CCE11_SHIFT (0x0000000B)\r
- \r
- #define HEDMA_CCER_CCE11_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_CCER_CCE11)\r
-\r
- #define HEDMA_CCER_CCE11_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_CCER_CCE11,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_CCER\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_CCER_GET(RegAddr) HREG32_GET(RegAddr)\r
- #define HEDMA_CCER_SET(RegAddr,Val) HREG32_SET(RegAddr,Val)\r
-\r
- #define HEDMA_CCER_CFG(RegAddr,cce8,cce9,cce10,cce11)\\r
- REG32(RegAddr)=(UINT32)(\\r
- HFIELD_SHIFT(HEDMA_CCER_CCE8,cce8)|\\r
- HFIELD_SHIFT(HEDMA_CCER_CCE9,cce9)|\\r
- HFIELD_SHIFT(HEDMA_CCER_CCE10,cce10)|\\r
- HFIELD_SHIFT(HEDMA_CCER_CCE11,cce11)\\r
- )\r
-\r
-/******************************************************************************\\r
-* HEDMA_ER - event register\r
-*\r
-* Fields:\r
-* (R) HEDMA_ER_EVT0\r
-* (R) HEDMA_ER_EVT1\r
-* (R) HEDMA_ER_EVT2\r
-* (R) HEDMA_ER_EVT3\r
-* (R) HEDMA_ER_EVT4\r
-* (R) HEDMA_ER_EVT5\r
-* (R) HEDMA_ER_EVT6\r
-* (R) HEDMA_ER_EVT7\r
-* (R) HEDMA_ER_EVT8\r
-* (R) HEDMA_ER_EVT9\r
-* (R) HEDMA_ER_EVT10\r
-* (R) HEDMA_ER_EVT11\r
-* (R) HEDMA_ER_EVT12\r
-* (R) HEDMA_ER_EVT13\r
-* (R) HEDMA_ER_EVT14\r
-* (R) HEDMA_ER_EVT15\r
-*\r
-\******************************************************************************/\r
- #define HEDMA_ER_ADDR (HEDMA_BASE0_ADDR+0xFFF0)\r
- #define HEDMA_ER REG32(HEDMA_ER_ADDR)\r
- \r
-/*----------------------------------------------------------------------------*\\r
-* (R) HEDMA_ER_EVT0\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_ER_EVT0_MASK (0x00000001)\r
- #define HEDMA_ER_EVT0_SHIFT (0x00000000)\r
- \r
- #define HEDMA_ER_EVT0_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_ER_EVT0)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (R) HEDMA_ER_EVT1\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_ER_EVT1_MASK (0x00000002)\r
- #define HEDMA_ER_EVT1_SHIFT (0x00000001)\r
- \r
- #define HEDMA_ER_EVT1_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_ER_EVT1)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (R) HEDMA_ER_EVT2\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_ER_EVT2_MASK (0x00000004)\r
- #define HEDMA_ER_EVT2_SHIFT (0x00000002)\r
- \r
- #define HEDMA_ER_EVT2_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_ER_EVT2)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (R) HEDMA_ER_EVT3\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_ER_EVT3_MASK (0x00000008)\r
- #define HEDMA_ER_EVT3_SHIFT (0x00000003)\r
- \r
- #define HEDMA_ER_EVT3_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_ER_EVT3)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (R) HEDMA_ER_EVT4\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_ER_EVT4_MASK (0x00000010)\r
- #define HEDMA_ER_EVT4_SHIFT (0x00000004)\r
- \r
- #define HEDMA_ER_EVT4_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_ER_EVT4)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (R) HEDMA_ER_EVT5\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_ER_EVT5_MASK (0x00000020)\r
- #define HEDMA_ER_EVT5_SHIFT (0x00000005)\r
- \r
- #define HEDMA_ER_EVT5_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_ER_EVT5)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (R) HEDMA_ER_EVT6\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_ER_EVT6_MASK (0x00000040)\r
- #define HEDMA_ER_EVT6_SHIFT (0x00000006)\r
- \r
- #define HEDMA_ER_EVT6_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_ER_EVT6)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (R) HEDMA_ER_EVT7\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_ER_EVT7_MASK (0x00000080)\r
- #define HEDMA_ER_EVT7_SHIFT (0x00000007)\r
- \r
- #define HEDMA_ER_EVT7_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_ER_EVT7)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (R) HEDMA_ER_EVT8\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_ER_EVT8_MASK (0x00000100)\r
- #define HEDMA_ER_EVT8_SHIFT (0x00000008)\r
- \r
- #define HEDMA_ER_EVT8_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_ER_EVT8)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (R) HEDMA_ER_EVT9\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_ER_EVT9_MASK (0x00000200)\r
- #define HEDMA_ER_EVT9_SHIFT (0x00000009)\r
- \r
- #define HEDMA_ER_EVT9_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_ER_EVT9)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (R) HEDMA_ER_EVT10\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_ER_EVT10_MASK (0x00000400)\r
- #define HEDMA_ER_EVT10_SHIFT (0x0000000A)\r
- \r
- #define HEDMA_ER_EVT10_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_ER_EVT10)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (R) HEDMA_ER_EVT11\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_ER_EVT11_MASK (0x00000800)\r
- #define HEDMA_ER_EVT11_SHIFT (0x0000000B)\r
- \r
- #define HEDMA_ER_EVT11_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_ER_EVT11)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (R) HEDMA_ER_EVT12\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_ER_EVT12_MASK (0x00001000)\r
- #define HEDMA_ER_EVT12_SHIFT (0x0000000C)\r
- \r
- #define HEDMA_ER_EVT12_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_ER_EVT12)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (R) HEDMA_ER_EVT13\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_ER_EVT13_MASK (0x00002000)\r
- #define HEDMA_ER_EVT13_SHIFT (0x0000000D)\r
- \r
- #define HEDMA_ER_EVT13_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_ER_EVT13)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (R) HEDMA_ER_EVT14\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_ER_EVT14_MASK (0x00004000)\r
- #define HEDMA_ER_EVT14_SHIFT (0x0000000E)\r
- \r
- #define HEDMA_ER_EVT14_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_ER_EVT14)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (R) HEDMA_ER_EVT15\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_ER_EVT15_MASK (0x00008000)\r
- #define HEDMA_ER_EVT15_SHIFT (0x0000000F)\r
- \r
- #define HEDMA_ER_EVT15_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_ER_EVT15)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (R) HEDMA_ER\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_ER_GET(RegAddr) HREG32_GET(RegAddr)\r
-\r
-/******************************************************************************\\r
-* HEDMA_EER - event enable register\r
-*\r
-* Fields:\r
-* (RW) HEDMA_EER_EE0\r
-* (RW) HEDMA_EER_EE1\r
-* (RW) HEDMA_EER_EE2\r
-* (RW) HEDMA_EER_EE3\r
-* (RW) HEDMA_EER_EE4\r
-* (RW) HEDMA_EER_EE5\r
-* (RW) HEDMA_EER_EE6\r
-* (RW) HEDMA_EER_EE7\r
-* (RW) HEDMA_EER_EE8\r
-* (RW) HEDMA_EER_EE9\r
-* (RW) HEDMA_EER_EE10\r
-* (RW) HEDMA_EER_EE11\r
-* (RW) HEDMA_EER_EE12\r
-* (RW) HEDMA_EER_EE13\r
-* (RW) HEDMA_EER_EE14\r
-* (RW) HEDMA_EER_EE15\r
-*\r
-\******************************************************************************/\r
- #define HEDMA_EER_ADDR (HEDMA_BASE0_ADDR+0xFFF4)\r
- #define HEDMA_EER REG32(HEDMA_EER_ADDR)\r
- \r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_EER_EE0\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_EER_EE0_MASK (0x00000001)\r
- #define HEDMA_EER_EE0_SHIFT (0x00000000)\r
- \r
- #define HEDMA_EER_EE0_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_EER_EE0)\r
-\r
- #define HEDMA_EER_EE0_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_EER_EE0,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_EER_EE1\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_EER_EE1_MASK (0x00000002)\r
- #define HEDMA_EER_EE1_SHIFT (0x00000001)\r
- \r
- #define HEDMA_EER_EE1_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_EER_EE1)\r
-\r
- #define HEDMA_EER_EE1_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_EER_EE1,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_EER_EE2\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_EER_EE2_MASK (0x00000004)\r
- #define HEDMA_EER_EE2_SHIFT (0x00000002)\r
- \r
- #define HEDMA_EER_EE2_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_EER_EE2)\r
-\r
- #define HEDMA_EER_EE2_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_EER_EE2,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_EER_EE3\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_EER_EE3_MASK (0x00000008)\r
- #define HEDMA_EER_EE3_SHIFT (0x00000003)\r
- \r
- #define HEDMA_EER_EE3_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_EER_EE3)\r
-\r
- #define HEDMA_EER_EE3_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_EER_EE3,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_EER_EE4\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_EER_EE4_MASK (0x00000010)\r
- #define HEDMA_EER_EE4_SHIFT (0x00000004)\r
- \r
- #define HEDMA_EER_EE4_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_EER_EE4)\r
-\r
- #define HEDMA_EER_EE4_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_EER_EE4,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_EER_EE5\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_EER_EE5_MASK (0x00000020)\r
- #define HEDMA_EER_EE5_SHIFT (0x00000005)\r
- \r
- #define HEDMA_EER_EE5_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_EER_EE5)\r
-\r
- #define HEDMA_EER_EE5_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_EER_EE5,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_EER_EE6\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_EER_EE6_MASK (0x00000040)\r
- #define HEDMA_EER_EE6_SHIFT (0x00000006)\r
- \r
- #define HEDMA_EER_EE6_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_EER_EE6)\r
-\r
- #define HEDMA_EER_EE6_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_EER_EE6,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_EER_EE7\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_EER_EE7_MASK (0x00000080)\r
- #define HEDMA_EER_EE7_SHIFT (0x00000007)\r
- \r
- #define HEDMA_EER_EE7_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_EER_EE7)\r
-\r
- #define HEDMA_EER_EE7_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_EER_EE7,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_EER_EE8\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_EER_EE8_MASK (0x00000100)\r
- #define HEDMA_EER_EE8_SHIFT (0x00000008)\r
- \r
- #define HEDMA_EER_EE8_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_EER_EE8)\r
-\r
- #define HEDMA_EER_EE8_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_EER_EE8,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_EER_EE9\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_EER_EE9_MASK (0x00000200)\r
- #define HEDMA_EER_EE9_SHIFT (0x00000009)\r
- \r
- #define HEDMA_EER_EE9_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_EER_EE9)\r
-\r
- #define HEDMA_EER_EE9_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_EER_EE9,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_EER_EE10\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_EER_EE10_MASK (0x00000400)\r
- #define HEDMA_EER_EE10_SHIFT (0x0000000A)\r
- \r
- #define HEDMA_EER_EE10_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_EER_EE10)\r
-\r
- #define HEDMA_EER_EE10_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_EER_EE10,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_EER_EE11\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_EER_EE11_MASK (0x00000800)\r
- #define HEDMA_EER_EE11_SHIFT (0x0000000B)\r
- \r
- #define HEDMA_EER_EE11_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_EER_EE11)\r
-\r
- #define HEDMA_EER_EE11_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_EER_EE11,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_EER_EE12\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_EER_EE12_MASK (0x00001000)\r
- #define HEDMA_EER_EE12_SHIFT (0x0000000C)\r
- \r
- #define HEDMA_EER_EE12_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_EER_EE12)\r
-\r
- #define HEDMA_EER_EE12_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_EER_EE12,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_EER_EE13\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_EER_EE13_MASK (0x00002000)\r
- #define HEDMA_EER_EE13_SHIFT (0x0000000D)\r
- \r
- #define HEDMA_EER_EE13_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_EER_EE13)\r
-\r
- #define HEDMA_EER_EE13_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_EER_EE13,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_EER_EE14\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_EER_EE14_MASK (0x00004000)\r
- #define HEDMA_EER_EE14_SHIFT (0x0000000E)\r
- \r
- #define HEDMA_EER_EE14_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_EER_EE14)\r
-\r
- #define HEDMA_EER_EE14_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_EER_EE14,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_EER_EE15\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_EER_EE15_MASK (0x00008000)\r
- #define HEDMA_EER_EE15_SHIFT (0x0000000F)\r
- \r
- #define HEDMA_EER_EE15_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_EER_EE15)\r
-\r
- #define HEDMA_EER_EE15_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_EER_EE15,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_EER\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_EER_GET(RegAddr) HREG32_GET(RegAddr)\r
- #define HEDMA_EER_SET(RegAddr,Val) HREG32_SET(RegAddr,Val)\r
-\r
- #define HEDMA_EER_CFG(RegAddr,ee0,ee1,ee2,ee3,ee4,ee5,ee6,ee7,\\r
- ee8,ee9,ee10,ee11,ee12,ee13,ee14,ee15) REG32(RegAddr)=(UINT32)(\\r
- HFIELD_SHIFT(HEDMA_EER_EE0,ee0)|\\r
- HFIELD_SHIFT(HEDMA_EER_EE1,ee1)|\\r
- HFIELD_SHIFT(HEDMA_EER_EE2,ee2)|\\r
- HFIELD_SHIFT(HEDMA_EER_EE3,ee3)|\\r
- HFIELD_SHIFT(HEDMA_EER_EE4,ee4)|\\r
- HFIELD_SHIFT(HEDMA_EER_EE5,ee5)|\\r
- HFIELD_SHIFT(HEDMA_EER_EE6,ee6)|\\r
- HFIELD_SHIFT(HEDMA_EER_EE7,ee7)|\\r
- HFIELD_SHIFT(HEDMA_EER_EE8,ee8)|\\r
- HFIELD_SHIFT(HEDMA_EER_EE9,ee9)|\\r
- HFIELD_SHIFT(HEDMA_EER_EE10,ee10)|\\r
- HFIELD_SHIFT(HEDMA_EER_EE11,ee11)|\\r
- HFIELD_SHIFT(HEDMA_EER_EE12,ee12)|\\r
- HFIELD_SHIFT(HEDMA_EER_EE13,ee13)|\\r
- HFIELD_SHIFT(HEDMA_EER_EE14,ee14)|\\r
- HFIELD_SHIFT(HEDMA_EER_EE15,ee15)\\r
- )\r
-\r
-/******************************************************************************\\r
-* HEDMA_ECR - event clear register\r
-*\r
-* Fields:\r
-* (RW) HEDMA_ECR_EC0\r
-* (RW) HEDMA_ECR_EC1\r
-* (RW) HEDMA_ECR_EC2\r
-* (RW) HEDMA_ECR_EC3\r
-* (RW) HEDMA_ECR_EC4\r
-* (RW) HEDMA_ECR_EC5\r
-* (RW) HEDMA_ECR_EC6\r
-* (RW) HEDMA_ECR_EC7\r
-* (RW) HEDMA_ECR_EC8\r
-* (RW) HEDMA_ECR_EC9\r
-* (RW) HEDMA_ECR_EC10\r
-* (RW) HEDMA_ECR_EC11\r
-* (RW) HEDMA_ECR_EC12\r
-* (RW) HEDMA_ECR_EC13\r
-* (RW) HEDMA_ECR_EC14\r
-* (RW) HEDMA_ECR_EC15\r
-*\r
-\******************************************************************************/\r
- #define HEDMA_ECR_ADDR (HEDMA_BASE0_ADDR+0xFFF8)\r
- #define HEDMA_ECR REG32(HEDMA_ECR_ADDR)\r
- \r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_ECR_EC0\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_ECR_EC0_MASK (0x00000001)\r
- #define HEDMA_ECR_EC0_SHIFT (0x00000000)\r
- \r
- #define HEDMA_ECR_EC0_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_ECR_EC0)\r
-\r
- #define HEDMA_ECR_EC0_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_ECR_EC0,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_ECR_EC1\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_ECR_EC1_MASK (0x00000002)\r
- #define HEDMA_ECR_EC1_SHIFT (0x00000001)\r
- \r
- #define HEDMA_ECR_EC1_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_ECR_EC1)\r
-\r
- #define HEDMA_ECR_EC1_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_ECR_EC1,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_ECR_EC2\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_ECR_EC2_MASK (0x00000004)\r
- #define HEDMA_ECR_EC2_SHIFT (0x00000002)\r
- \r
- #define HEDMA_ECR_EC2_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_ECR_EC2)\r
-\r
- #define HEDMA_ECR_EC2_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_ECR_EC2,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_ECR_EC3\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_ECR_EC3_MASK (0x00000008)\r
- #define HEDMA_ECR_EC3_SHIFT (0x00000003)\r
- \r
- #define HEDMA_ECR_EC3_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_ECR_EC3)\r
-\r
- #define HEDMA_ECR_EC3_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_ECR_EC3,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_ECR_EC4\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_ECR_EC4_MASK (0x00000010)\r
- #define HEDMA_ECR_EC4_SHIFT (0x00000004)\r
- \r
- #define HEDMA_ECR_EC4_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_ECR_EC4)\r
-\r
- #define HEDMA_ECR_EC4_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_ECR_EC4,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_ECR_EC5\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_ECR_EC5_MASK (0x00000020)\r
- #define HEDMA_ECR_EC5_SHIFT (0x00000005)\r
- \r
- #define HEDMA_ECR_EC5_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_ECR_EC5)\r
-\r
- #define HEDMA_ECR_EC5_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_ECR_EC5,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_ECR_EC6\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_ECR_EC6_MASK (0x00000040)\r
- #define HEDMA_ECR_EC6_SHIFT (0x00000006)\r
- \r
- #define HEDMA_ECR_EC6_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_ECR_EC6)\r
-\r
- #define HEDMA_ECR_EC6_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_ECR_EC6,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_ECR_EC7\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_ECR_EC7_MASK (0x00000080)\r
- #define HEDMA_ECR_EC7_SHIFT (0x00000007)\r
- \r
- #define HEDMA_ECR_EC7_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_ECR_EC7)\r
-\r
- #define HEDMA_ECR_EC7_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_ECR_EC7,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_ECR_EC8\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_ECR_EC8_MASK (0x00000100)\r
- #define HEDMA_ECR_EC8_SHIFT (0x00000008)\r
- \r
- #define HEDMA_ECR_EC8_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_ECR_EC8)\r
-\r
- #define HEDMA_ECR_EC8_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_ECR_EC8,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_ECR_EC9\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_ECR_EC9_MASK (0x00000200)\r
- #define HEDMA_ECR_EC9_SHIFT (0x00000009)\r
- \r
- #define HEDMA_ECR_EC9_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_ECR_EC9)\r
-\r
- #define HEDMA_ECR_EC9_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_ECR_EC9,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_ECR_EC10\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_ECR_EC10_MASK (0x00000400)\r
- #define HEDMA_ECR_EC10_SHIFT (0x0000000A)\r
- \r
- #define HEDMA_ECR_EC10_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_ECR_EC10)\r
-\r
- #define HEDMA_ECR_EC10_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_ECR_EC10,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_ECR_EC11\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_ECR_EC11_MASK (0x00000800)\r
- #define HEDMA_ECR_EC11_SHIFT (0x0000000B)\r
- \r
- #define HEDMA_ECR_EC11_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_ECR_EC11)\r
-\r
- #define HEDMA_ECR_EC11_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_ECR_EC11,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_ECR_EC12\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_ECR_EC12_MASK (0x00001000)\r
- #define HEDMA_ECR_EC12_SHIFT (0x0000000C)\r
- \r
- #define HEDMA_ECR_EC12_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_ECR_EC12)\r
-\r
- #define HEDMA_ECR_EC12_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_ECR_EC12,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_ECR_EC13\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_ECR_EC13_MASK (0x00002000)\r
- #define HEDMA_ECR_EC13_SHIFT (0x0000000D)\r
- \r
- #define HEDMA_ECR_EC13_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_ECR_EC13)\r
-\r
- #define HEDMA_ECR_EC13_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_ECR_EC13,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_ECR_EC14\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_ECR_EC14_MASK (0x00004000)\r
- #define HEDMA_ECR_EC14_SHIFT (0x0000000E)\r
- \r
- #define HEDMA_ECR_EC14_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_ECR_EC14)\r
-\r
- #define HEDMA_ECR_EC14_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_ECR_EC14,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_ECR_EC15\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_ECR_EC15_MASK (0x00008000)\r
- #define HEDMA_ECR_EC15_SHIFT (0x0000000F)\r
- \r
- #define HEDMA_ECR_EC15_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_ECR_EC15)\r
-\r
- #define HEDMA_ECR_EC15_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_ECR_EC15,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_ECR\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_ECR_GET(RegAddr) HREG32_GET(RegAddr)\r
- #define HEDMA_ECR_SET(RegAddr,Val) HREG32_SET(RegAddr,Val)\r
-\r
- #define HEDMA_ECR_CFG(RegAddr,ec0,ec1,ec2,ec3,ec4,ec5,ec6,ec7,\\r
- ec8,ec9,ec10,ec11,ec12,ec13,ec14,ec15) REG32(RegAddr)=(UINT32)(\\r
- HFIELD_SHIFT(HEDMA_ECR_EC0,ec0)|\\r
- HFIELD_SHIFT(HEDMA_ECR_EC1,ec1)|\\r
- HFIELD_SHIFT(HEDMA_ECR_EC2,ec2)|\\r
- HFIELD_SHIFT(HEDMA_ECR_EC3,ec3)|\\r
- HFIELD_SHIFT(HEDMA_ECR_EC4,ec4)|\\r
- HFIELD_SHIFT(HEDMA_ECR_EC5,ec5)|\\r
- HFIELD_SHIFT(HEDMA_ECR_EC6,ec6)|\\r
- HFIELD_SHIFT(HEDMA_ECR_EC7,ec7)|\\r
- HFIELD_SHIFT(HEDMA_ECR_EC8,ec8)|\\r
- HFIELD_SHIFT(HEDMA_ECR_EC9,ec9)|\\r
- HFIELD_SHIFT(HEDMA_ECR_EC10,ec10)|\\r
- HFIELD_SHIFT(HEDMA_ECR_EC11,ec11)|\\r
- HFIELD_SHIFT(HEDMA_ECR_EC12,ec12)|\\r
- HFIELD_SHIFT(HEDMA_ECR_EC13,ec13)|\\r
- HFIELD_SHIFT(HEDMA_ECR_EC14,ec14)|\\r
- HFIELD_SHIFT(HEDMA_ECR_EC15,ec15)\\r
- )\r
- \r
-/******************************************************************************\\r
-* HEDMA_ESR - event set register\r
-*\r
-* Fields:\r
-* (RW) HEDMA_ESR_ES0\r
-* (RW) HEDMA_ESR_ES1\r
-* (RW) HEDMA_ESR_ES2\r
-* (RW) HEDMA_ESR_ES3\r
-* (RW) HEDMA_ESR_ES4\r
-* (RW) HEDMA_ESR_ES5\r
-* (RW) HEDMA_ESR_ES6\r
-* (RW) HEDMA_ESR_ES7\r
-* (RW) HEDMA_ESR_ES8\r
-* (RW) HEDMA_ESR_ES9\r
-* (RW) HEDMA_ESR_ES10\r
-* (RW) HEDMA_ESR_ES11\r
-* (RW) HEDMA_ESR_ES12\r
-* (RW) HEDMA_ESR_ES13\r
-* (RW) HEDMA_ESR_ES14\r
-* (RW) HEDMA_ESR_ES15\r
-*\r
-\******************************************************************************/\r
- #define HEDMA_ESR_ADDR (HEDMA_BASE0_ADDR+0xFFFC)\r
- #define HEDMA_ESR REG32(HEDMA_ESR_ADDR)\r
- \r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_ESR_ES0\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_ESR_ES0_MASK (0x00000001)\r
- #define HEDMA_ESR_ES0_SHIFT (0x00000000)\r
- \r
- #define HEDMA_ESR_ES0_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_ESR_ES0)\r
-\r
- #define HEDMA_ESR_ES0_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_ESR_ES0,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_ESR_ES1\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_ESR_ES1_MASK (0x00000002)\r
- #define HEDMA_ESR_ES1_SHIFT (0x00000001)\r
- \r
- #define HEDMA_ESR_ES1_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_ESR_ES1)\r
-\r
- #define HEDMA_ESR_ES1_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_ESR_ES1,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_ESR_ES2\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_ESR_ES2_MASK (0x00000004)\r
- #define HEDMA_ESR_ES2_SHIFT (0x00000002)\r
- \r
- #define HEDMA_ESR_ES2_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_ESR_ES2)\r
-\r
- #define HEDMA_ESR_ES2_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_ESR_ES2,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_ESR_ES3\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_ESR_ES3_MASK (0x00000008)\r
- #define HEDMA_ESR_ES3_SHIFT (0x00000003)\r
- \r
- #define HEDMA_ESR_ES3_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_ESR_ES3)\r
-\r
- #define HEDMA_ESR_ES3_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_ESR_ES3,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_ESR_ES4\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_ESR_ES4_MASK (0x00000010)\r
- #define HEDMA_ESR_ES4_SHIFT (0x00000004)\r
- \r
- #define HEDMA_ESR_ES4_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_ESR_ES4)\r
-\r
- #define HEDMA_ESR_ES4_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_ESR_ES4,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_ESR_ES5\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_ESR_ES5_MASK (0x00000020)\r
- #define HEDMA_ESR_ES5_SHIFT (0x00000005)\r
- \r
- #define HEDMA_ESR_ES5_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_ESR_ES5)\r
-\r
- #define HEDMA_ESR_ES5_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_ESR_ES5,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_ESR_ES6\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_ESR_ES6_MASK (0x00000040)\r
- #define HEDMA_ESR_ES6_SHIFT (0x00000006)\r
- \r
- #define HEDMA_ESR_ES6_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_ESR_ES6)\r
-\r
- #define HEDMA_ESR_ES6_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_ESR_ES6,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_ESR_ES7\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_ESR_ES7_MASK (0x00000080)\r
- #define HEDMA_ESR_ES7_SHIFT (0x00000007)\r
- \r
- #define HEDMA_ESR_ES7_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_ESR_ES7)\r
-\r
- #define HEDMA_ESR_ES7_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_ESR_ES7,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_ESR_ES8\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_ESR_ES8_MASK (0x00000100)\r
- #define HEDMA_ESR_ES8_SHIFT (0x00000008)\r
- \r
- #define HEDMA_ESR_ES8_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_ESR_ES8)\r
-\r
- #define HEDMA_ESR_ES8_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_ESR_ES8,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_ESR_ES9\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_ESR_ES9_MASK (0x00000200)\r
- #define HEDMA_ESR_ES9_SHIFT (0x00000009)\r
- \r
- #define HEDMA_ESR_ES9_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_ESR_ES9)\r
-\r
- #define HEDMA_ESR_ES9_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_ESR_ES9,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_ESR_ES10\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_ESR_ES10_MASK (0x00000400)\r
- #define HEDMA_ESR_ES10_SHIFT (0x0000000A)\r
- \r
- #define HEDMA_ESR_ES10_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_ESR_ES10)\r
-\r
- #define HEDMA_ESR_ES10_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_ESR_ES10,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_ESR_ES11\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_ESR_ES11_MASK (0x00000800)\r
- #define HEDMA_ESR_ES11_SHIFT (0x0000000B)\r
- \r
- #define HEDMA_ESR_ES11_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_ESR_ES11)\r
-\r
- #define HEDMA_ESR_ES11_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_ESR_ES11,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_ESR_ES12\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_ESR_ES12_MASK (0x00001000)\r
- #define HEDMA_ESR_ES12_SHIFT (0x0000000C)\r
- \r
- #define HEDMA_ESR_ES12_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_ESR_ES12)\r
-\r
- #define HEDMA_ESR_ES12_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_ESR_ES12,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_ESR_ES13\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_ESR_ES13_MASK (0x00002000)\r
- #define HEDMA_ESR_ES13_SHIFT (0x0000000D)\r
- \r
- #define HEDMA_ESR_ES13_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_ESR_ES13)\r
-\r
- #define HEDMA_ESR_ES13_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_ESR_ES13,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_ESR_ES14\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_ESR_ES14_MASK (0x00004000)\r
- #define HEDMA_ESR_ES14_SHIFT (0x0000000E)\r
- \r
- #define HEDMA_ESR_ES14_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_ESR_ES14)\r
-\r
- #define HEDMA_ESR_ES14_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_ESR_ES14,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_ESR_ES15\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_ESR_ES15_MASK (0x00008000)\r
- #define HEDMA_ESR_ES15_SHIFT (0x0000000F)\r
- \r
- #define HEDMA_ESR_ES15_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEDMA_ESR_ES15)\r
-\r
- #define HEDMA_ESR_ES15_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEDMA_ESR_ES15,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEDMA_ESR\r
-\*----------------------------------------------------------------------------*/\r
- #define HEDMA_ESR_GET(RegAddr) HREG32_GET(RegAddr)\r
- #define HEDMA_ESR_SET(RegAddr,Val) HREG32_SET(RegAddr,Val)\r
-\r
- #define HEDMA_ESR_CFG(RegAddr,es0,es1,es2,es3,es4,es5,es6,es7,\\r
- es8,es9,es10,es11,es12,es13,es14,es15) REG32(RegAddr)=(UINT32)(\\r
- HFIELD_SHIFT(HEDMA_ESR_ES0,es0)|\\r
- HFIELD_SHIFT(HEDMA_ESR_ES1,es1)|\\r
- HFIELD_SHIFT(HEDMA_ESR_ES2,es2)|\\r
- HFIELD_SHIFT(HEDMA_ESR_ES3,es3)|\\r
- HFIELD_SHIFT(HEDMA_ESR_ES4,es4)|\\r
- HFIELD_SHIFT(HEDMA_ESR_ES5,es5)|\\r
- HFIELD_SHIFT(HEDMA_ESR_ES6,es6)|\\r
- HFIELD_SHIFT(HEDMA_ESR_ES7,es7)|\\r
- HFIELD_SHIFT(HEDMA_ESR_ES8,es8)|\\r
- HFIELD_SHIFT(HEDMA_ESR_ES9,es9)|\\r
- HFIELD_SHIFT(HEDMA_ESR_ES10,es10)|\\r
- HFIELD_SHIFT(HEDMA_ESR_ES11,es11)|\\r
- HFIELD_SHIFT(HEDMA_ESR_ES12,es12)|\\r
- HFIELD_SHIFT(HEDMA_ESR_ES13,es13)|\\r
- HFIELD_SHIFT(HEDMA_ESR_ES14,es14)|\\r
- HFIELD_SHIFT(HEDMA_ESR_ES15,es15)\\r
- )\r
-\r
-/*----------------------------------------------------------------------------*/\r
-\r
-#endif /* EDMA_SUPPORT */\r
-#endif /* _EDMAHAL_H_ */\r
-/******************************************************************************\\r
-* End of edmahal.h\r
-\******************************************************************************/\r
-/******************************************************************************\\r
-* Copyright (C) 1999-2000 Texas Instruments Incorporated.\r
-* All Rights Reserved\r
-*------------------------------------------------------------------------------\r
-* FILENAME...... emifhal.h\r
-* DATE CREATED.. 06/12/1999 \r
-* LAST MODIFIED. 03/08/2000\r
-* \r
-*------------------------------------------------------------------------------\r
-* DESCRIPTION: (HAL interface file for the EMIF module)\r
-*\r
-* Registers Covered:\r
-* (RW) HEMIF_GBLCTL - global control register\r
-* (RW) HEMIF_CE0CTL - chip-enable space 0 control register\r
-* (RW) HEMIF_CE1CTL - chip-enable space 1 control register\r
-* (RW) HEMIF_CE2CTL - chip-enable space 2 control register\r
-* (RW) HEMIF_CE3CTL - chip-enable space 3 control register\r
-* (RW) HEMIF_SDCTL - SDRAM control register\r
-* (RW) HEMIF_SDTIM - SDRAM timing register\r
-* (RW) HEMIF_SDEXT - SDRAM extension register (1)\r
-*\r
-* (1) Only available for C11_SUPPORT\r
-*\r
-\******************************************************************************/\r
-#ifndef _EMIFHAL_H_\r
-#define _EMIFHAL_H_\r
-\r
-#if (EMIF_SUPPORT)\r
-#define HEMIF_BASE_ADDR (HCHIP_PERBASE_ADDR+0x00000000)\r
-\r
-/******************************************************************************\\r
-* HEMIF_GBLCTL - global control register\r
-*\r
-* Fields:\r
-* (R) HEMIF_GBLCTL_MAP (2)\r
-* (RW) HEMIF_GBLCTL_RBTR8 (2)\r
-* (RW) HEMIF_GBLCTL_SSCRT (2)(3)\r
-* (RW) HEMIF_GBLCTL_CLK2EN (3)\r
-* (RW) HEMIF_GBLCTL_CLK1EN\r
-* (RW) HEMIF_GBLCTL_SSCEN (2)\r
-* (RW) HEMIF_GBLCTL_SDCEN (2)\r
-* (RW) HEMIF_GBLCTL_NOHOLD\r
-* (R) HEMIF_GBLCTL_HOLDA\r
-* (R) HEMIF_GBLCTL_HOLD\r
-* (R) HEMIF_GBLCTL_ARDY\r
-* (R) HEMIF_GBLCTL_BUSREQ (1)\r
-*\r
-* (1) Field only exists for C11_SUPPORT\r
-* (2) Field does not exist for C11_SUPPORT\r
-* (3) Field does not exist for CHIP_6202, CHIP_6203\r
-*\r
-\******************************************************************************/\r
- #define HEMIF_GBLCTL_ADDR (HEMIF_BASE_ADDR+0x0000)\r
- #define HEMIF_GBLCTL REG32(HEMIF_GBLCTL_ADDR)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (R) HEMIF_GBLCTL_MAP\r
-\*----------------------------------------------------------------------------*/\r
-#if !(C11_SUPPORT)\r
- #define HEMIF_GBLCTL_MAP_MASK (0x00000001)\r
- #define HEMIF_GBLCTL_MAP_SHIFT (0x00000000) \r
-#else\r
- #define HEMIF_GBLCTL_MAP_MASK (0x00000000)\r
- #define HEMIF_GBLCTL_MAP_SHIFT (0x00000000) \r
-#endif\r
-\r
- #define HEMIF_GBLCTL_MAP_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEMIF_GBLCTL_MAP)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEMIF_GBLCTL_RBTR8\r
-\*----------------------------------------------------------------------------*/\r
-#if !(C11_SUPPORT)\r
- #define HEMIF_GBLCTL_RBTR8_MASK (0x00000002)\r
- #define HEMIF_GBLCTL_RBTR8_SHIFT (0x00000001) \r
-#else\r
- #define HEMIF_GBLCTL_RBTR8_MASK (0x00000000)\r
- #define HEMIF_GBLCTL_RBTR8_SHIFT (0x00000000) \r
-#endif\r
-\r
- #define HEMIF_GBLCTL_RBTR8_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEMIF_GBLCTL_RBTR8)\r
-\r
- #define HEMIF_GBLCTL_RBTR8_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEMIF_GBLCTL_RBTR8,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEMIF_GBLCTL_SSCRT\r
-\*----------------------------------------------------------------------------*/\r
-#if !(CHIP_6202|CHIP_6203|C11_SUPPORT)\r
- #define HEMIF_GBLCTL_SSCRT_MASK (0x00000004)\r
- #define HEMIF_GBLCTL_SSCRT_SHIFT (0x00000002)\r
-#else\r
- #define HEMIF_GBLCTL_SSCRT_MASK (0x00000000)\r
- #define HEMIF_GBLCTL_SSCRT_SHIFT (0x00000000)\r
-#endif\r
-\r
- #define HEMIF_GBLCTL_SSCRT_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEMIF_GBLCTL_SSCRT)\r
-\r
- #define HEMIF_GBLCTL_SSCRT_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEMIF_GBLCTL_SSCRT,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEMIF_GBLCTL_CLK2EN\r
-\*----------------------------------------------------------------------------*/\r
-#if !(CHIP_6202|CHIP_6203)\r
- #define HEMIF_GBLCTL_CLK2EN_MASK (0x00000008)\r
- #define HEMIF_GBLCTL_CLK2EN_SHIFT (0x00000003)\r
-#else\r
- #define HEMIF_GBLCTL_CLK2EN_MASK (0x00000000)\r
- #define HEMIF_GBLCTL_CLK2EN_SHIFT (0x00000000)\r
-#endif\r
-\r
- #define HEMIF_GBLCTL_CLK2EN_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEMIF_GBLCTL_CLK2EN)\r
-\r
- #define HEMIF_GBLCTL_CLK2EN_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEMIF_GBLCTL_CLK2EN,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEMIF_GBLCTL_CLK1EN\r
-\*----------------------------------------------------------------------------*/\r
- #define HEMIF_GBLCTL_CLK1EN_MASK (0x00000010)\r
- #define HEMIF_GBLCTL_CLK1EN_SHIFT (0x00000004)\r
-\r
- #define HEMIF_GBLCTL_CLK1EN_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEMIF_GBLCTL_CLK1EN)\r
-\r
- #define HEMIF_GBLCTL_CLK1EN_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEMIF_GBLCTL_CLK1EN,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEMIF_GBLCTL_SSCEN\r
-\*----------------------------------------------------------------------------*/\r
-#if !(C11_SUPPORT)\r
- #define HEMIF_GBLCTL_SSCEN_MASK (0x00000020)\r
- #define HEMIF_GBLCTL_SSCEN_SHIFT (0x00000005)\r
-#else\r
- #define HEMIF_GBLCTL_SSCEN_MASK (0x00000000)\r
- #define HEMIF_GBLCTL_SSCEN_SHIFT (0x00000000)\r
-#endif\r
-\r
- #define HEMIF_GBLCTL_SSCEN_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEMIF_GBLCTL_SSCEN)\r
-\r
- #define HEMIF_GBLCTL_SSCEN_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEMIF_GBLCTL_SSCEN,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEMIF_GBLCTL_SDCEN\r
-\*----------------------------------------------------------------------------*/\r
-#if !(C11_SUPPORT)\r
- #define HEMIF_GBLCTL_SDCEN_MASK (0x00000040)\r
- #define HEMIF_GBLCTL_SDCEN_SHIFT (0x00000006)\r
-#else\r
- #define HEMIF_GBLCTL_SDCEN_MASK (0x00000000)\r
- #define HEMIF_GBLCTL_SDCEN_SHIFT (0x00000000)\r
-#endif\r
-\r
- #define HEMIF_GBLCTL_SDCEN_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEMIF_GBLCTL_SDCEN)\r
-\r
- #define HEMIF_GBLCTL_SDCEN_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEMIF_GBLCTL_SDCEN,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEMIF_GBLCTL_NOHOLD\r
-\*----------------------------------------------------------------------------*/\r
- #define HEMIF_GBLCTL_NOHOLD_MASK (0x00000080)\r
- #define HEMIF_GBLCTL_NOHOLD_SHIFT (0x00000007)\r
-\r
- #define HEMIF_GBLCTL_NOHOLD_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEMIF_GBLCTL_NOHOLD)\r
-\r
- #define HEMIF_GBLCTL_NOHOLD_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEMIF_GBLCTL_NOHOLD,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (R) HEMIF_GBLCTL_HOLDA\r
-\*----------------------------------------------------------------------------*/\r
- #define HEMIF_GBLCTL_HOLDA_MASK (0x00000100)\r
- #define HEMIF_GBLCTL_HOLDA_SHIFT (0x00000008)\r
- \r
- #define HEMIF_GBLCTL_HOLDA_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEMIF_GBLCTL_HOLDA)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (R) HEMIF_GBLCTL_HOLD\r
-\*----------------------------------------------------------------------------*/\r
- #define HEMIF_GBLCTL_HOLD_MASK (0x00000200)\r
- #define HEMIF_GBLCTL_HOLD_SHIFT (0x00000009)\r
- \r
- #define HEMIF_GBLCTL_HOLD_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEMIF_GBLCTL_HOLD)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (R) HEMIF_GBLCTL_ARDY\r
-\*----------------------------------------------------------------------------*/\r
- #define HEMIF_GBLCTL_ARDY_MASK (0x00000400)\r
- #define HEMIF_GBLCTL_ARDY_SHIFT (0x0000000A)\r
- \r
- #define HEMIF_GBLCTL_ARDY_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEMIF_GBLCTL_ARDY)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (R) HEMIF_GBLCTL_BUSREQ\r
-\*----------------------------------------------------------------------------*/\r
-#if (C11_SUPPORT)\r
- #define HEMIF_GBLCTL_BUSREQ_MASK (0x00000800)\r
- #define HEMIF_GBLCTL_BUSREQ_SHIFT (0x0000000B)\r
-#else\r
- #define HEMIF_GBLCTL_BUSREQ_MASK (0x00000000)\r
- #define HEMIF_GBLCTL_BUSREQ_SHIFT (0x00000000)\r
-#endif\r
-\r
- #define HEMIF_GBLCTL_BUSREQ_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEMIF_GBLCTL_BUSREQ)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEMIF_GBLCTL\r
-\*----------------------------------------------------------------------------*/\r
- #define HEMIF_GBLCTL_GET(RegAddr) HREG32_GET(RegAddr)\r
- #define HEMIF_GBLCTL_SET(RegAddr,Val) HREG32_SET(RegAddr,Val)\r
- \r
- #define HEMIF_GBLCTL_CFG(RegAddr,rbtr8,sscrt,clk2en,clk1en,sscen,sdcen,\\r
- nohold) REG32(RegAddr) = (UINT32)( \\r
- HFIELD_SHIFT(HEMIF_GBLCTL_RBTR8,rbtr8)|\\r
- HFIELD_SHIFT(HEMIF_GBLCTL_SSCRT,sscrt)|\\r
- HFIELD_SHIFT(HEMIF_GBLCTL_CLK2EN,clk2en)|\\r
- HFIELD_SHIFT(HEMIF_GBLCTL_CLK1EN,clk1en)|\\r
- HFIELD_SHIFT(HEMIF_GBLCTL_SSCEN,sscen)|\\r
- HFIELD_SHIFT(HEMIF_GBLCTL_SDCEN,sdcen)|\\r
- HFIELD_SHIFT(HEMIF_GBLCTL_NOHOLD,nohold)|\\r
- 0x00003000 \\r
- )\r
-\r
-/*----------------------------------------------------------------------------*/\r
-\r
-/******************************************************************************\\r
-* HEMIF_CE0CTL - chip-enable space 0 control register\r
-* HEMIF_CE1CTL - chip-enable space 1 control register\r
-* HEMIF_CE2CTL - chip-enable space 2 control register\r
-* HEMIF_CE3CTL - chip-enable space 3 control register\r
-*\r
-* Fields:\r
-* (RW) HEMIF_CECTL_RDHLD\r
-* (RW) HEMIF_CECTL_WRHLDMSB (1)\r
-* (RW) HEMIF_CECTL_MTYPE\r
-* (RW) HEMIF_CECTL_RDSTRB\r
-* (RW) HEMIF_CECTL_TA (1)\r
-* (RW) HEMIF_CECTL_RDSETUP\r
-* (RW) HEMIF_CECTL_WRHLD\r
-* (RW) HEMIF_CECTL_WRSTRB\r
-* (RW) HEMIF_CECTL_WRSETUP\r
-*\r
-* (1) Field only exists for C11_SUPPORT\r
-*\r
-\******************************************************************************/\r
- #define HEMIF_CE0CTL_ADDR (HEMIF_BASE_ADDR+0x0008)\r
- #define HEMIF_CE1CTL_ADDR (HEMIF_BASE_ADDR+0x0004)\r
- #define HEMIF_CE2CTL_ADDR (HEMIF_BASE_ADDR+0x0010)\r
- #define HEMIF_CE3CTL_ADDR (HEMIF_BASE_ADDR+0x0014)\r
-\r
- #define HEMIF_CE0CTL REG32(HEMIF_CE0CTL_ADDR)\r
- #define HEMIF_CE1CTL REG32(HEMIF_CE1CTL_ADDR)\r
- #define HEMIF_CE2CTL REG32(HEMIF_CE2CTL_ADDR)\r
- #define HEMIF_CE3CTL REG32(HEMIF_CE3CTL_ADDR)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEMIF_CECTL_RDHLD\r
-\*----------------------------------------------------------------------------*/\r
-#if (C11_SUPPORT)\r
- #define HEMIF_CECTL_RDHLD_MASK (0x00000007)\r
- #define HEMIF_CECTL_RDHLD_SHIFT (0x00000000)\r
-#elif (C01_SUPPORT)\r
- #define HEMIF_CECTL_RDHLD_MASK (0x00000003)\r
- #define HEMIF_CECTL_RDHLD_SHIFT (0x00000000)\r
-#endif\r
-\r
- #define HEMIF_CECTL_RDHLD_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEMIF_CECTL_RDHLD)\r
-\r
- #define HEMIF_CECTL_RDHLD_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEMIF_CECTL_RDHLD,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEMIF_CECTL_WRHLDMSB\r
-\*----------------------------------------------------------------------------*/\r
-#if (C11_SUPPORT) \r
- #define HEMIF_CECTL_WRHLDMSB_MASK (0x00000008)\r
- #define HEMIF_CECTL_WRHLDMSB_SHIFT (0x00000003)\r
-#else\r
- #define HEMIF_CECTL_WRHLDMSB_MASK (0x00000000)\r
- #define HEMIF_CECTL_WRHLDMSB_SHIFT (0x00000000)\r
-#endif\r
-\r
- #define HEMIF_CECTL_WRHLDMSB_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEMIF_CECTL_WRHLDMSB)\r
-\r
- #define HEMIF_CECTL_WRHLDMSB_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEMIF_CECTL_WRHLDMSB,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEMIF_CECTL_MTYPE\r
-\*----------------------------------------------------------------------------*/\r
-#if (C11_SUPPORT)\r
- #define HEMIF_CECTL_MTYPE_MASK (0x000000F0)\r
- #define HEMIF_CECTL_MTYPE_SHIFT (0x00000004)\r
-#elif (C01_SUPPORT)\r
- #define HEMIF_CECTL_MTYPE_MASK (0x00000070)\r
- #define HEMIF_CECTL_MTYPE_SHIFT (0x00000004)\r
-#else\r
- #define HEMIF_CECTL_MTYPE_MASK (0x00000000)\r
- #define HEMIF_CECTL_MTYPE_SHIFT (0x00000000)\r
-#endif\r
-\r
- #define HEMIF_CECTL_MTYPE_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEMIF_CECTL_MTYPE)\r
-\r
- #define HEMIF_CECTL_MTYPE_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEMIF_CECTL_MTYPE,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEMIF_CECTL_RDSTRB\r
-\*----------------------------------------------------------------------------*/\r
- #define HEMIF_CECTL_RDSTRB_MASK (0x00003F00)\r
- #define HEMIF_CECTL_RDSTRB_SHIFT (0x00000008)\r
- \r
- #define HEMIF_CECTL_RDSTRB_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEMIF_CECTL_RDSTRB)\r
-\r
- #define HEMIF_CECTL_RDSTRB_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEMIF_CECTL_RDSTRB,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEMIF_CECTL_TA\r
-\*----------------------------------------------------------------------------*/\r
-#if (C11_SUPPORT)\r
- #define HEMIF_CECTL_TA_MASK (0x0000C000)\r
- #define HEMIF_CECTL_TA_SHIFT (0x0000000E)\r
-#else\r
- #define HEMIF_CECTL_TA_MASK (0x00000000)\r
- #define HEMIF_CECTL_TA_SHIFT (0x00000000)\r
-#endif\r
-\r
- #define HEMIF_CECTL_TA_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEMIF_CECTL_TA)\r
-\r
- #define HEMIF_CECTL_TA_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEMIF_CECTL_TA,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEMIF_CECTL_RDSETUP\r
-\*----------------------------------------------------------------------------*/\r
- #define HEMIF_CECTL_RDSETUP_MASK (0x000F0000)\r
- #define HEMIF_CECTL_RDSETUP_SHIFT (0x00000010)\r
-\r
- #define HEMIF_CECTL_RDSETUP_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEMIF_CECTL_RDSETUP)\r
-\r
- #define HEMIF_CECTL_RDSETUP_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEMIF_CECTL_RDSETUP,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEMIF_CECTL_WRHLD\r
-\*----------------------------------------------------------------------------*/\r
- #define HEMIF_CECTL_WRHLD_MASK (0x00300000)\r
- #define HEMIF_CECTL_WRHLD_SHIFT (0x00000014)\r
- \r
- #define HEMIF_CECTL_WRHLD_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEMIF_CECTL_WRHLD)\r
-\r
- #define HEMIF_CECTL_WRHLD_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEMIF_CECTL_WRHLD,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEMIF_CECTL_WRSTRB\r
-\*----------------------------------------------------------------------------*/\r
- #define HEMIF_CECTL_WRSTRB_MASK (0x0FC00000)\r
- #define HEMIF_CECTL_WRSTRB_SHIFT (0x00000016)\r
-\r
- #define HEMIF_CECTL_WRSTRB_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEMIF_CECTL_WRSTRB)\r
-\r
- #define HEMIF_CECTL_WRSTRB_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEMIF_CECTL_WRSTRB,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEMIF_CECTL_WRSETUP\r
-\*----------------------------------------------------------------------------*/\r
- #define HEMIF_CECTL_WRSETUP_MASK (0xF0000000)\r
- #define HEMIF_CECTL_WRSETUP_SHIFT (0x0000001C)\r
-\r
- #define HEMIF_CECTL_WRSETUP_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEMIF_CECTL_WRSETUP)\r
-\r
- #define HEMIF_CECTL_WRSETUP_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEMIF_CECTL_WRSETUP,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEMIF_CECTL\r
-\*----------------------------------------------------------------------------*/\r
- #define HEMIF_CECTL_GET(RegAddr) HREG32_GET(RegAddr)\r
- #define HEMIF_CECTL_SET(RegAddr,Val) HREG32_SET(RegAddr,Val)\r
- \r
- #define HEMIF_CECTL_CFG(RegAddr,rdhld,wrhldmsb,mtype,rdstrb,ta,\\r
- rdsetup,wrhld,wrstrb,wrsetup) REG32(RegAddr) = (UINT32)( \\r
- HFIELD_SHIFT(HEMIF_CECTL_RDHLD,rdhld)|\\r
- HFIELD_SHIFT(HEMIF_CECTL_WRHLDMSB,wrhldmsb)|\\r
- HFIELD_SHIFT(HEMIF_CECTL_MTYPE,mtype)|\\r
- HFIELD_SHIFT(HEMIF_CECTL_RDSTRB,rdstrb)|\\r
- HFIELD_SHIFT(HEMIF_CECTL_TA,ta)|\\r
- HFIELD_SHIFT(HEMIF_CECTL_RDSETUP,rdsetup)|\\r
- HFIELD_SHIFT(HEMIF_CECTL_WRHLD,wrhld)|\\r
- HFIELD_SHIFT(HEMIF_CECTL_WRSTRB,wrstrb)|\\r
- HFIELD_SHIFT(HEMIF_CECTL_WRSETUP,wrsetup)\\r
- )\r
-\r
-/******************************************************************************\\r
-* HEMIF_SDCTL - SDRAM control register\r
-*\r
-* Fields:\r
-* (RW) HEMIF_SDCTL_TRC\r
-* (RW) HEMIF_SDCTL_TRP\r
-* (RW) HEMIF_SDCTL_TRCD\r
-* (W) HEMIF_SDCTL_INIT\r
-* (RW) HEMIF_SDCTL_RFEN\r
-* (RW) HEMIF_SDCTL_SDWID (1)\r
-* (RW) HEMIF_SDCTL_SDCSZ (2)\r
-* (RW) HEMIF_SDCTL_SDRSZ (2)\r
-* (RW) HEMIF_SDCTL_SDBSZ (2)\r
-*\r
-* (1) Field only exists for C01_SUPPORT\r
-* (2) Field only exists for C11_SUPPORT\r
-*\r
-\******************************************************************************/\r
- #define HEMIF_SDCTL_ADDR (HEMIF_BASE_ADDR+0x0018)\r
- #define HEMIF_SDCTL REG32(HEMIF_SDCTL_ADDR)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEMIF_SDCTL_TRC\r
-\*----------------------------------------------------------------------------*/\r
- #define HEMIF_SDCTL_TRC_MASK (0x0000F000)\r
- #define HEMIF_SDCTL_TRC_SHIFT (0x0000000C)\r
- \r
- #define HEMIF_SDCTL_TRC_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEMIF_SDCTL_TRC)\r
-\r
- #define HEMIF_SDCTL_TRC_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEMIF_SDCTL_TRC,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEMIF_SDCTL_TRP\r
-\*----------------------------------------------------------------------------*/\r
- #define HEMIF_SDCTL_TRP_MASK (0x000F0000)\r
- #define HEMIF_SDCTL_TRP_SHIFT (0x00000010)\r
-\r
- #define HEMIF_SDCTL_TRP_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEMIF_SDCTL_TRP)\r
-\r
- #define HEMIF_SDCTL_TRP_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEMIF_SDCTL_TRP,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEMIF_SDCTL_TRCD\r
-\*----------------------------------------------------------------------------*/\r
- #define HEMIF_SDCTL_TRCD_MASK (0x00F00000)\r
- #define HEMIF_SDCTL_TRCD_SHIFT (0x00000014)\r
-\r
- #define HEMIF_SDCTL_TRCD_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEMIF_SDCTL_TRCD)\r
-\r
- #define HEMIF_SDCTL_TRCD_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEMIF_SDCTL_TRCD,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (W) HEMIF_SDCTL_INIT\r
-\*----------------------------------------------------------------------------*/\r
- #define HEMIF_SDCTL_INIT_MASK (0x01000000)\r
- #define HEMIF_SDCTL_INIT_SHIFT (0x00000018)\r
-\r
- #define HEMIF_SDCTL_INIT_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEMIF_SDCTL_INIT,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEMIF_SDCTL_RFEN\r
-\*----------------------------------------------------------------------------*/\r
- #define HEMIF_SDCTL_RFEN_MASK (0x02000000)\r
- #define HEMIF_SDCTL_RFEN_SHIFT (0x00000019) \r
-\r
- #define HEMIF_SDCTL_RFEN_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEMIF_SDCTL_RFEN)\r
-\r
- #define HEMIF_SDCTL_RFEN_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEMIF_SDCTL_RFEN,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEMIF_SDCTL_SDWID\r
-\*----------------------------------------------------------------------------*/\r
-#if (C01_SUPPORT)\r
- #define HEMIF_SDCTL_SDWID_MASK (0x04000000)\r
- #define HEMIF_SDCTL_SDWID_SHIFT (0x0000001A)\r
-#else\r
- #define HEMIF_SDCTL_SDWID_MASK (0x00000000)\r
- #define HEMIF_SDCTL_SDWID_SHIFT (0x00000000)\r
-#endif\r
- \r
- #define HEMIF_SDCTL_SDWID_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEMIF_SDCTL_SDWID)\r
-\r
- #define HEMIF_SDCTL_SDWID_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEMIF_SDCTL_SDWID,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEMIF_SDCTL_SDCSZ\r
-\*----------------------------------------------------------------------------*/\r
-#if (C11_SUPPORT)\r
- #define HEMIF_SDCTL_SDCSZ_MASK (0x0C000000)\r
- #define HEMIF_SDCTL_SDCSZ_SHIFT (0x0000001A)\r
-#else\r
- #define HEMIF_SDCTL_SDCSZ_MASK (0x00000000)\r
- #define HEMIF_SDCTL_SDCSZ_SHIFT (0x00000000)\r
-#endif\r
- \r
- #define HEMIF_SDCTL_SDCSZ_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEMIF_SDCTL_SDCSZ)\r
-\r
- #define HEMIF_SDCTL_SDCSZ_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEMIF_SDCTL_SDCSZ,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEMIF_SDCTL_SDRSZ\r
-\*----------------------------------------------------------------------------*/\r
-#if (C11_SUPPORT)\r
- #define HEMIF_SDCTL_SDRSZ_MASK (0x30000000)\r
- #define HEMIF_SDCTL_SDRSZ_SHIFT (0x0000001C)\r
-#else\r
- #define HEMIF_SDCTL_SDRSZ_MASK (0x00000000)\r
- #define HEMIF_SDCTL_SDRSZ_SHIFT (0x00000000)\r
-#endif\r
- \r
- #define HEMIF_SDCTL_SDRSZ_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEMIF_SDCTL_SDRSZ)\r
-\r
- #define HEMIF_SDCTL_SDRSZ_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEMIF_SDCTL_SDRSZ,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEMIF_SDCTL_SDBSZ\r
-\*----------------------------------------------------------------------------*/\r
-#if (C11_SUPPORT)\r
- #define HEMIF_SDCTL_SDBSZ_MASK (0x40000000)\r
- #define HEMIF_SDCTL_SDBSZ_SHIFT (0x0000001E)\r
-#else\r
- #define HEMIF_SDCTL_SDBSZ_MASK (0x00000000)\r
- #define HEMIF_SDCTL_SDBSZ_SHIFT (0x00000000)\r
-#endif\r
- \r
- #define HEMIF_SDCTL_SDBSZ_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEMIF_SDCTL_SDBSZ)\r
-\r
- #define HEMIF_SDCTL_SDBSZ_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEMIF_SDCTL_SDBSZ,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEMIF_SDCTL\r
-\*----------------------------------------------------------------------------*/\r
- #define HEMIF_SDCTL_GET(RegAddr) HREG32_GET(RegAddr)\r
- #define HEMIF_SDCTL_SET(RegAddr,Val) HREG32_SET(RegAddr,Val)\r
- \r
- #define HEMIF_SDCTL_CFG(RegAddr,trc,trp,trcd,init,rfen,sdwid,\\r
- sdcsz,sdrsz,sdbsz) REG32(RegAddr) = (UINT32)( \\r
- HFIELD_SHIFT(HEMIF_SDCTL_TRC,trc)|\\r
- HFIELD_SHIFT(HEMIF_SDCTL_TRP,trp)|\\r
- HFIELD_SHIFT(HEMIF_SDCTL_TRCD,trcd)|\\r
- HFIELD_SHIFT(HEMIF_SDCTL_INIT,init)|\\r
- HFIELD_SHIFT(HEMIF_SDCTL_RFEN,rfen)|\\r
- HFIELD_SHIFT(HEMIF_SDCTL_SDWID,sdwid)|\\r
- HFIELD_SHIFT(HEMIF_SDCTL_SDCSZ,sdcsz)|\\r
- HFIELD_SHIFT(HEMIF_SDCTL_SDRSZ,sdrsz)|\\r
- HFIELD_SHIFT(HEMIF_SDCTL_SDBSZ,sdbsz)\\r
- )\r
-\r
-/******************************************************************************\\r
-* HEMIF_SDTIM - SDRAM timing register\r
-*\r
-* Fields:\r
-* (RW) HEMIF_SDTIM_PERIOD\r
-* (R) HEMIF_SDTIM_CNTR\r
-* (RW) HEMIF_SDTIM_XRFR (1)\r
-*\r
-* (1) Field only exists for C11_SUPPORT\r
-*\r
-\******************************************************************************/\r
- #define HEMIF_SDTIM_ADDR (HEMIF_BASE_ADDR+0x001C)\r
- #define HEMIF_SDTIM REG32(HEMIF_SDTIM_ADDR)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEMIF_SDTIM_PERIOD\r
-\*----------------------------------------------------------------------------*/\r
- #define HEMIF_SDTIM_PERIOD_MASK (0x00000FFF)\r
- #define HEMIF_SDTIM_PERIOD_SHIFT (0x00000000) \r
- \r
- #define HEMIF_SDTIM_PERIOD_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEMIF_SDTIM_PERIOD)\r
-\r
- #define HEMIF_SDTIM_PERIOD_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEMIF_SDTIM_PERIOD,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (R) HEMIF_SDTIM_CNTR\r
-\*----------------------------------------------------------------------------*/\r
- #define HEMIF_SDTIM_CNTR_MASK (0x00FFF000)\r
- #define HEMIF_SDTIM_CNTR_SHIFT (0x0000000C)\r
- \r
- #define HEMIF_SDTIM_CNTR_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEMIF_SDTIM_CNTR)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEMIF_SDTIM_XRFR\r
-\*----------------------------------------------------------------------------*/\r
-#if (C11_SUPPORT)\r
- #define HEMIF_SDTIM_XRFR_MASK (0x03000000)\r
- #define HEMIF_SDTIM_XRFR_SHIFT (0x00000018)\r
-#else\r
- #define HEMIF_SDTIM_XRFR_MASK (0x00000000)\r
- #define HEMIF_SDTIM_XRFR_SHIFT (0x00000000)\r
-#endif\r
-\r
- #define HEMIF_SDTIM_XRFR_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEMIF_SDTIM_XRFR)\r
-\r
- #define HEMIF_SDTIM_XRFR_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEMIF_SDTIM_XRFR,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEMIF_SDTIM\r
-\*----------------------------------------------------------------------------*/\r
- #define HEMIF_SDTIM_GET(RegAddr) HREG32_GET(RegAddr)\r
- #define HEMIF_SDTIM_SET(RegAddr,Val) HREG32_SET(RegAddr,Val)\r
-\r
- #define HEMIF_SDTIM_CFG(RegAddr,period,xrfr) REG32(RegAddr)=(UINT32)(\\r
- HFIELD_SHIFT(HEMIF_SDTIM_PERIOD,period)|\\r
- HFIELD_SHIFT(HEMIF_SDTIM_XRFR,xrfr)\\r
- )\r
-\r
-/******************************************************************************\\r
-* HEMIF_SDEXT - SDRAM extension register (1)\r
-* (1) Only available for C11_SUPPORT\r
-*\r
-* Fields:\r
-* (RW) HEMIF_SDEXT_TCL\r
-* (RW) HEMIF_SDEXT_TRAS\r
-* (RW) HEMIF_SDEXT_TRRD\r
-* (RW) HEMIF_SDEXT_TWR\r
-* (RW) HEMIF_SDEXT_THZP\r
-* (RW) HEMIF_SDEXT_RD2RD\r
-* (RW) HEMIF_SDEXT_RD2DEAC\r
-* (RW) HEMIF_SDEXT_RD2WR\r
-* (RW) HEMIF_SDEXT_R2WDQM\r
-* (RW) HEMIF_SDEXT_WR2WR\r
-* (RW) HEMIF_SDEXT_WR2DEAC\r
-* (RW) HEMIF_SDEXT_WR2RD\r
-*\r
-\******************************************************************************/\r
-#if (C11_SUPPORT)\r
- #define HEMIF_SDEXT_ADDR (HEMIF_BASE_ADDR+0x0020)\r
- #define HEMIF_SDEXT REG32(HEMIF_SDEXT_ADDR)\r
-#else\r
- #define HEMIF_SDEXT_ADDR HCHIP_NULL_ADDR\r
- #define HEMIF_SDEXT REG32(HEMIF_SDEXT_ADDR)\r
-#endif\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEMIF_SDEXT_TCL\r
-\*----------------------------------------------------------------------------*/\r
-#if (C11_SUPPORT)\r
- #define HEMIF_SDEXT_TCL_MASK (0x00000001)\r
- #define HEMIF_SDEXT_TCL_SHIFT (0x00000000)\r
-#else\r
- #define HEMIF_SDEXT_TCL_MASK (0x00000000)\r
- #define HEMIF_SDEXT_TCL_SHIFT (0x00000000)\r
-#endif\r
-\r
- #define HEMIF_SDEXT_TCL_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEMIF_SDEXT_TCL)\r
-\r
- #define HEMIF_SDEXT_TCL_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEMIF_SDEXT_TCL,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEMIF_SDEXT_TRAS\r
-\*----------------------------------------------------------------------------*/\r
-#if (C11_SUPPORT)\r
- #define HEMIF_SDEXT_TRAS_MASK (0x0000000D)\r
- #define HEMIF_SDEXT_TRAS_SHIFT (0x00000001)\r
-#else\r
- #define HEMIF_SDEXT_TRAS_MASK (0x00000000)\r
- #define HEMIF_SDEXT_TRAS_SHIFT (0x00000000)\r
-#endif\r
-\r
- #define HEMIF_SDEXT_TRAS_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEMIF_SDEXT_TRAS)\r
-\r
- #define HEMIF_SDEXT_TRAS_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEMIF_SDEXT_TRAS,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEMIF_SDEXT_TRRD\r
-\*----------------------------------------------------------------------------*/\r
-#if (C11_SUPPORT)\r
- #define HEMIF_SDEXT_TRRD_MASK (0x00000010)\r
- #define HEMIF_SDEXT_TRRD_SHIFT (0x00000004)\r
-#else\r
- #define HEMIF_SDEXT_TRRD_MASK (0x00000000)\r
- #define HEMIF_SDEXT_TRRD_SHIFT (0x00000000)\r
-#endif\r
-\r
- #define HEMIF_SDEXT_TRRD_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEMIF_SDEXT_TRRD)\r
-\r
- #define HEMIF_SDEXT_TRRD_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEMIF_SDEXT_TRRD,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEMIF_SDEXT_TWR\r
-\*----------------------------------------------------------------------------*/\r
-#if (C11_SUPPORT)\r
- #define HEMIF_SDEXT_TWR_MASK (0x00000060)\r
- #define HEMIF_SDEXT_TWR_SHIFT (0x00000005)\r
-#else\r
- #define HEMIF_SDEXT_TWR_MASK (0x00000000)\r
- #define HEMIF_SDEXT_TWR_SHIFT (0x00000000)\r
-#endif\r
-\r
- #define HEMIF_SDEXT_TWR_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEMIF_SDEXT_TWR)\r
-\r
- #define HEMIF_SDEXT_TWR_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEMIF_SDEXT_TWR,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEMIF_SDEXT_THZP\r
-\*----------------------------------------------------------------------------*/\r
-#if (C11_SUPPORT)\r
- #define HEMIF_SDEXT_THZP_MASK (0x00000180)\r
- #define HEMIF_SDEXT_THZP_SHIFT (0x00000007)\r
-#else\r
- #define HEMIF_SDEXT_THZP_MASK (0x00000000)\r
- #define HEMIF_SDEXT_THZP_SHIFT (0x00000000)\r
-#endif\r
-\r
- #define HEMIF_SDEXT_THZP_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEMIF_SDEXT_THZP)\r
-\r
- #define HEMIF_SDEXT_THZP_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEMIF_SDEXT_THZP,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEMIF_SDEXT_RD2RD\r
-\*----------------------------------------------------------------------------*/\r
-#if (C11_SUPPORT)\r
- #define HEMIF_SDEXT_RD2RD_MASK (0x00000200)\r
- #define HEMIF_SDEXT_RD2RD_SHIFT (0x00000009)\r
-#else\r
- #define HEMIF_SDEXT_RD2RD_MASK (0x00000000)\r
- #define HEMIF_SDEXT_RD2RD_SHIFT (0x00000000)\r
-#endif\r
-\r
- #define HEMIF_SDEXT_RD2RD_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEMIF_SDEXT_RD2RD)\r
-\r
- #define HEMIF_SDEXT_RD2RD_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEMIF_SDEXT_RD2RD,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEMIF_SDEXT_RD2DEAC\r
-\*----------------------------------------------------------------------------*/\r
-#if (C11_SUPPORT)\r
- #define HEMIF_SDEXT_RD2DEAC_MASK (0x00000C00)\r
- #define HEMIF_SDEXT_RD2DEAC_SHIFT (0x0000000A)\r
-#else\r
- #define HEMIF_SDEXT_RD2DEAC_MASK (0x00000000)\r
- #define HEMIF_SDEXT_RD2DEAC_SHIFT (0x00000000)\r
-#endif\r
-\r
- #define HEMIF_SDEXT_RD2DEAC_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEMIF_SDEXT_RD2DEAC)\r
-\r
- #define HEMIF_SDEXT_RD2DEAC_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEMIF_SDEXT_RD2DEAC,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEMIF_SDEXT_RD2WR\r
-\*----------------------------------------------------------------------------*/\r
-#if (C11_SUPPORT)\r
- #define HEMIF_SDEXT_RD2WR_MASK (0x00007000)\r
- #define HEMIF_SDEXT_RD2WR_SHIFT (0x0000000C)\r
-#else\r
- #define HEMIF_SDEXT_RD2WR_MASK (0x00000000)\r
- #define HEMIF_SDEXT_RD2WR_SHIFT (0x00000000)\r
-#endif\r
-\r
- #define HEMIF_SDEXT_RD2WR_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEMIF_SDEXT_RD2WR)\r
-\r
- #define HEMIF_SDEXT_RD2WR_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEMIF_SDEXT_RD2WR,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEMIF_SDEXT_R2WDQM\r
-\*----------------------------------------------------------------------------*/\r
-#if (C11_SUPPORT)\r
- #define HEMIF_SDEXT_R2WDQM_MASK (0x00018000)\r
- #define HEMIF_SDEXT_R2WDQM_SHIFT (0x0000000F)\r
-#else\r
- #define HEMIF_SDEXT_R2WDQM_MASK (0x00000000)\r
- #define HEMIF_SDEXT_R2WDQM_SHIFT (0x00000000)\r
-#endif\r
-\r
- #define HEMIF_SDEXT_R2WDQM_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEMIF_SDEXT_R2WDQM)\r
-\r
- #define HEMIF_SDEXT_R2WDQM_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEMIF_SDEXT_R2WDQM,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEMIF_SDEXT_WR2WR\r
-\*----------------------------------------------------------------------------*/\r
-#if (C11_SUPPORT)\r
- #define HEMIF_SDEXT_WR2WR_MASK (0x00020000)\r
- #define HEMIF_SDEXT_WR2WR_SHIFT (0x00000011)\r
-#else\r
- #define HEMIF_SDEXT_WR2WR_MASK (0x00000000)\r
- #define HEMIF_SDEXT_WR2WR_SHIFT (0x00000000)\r
-#endif\r
-\r
- #define HEMIF_SDEXT_WR2WR_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEMIF_SDEXT_WR2WR)\r
-\r
- #define HEMIF_SDEXT_WR2WR_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEMIF_SDEXT_WR2WR,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEMIF_SDEXT_WR2DEAC\r
-\*----------------------------------------------------------------------------*/\r
-#if (C11_SUPPORT)\r
- #define HEMIF_SDEXT_WR2DEAC_MASK (0x000C0000)\r
- #define HEMIF_SDEXT_WR2DEAC_SHIFT (0x00000012)\r
-#else\r
- #define HEMIF_SDEXT_WR2DEAC_MASK (0x00000000)\r
- #define HEMIF_SDEXT_WR2DEAC_SHIFT (0x00000000)\r
-#endif\r
-\r
- #define HEMIF_SDEXT_WR2DEAC_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEMIF_SDEXT_WR2DEAC)\r
-\r
- #define HEMIF_SDEXT_WR2DEAC_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEMIF_SDEXT_WR2DEAC,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEMIF_SDEXT_WR2RD\r
-\*----------------------------------------------------------------------------*/\r
-#if (C11_SUPPORT)\r
- #define HEMIF_SDEXT_WR2RD_MASK (0x00100000)\r
- #define HEMIF_SDEXT_WR2RD_SHIFT (0x00000014)\r
-#else\r
- #define HEMIF_SDEXT_WR2RD_MASK (0x00000000)\r
- #define HEMIF_SDEXT_WR2RD_SHIFT (0x00000000)\r
-#endif\r
-\r
- #define HEMIF_SDEXT_WR2RD_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HEMIF_SDEXT_WR2RD)\r
-\r
- #define HEMIF_SDEXT_WR2RD_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HEMIF_SDEXT_WR2RD,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HEMIF_SDEXT\r
-\*----------------------------------------------------------------------------*/\r
- #define HEMIF_SDEXT_GET(RegAddr) HREG32_GET(RegAddr)\r
- #define HEMIF_SDEXT_SET(RegAddr,Val) HREG32_SET(RegAddr,Val)\r
-\r
- #define HEMIF_SDEXT_CFG(RegAddr,tcl,tras,trrd,twr,thzp,rd2rd,rd2deac,\\r
- rd2wr,r2wdqm,wr2wr,wr2deac,wr2rd) REG32(RagAddr)=(UINT32)(\\r
- HFIELD_SHIFT(HEMIF_SDEXT_TCL,tcl)|\\r
- HFIELD_SHIFT(HEMIF_SDEXT_TRAS,tras)|\\r
- HFIELD_SHIFT(HEMIF_SDEXT_TRRD,trrd)|\\r
- HFIELD_SHIFT(HEMIF_SDEXT_TWR,twr)|\\r
- HFIELD_SHIFT(HEMIF_SDEXT_THZP,thzp)|\\r
- HFIELD_SHIFT(HEMIF_SDEXT_RD2RD,rd2rd)|\\r
- HFIELD_SHIFT(HEMIF_SDEXT_RD2DEAC,rd2deac)|\\r
- HFIELD_SHIFT(HEMIF_SDEXT_RD2WR,rd2wr)|\\r
- HFIELD_SHIFT(HEMIF_SDEXT_R2WDQM,r2wdqm)|\\r
- HFIELD_SHIFT(HEMIF_SDEXT_WR2WR,wr2wr)|\\r
- HFIELD_SHIFT(HEMIF_SDEXT_WR2DEAC,wr2deac)|\\r
- HFIELD_SHIFT(HEMIF_SDEXT_WR2RD,wr2rd)\\r
- ) \r
-\r
-/******************************************************************************/\r
-\r
-#endif /* EMIF_SUPPORT */\r
-#endif /* _EMIFHAL_H_ */\r
-/******************************************************************************\\r
-* End of emifhal.h\r
-\******************************************************************************/\r
-\r
-/******************************************************************************\\r
-* Copyright (C) 1999-2000 Texas Instruments Incorporated.\r
-* All Rights Reserved\r
-*------------------------------------------------------------------------------\r
-* FILENAME...... hpihal.h\r
-* DATE CREATED.. 06/20/1999 \r
-* LAST MODIFIED. 03/08/2000\r
-* \r
-*------------------------------------------------------------------------------\r
-* DESCRIPTION: (HAL interface file for the HPI module)\r
-*\r
-* Registers Covered:\r
-* (RW) HHPI_HPIC - HPI control register\r
-*\r
-\******************************************************************************/\r
-#ifndef _HPIHAL_H_\r
-#define _HPIHAL_H_\r
-\r
-#if (HPI_SUPPORT)\r
-#define HHPI_BASE_ADDR (HCHIP_PERBASE_ADDR+0x00080000)\r
-\r
-/******************************************************************************\\r
-* HHPI_HPIC - HPI control register\r
-*\r
-* Fields:\r
-* (R) HHPI_HPIC_HWOB\r
-* (RW) HHPI_HPIC_DSPINT\r
-* (RW) HHPI_HPIC_HINT\r
-* (R) HHPI_HPIC_HRDY\r
-* (R) HHPI_HPIC_FETCH\r
-*\r
-\******************************************************************************/\r
- #define HHPI_HPIC_ADDR (HHPI_BASE_ADDR+0x0000)\r
- #define HHPI_HPIC REG32(HHPI_HPIC_ADDR)\r
- \r
-/*----------------------------------------------------------------------------*\\r
-* (R) HHPI_HPIC_HWOB\r
-\*----------------------------------------------------------------------------*/\r
- #define HHPI_HPIC_HWOB_MASK (0x00000001)\r
- #define HHPI_HPIC_HWOB_SHIFT (0x00000000)\r
- \r
- #define HHPI_HPIC_HWOB_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HHPI_HPIC_HWOB)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HHPI_HPIC_DSPINT\r
-\*----------------------------------------------------------------------------*/\r
- #define HHPI_HPIC_DSPINT_MASK (0x00000002)\r
- #define HHPI_HPIC_DSPINT_SHIFT (0x00000001)\r
-\r
- #define HHPI_HPIC_DSPINT_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HHPI_HPIC_DSPINT)\r
-\r
- #define HHPI_HPIC_DSPINT_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HHPI_HPIC_DSPINT,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HHPI_HPIC_HINT\r
-\*----------------------------------------------------------------------------*/\r
- #define HHPI_HPIC_HINT_MASK (0x00000004)\r
- #define HHPI_HPIC_HINT_SHIFT (0x00000002)\r
-\r
- #define HHPI_HPIC_HINT_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HHPI_HPIC_HINT)\r
-\r
- #define HHPI_HPIC_HINT_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HHPI_HPIC_HINT,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (R) HHPI_HPIC_HRDY\r
-\*----------------------------------------------------------------------------*/\r
- #define HHPI_HPIC_HRDY_MASK (0x00000008)\r
- #define HHPI_HPIC_HRDY_SHIFT (0x00000003)\r
-\r
- #define HHPI_HPIC_HRDY_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HHPI_HPIC_HRDY)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (R) HHPI_HPIC_FETCH\r
-\*----------------------------------------------------------------------------*/\r
- #define HHPI_HPIC_FETCH_MASK (0x00000010)\r
- #define HHPI_HPIC_FETCH_SHIFT (0x00000004)\r
-\r
- #define HHPI_HPIC_FETCH_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HHPI_HPIC_FETCH)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HHPI_HPIC\r
-\*----------------------------------------------------------------------------*/\r
- #define HHPI_HPIC_GET(RegAddr) HREG32_GET(RegAddr)\r
- #define HHPI_HPIC_SET(RegAddr,Val) HREG32_SET(RegAddr,Val)\r
- \r
- #define HHPI_HPIC_CFG(RegAddr,dspint,hint)\\r
- REG32(RegAddr) = (\\r
- HFIELD_SHIFT(HHPI_HPIC_DSPINT, dspint)|\\r
- HFIELD_SHIFT(HHPI_HPIC_HINT, hint)\\r
- )\r
-\r
-/*----------------------------------------------------------------------------*/\r
-\r
-#endif /* HPI_SUPPORT */\r
-#endif /* _HPIHAL_H_ */\r
-/******************************************************************************\\r
-* End of hpihal.h\r
-\******************************************************************************/\r
-\r
-/******************************************************************************\\r
-* Copyright (C) 1999-2000 Texas Instruments Incorporated.\r
-* All Rights Reserved\r
-*------------------------------------------------------------------------------\r
-* FILENAME...... irqhal.h\r
-* DATE CREATED.. 06/20/1999 \r
-* LAST MODIFIED. 03/08/2000\r
-* \r
-*------------------------------------------------------------------------------\r
-* DESCRIPTION: (HAL interface file for the IRQ module)\r
-*\r
-* Registers Covered:\r
-* (RW) HIRQ_MUXL - interrupt multiplexer low register\r
-* (RW) HIRQ_MUXH - interrupt multiplexer high register\r
-* (RW) HIRQ_EXTPOL - external interrupt polarity register\r
-*\r
-\******************************************************************************/\r
-#ifndef _IRQHAL_H_\r
-#define _IRQHAL_H_\r
-\r
-#if (IRQ_SUPPORT)\r
-/*============================================================================*\\r
-* misc declarations\r
-\*============================================================================*/\r
-#define HIRQ_BASE_ADDR (HCHIP_PERBASE_ADDR+0x001C0000)\r
-\r
-#define HIRQ_INT_CNT (16) /* number of interrupts */\r
-#define HIRQ_EVENT_CNT (19) /* number of mappable events */\r
-\r
-/******************************************************************************\\r
-* HIRQ_MUXL - interrupt multiplexer low register\r
-*\r
-* Fields:\r
-* (RW) HIRQ_MUXL_INTSEL4\r
-* (RW) HIRQ_MUXL_INTSEL5\r
-* (RW) HIRQ_MUXL_INTSEL6\r
-* (RW) HIRQ_MUXL_INTSEL7\r
-* (RW) HIRQ_MUXL_INTSEL8\r
-* (RW) HIRQ_MUXL_INTSEL9\r
-*\r
-\******************************************************************************/\r
- #define HIRQ_MUXL_ADDR (HIRQ_BASE_ADDR+0x0004)\r
- #define HIRQ_MUXL REG32(HIRQ_MUXL_ADDR)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HIRQ_MUXL_INTSEL4\r
-\*----------------------------------------------------------------------------*/\r
- #define HIRQ_MUXL_INTSEL4_MASK (0x0000001F)\r
- #define HIRQ_MUXL_INTSEL4_SHIFT (0x00000000)\r
- \r
- #define HIRQ_MUXL_INTSEL4_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HIRQ_MUXL_INTSEL4)\r
-\r
- #define HIRQ_MUXL_INTSEL4_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HIRQ_MUXL_INTSEL4,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HIRQ_MUXL_INTSEL5\r
-\*----------------------------------------------------------------------------*/\r
- #define HIRQ_MUXL_INTSEL5_MASK (0x000003E0)\r
- #define HIRQ_MUXL_INTSEL5_SHIFT (0x00000005)\r
-\r
- #define HIRQ_MUXL_INTSEL5_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HIRQ_MUXL_INTSEL5)\r
-\r
- #define HIRQ_MUXL_INTSEL5_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HIRQ_MUXL_INTSEL5,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HIRQ_MUXL_INTSEL6\r
-\*----------------------------------------------------------------------------*/\r
- #define HIRQ_MUXL_INTSEL6_MASK (0x00007C00)\r
- #define HIRQ_MUXL_INTSEL6_SHIFT (0x0000000A)\r
-\r
- #define HIRQ_MUXL_INTSEL6_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HIRQ_MUXL_INTSEL6)\r
-\r
- #define HIRQ_MUXL_INTSEL6_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HIRQ_MUXL_INTSEL6,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HIRQ_MUXL_INTSEL7\r
-\*----------------------------------------------------------------------------*/\r
- #define HIRQ_MUXL_INTSEL7_MASK (0x001F0000)\r
- #define HIRQ_MUXL_INTSEL7_SHIFT (0x00000010)\r
-\r
- #define HIRQ_MUXL_INTSEL7_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HIRQ_MUXL_INTSEL7)\r
-\r
- #define HIRQ_MUXL_INTSEL7_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HIRQ_MUXL_INTSEL7,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HIRQ_MUXL_INTSEL8\r
-\*----------------------------------------------------------------------------*/\r
- #define HIRQ_MUXL_INTSEL8_MASK (0x03E00000)\r
- #define HIRQ_MUXL_INTSEL8_SHIFT (0x00000015)\r
-\r
- #define HIRQ_MUXL_INTSEL8_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HIRQ_MUXL_INTSEL8)\r
-\r
- #define HIRQ_MUXL_INTSEL8_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HIRQ_MUXL_INTSEL8,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HIRQ_MUXL_INTSEL9\r
-\*----------------------------------------------------------------------------*/\r
- #define HIRQ_MUXL_INTSEL9_MASK (0x7C000000)\r
- #define HIRQ_MUXL_INTSEL9_SHIFT (0x0000001A)\r
-\r
- #define HIRQ_MUXL_INTSEL9_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HIRQ_MUXL_INTSEL9)\r
-\r
- #define HIRQ_MUXL_INTSEL9_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HIRQ_MUXL_INTSEL9,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HIRQ_MUXL\r
-\*----------------------------------------------------------------------------*/\r
- #define HIRQ_MUXL_GET(RegAddr) HREG32_GET(RegAddr)\r
- #define HIRQ_MUXL_SET(RegAddr,Val) HREG32_SET(RegAddr,Val)\r
- \r
- #define HIRQ_MUXL_CFG(RegAddr,intsel4,intsel5,intsel6,intsel7,intsel8,\\r
- intsel9) REG32(RegAddr) = (\\r
- HFIELD_SHIFT(HIRQ_MUXL_INTSEL4, intsel4)|\\r
- HFIELD_SHIFT(HIRQ_MUXL_INTSEL5, intsel5)|\\r
- HFIELD_SHIFT(HIRQ_MUXL_INTSEL6, intsel6)|\\r
- HFIELD_SHIFT(HIRQ_MUXL_INTSEL7, intsel7)|\\r
- HFIELD_SHIFT(HIRQ_MUXL_INTSEL8, intsel8)|\\r
- HFIELD_SHIFT(HIRQ_MUXL_INTSEL9, intsel9)\\r
- )\r
-\r
-/******************************************************************************\\r
-* HIRQ_MUXH - interrupt multiplexer high register\r
-*\r
-* Fields:\r
-* (RW) HIRQ_MUXH_INTSEL10\r
-* (RW) HIRQ_MUXH_INTSEL11\r
-* (RW) HIRQ_MUXH_INTSEL12\r
-* (RW) HIRQ_MUXH_INTSEL13\r
-* (RW) HIRQ_MUXH_INTSEL14\r
-* (RW) HIRQ_MUXH_INTSEL15\r
-*\r
-\******************************************************************************/\r
- #define HIRQ_MUXH_ADDR (HIRQ_BASE_ADDR+0x0000)\r
- #define HIRQ_MUXH REG32(HIRQ_MUXH_ADDR)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HIRQ_MUXH_INTSEL10\r
-\*----------------------------------------------------------------------------*/\r
- #define HIRQ_MUXH_INTSEL10_MASK (0x0000001F)\r
- #define HIRQ_MUXH_INTSEL10_SHIFT (0x00000000)\r
- \r
- #define HIRQ_MUXH_INTSEL10_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HIRQ_MUXH_INTSEL10)\r
-\r
- #define HIRQ_MUXH_INTSEL10_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HIRQ_MUXH_INTSEL10,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HIRQ_MUXH_INTSEL11\r
-\*----------------------------------------------------------------------------*/\r
- #define HIRQ_MUXH_INTSEL11_MASK (0x000003E0)\r
- #define HIRQ_MUXH_INTSEL11_SHIFT (0x00000005)\r
-\r
- #define HIRQ_MUXH_INTSEL11_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HIRQ_MUXH_INTSEL11)\r
-\r
- #define HIRQ_MUXH_INTSEL11_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HIRQ_MUXH_INTSEL11,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HIRQ_MUXH_INTSEL12\r
-\*----------------------------------------------------------------------------*/\r
- #define HIRQ_MUXH_INTSEL12_MASK (0x00007C00)\r
- #define HIRQ_MUXH_INTSEL12_SHIFT (0x0000000A)\r
-\r
- #define HIRQ_MUXH_INTSEL12_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HIRQ_MUXH_INTSEL12)\r
-\r
- #define HIRQ_MUXH_INTSEL12_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HIRQ_MUXH_INTSEL12,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HIRQ_MUXH_INTSEL13\r
-\*----------------------------------------------------------------------------*/\r
- #define HIRQ_MUXH_INTSEL13_MASK (0x001F0000)\r
- #define HIRQ_MUXH_INTSEL13_SHIFT (0x00000010)\r
-\r
- #define HIRQ_MUXH_INTSEL13_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HIRQ_MUXH_INTSEL13)\r
-\r
- #define HIRQ_MUXH_INTSEL13_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HIRQ_MUXH_INTSEL13,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HIRQ_MUXH_INTSEL14\r
-\*----------------------------------------------------------------------------*/\r
- #define HIRQ_MUXH_INTSEL14_MASK (0x03E00000)\r
- #define HIRQ_MUXH_INTSEL14_SHIFT (0x00000015)\r
-\r
- #define HIRQ_MUXH_INTSEL14_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HIRQ_MUXH_INTSEL14)\r
-\r
- #define HIRQ_MUXH_INTSEL14_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HIRQ_MUXH_INTSEL14,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HIRQ_MUXH_INTSEL15\r
-\*----------------------------------------------------------------------------*/\r
- #define HIRQ_MUXH_INTSEL15_MASK (0x7C000000)\r
- #define HIRQ_MUXH_INTSEL15_SHIFT (0x0000001A)\r
-\r
- #define HIRQ_MUXH_INTSEL15_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HIRQ_MUXH_INTSEL15)\r
-\r
- #define HIRQ_MUXH_INTSEL15_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HIRQ_MUXH_INTSEL15,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HIRQ_MUXH\r
-\*----------------------------------------------------------------------------*/\r
- #define HIRQ_MUXH_GET(RegAddr) HREG32_GET(RegAddr)\r
- #define HIRQ_MUXH_SET(RegAddr,Val) HREG32_SET(RegAddr,Val)\r
- \r
- #define HIRQ_MUXH_CFG(RegAddr,intsel10,intsel11,intsel12,intsel13,intsel14,\\r
- intsel15) REG32(RegAddr) = (\\r
- HFIELD_SHIFT(HIRQ_MUXH_INTSEL10, intsel10)|\\r
- HFIELD_SHIFT(HIRQ_MUXH_INTSEL11, intsel11)|\\r
- HFIELD_SHIFT(HIRQ_MUXH_INTSEL12, intsel12)|\\r
- HFIELD_SHIFT(HIRQ_MUXH_INTSEL13, intsel13)|\\r
- HFIELD_SHIFT(HIRQ_MUXH_INTSEL14, intsel14)|\\r
- HFIELD_SHIFT(HIRQ_MUXH_INTSEL15, intsel15)\\r
- )\r
-\r
-/******************************************************************************\\r
-* HIRQ_EXTPOL - external interrupt polarity register\r
-*\r
-* Fields:\r
-* (RW) HIRQ_EXTPOL_XIP4\r
-* (RW) HIRQ_EXTPOL_XIP5\r
-* (RW) HIRQ_EXTPOL_XIP6\r
-* (RW) HIRQ_EXTPOL_XIP7\r
-*\r
-\******************************************************************************/\r
- #define HIRQ_EXTPOL_ADDR (HIRQ_BASE_ADDR+0x0008)\r
- #define HIRQ_EXTPOL REG32(HIRQ_EXTPOL_ADDR)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HIRQ_EXTPOL_XIP4\r
-\*----------------------------------------------------------------------------*/\r
- #define HIRQ_EXTPOL_XIP4_MASK (0x00000001)\r
- #define HIRQ_EXTPOL_XIP4_SHIFT (0x00000000)\r
- \r
- #define HIRQ_EXTPOL_XIP4_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HIRQ_EXTPOL_XIP4)\r
-\r
- #define HIRQ_EXTPOL_XIP4_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HIRQ_EXTPOL_XIP4,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HIRQ_EXTPOL_XIP5\r
-\*----------------------------------------------------------------------------*/\r
- #define HIRQ_EXTPOL_XIP5_MASK (0x00000002)\r
- #define HIRQ_EXTPOL_XIP5_SHIFT (0x00000001)\r
- \r
- #define HIRQ_EXTPOL_XIP5_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HIRQ_EXTPOL_XIP5)\r
-\r
- #define HIRQ_EXTPOL_XIP5_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HIRQ_EXTPOL_XIP5,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HIRQ_EXTPOL_XIP6\r
-\*----------------------------------------------------------------------------*/\r
- #define HIRQ_EXTPOL_XIP6_MASK (0x00000004)\r
- #define HIRQ_EXTPOL_XIP6_SHIFT (0x00000002)\r
- \r
- #define HIRQ_EXTPOL_XIP6_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HIRQ_EXTPOL_XIP6)\r
-\r
- #define HIRQ_EXTPOL_XIP6_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HIRQ_EXTPOL_XIP6,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HIRQ_EXTPOL_XIP7\r
-\*----------------------------------------------------------------------------*/\r
- #define HIRQ_EXTPOL_XIP7_MASK (0x00000008)\r
- #define HIRQ_EXTPOL_XIP7_SHIFT (0x00000003)\r
- \r
- #define HIRQ_EXTPOL_XIP7_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HIRQ_EXTPOL_XIP7)\r
-\r
- #define HIRQ_EXTPOL_XIP7_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HIRQ_EXTPOL_XIP7,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HIRQ_EXTPOL\r
-\*----------------------------------------------------------------------------*/\r
- #define HIRQ_EXTPOL_GET(RegAddr) HREG32_GET(RegAddr)\r
- #define HIRQ_EXTPOL_SET(RegAddr,Val) HREG32_SET(RegAddr,Val)\r
- \r
- #define HIRQ_EXTPOL_CFG(RegAddr,xip4,xip5,xip6,xip7)\\r
- REG32(RegAddr) = (\\r
- HFIELD_SHIFT(HIRQ_EXTPOL_XIP4, xip4)|\\r
- HFIELD_SHIFT(HIRQ_EXTPOL_XIP5, xip5)|\\r
- HFIELD_SHIFT(HIRQ_EXTPOL_XIP6, xip6)|\\r
- HFIELD_SHIFT(HIRQ_EXTPOL_XIP7, xip7)\\r
- )\r
-\r
-/*----------------------------------------------------------------------------*/\r
-\r
-#endif /* IRQ_SUPPORT */\r
-#endif /* _IRQHAL_H_ */\r
-/******************************************************************************\\r
-* End of irqhal.h\r
-\******************************************************************************/\r
-\r
-/******************************************************************************\\r
-* Copyright (C) 1999-2000 Texas Instruments Incorporated.\r
-* All Rights Reserved\r
-*------------------------------------------------------------------------------\r
-* FILENAME...... mcbsphal.h\r
-* DATE CREATED.. 06/12/1999 \r
-* LAST MODIFIED. 03/08/2000\r
-*\r
-*------------------------------------------------------------------------------\r
-* DESCRIPTION: (HAL interface file for the MCBSP module)\r
-*\r
-* Registers Covered:\r
-* HMCBSP_DRR0 - serial port 0 data receive register\r
-* HMCBSP_DXR0 - serial port 0 data transmit register\r
-* HMCBSP_SPCR0 - serial port 0 control register\r
-* HMCBSP_RCR0 - serial port 0 receive control register\r
-* HMCBSP_XCR0 - serial port 0 transmit control register\r
-* HMCBSP_SRGR0 - serial port 0 sample rate generator register\r
-* HMCBSP_MCR0 - serial port 0 multichannel control register\r
-* HMCBSP_RCER0 - serial port 0 receive channel enable register\r
-* HMCBSP_XCER0 - serial port 0 transmit channel enable register\r
-* HMCBSP_PCR0 - serial port 0 pin control register\r
-*\r
-* HMCBSP_DRR1 - serial port 1 data receive register\r
-* HMCBSP_DXR1 - serial port 1 data transmit register\r
-* HMCBSP_SPCR1 - serial port 1 control register\r
-* HMCBSP_RCR1 - serial port 1 receive control register\r
-* HMCBSP_XCR1 - serial port 1 transmit control register\r
-* HMCBSP_SRGR1 - serial port 1 sample rate generator register\r
-* HMCBSP_MCR1 - serial port 1 multichannel control register\r
-* HMCBSP_RCER1 - serial port 1 receive channel enable register\r
-* HMCBSP_XCER1 - serial port 1 transmit channel enable register\r
-* HMCBSP_PCR1 - serial port 1 pin control register\r
-*\r
-* HMCBSP_DRR2 - serial port 2 data receive register (1)\r
-* HMCBSP_DXR2 - serial port 2 data transmit register (1)\r
-* HMCBSP_SPCR2 - serial port 2 control register (1)\r
-* HMCBSP_RCR2 - serial port 2 receive control register (1)\r
-* HMCBSP_XCR2 - serial port 2 transmit control register (1)\r
-* HMCBSP_SRGR2 - serial port 2 sample rate generator register (1)\r
-* HMCBSP_MCR2 - serial port 2 multichannel control register (1)\r
-* HMCBSP_RCER2 - serial port 2 receive channel enable register (1)\r
-* HMCBSP_XCER2 - serial port 2 transmit channel enable register (1)\r
-* HMCBSP_PCR2 - serial port 2 pin control register (1)\r
-*\r
-* (1) only on devices with three serial ports\r
-*\r
-\******************************************************************************/\r
-#ifndef _MCBSPHAL_H_\r
-#define _MCBSPHAL_H_\r
-\r
-#if (MCBSP_SUPPORT)\r
-/*============================================================================*\\r
-* misc declarations\r
-\*============================================================================*/\r
-#define HMCBSP_BASE0_ADDR (HCHIP_PERBASE_ADDR+0x000C0000)\r
-#define HMCBSP_BASE1_ADDR (HCHIP_PERBASE_ADDR+0x00100000)\r
-#define HMCBSP_BASE2_ADDR (HCHIP_PERBASE_ADDR+0x00240000)\r
-\r
-#if (CHIP_6202 | CHIP_6203)\r
- #define HMCBSP_PORT_CNT (3)\r
-#else\r
- #define HMCBSP_PORT_CNT (2)\r
-#endif\r
-\r
-/******************************************************************************\\r
-* HMCBSP_DRR0 - serial port 0 data receive register\r
-* HMCBSP_DRR1 - serial port 1 data receive register\r
-* HMCBSP_DRR2 - serial port 2 data receive register (1)\r
-*\r
-* (1) only on devices with three serial ports\r
-*\r
-* Fields:\r
-* (R) HMCBSP_DRR_DRR\r
-*\r
-\******************************************************************************/\r
-#if (C11_SUPPORT & 0)\r
- #define HMCBSP_DRR0_ADDR (0x30000000)\r
- #define HMCBSP_DRR1_ADDR (0x34000000)\r
-#else\r
- #define HMCBSP_DRR0_ADDR (HMCBSP_BASE0_ADDR+0x0000)\r
- #define HMCBSP_DRR1_ADDR (HMCBSP_BASE1_ADDR+0x0000)\r
-#endif \r
- #define HMCBSP_DRR0 REG32(HMCBSP_DRR0_ADDR)\r
- #define HMCBSP_DRR1 REG32(HMCBSP_DRR1_ADDR)\r
-\r
-#if (HMCBSP_PORT_CNT==3)\r
- #define HMCBSP_DRR2_ADDR (HMCBSP_BASE2_ADDR+0x0000)\r
- #define HMCBSP_DRR2 REG32(HMCBSP_DRR2_ADDR)\r
-#endif\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (R) HMCBSP_DRR_DRR\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_DRR_DRR_MASK (0xFFFFFFFF)\r
- #define HMCBSP_DRR_DRR_SHIFT (0x00000000)\r
-\r
- #define HMCBSP_DRR_DRR_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_DRR_DRR)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (R) HMCBSP_DRR\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_DRR_GET(RegAddr) HREG32_GET(RegAddr)\r
-\r
-/******************************************************************************\\r
-* HMCBSP_DXR0 - serial port 0 data transmit register\r
-* HMCBSP_DXR1 - serial port 1 data transmit register\r
-* HMCBSP_DXR2 - serial port 2 data transmit register (1)\r
-*\r
-* (1) only on devices with three serial ports\r
-*\r
-* Fields:\r
-* (W) HMCBSP_DXR_DXR\r
-*\r
-\******************************************************************************/\r
-#if (C11_SUPPORT & 0)\r
- #define HMCBSP_DXR0_ADDR (0x30000000)\r
- #define HMCBSP_DXR1_ADDR (0x34000000)\r
-#else\r
- #define HMCBSP_DXR0_ADDR (HMCBSP_BASE0_ADDR+0x0004)\r
- #define HMCBSP_DXR1_ADDR (HMCBSP_BASE1_ADDR+0x0004)\r
-#endif \r
- #define HMCBSP_DXR0 REG32(HMCBSP_DXR0_ADDR)\r
- #define HMCBSP_DXR1 REG32(HMCBSP_DXR1_ADDR)\r
-\r
-#if (HMCBSP_PORT_CNT==3)\r
- #define HMCBSP_DXR2_ADDR (HMCBSP_BASE2_ADDR+0x0004)\r
- #define HMCBSP_DXR2 REG32(HMCBSP_DXR2_ADDR)\r
-#endif\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (W) HMCBSP_DXR_DXR\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_DXR_DXR_MASK (0xFFFFFFFF)\r
- #define HMCBSP_DXR_DXR_SHIFT (0x00000000)\r
- \r
- #define HMCBSP_DXR_DXR_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_DXR_DXR,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (W) HMCBSP_DXR\r
-\*----------------------------------------------------------------------------*/ \r
- #define HMCBSP_DXR_SET(RegAddr,Val) HREG32_SET(RegAddr,Val)\r
-\r
- #define HMCBSP_DXR_CFG(RegAddr,dxr) REG32(RegAddr)=(UINT32)( \\r
- HFIELD_SHIFT(HMCBSP_DXR_DXR,dxr) \\r
- )\r
- \r
-/******************************************************************************\\r
-* HMCBSP_SPCR0 - serial port 0 control register\r
-* HMCBSP_SPCR1 - serial port 1 control register\r
-* HMCBSP_SPCR2 - serial port 2 control register (1)\r
-*\r
-* (1) only on devices with three serial ports\r
-*\r
-* Fields:\r
-* (RW) HMCBSP_SPCR_RRST\r
-* (R) HMCBSP_SPCR_RRDY\r
-* (R) HMCBSP_SPCR_FULL\r
-* (RW) HMCBSP_SPCR_RSYNCERR\r
-* (RW) HMCBSP_SPCR_RINTM\r
-* (RW) HMCBSP_SPCR_DXENA\r
-* (RW) HMCBSP_SPCR_CLKSTP\r
-* (RW) HMCBSP_SPCR_RJUST\r
-* (RW) HMCBSP_SPCR_DLB\r
-* (RW) HMCBSP_SPCR_XRST\r
-* (R) HMCBSP_SPCR_XRDY\r
-* (R) HMCBSP_SPCR_XEMPTY\r
-* (RW) HMCBSP_SPCR_XSYNCERR\r
-* (RW) HMCBSP_SPCR_XINTM\r
-* (RW) HMCBSP_SPCR_GRST\r
-* (RW) HMCBSP_SPCR_FRST\r
-*\r
-\******************************************************************************/\r
- #define HMCBSP_SPCR0_ADDR (HMCBSP_BASE0_ADDR+0x0008)\r
- #define HMCBSP_SPCR1_ADDR (HMCBSP_BASE1_ADDR+0x0008)\r
- #define HMCBSP_SPCR0 REG32(HMCBSP_SPCR0_ADDR)\r
- #define HMCBSP_SPCR1 REG32(HMCBSP_SPCR1_ADDR)\r
-\r
-#if (HMCBSP_PORT_CNT==3)\r
- #define HMCBSP_SPCR2_ADDR (HMCBSP_BASE2_ADDR+0x0008)\r
- #define HMCBSP_SPCR2 REG32(HMCBSP_SPCR2_ADDR)\r
-#endif\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_SPCR_RRST\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_SPCR_RRST_MASK (0x00000001)\r
- #define HMCBSP_SPCR_RRST_SHIFT (0x00000000) \r
- \r
- #define HMCBSP_SPCR_RRST_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_SPCR_RRST)\r
-\r
- #define HMCBSP_SPCR_RRST_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_SPCR_RRST,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (R) HMCBSP_SPCR_RRDY\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_SPCR_RRDY_MASK (0x00000002)\r
- #define HMCBSP_SPCR_RRDY_SHIFT (0x00000001)\r
-\r
- #define HMCBSP_SPCR_RRDY_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_SPCR_RRDY)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (R) HMCBSP_SPCR_RFULL\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_SPCR_RFULL_MASK (0x00000004)\r
- #define HMCBSP_SPCR_RFULL_SHIFT (0x00000002)\r
-\r
- #define HMCBSP_SPCR_RFULL_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_SPCR_RFULL)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_SPCR_RSYNCERR\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_SPCR_RSYNCERR_MASK (0x00000008)\r
- #define HMCBSP_SPCR_RSYNCERR_SHIFT (0x00000003)\r
-\r
- #define HMCBSP_SPCR_RSYNCERR_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_SPCR_RSYNCERR)\r
-\r
- #define HMCBSP_SPCR_RSYNCERR_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_SPCR_RSYNCERR,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_SPCR_RINTM\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_SPCR_RINTM_MASK (0x00000030)\r
- #define HMCBSP_SPCR_RINTM_SHIFT (0x00000004)\r
-\r
- #define HMCBSP_SPCR_RINTM_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_SPCR_RINTM)\r
-\r
- #define HMCBSP_SPCR_RINTM_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_SPCR_RINTM,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_SPCR_DXENA\r
-\*----------------------------------------------------------------------------*/\r
-#if (C11_SUPPORT) \r
- #define HMCBSP_SPCR_DXENA_MASK (0x00000080)\r
- #define HMCBSP_SPCR_DXENA_SHIFT (0x00000007)\r
-#else\r
- #define HMCBSP_SPCR_DXENA_MASK (0x00000000)\r
- #define HMCBSP_SPCR_DXENA_SHIFT (0x00000000)\r
-#endif \r
-\r
- #define HMCBSP_SPCR_DXENA_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_SPCR_DXENA)\r
-\r
- #define HMCBSP_SPCR_DXENA_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_SPCR_DXENA,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_SPCR_CLKSTP\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_SPCR_CLKSTP_MASK (0x00001800)\r
- #define HMCBSP_SPCR_CLKSTP_SHIFT (0x0000000B)\r
-\r
- #define HMCBSP_SPCR_CLKSTP_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_SPCR_CLKSTP)\r
-\r
- #define HMCBSP_SPCR_CLKSTP_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_SPCR_CLKSTP,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_SPCR_RJUST\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_SPCR_RJUST_MASK (0x00006000)\r
- #define HMCBSP_SPCR_RJUST_SHIFT (0x0000000D)\r
-\r
- #define HMCBSP_SPCR_RJUST_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_SPCR_RJUST)\r
-\r
- #define HMCBSP_SPCR_RJUST_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_SPCR_RJUST,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_SPCR_DLB\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_SPCR_DLB_MASK (0x00008000)\r
- #define HMCBSP_SPCR_DLB_SHIFT (0x0000000F)\r
-\r
- #define HMCBSP_SPCR_DLB_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_SPCR_DLB)\r
-\r
- #define HMCBSP_SPCR_DLB_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_SPCR_DLB,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_SPCR_XRST\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_SPCR_XRST_MASK (0x00010000)\r
- #define HMCBSP_SPCR_XRST_SHIFT (0x00000010)\r
-\r
- #define HMCBSP_SPCR_XRST_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_SPCR_XRST)\r
-\r
- #define HMCBSP_SPCR_XRST_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_SPCR_XRST,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (R) HMCBSP_SPCR_XRDY\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_SPCR_XRDY_MASK (0x00020000)\r
- #define HMCBSP_SPCR_XRDY_SHIFT (0x00000011)\r
-\r
- #define HMCBSP_SPCR_XRDY_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_SPCR_XRDY)\r
-\r
- #define HMCBSP_SPCR_XRDY_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_SPCR_XRDY,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (R) HMCBSP_SPCR_XEMPTY\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_SPCR_XEMPTY_MASK (0x00040000)\r
- #define HMCBSP_SPCR_XEMPTY_SHIFT (0x00000012)\r
-\r
- #define HMCBSP_SPCR_XEMPTY_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_SPCR_XEMPTY)\r
-\r
- #define HMCBSP_SPCR_XEMPTY_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_SPCR_XEMPTY,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_SPCR_XSYNCERR\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_SPCR_XSYNCERR_MASK (0x00080000)\r
- #define HMCBSP_SPCR_XSYNCERR_SHIFT (0x00000013)\r
-\r
- #define HMCBSP_SPCR_XSYNCERR_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_SPCR_XSYNCERR)\r
-\r
- #define HMCBSP_SPCR_XSYNCERR_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_SPCR_XSYNCERR,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_SPCR_XINTM\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_SPCR_XINTM_MASK (0x00300000)\r
- #define HMCBSP_SPCR_XINTM_SHIFT (0x00000014)\r
-\r
- #define HMCBSP_SPCR_XINTM_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_SPCR_XINTM)\r
-\r
- #define HMCBSP_SPCR_XINTM_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_SPCR_XINTM,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_SPCR_GRST\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_SPCR_GRST_MASK (0x00400000)\r
- #define HMCBSP_SPCR_GRST_SHIFT (0x00000016)\r
-\r
- #define HMCBSP_SPCR_GRST_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_SPCR_GRST)\r
-\r
- #define HMCBSP_SPCR_GRST_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_SPCR_GRST,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_SPCR_FRST\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_SPCR_FRST_MASK (0x00800000)\r
- #define HMCBSP_SPCR_FRST_SHIFT (0x00000017)\r
-\r
- #define HMCBSP_SPCR_FRST_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_SPCR_FRST)\r
-\r
- #define HMCBSP_SPCR_FRST_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_SPCR_FRST,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_SPCR\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_SPCR_GET(RegAddr) HREG32_GET(RegAddr)\r
- #define HMCBSP_SPCR_SET(RegAddr,Val) HREG32_SET(RegAddr,Val)\r
-\r
- #define HMCBSP_SPCR_CFG(RegAddr,rrst,rsyncerr,rintm,dxena,clkstp,rjust,dlb,\\r
- xrst,xsyncerr,xintm,grst,frst) REG32(RegAddr)=(UINT32)(\\r
- HFIELD_SHIFT(HMCBSP_SPCR_RRST, rrst) |\\r
- HFIELD_SHIFT(HMCBSP_SPCR_RSYNCERR,rsyncerr)|\\r
- HFIELD_SHIFT(HMCBSP_SPCR_RINTM, rintm) |\\r
- HFIELD_SHIFT(HMCBSP_SPCR_DXENA, dxena) |\\r
- HFIELD_SHIFT(HMCBSP_SPCR_CLKSTP, clkstp) |\\r
- HFIELD_SHIFT(HMCBSP_SPCR_RJUST, rjust) |\\r
- HFIELD_SHIFT(HMCBSP_SPCR_DLB, dlb) |\\r
- HFIELD_SHIFT(HMCBSP_SPCR_XRST, xrst) |\\r
- HFIELD_SHIFT(HMCBSP_SPCR_XSYNCERR,xsyncerr)|\\r
- HFIELD_SHIFT(HMCBSP_SPCR_XINTM, xintm) |\\r
- HFIELD_SHIFT(HMCBSP_SPCR_GRST, grst) |\\r
- HFIELD_SHIFT(HMCBSP_SPCR_FRST, frst) \\r
- )\r
-\r
-/******************************************************************************\\r
-* HMCBSP_RCR0 - serial port 0 receive control register\r
-* HMCBSP_RCR1 - serial port 1 receive control register\r
-* HMCBSP_RCR2 - serial port 2 receive control register (1)\r
-*\r
-* (1) only on devices with three serial ports\r
-*\r
-* Fields:\r
-* (RW) HMCBSP_RCR_RWDREVRS (2)\r
-* (RW) HMCBSP_RCR_RWDLEN1\r
-* (RW) HMCBSP_RCR_RFRLEN1\r
-* (RW) HMCBSP_RCR_RPHASE2 (2)\r
-* (RW) HMCBSP_RCR_RDATDLY\r
-* (RW) HMCBSP_RCR_RFIG\r
-* (RW) HMCBSP_RCR_RCOMPAND\r
-* (RW) HMCBSP_RCR_RWDLEN2\r
-* (RW) HMCBSP_RCR_RFRLEN2\r
-* (RW) HMCBSP_RCR_RPHASE \r
-*\r
-* (2) - C11_SUPPORT only\r
-*\r
-\******************************************************************************/\r
- #define HMCBSP_RCR0_ADDR (HMCBSP_BASE0_ADDR+0x000C)\r
- #define HMCBSP_RCR1_ADDR (HMCBSP_BASE1_ADDR+0x000C)\r
- #define HMCBSP_RCR0 REG32(HMCBSP_RCR0_ADDR)\r
- #define HMCBSP_RCR1 REG32(HMCBSP_RCR1_ADDR)\r
-\r
-#if (HMCBSP_PORT_CNT==3)\r
- #define HMCBSP_RCR2_ADDR (HMCBSP_BASE2_ADDR+0x000C)\r
- #define HMCBSP_RCR2 REG32(HMCBSP_RCR2_ADDR)\r
-#endif\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_RCR_RWDREVRS\r
-\*----------------------------------------------------------------------------*/\r
-#if (C11_SUPPORT)\r
- #define HMCBSP_RCR_RWDREVRS_MASK (0x00000010)\r
- #define HMCBSP_RCR_RWDREVRS_SHIFT (0x00000004)\r
-#else\r
- #define HMCBSP_RCR_RWDREVRS_MASK (0x00000000)\r
- #define HMCBSP_RCR_RWDREVRS_SHIFT (0x00000000)\r
-#endif \r
-\r
- #define HMCBSP_RCR_RWDREVRS_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_RCR_RWDREVRS)\r
-\r
- #define HMCBSP_RCR_RWDREVRS_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_RCR_RWDREVRS,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_RCR_RWDLEN1\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_RCR_RWDLEN1_MASK (0x000000E0)\r
- #define HMCBSP_RCR_RWDLEN1_SHIFT (0x00000005)\r
-\r
- #define HMCBSP_RCR_RWDLEN1_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_RCR_RWDLEN1)\r
-\r
- #define HMCBSP_RCR_RWDLEN1_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_RCR_RWDLEN1,Val)\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_RCR_RFRLEN1\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_RCR_RFRLEN1_MASK (0x00007F00)\r
- #define HMCBSP_RCR_RFRLEN1_SHIFT (0x00000008)\r
-\r
- #define HMCBSP_RCR_RFRLEN1_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_RCR_RFRLEN1)\r
-\r
- #define HMCBSP_RCR_RFRLEN1_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_RCR_RFRLEN1,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_RCR_RPHASE2\r
-\*----------------------------------------------------------------------------*/\r
-#if (C11_SUPPORT)\r
- #define HMCBSP_RCR_RPHASE2_MASK (0x00008000)\r
- #define HMCBSP_RCR_RPHASE2_SHIFT (0x0000000F)\r
-#else\r
- #define HMCBSP_RCR_RPHASE2_MASK (0x00000000)\r
- #define HMCBSP_RCR_RPHASE2_SHIFT (0x00000000)\r
-#endif\r
-\r
- #define HMCBSP_RCR_RPHASE2_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_RCR_RPHASE2)\r
-\r
- #define HMCBSP_RCR_RPHASE2_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_RCR_RPHASE2,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_RCR_RDATDLY\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_RCR_RDATDLY_MASK (0x00030000)\r
- #define HMCBSP_RCR_RDATDLY_SHIFT (0x00000010)\r
-\r
- #define HMCBSP_RCR_RDATDLY_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_RCR_RDATDLY)\r
-\r
- #define HMCBSP_RCR_RDATDLY_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_RCR_RDATDLY,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_RCR_RFIG\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_RCR_RFIG_MASK (0x00040000)\r
- #define HMCBSP_RCR_RFIG_SHIFT (0x00000012)\r
-\r
- #define HMCBSP_RCR_RFIG_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_RCR_RFIG)\r
-\r
- #define HMCBSP_RCR_RFIG_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_RCR_RFIG,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_RCR_RCOMPAND\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_RCR_RCOMPAND_MASK (0x00180000)\r
- #define HMCBSP_RCR_RCOMPAND_SHIFT (0x00000013)\r
-\r
- #define HMCBSP_RCR_RCOMPAND_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_RCR_RCOMPAND)\r
-\r
- #define HMCBSP_RCR_RCOMPAND_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_RCR_RCOMPAND,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_RCR_RWDLEN2\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_RCR_RWDLEN2_MASK (0x00E00000)\r
- #define HMCBSP_RCR_RWDLEN2_SHIFT (0x00000015)\r
-\r
- #define HMCBSP_RCR_RWDLEN2_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_RCR_RWDLEN2)\r
-\r
- #define HMCBSP_RCR_RWDLEN2_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_RCR_RWDLEN2,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_RCR_RFRLEN2\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_RCR_RFRLEN2_MASK (0x7F000000)\r
- #define HMCBSP_RCR_RFRLEN2_SHIFT (0x00000018)\r
-\r
- #define HMCBSP_RCR_FRFLEN2_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_RCR_FRFLEN2)\r
-\r
- #define HMCBSP_RCR_FRFLEN2_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_RCR_FRFLEN2,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_RCR_RPHASE\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_RCR_RPHASE_MASK (0x80000000)\r
- #define HMCBSP_RCR_RPHASE_SHIFT (0x0000001F)\r
- \r
- #define HMCBSP_RCR_RPHASE_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_RCR_RPHASE)\r
-\r
- #define HMCBSP_RCR_RPHASE_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_RCR_RPHASE,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_RCR\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_RCR_GET(RegAddr) HREG32_GET(RegAddr)\r
- #define HMCBSP_RCR_SET(RegAddr,Val) HREG32_SET(RegAddr,Val)\r
-\r
- #define HMCBSP_RCR_CFG(RegAddr,rwdrevrs,rwdlen1,rfrlen1,rphase2,rdatdly,\\r
- rfig,rcompand,rwdlen2,rfrlen2,rphase) REG32(RegAddr)=(UINT32)(\\r
- HFIELD_SHIFT(HMCBSP_RCR_RWDREVRS,rwdrevrs)|\\r
- HFIELD_SHIFT(HMCBSP_RCR_RWDLEN1, rwdlen1) |\\r
- HFIELD_SHIFT(HMCBSP_RCR_RFRLEN1, rfrlen1) |\\r
- HFIELD_SHIFT(HMCBSP_RCR_RPHASE2, rphase2) |\\r
- HFIELD_SHIFT(HMCBSP_RCR_RDATDLY, rdatdly) |\\r
- HFIELD_SHIFT(HMCBSP_RCR_RFIG, rfig) |\\r
- HFIELD_SHIFT(HMCBSP_RCR_RCOMPAND,rcompand)|\\r
- HFIELD_SHIFT(HMCBSP_RCR_RWDLEN2, rwdlen2) |\\r
- HFIELD_SHIFT(HMCBSP_RCR_RFRLEN2, rfrlen2) |\\r
- HFIELD_SHIFT(HMCBSP_RCR_RPHASE, rphase) \\r
- )\r
-\r
-/******************************************************************************\\r
-* HMCBSP_XCR0 - serial port 0 transmit control register\r
-* HMCBSP_XCR1 - serial port 1 transmit control register\r
-* HMCBSP_XCR2 - serial port 2 transmit control register (1)\r
-*\r
-* (1) only on devices with three serial ports\r
-*\r
-* Fields:\r
-* (RW) HMCBSP_XCR_XWDREVRS (2)\r
-* (RW) HMCBSP_XCR_XWDLEN1\r
-* (RW) HMCBSP_XCR_XFRLEN1\r
-* (RW) HMCBSP_XCR_XPHASE2 (2)\r
-* (RW) HMCBSP_XCR_XDATDLY\r
-* (RW) HMCBSP_XCR_XFIG\r
-* (RW) HMCBSP_XCR_XCOMPAND\r
-* (RW) HMCBSP_XCR_XWDLEN2\r
-* (RW) HMCBSP_XCR_XFRLEN2\r
-* (RW) HMCBSP_XCR_XPHASE \r
-*\r
-* (2) - C11_SUPPORT only\r
-*\r
-\******************************************************************************/\r
- #define HMCBSP_XCR0_ADDR (HMCBSP_BASE0_ADDR+0x0010)\r
- #define HMCBSP_XCR1_ADDR (HMCBSP_BASE1_ADDR+0x0010)\r
- #define HMCBSP_XCR0 REG32(HMCBSP_XCR0_ADDR)\r
- #define HMCBSP_XCR1 REG32(HMCBSP_XCR1_ADDR)\r
-\r
-#if (HMCBSP_PORT_CNT==3)\r
- #define HMCBSP_XCR2_ADDR (HMCBSP_BASE2_ADDR+0x0010)\r
- #define HMCBSP_XCR2 REG32(HMCBSP_XCR2_ADDR)\r
-#endif\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_XCR_RWDREVRS\r
-\*----------------------------------------------------------------------------*/\r
-#if (C11_SUPPORT)\r
- #define HMCBSP_XCR_XWDREVRS_MASK (0x00000010)\r
- #define HMCBSP_XCR_XWDREVRS_SHIFT (0x00000004)\r
-#else\r
- #define HMCBSP_XCR_XWDREVRS_MASK (0x00000000)\r
- #define HMCBSP_XCR_XWDREVRS_SHIFT (0x00000000)\r
-#endif \r
-\r
- #define HMCBSP_XCR_XWDREVRS_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_XCR_XWDREVRS)\r
-\r
- #define HMCBSP_XCR_XWDREVRS_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_XCR_XWDREVRS,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_XCR_XWDLEN1\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_XCR_XWDLEN1_MASK (0x000000E0)\r
- #define HMCBSP_XCR_XWDLEN1_SHIFT (0x00000005)\r
- \r
- #define HMCBSP_XCR_XWDLEN1_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_XCR_XWDLEN1)\r
-\r
- #define HMCBSP_XCR_XWDLEN1_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_XCR_XWDLEN1,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_XCR_XFRLEN1\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_XCR_XFRLEN1_MASK (0x00007F00)\r
- #define HMCBSP_XCR_XFRLEN1_SHIFT (0x00000008)\r
-\r
- #define HMCBSP_XCR_XFRLEN1_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_XCR_XFRLEN1)\r
-\r
- #define HMCBSP_XCR_XFRLEN1_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_XCR_XFRLEN1,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_XCR_XPHASE2\r
-\*----------------------------------------------------------------------------*/\r
-#if (C11_SUPPORT)\r
- #define HMCBSP_XCR_XPHASE2_MASK (0x00008000)\r
- #define HMCBSP_XCR_XPHASE2_SHIFT (0x0000000F)\r
-#else\r
- #define HMCBSP_XCR_XPHASE2_MASK (0x00000000)\r
- #define HMCBSP_XCR_XPHASE2_SHIFT (0x00000000)\r
-#endif\r
-\r
- #define HMCBSP_XCR_XPHASE2_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_XCR_XPHASE2)\r
-\r
- #define HMCBSP_XCR_XPHASE2_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_XCR_XPHASE2,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_XCR_XDATDLY\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_XCR_XDATDLY_MASK (0x00030000)\r
- #define HMCBSP_XCR_XDATDLY_SHIFT (0x00000010)\r
-\r
- #define HMCBSP_XCR_XDATDLY_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_XCR_XDATDLY)\r
-\r
- #define HMCBSP_XCR_XDATDLY_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_XCR_XDATDLY,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_XCR_XFIG\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_XCR_XFIG_MASK (0x00040000)\r
- #define HMCBSP_XCR_XFIG_SHIFT (0x00000012)\r
-\r
- #define HMCBSP_XCR_XFIG_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_XCR_XFIG)\r
-\r
- #define HMCBSP_XCR_XFIG_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_XCR_XFIG,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_XCR_XCOMPAND\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_XCR_XCOMPAND_MASK (0x00180000)\r
- #define HMCBSP_XCR_XCOMPAND_SHIFT (0x00000013)\r
-\r
- #define HMCBSP_XCR_XCOMPAND_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_XCR_XCOMPAND)\r
-\r
- #define HMCBSP_XCR_XCOMPAND_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_XCR_XCOMPAND,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_XCR_XWDLEN2\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_XCR_XWDLEN2_MASK (0x00E00000)\r
- #define HMCBSP_XCR_XWDLEN2_SHIFT (0x00000015)\r
-\r
- #define HMCBSP_XCR_XWDLEN2_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_XCR_XWDLEN2)\r
-\r
- #define HMCBSP_XCR_XWDLEN2_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_XCR_XWDLEN2,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_XCR_XFRLEN2\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_XCR_XFRLEN2_MASK (0x7F000000)\r
- #define HMCBSP_XCR_XFRLEN2_SHIFT (0x00000018)\r
-\r
- #define HMCBSP_XCR_XFRLEN2_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_XCR_XFRLEN2)\r
-\r
- #define HMCBSP_XCR_XFRLEN2_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_XCR_XFRLEN2,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_XCR_XPHASE\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_XCR_XPHASE_MASK (0x80000000)\r
- #define HMCBSP_XCR_XPHASE_SHIFT (0x0000001F)\r
-\r
- #define HMCBSP_XCR_XPHASE_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_XCR_XPHASE)\r
-\r
- #define HMCBSP_XCR_XPHASE_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_XCR_XPHASE,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_XCR\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_XCR_GET(RegAddr) HREG32_GET(RegAddr)\r
- #define HMCBSP_XCR_SET(RegAddr,Val) HREG32_SET(RegAddr,Val)\r
-\r
- #define HMCBSP_XCR_CFG(RegAddr,xwdrevrs,xwdlen1,xfrlen1,xphase2,xdatdly,\\r
- xfig,xcompand,xwdlen2,xfrlen2,xphase) (REG32(RegAddr)=(UINT32)(\\r
- HFIELD_SHIFT(HMCBSP_XCR_XWDREVRS,xwdrevrs)|\\r
- HFIELD_SHIFT(HMCBSP_XCR_XWDLEN1, xwdlen1) |\\r
- HFIELD_SHIFT(HMCBSP_XCR_XFRLEN1, xfrlen1) |\\r
- HFIELD_SHIFT(HMCBSP_XCR_XPHASE2, xphase2) |\\r
- HFIELD_SHIFT(HMCBSP_XCR_XDATDLY, xdatdly) |\\r
- HFIELD_SHIFT(HMCBSP_XCR_XFIG, xfig) |\\r
- HFIELD_SHIFT(HMCBSP_XCR_XCOMPAND,xcompand)|\\r
- HFIELD_SHIFT(HMCBSP_XCR_XWDLEN2, xwdlen2) |\\r
- HFIELD_SHIFT(HMCBSP_XCR_XFRLEN2, xfrlen2) |\\r
- HFIELD_SHIFT(HMCBSP_XCR_XPHASE, xphase) \\r
- )\r
-\r
-/******************************************************************************\\r
-* HMCBSP_SRGR0 - serial port 0 sample rate generator register\r
-* HMCBSP_SRGR1 - serial port 1 sample rate generator register\r
-* HMCBSP_SRGR2 - serial port 2 sample rate generator register (1)\r
-*\r
-* (1) only on devices with three serial ports\r
-*\r
-* Fields:\r
-* (RW) HMCBSP_SRGR_CLKGDV\r
-* (RW) HMCBSP_SRGR_FWID\r
-* (RW) HMCBSP_SRGR_FPER\r
-* (RW) HMCBSP_SRGR_FSGM\r
-* (RW) HMCBSP_SRGR_CLKSM\r
-* (RW) HMCBSP_SRGR_CLKSP\r
-* (RW) HMCBSP_SRGR_GSYNC\r
-*\r
-\******************************************************************************/\r
- #define HMCBSP_SRGR0_ADDR (HMCBSP_BASE0_ADDR+0x0014)\r
- #define HMCBSP_SRGR1_ADDR (HMCBSP_BASE1_ADDR+0x0014)\r
- #define HMCBSP_SRGR0 REG32(HMCBSP_SRGR0_ADDR)\r
- #define HMCBSP_SRGR1 REG32(HMCBSP_SRGR1_ADDR)\r
-\r
-#if (HMCBSP_PORT_CNT==3)\r
- #define HMCBSP_SRGR2_ADDR (HMCBSP_BASE2_ADDR+0x0014)\r
- #define HMCBSP_SRGR2 REG32(HMCBSP_SRGR2_ADDR)\r
-#endif\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_SRGR_CLKGDV\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_SRGR_CLKGDV_MASK (0x000000FF)\r
- #define HMCBSP_SRGR_CLKGDV_SHIFT (0x00000000)\r
- \r
- #define HMCBSP_SRGR_CLKGDV_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_SRGR_CLKGDV)\r
-\r
- #define HMCBSP_SRGR_CLKGDV_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_SRGR_CLKGDV,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_SRGR_FWID\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_SRGR_FWID_MASK (0x0000FF00)\r
- #define HMCBSP_SRGR_FWID_SHIFT (0x00000008)\r
-\r
- #define HMCBSP_SRGR_FWID_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_SRGR_FWID)\r
-\r
- #define HMCBSP_SRGR_FWID_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_SRGR_FWID,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_SRGR_FPER\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_SRGR_FPER_MASK (0x0FFF0000)\r
- #define HMCBSP_SRGR_FPER_SHIFT (0x00000010)\r
-\r
- #define HMCBSP_SRGR_FPER_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_SRGR_FPER)\r
-\r
- #define HMCBSP_SRGR_FPER_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_SRGR_FPER,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_SRGR_FSGM\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_SRGR_FSGM_MASK (0x10000000)\r
- #define HMCBSP_SRGR_FSGM_SHIFT (0x0000001C)\r
-\r
- #define HMCBSP_SRGR_FSGM_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_SRGR_FSGM)\r
-\r
- #define HMCBSP_SRGR_FSGM_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_SRGR_FSGM,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_SRGR_CLKSM\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_SRGR_CLKSM_MASK (0x20000000)\r
- #define HMCBSP_SRGR_CLKSM_SHIFT (0x0000001D)\r
-\r
- #define HMCBSP_SRGR_CLKSM_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_SRGR_CLKSM)\r
-\r
- #define HMCBSP_SRGR_CLKSM_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_SRGR_CLKSM,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_SRGR_CLKSP\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_SRGR_CLKSP_MASK (0x40000000)\r
- #define HMCBSP_SRGR_CLKSP_SHIFT (0x0000001E)\r
-\r
- #define HMCBSP_SRGR_CLKSP_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_SRGR_CLKSP)\r
-\r
- #define HMCBSP_SRGR_CLKSP_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_SRGR_CLKSP,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_SRGR_GSYNC\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_SRGR_GSYNC_MASK (0x80000000)\r
- #define HMCBSP_SRGR_GSYNC_SHIFT (0x0000001F)\r
-\r
- #define HMCBSP_SRGR_GSYNC_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_SRGR_GSYNC)\r
-\r
- #define HMCBSP_SRGR_GSYNC_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_SRGR_GSYNC,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_SRGR\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_SRGR_GET(RegAddr) HREG32_GET(RegAddr)\r
- #define HMCBSP_SRGR_SET(RegAddr,Val) HREG32_SET(RegAddr,Val)\r
-\r
- #define HMCBSP_SRGR_CFG(RegAddr,clkgdv,fwid,fper,fsgm,clksm,clksp,gsync) \\r
- REG32(RegAddr)=(UINT32)( \\r
- HFIELD_SHIFT(HMCBSP_SRGR_CLKGDV , clkgdv )|\\r
- HFIELD_SHIFT(HMCBSP_SRGR_FWID , fwid )|\\r
- HFIELD_SHIFT(HMCBSP_SRGR_FPER , fper )|\\r
- HFIELD_SHIFT(HMCBSP_SRGR_FSGM , fsgm )|\\r
- HFIELD_SHIFT(HMCBSP_SRGR_CLKSM , clksm )|\\r
- HFIELD_SHIFT(HMCBSP_SRGR_CLKSP , clksp )|\\r
- HFIELD_SHIFT(HMCBSP_SRGR_GSYNC , gsync ) \\r
- )\r
-\r
-/******************************************************************************\\r
-* HMCBSP_MCR0 - serial port 0 multichannel control register\r
-* HMCBSP_MCR1 - serial port 1 multichannel control register\r
-* HMCBSP_MCR2 - serial port 2 multichannel control register (1)\r
-*\r
-* (1) only on devices with three serial ports\r
-*\r
-* Fields:\r
-* (RW) HMCBSP_MCR_RMCM\r
-* (R) HMCBSP_MCR_RCBLK\r
-* (RW) HMCBSP_MCR_RPABLK\r
-* (RW) HMCBSP_MCR_RPBBLK\r
-* (RW) HMCBSP_MCR_XMCM\r
-* (R) HMCBSP_MCR_XCBLK\r
-* (RW) HMCBSP_MCR_XPABLK\r
-* (RW) HMCBSP_MCR_XPBBLK\r
-*\r
-\******************************************************************************/\r
- #define HMCBSP_MCR0_ADDR (HMCBSP_BASE0_ADDR+0x0018)\r
- #define HMCBSP_MCR1_ADDR (HMCBSP_BASE1_ADDR+0x0018)\r
- #define HMCBSP_MCR0 REG32(HMCBSP_MCR0_ADDR)\r
- #define HMCBSP_MCR1 REG32(HMCBSP_MCR1_ADDR)\r
-\r
-#if (HMCBSP_PORT_CNT==3)\r
- #define HMCBSP_MCR2_ADDR (HMCBSP_BASE2_ADDR+0x0018)\r
- #define HMCBSP_MCR2 REG32(HMCBSP_MCR2_ADDR)\r
-#endif\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_MCR_RMCM\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_MCR_RMCM_MASK (0x00000001)\r
- #define HMCBSP_MCR_RMCM_SHIFT (0x00000000)\r
-\r
- #define HMCBSP_MCR_RMCM_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_MCR_RMCM)\r
-\r
- #define HMCBSP_MCR_RMCM_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_MCR_RMCM,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (R) HMCBSP_MCR_RCBLK\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_MCR_RCBLK_MASK (0x0000001C)\r
- #define HMCBSP_MCR_RCBLK_SHIFT (0x00000002)\r
-\r
- #define HMCBSP_MCR_RCBLK_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_MCR_RCBLK)\r
-\r
- #define HMCBSP_MCR_RCBLK_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_MCR_RCBLK,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_MCR_RPABLK\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_MCR_RPABLK_MASK (0x00000060)\r
- #define HMCBSP_MCR_RPABLK_SHIFT (0x00000005)\r
-\r
- #define HMCBSP_MCR_RPABLK_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_MCR_RPABLK)\r
-\r
- #define HMCBSP_MCR_RPABLK_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_MCR_RPABLK,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_MCR_RPBBLK\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_MCR_RPBBLK_MASK (0x00000180)\r
- #define HMCBSP_MCR_RPBBLK_SHIFT (0x00000007)\r
-\r
- #define HMCBSP_MCR_RPBBLK_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_MCR_RPBBLK)\r
-\r
- #define HMCBSP_MCR_RPBBLK_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_MCR_RPBBLK,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_MCR_XMCM\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_MCR_XMCM_MASK (0x00030000)\r
- #define HMCBSP_MCR_XMCM_SHIFT (0x00000010)\r
-\r
- #define HMCBSP_MCR_XMCM_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_MCR_XMCM)\r
-\r
- #define HMCBSP_MCR_XMCM_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_MCR_XMCM,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (R) HMCBSP_MCR_XCBLK\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_MCR_XCBLK_MASK (0x001C0000)\r
- #define HMCBSP_MCR_XCBLK_SHIFT (0x00000012)\r
-\r
- #define HMCBSP_MCR_XCBLK_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_MCR_XCBLK)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_MCR_XPABLK\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_MCR_XPABLK_MASK (0x00600000)\r
- #define HMCBSP_MCR_XPABLK_SHIFT (0x00000015)\r
-\r
- #define HMCBSP_MCR_XPABLK_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_MCR_XPABLK)\r
-\r
- #define HMCBSP_MCR_XPABLK_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_MCR_XPABLK,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_MCR_XPBBLK\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_MCR_XPBBLK_MASK (0x01800000)\r
- #define HMCBSP_MCR_XPBBLK_SHIFT (0x00000017)\r
-\r
- #define HMCBSP_MCR_XPBBLK_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_MCR_XPBBLK)\r
-\r
- #define HMCBSP_MCR_XPBBLK_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_MCR_XPBBLK,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_MCR\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_MCR_GET(RegAddr) HREG32_GET(RegAddr)\r
- #define HMCBSP_MCR_SET(RegAddr,Val) HREG32_SET(RegAddr,Val)\r
-\r
- #define HMCBSP_MCR_CFG(RegAddr,rmcm,rpablk,rpbblk,xmcm,xpablk,xpbblk) \\r
- REG32(RegAddr)=(UINT32)( \\r
- HFIELD_SHIFT(HMCBSP_MCR_RMCM ,rmcm )|\\r
- HFIELD_SHIFT(HMCBSP_MCR_RPABLK,rpablk)|\\r
- HFIELD_SHIFT(HMCBSP_MCR_RPBBLK,rpbblk)|\\r
- HFIELD_SHIFT(HMCBSP_MCR_XMCM ,xmcm )|\\r
- HFIELD_SHIFT(HMCBSP_MCR_XPABLK,xpablk)|\\r
- HFIELD_SHIFT(HMCBSP_MCR_XPBBLK,xpbblk) \\r
- )\r
-\r
-/******************************************************************************\\r
-* HMCBSP_RCER0 - serial port 0 receive channel enable register\r
-* HMCBSP_RCER1 - serial port 1 receive channel enable register\r
-* HMCBSP_RCER2 - serial port 2 receive channel enable register (1)\r
-*\r
-* (1) only on devices with three serial ports\r
-*\r
-* Fields:\r
-*\r
-\******************************************************************************/\r
- #define HMCBSP_RCER0_ADDR (HMCBSP_BASE0_ADDR+0x001C)\r
- #define HMCBSP_RCER1_ADDR (HMCBSP_BASE1_ADDR+0x001C)\r
- #define HMCBSP_RCER0 REG32(HMCBSP_RCER0_ADDR)\r
- #define HMCBSP_RCER1 REG32(HMCBSP_RCER1_ADDR)\r
-\r
-#if (HMCBSP_PORT_CNT==3)\r
- #define HMCBSP_RCER2_ADDR (HMCBSP_BASE2_ADDR+0x001C)\r
- #define HMCBSP_RCER2 REG32(HMCBSP_RCER2_ADDR)\r
-#endif\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_RCER_RCEA0\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_RCER_RCEA0_MASK (0x00000001)\r
- #define HMCBSP_RCER_RCEA0_SHIFT (0x00000000)\r
-\r
- #define HMCBSP_RCER_RCEA0_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_RCER_RCEA0)\r
-\r
- #define HMCBSP_RCER_RCEA0_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_RCER_RCEA0,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_RCER_RCEA1\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_RCER_RCEA1_MASK (0x00000002)\r
- #define HMCBSP_RCER_RCEA1_SHIFT (0x00000001)\r
-\r
- #define HMCBSP_RCER_RCEA1_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_RCER_RCEA1)\r
-\r
- #define HMCBSP_RCER_RCEA1_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_RCER_RCEA1,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_RCER_RCEA2\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_RCER_RCEA2_MASK (0x00000004)\r
- #define HMCBSP_RCER_RCEA2_SHIFT (0x00000002)\r
-\r
- #define HMCBSP_RCER_RCEA2_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_RCER_RCEA2)\r
-\r
- #define HMCBSP_RCER_RCEA2_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_RCER_RCEA2,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_RCER_RCEA3\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_RCER_RCEA3_MASK (0x00000008)\r
- #define HMCBSP_RCER_RCEA3_SHIFT (0x00000003)\r
-\r
- #define HMCBSP_RCER_RCEA3_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_RCER_RCEA3)\r
-\r
- #define HMCBSP_RCER_RCEA3_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_RCER_RCEA3,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_RCER_RCEA4\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_RCER_RCEA4_MASK (0x00000010)\r
- #define HMCBSP_RCER_RCEA4_SHIFT (0x00000004)\r
-\r
- #define HMCBSP_RCER_RCEA4_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_RCER_RCEA4)\r
-\r
- #define HMCBSP_RCER_RCEA4_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_RCER_RCEA4,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_RCER_RCEA5\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_RCER_RCEA5_MASK (0x00000020)\r
- #define HMCBSP_RCER_RCEA5_SHIFT (0x00000005)\r
-\r
- #define HMCBSP_RCER_RCEA5_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_RCER_RCEA5)\r
-\r
- #define HMCBSP_RCER_RCEA5_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_RCER_RCEA5,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_RCER_RCEA6\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_RCER_RCEA6_MASK (0x00000040)\r
- #define HMCBSP_RCER_RCEA6_SHIFT (0x00000006)\r
-\r
- #define HMCBSP_RCER_RCEA6_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_RCER_RCEA6)\r
-\r
- #define HMCBSP_RCER_RCEA6_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_RCER_RCEA6,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_RCER_RCEA7\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_RCER_RCEA7_MASK (0x00000080)\r
- #define HMCBSP_RCER_RCEA7_SHIFT (0x00000007)\r
-\r
- #define HMCBSP_RCER_RCEA7_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_RCER_RCEA7)\r
-\r
- #define HMCBSP_RCER_RCEA7_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_RCER_RCEA7,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_RCER_RCEA8\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_RCER_RCEA8_MASK (0x00000100)\r
- #define HMCBSP_RCER_RCEA8_SHIFT (0x00000008)\r
-\r
- #define HMCBSP_RCER_RCEA8_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_RCER_RCEA8)\r
-\r
- #define HMCBSP_RCER_RCEA8_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_RCER_RCEA8,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_RCER_RCEA9\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_RCER_RCEA9_MASK (0x00000200)\r
- #define HMCBSP_RCER_RCEA9_SHIFT (0x00000009)\r
-\r
- #define HMCBSP_RCER_RCEA9_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_RCER_RCEA9)\r
-\r
- #define HMCBSP_RCER_RCEA9_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_RCER_RCEA9,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_RCER_RCEA10\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_RCER_RCEA10_MASK (0x00000400)\r
- #define HMCBSP_RCER_RCEA10_SHIFT (0x0000000A)\r
-\r
- #define HMCBSP_RCER_RCEA10_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_RCER_RCEA10)\r
-\r
- #define HMCBSP_RCER_RCEA10_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_RCER_RCEA10,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_RCER_RCEA11\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_RCER_RCEA11_MASK (0x00000800)\r
- #define HMCBSP_RCER_RCEA11_SHIFT (0x0000000B)\r
-\r
- #define HMCBSP_RCER_RCEA11_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_RCER_RCEA11)\r
-\r
- #define HMCBSP_RCER_RCEA11_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_RCER_RCEA11,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_RCER_RCEA12\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_RCER_RCEA12_MASK (0x00001000)\r
- #define HMCBSP_RCER_RCEA12_SHIFT (0x0000000C)\r
-\r
- #define HMCBSP_RCER_RCEA12_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_RCER_RCEA12)\r
-\r
- #define HMCBSP_RCER_RCEA12_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_RCER_RCEA12,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_RCER_RCEA13\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_RCER_RCEA13_MASK (0x00002000)\r
- #define HMCBSP_RCER_RCEA13_SHIFT (0x0000000D)\r
-\r
- #define HMCBSP_RCER_RCEA13_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_RCER_RCEA13)\r
-\r
- #define HMCBSP_RCER_RCEA13_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_RCER_RCEA13,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_RCER_RCEA14\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_RCER_RCEA14_MASK (0x00004000)\r
- #define HMCBSP_RCER_RCEA14_SHIFT (0x0000000E)\r
-\r
- #define HMCBSP_RCER_RCEA14_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_RCER_RCEA14)\r
-\r
- #define HMCBSP_RCER_RCEA14_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_RCER_RCEA14,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_RCER_RCEA15\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_RCER_RCEA15_MASK (0x00008000)\r
- #define HMCBSP_RCER_RCEA15_SHIFT (0x0000000F)\r
-\r
- #define HMCBSP_RCER_RCEA15_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_RCER_RCEA15)\r
-\r
- #define HMCBSP_RCER_RCEA15_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_RCER_RCEA15,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_RCER_RCEB0\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_RCER_RCEB0_MASK (0x00010000)\r
- #define HMCBSP_RCER_RCEB0_SHIFT (0x00000010)\r
- \r
- #define HMCBSP_RCER_RCEB0_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_RCER_RCEB0)\r
-\r
- #define HMCBSP_RCER_RCEB0_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_RCER_RCEB0,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_RCER_RCEB1\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_RCER_RCEB1_MASK (0x00020000)\r
- #define HMCBSP_RCER_RCEB1_SHIFT (0x00000011)\r
- \r
- #define HMCBSP_RCER_RCEB1_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_RCER_RCEB1)\r
-\r
- #define HMCBSP_RCER_RCEB1_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_RCER_RCEB1,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_RCER_RCEB2\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_RCER_RCEB2_MASK (0x00040000)\r
- #define HMCBSP_RCER_RCEB2_SHIFT (0x00000012)\r
- \r
- #define HMCBSP_RCER_RCEB2_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_RCER_RCEB2)\r
-\r
- #define HMCBSP_RCER_RCEB2_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_RCER_RCEB2,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_RCER_RCEB3\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_RCER_RCEB3_MASK (0x00080000)\r
- #define HMCBSP_RCER_RCEB3_SHIFT (0x00000013)\r
- \r
- #define HMCBSP_RCER_RCEB3_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_RCER_RCEB3)\r
-\r
- #define HMCBSP_RCER_RCEB3_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_RCER_RCEB3,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_RCER_RCEB4\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_RCER_RCEB4_MASK (0x00100000)\r
- #define HMCBSP_RCER_RCEB4_SHIFT (0x00000014)\r
- \r
- #define HMCBSP_RCER_RCEB4_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_RCER_RCEB4)\r
-\r
- #define HMCBSP_RCER_RCEB4_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_RCER_RCEB4,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_RCER_RCEB5\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_RCER_RCEB5_MASK (0x00200000)\r
- #define HMCBSP_RCER_RCEB5_SHIFT (0x00000015)\r
- \r
- #define HMCBSP_RCER_RCEB5_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_RCER_RCEB5)\r
-\r
- #define HMCBSP_RCER_RCEB5_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_RCER_RCEB5,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_RCER_RCEB6\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_RCER_RCEB6_MASK (0x00400000)\r
- #define HMCBSP_RCER_RCEB6_SHIFT (0x00000016)\r
- \r
- #define HMCBSP_RCER_RCEB6_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_RCER_RCEB6)\r
-\r
- #define HMCBSP_RCER_RCEB6_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_RCER_RCEB6,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_RCER_RCEB7\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_RCER_RCEB7_MASK (0x00800000)\r
- #define HMCBSP_RCER_RCEB7_SHIFT (0x00000017)\r
- \r
- #define HMCBSP_RCER_RCEB7_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_RCER_RCEB7)\r
-\r
- #define HMCBSP_RCER_RCEB7_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_RCER_RCEB7,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_RCER_RCEB8\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_RCER_RCEB8_MASK (0x01000000)\r
- #define HMCBSP_RCER_RCEB8_SHIFT (0x00000018)\r
- \r
- #define HMCBSP_RCER_RCEB8_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_RCER_RCEB8)\r
-\r
- #define HMCBSP_RCER_RCEB8_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_RCER_RCEB8,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_RCER_RCEB9\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_RCER_RCEB9_MASK (0x02000000)\r
- #define HMCBSP_RCER_RCEB9_SHIFT (0x00000019)\r
- \r
- #define HMCBSP_RCER_RCEB9_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_RCER_RCEB9)\r
-\r
- #define HMCBSP_RCER_RCEB9_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_RCER_RCEB9,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_RCER_RCEB10\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_RCER_RCEB10_MASK (0x04000000)\r
- #define HMCBSP_RCER_RCEB10_SHIFT (0x0000001A)\r
- \r
- #define HMCBSP_RCER_RCEB10_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_RCER_RCEB10)\r
-\r
- #define HMCBSP_RCER_RCEB10_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_RCER_RCEB10,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_RCER_RCEB11\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_RCER_RCEB11_MASK (0x08000000)\r
- #define HMCBSP_RCER_RCEB11_SHIFT (0x0000001B)\r
- \r
- #define HMCBSP_RCER_RCEB11_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_RCER_RCEB11)\r
-\r
- #define HMCBSP_RCER_RCEB11_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_RCER_RCEB11,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_RCER_RCEB12\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_RCER_RCEB12_MASK (0x10000000)\r
- #define HMCBSP_RCER_RCEB12_SHIFT (0x0000001C)\r
- \r
- #define HMCBSP_RCER_RCEB12_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_RCER_RCEB12)\r
-\r
- #define HMCBSP_RCER_RCEB12_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_RCER_RCEB12,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_RCER_RCEB13\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_RCER_RCEB13_MASK (0x20000000)\r
- #define HMCBSP_RCER_RCEB13_SHIFT (0x0000001D)\r
- \r
- #define HMCBSP_RCER_RCEB13_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_RCER_RCEB13)\r
-\r
- #define HMCBSP_RCER_RCEB13_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_RCER_RCEB13,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_RCER_RCEB14\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_RCER_RCEB14_MASK (0x40000000)\r
- #define HMCBSP_RCER_RCEB14_SHIFT (0x0000001E)\r
- \r
- #define HMCBSP_RCER_RCEB14_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_RCER_RCEB14)\r
-\r
- #define HMCBSP_RCER_RCEB14_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_RCER_RCEB14,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_RCER_RCEB15\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_RCER_RCEB15_MASK (0x80000000)\r
- #define HMCBSP_RCER_RCEB15_SHIFT (0x0000001F)\r
- \r
- #define HMCBSP_RCER_RCEB15_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_RCER_RCEB15)\r
-\r
- #define HMCBSP_RCER_RCEB15_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_RCER_RCEB15,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_RCER\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_RCER_GET(RegAddr) HREG32_GET(RegAddr)\r
- #define HMCBSP_RCER_SET(RegAddr,Val) HREG32_SET(RegAddr,Val)\r
-\r
- #define HMCBSP_RCER_CFG(RegAddr,rcea0,rcea1,rcea2,rcea3,rcea4,rcea5,rcea6,\\r
- rcea7,rcea8,rcea9,rcea10,rcea11,rcea12,rcea13,rcea14,rcea15,rceb0,rceb1,\\r
- rceb2,rceb3,rceb4,rceb5,rceb6,rceb7,rceb8,rceb9,rceb10,rceb11,rceb12,rceb13,\\r
- rceb14,rceb15) REG32(RegAddr)=(UINT32)(\\r
- HFIELD_SHIFT(HMCBSP_RCER_RCEA0, rcea0 )|\\r
- HFIELD_SHIFT(HMCBSP_RCER_RCEA1, rcea1 )|\\r
- HFIELD_SHIFT(HMCBSP_RCER_RCEA2, rcea2 )|\\r
- HFIELD_SHIFT(HMCBSP_RCER_RCEA3, rcea3 )|\\r
- HFIELD_SHIFT(HMCBSP_RCER_RCEA4, rcea4 )|\\r
- HFIELD_SHIFT(HMCBSP_RCER_RCEA5, rcea5 )|\\r
- HFIELD_SHIFT(HMCBSP_RCER_RCEA6, rcea6 )|\\r
- HFIELD_SHIFT(HMCBSP_RCER_RCEA7, rcea7 )|\\r
- HFIELD_SHIFT(HMCBSP_RCER_RCEA8, rcea8 )|\\r
- HFIELD_SHIFT(HMCBSP_RCER_RCEA9, rcea9 )|\\r
- HFIELD_SHIFT(HMCBSP_RCER_RCEA10,rcea10)|\\r
- HFIELD_SHIFT(HMCBSP_RCER_RCEA11,rcea11)|\\r
- HFIELD_SHIFT(HMCBSP_RCER_RCEA12,rcea12)|\\r
- HFIELD_SHIFT(HMCBSP_RCER_RCEA13,rcea13)|\\r
- HFIELD_SHIFT(HMCBSP_RCER_RCEA14,rcea14)|\\r
- HFIELD_SHIFT(HMCBSP_RCER_RCEA15,rcea15)|\\r
- HFIELD_SHIFT(HMCBSP_RCER_RCEB0, rceb0 )|\\r
- HFIELD_SHIFT(HMCBSP_RCER_RCEB1, rceb1 )|\\r
- HFIELD_SHIFT(HMCBSP_RCER_RCEB2, rceb2 )|\\r
- HFIELD_SHIFT(HMCBSP_RCER_RCEB3, rceb3 )|\\r
- HFIELD_SHIFT(HMCBSP_RCER_RCEB4, rceb4 )|\\r
- HFIELD_SHIFT(HMCBSP_RCER_RCEB5, rceb5 )|\\r
- HFIELD_SHIFT(HMCBSP_RCER_RCEB6, rceb6 )|\\r
- HFIELD_SHIFT(HMCBSP_RCER_RCEB7, rceb7 )|\\r
- HFIELD_SHIFT(HMCBSP_RCER_RCEB8, rceb8 )|\\r
- HFIELD_SHIFT(HMCBSP_RCER_RCEB9, rceb9 )|\\r
- HFIELD_SHIFT(HMCBSP_RCER_RCEB10,rceb10)|\\r
- HFIELD_SHIFT(HMCBSP_RCER_RCEB11,rceb11)|\\r
- HFIELD_SHIFT(HMCBSP_RCER_RCEB12,rceb12)|\\r
- HFIELD_SHIFT(HMCBSP_RCER_RCEB13,rceb13)|\\r
- HFIELD_SHIFT(HMCBSP_RCER_RCEB14,rceb14)|\\r
- HFIELD_SHIFT(HMCBSP_RCER_RCEB15,rceb15) \\r
- )\r
-\r
-/******************************************************************************\\r
-* HMCBSP_XCER0 - serial port 0 transmit channel enable register\r
-* HMCBSP_XCER1 - serial port 1 transmit channel enable register\r
-* HMCBSP_XCER2 - serial port 2 transmit channel enable register (1)\r
-*\r
-* (1) only on devices with three serial ports\r
-*\r
-* Fields:\r
-*\r
-\******************************************************************************/\r
- #define HMCBSP_XCER0_ADDR (HMCBSP_BASE0_ADDR+0x0020)\r
- #define HMCBSP_XCER1_ADDR (HMCBSP_BASE1_ADDR+0x0020)\r
- #define HMCBSP_XCER0 REG32(HMCBSP_XCER0_ADDR)\r
- #define HMCBSP_XCER1 REG32(HMCBSP_XCER1_ADDR)\r
-\r
-#if (HMCBSP_PORT_CNT==3)\r
- #define HMCBSP_XCER2_ADDR (HMCBSP_BASE2_ADDR+0x0020)\r
- #define HMCBSP_XCER2 REG32(HMCBSP_XCER2_ADDR)\r
-#endif\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_XCER_XCEA0\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_XCER_XCEA0_MASK (0x00000001)\r
- #define HMCBSP_XCER_XCEA0_SHIFT (0x00000000)\r
-\r
- #define HMCBSP_XCER_XCEA0_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_XCER_XCEA0)\r
-\r
- #define HMCBSP_XCER_XCEA0_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_XCER_XCEA0,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_XCER_XCEA1\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_XCER_XCEA1_MASK (0x00000002)\r
- #define HMCBSP_XCER_XCEA1_SHIFT (0x00000001)\r
-\r
- #define HMCBSP_XCER_XCEA1_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_XCER_XCEA1)\r
-\r
- #define HMCBSP_XCER_XCEA1_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_XCER_XCEA1,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_XCER_XCEA2\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_XCER_XCEA2_MASK (0x00000004)\r
- #define HMCBSP_XCER_XCEA2_SHIFT (0x00000002)\r
-\r
- #define HMCBSP_XCER_XCEA2_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_XCER_XCEA2)\r
-\r
- #define HMCBSP_XCER_XCEA2_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_XCER_XCEA2,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_XCER_XCEA3\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_XCER_XCEA3_MASK (0x00000008)\r
- #define HMCBSP_XCER_XCEA3_SHIFT (0x00000003)\r
-\r
- #define HMCBSP_XCER_XCEA3_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_XCER_XCEA3)\r
-\r
- #define HMCBSP_XCER_XCEA3_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_XCER_XCEA3,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_XCER_XCEA4\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_XCER_XCEA4_MASK (0x00000010)\r
- #define HMCBSP_XCER_XCEA4_SHIFT (0x00000004)\r
-\r
- #define HMCBSP_XCER_XCEA4_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_XCER_XCEA4)\r
-\r
- #define HMCBSP_XCER_XCEA4_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_XCER_XCEA4,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_XCER_XCEA5\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_XCER_XCEA5_MASK (0x00000020)\r
- #define HMCBSP_XCER_XCEA5_SHIFT (0x00000005)\r
-\r
- #define HMCBSP_XCER_XCEA5_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_XCER_XCEA5)\r
-\r
- #define HMCBSP_XCER_XCEA5_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_XCER_XCEA5,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_XCER_XCEA6\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_XCER_XCEA6_MASK (0x00000040)\r
- #define HMCBSP_XCER_XCEA6_SHIFT (0x00000006)\r
-\r
- #define HMCBSP_XCER_XCEA6_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_XCER_XCEA6)\r
-\r
- #define HMCBSP_XCER_XCEA6_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_XCER_XCEA6,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_XCER_XCEA7\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_XCER_XCEA7_MASK (0x00000080)\r
- #define HMCBSP_XCER_XCEA7_SHIFT (0x00000007)\r
-\r
- #define HMCBSP_XCER_XCEA7_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_XCER_XCEA7)\r
-\r
- #define HMCBSP_XCER_XCEA7_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_XCER_XCEA7,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_XCER_XCEA8\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_XCER_XCEA8_MASK (0x00000100)\r
- #define HMCBSP_XCER_XCEA8_SHIFT (0x00000008)\r
-\r
- #define HMCBSP_XCER_XCEA8_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_XCER_XCEA8)\r
-\r
- #define HMCBSP_XCER_XCEA8_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_XCER_XCEA8,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_XCER_XCEA9\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_XCER_XCEA9_MASK (0x00000200)\r
- #define HMCBSP_XCER_XCEA9_SHIFT (0x00000009)\r
-\r
- #define HMCBSP_XCER_XCEA9_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_XCER_XCEA9)\r
-\r
- #define HMCBSP_XCER_XCEA9_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_XCER_XCEA9,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_XCER_XCEA10\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_XCER_XCEA10_MASK (0x00000400)\r
- #define HMCBSP_XCER_XCEA10_SHIFT (0x0000000A)\r
-\r
- #define HMCBSP_XCER_XCEA10_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_XCER_XCEA10)\r
-\r
- #define HMCBSP_XCER_XCEA10_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_XCER_XCEA10,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_XCER_XCEA11\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_XCER_XCEA11_MASK (0x00000800)\r
- #define HMCBSP_XCER_XCEA11_SHIFT (0x0000000B)\r
-\r
- #define HMCBSP_XCER_XCEA11_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_XCER_XCEA11)\r
-\r
- #define HMCBSP_XCER_XCEA11_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_XCER_XCEA11,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_XCER_XCEA12\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_XCER_XCEA12_MASK (0x00001000)\r
- #define HMCBSP_XCER_XCEA12_SHIFT (0x0000000C)\r
-\r
- #define HMCBSP_XCER_XCEA12_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_XCER_XCEA12)\r
-\r
- #define HMCBSP_XCER_XCEA12_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_XCER_XCEA12,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_XCER_XCEA13\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_XCER_XCEA13_MASK (0x00002000)\r
- #define HMCBSP_XCER_XCEA13_SHIFT (0x0000000D)\r
-\r
- #define HMCBSP_XCER_XCEA13_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_XCER_XCEA13)\r
-\r
- #define HMCBSP_XCER_XCEA13_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_XCER_XCEA13,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_XCER_XCEA14\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_XCER_XCEA14_MASK (0x00004000)\r
- #define HMCBSP_XCER_XCEA14_SHIFT (0x0000000E)\r
-\r
- #define HMCBSP_XCER_XCEA14_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_XCER_XCEA14)\r
-\r
- #define HMCBSP_XCER_XCEA14_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_XCER_XCEA14,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_XCER_XCEA15\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_XCER_XCEA15_MASK (0x00008000)\r
- #define HMCBSP_XCER_XCEA15_SHIFT (0x0000000F)\r
-\r
- #define HMCBSP_XCER_XCEA15_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_XCER_XCEA15)\r
-\r
- #define HMCBSP_XCER_XCEA15_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_XCER_XCEA15,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_XCER_XCEB0\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_XCER_XCEB0_MASK (0x00010000)\r
- #define HMCBSP_XCER_XCEB0_SHIFT (0x00000010)\r
- \r
- #define HMCBSP_XCER_XCEB0_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_XCER_XCEB0)\r
-\r
- #define HMCBSP_XCER_XCEB0_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_XCER_XCEB0,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_XCER_XCEB1\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_XCER_XCEB1_MASK (0x00020000)\r
- #define HMCBSP_XCER_XCEB1_SHIFT (0x00000011)\r
- \r
- #define HMCBSP_XCER_XCEB1_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_XCER_XCEB1)\r
-\r
- #define HMCBSP_XCER_XCEB1_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_XCER_XCEB1,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_XCER_XCEB2\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_XCER_XCEB2_MASK (0x00040000)\r
- #define HMCBSP_XCER_XCEB2_SHIFT (0x00000012)\r
- \r
- #define HMCBSP_XCER_XCEB2_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_XCER_XCEB2)\r
-\r
- #define HMCBSP_XCER_XCEB2_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_XCER_XCEB2,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_XCER_XCEB3\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_XCER_XCEB3_MASK (0x00080000)\r
- #define HMCBSP_XCER_XCEB3_SHIFT (0x00000013)\r
- \r
- #define HMCBSP_XCER_XCEB3_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_XCER_XCEB3)\r
-\r
- #define HMCBSP_XCER_XCEB3_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_XCER_XCEB3,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_XCER_XCEB4\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_XCER_XCEB4_MASK (0x00100000)\r
- #define HMCBSP_XCER_XCEB4_SHIFT (0x00000014)\r
- \r
- #define HMCBSP_XCER_XCEB4_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_XCER_XCEB4)\r
-\r
- #define HMCBSP_XCER_XCEB4_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_XCER_XCEB4,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_XCER_XCEB5\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_XCER_XCEB5_MASK (0x00200000)\r
- #define HMCBSP_XCER_XCEB5_SHIFT (0x00000015)\r
- \r
- #define HMCBSP_XCER_XCEB5_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_XCER_XCEB5)\r
-\r
- #define HMCBSP_XCER_XCEB5_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_XCER_XCEB5,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_XCER_XCEB6\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_XCER_XCEB6_MASK (0x00400000)\r
- #define HMCBSP_XCER_XCEB6_SHIFT (0x00000016)\r
- \r
- #define HMCBSP_XCER_XCEB6_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_XCER_XCEB6)\r
-\r
- #define HMCBSP_XCER_XCEB6_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_XCER_XCEB6,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_XCER_XCEB7\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_XCER_XCEB7_MASK (0x00800000)\r
- #define HMCBSP_XCER_XCEB7_SHIFT (0x00000017)\r
- \r
- #define HMCBSP_XCER_XCEB7_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_XCER_XCEB7)\r
-\r
- #define HMCBSP_XCER_XCEB7_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_XCER_XCEB7,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_XCER_XCEB8\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_XCER_XCEB8_MASK (0x01000000)\r
- #define HMCBSP_XCER_XCEB8_SHIFT (0x00000018)\r
- \r
- #define HMCBSP_XCER_XCEB8_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_XCER_XCEB8)\r
-\r
- #define HMCBSP_XCER_XCEB8_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_XCER_XCEB8,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_XCER_XCEB9\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_XCER_XCEB9_MASK (0x02000000)\r
- #define HMCBSP_XCER_XCEB9_SHIFT (0x00000019)\r
- \r
- #define HMCBSP_XCER_XCEB9_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_XCER_XCEB9)\r
-\r
- #define HMCBSP_XCER_XCEB9_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_XCER_XCEB9,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_XCER_XCEB10\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_XCER_XCEB10_MASK (0x04000000)\r
- #define HMCBSP_XCER_XCEB10_SHIFT (0x0000001A)\r
- \r
- #define HMCBSP_XCER_XCEB10_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_XCER_XCEB10)\r
-\r
- #define HMCBSP_XCER_XCEB10_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_XCER_XCEB10,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_XCER_XCEB11\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_XCER_XCEB11_MASK (0x08000000)\r
- #define HMCBSP_XCER_XCEB11_SHIFT (0x0000001B)\r
- \r
- #define HMCBSP_XCER_XCEB11_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_XCER_XCEB11)\r
-\r
- #define HMCBSP_XCER_XCEB11_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_XCER_XCEB11,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_XCER_XCEB12\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_XCER_XCEB12_MASK (0x10000000)\r
- #define HMCBSP_XCER_XCEB12_SHIFT (0x0000001C)\r
- \r
- #define HMCBSP_XCER_XCEB12_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_XCER_XCEB12)\r
-\r
- #define HMCBSP_XCER_XCEB12_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_XCER_XCEB12,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_XCER_XCEB13\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_XCER_XCEB13_MASK (0x20000000)\r
- #define HMCBSP_XCER_XCEB13_SHIFT (0x0000001D)\r
- \r
- #define HMCBSP_XCER_XCEB13_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_XCER_XCEB13)\r
-\r
- #define HMCBSP_XCER_XCEB13_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_XCER_XCEB13,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_XCER_XCEB14\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_XCER_XCEB14_MASK (0x40000000)\r
- #define HMCBSP_XCER_XCEB14_SHIFT (0x0000001E)\r
- \r
- #define HMCBSP_XCER_XCEB14_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_XCER_XCEB14)\r
-\r
- #define HMCBSP_XCER_XCEB14_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_XCER_XCEB14,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_XCER_XCEB15\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_XCER_XCEB15_MASK (0x80000000)\r
- #define HMCBSP_XCER_XCEB15_SHIFT (0x0000001F)\r
- \r
- #define HMCBSP_XCER_XCEB15_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_XCER_XCEB15)\r
-\r
- #define HMCBSP_XCER_XCEB15_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_XCER_XCEB15,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_XCER\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_XCER_GET(RegAddr) HREG32_GET(RegAddr)\r
- #define HMCBSP_XCER_SET(RegAddr,Val) HREG32_SET(RegAddr,Val)\r
-\r
- #define HMCBSP_XCER_CFG(RegAddr,xcea0,xcea1,xcea2,xcea3,xcea4,xcea5,xcea6,\\r
- xcea7,xcea8,xcea9,xcea10,xcea11,xcea12,xcea13,xcea14,xcea15,xceb0,xceb1,\\r
- xceb2,xceb3,xceb4,xceb5,xceb6,xceb7,xceb8,xceb9,xceb10,xceb11,xceb12,xceb13,\\r
- xceb14,xceb15) REG32(RegAddr)=(UINT32)(\\r
- HFIELD_SHIFT(HMCBSP_XCER_XCEA0, xcea0 )|\\r
- HFIELD_SHIFT(HMCBSP_XCER_XCEA1, xcea1 )|\\r
- HFIELD_SHIFT(HMCBSP_XCER_XCEA2, xcea2 )|\\r
- HFIELD_SHIFT(HMCBSP_XCER_XCEA3, xcea3 )|\\r
- HFIELD_SHIFT(HMCBSP_XCER_XCEA4, xcea4 )|\\r
- HFIELD_SHIFT(HMCBSP_XCER_XCEA5, xcea5 )|\\r
- HFIELD_SHIFT(HMCBSP_XCER_XCEA6, xcea6 )|\\r
- HFIELD_SHIFT(HMCBSP_XCER_XCEA7, xcea7 )|\\r
- HFIELD_SHIFT(HMCBSP_XCER_XCEA8, xcea8 )|\\r
- HFIELD_SHIFT(HMCBSP_XCER_XCEA9, xcea9 )|\\r
- HFIELD_SHIFT(HMCBSP_XCER_XCEA10,xcea10)|\\r
- HFIELD_SHIFT(HMCBSP_XCER_XCEA11,xcea11)|\\r
- HFIELD_SHIFT(HMCBSP_XCER_XCEA12,xcea12)|\\r
- HFIELD_SHIFT(HMCBSP_XCER_XCEA13,xcea13)|\\r
- HFIELD_SHIFT(HMCBSP_XCER_XCEA14,xcea14)|\\r
- HFIELD_SHIFT(HMCBSP_XCER_XCEA15,xcea15)|\\r
- HFIELD_SHIFT(HMCBSP_XCER_XCEB0, xceb0 )|\\r
- HFIELD_SHIFT(HMCBSP_XCER_XCEB1, xceb1 )|\\r
- HFIELD_SHIFT(HMCBSP_XCER_XCEB2, xceb2 )|\\r
- HFIELD_SHIFT(HMCBSP_XCER_XCEB3, xceb3 )|\\r
- HFIELD_SHIFT(HMCBSP_XCER_XCEB4, xceb4 )|\\r
- HFIELD_SHIFT(HMCBSP_XCER_XCEB5, xceb5 )|\\r
- HFIELD_SHIFT(HMCBSP_XCER_XCEB6, xceb6 )|\\r
- HFIELD_SHIFT(HMCBSP_XCER_XCEB7, xceb7 )|\\r
- HFIELD_SHIFT(HMCBSP_XCER_XCEB8, xceb8 )|\\r
- HFIELD_SHIFT(HMCBSP_XCER_XCEB9, xceb9 )|\\r
- HFIELD_SHIFT(HMCBSP_XCER_XCEB10,xceb10)|\\r
- HFIELD_SHIFT(HMCBSP_XCER_XCEB11,xceb11)|\\r
- HFIELD_SHIFT(HMCBSP_XCER_XCEB12,xceb12)|\\r
- HFIELD_SHIFT(HMCBSP_XCER_XCEB13,xceb13)|\\r
- HFIELD_SHIFT(HMCBSP_XCER_XCEB14,xceb14)|\\r
- HFIELD_SHIFT(HMCBSP_XCER_XCEB15,xceb15) \\r
- )\r
-\r
-/******************************************************************************\\r
-* HMCBSP_PCR0 - serial port 0 pin control register\r
-* HMCBSP_PCR1 - serial port 1 pin control register\r
-* HMCBSP_PCR2 - serial port 2 pin control register (1)\r
-*\r
-* (1) only on devices with three serial ports\r
-*\r
-* Fields:\r
-* (RW) HMCBSP_PCR_CLKRP\r
-* (RW) HMCBSP_PCR_CLKXP\r
-* (RW) HMCBSP_PCR_FSRP\r
-* (RW) HMCBSP_PCR_FSXP\r
-* (R) HMCBSP_PCR_DRSTAT\r
-* (RW) HMCBSP_PCR_DXSTAT\r
-* (RW) HMCBSP_PCR_CLKSSTAT\r
-* (RW) HMCBSP_PCR_CLKRM\r
-* (RW) HMCBSP_PCR_CLKXM\r
-* (RW) HMCBSP_PCR_FSRM\r
-* (RW) HMCBSP_PCR_FSXM\r
-* (RW) HMCBSP_PCR_RIOEN\r
-* (RW) HMCBSP_PCR_XIOEN\r
-*\r
-\******************************************************************************/\r
- #define HMCBSP_PCR0_ADDR (HMCBSP_BASE0_ADDR+0x0024)\r
- #define HMCBSP_PCR1_ADDR (HMCBSP_BASE1_ADDR+0x0024)\r
- #define HMCBSP_PCR0 REG32(HMCBSP_PCR0_ADDR)\r
- #define HMCBSP_PCR1 REG32(HMCBSP_PCR1_ADDR)\r
-\r
-#if (HMCBSP_PORT_CNT==3)\r
- #define HMCBSP_PCR2_ADDR (HMCBSP_BASE2_ADDR+0x0024)\r
- #define HMCBSP_PCR2 REG32(HMCBSP_PCR2_ADDR)\r
-#endif\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_PCR_CLKRP\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_PCR_CLKRP_MASK (0x00000001)\r
- #define HMCBSP_PCR_CLKRP_SHIFT (0x00000000)\r
-\r
- #define HMCBSP_PCR_CLKRP_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_PCR_CLKRP)\r
-\r
- #define HMCBSP_PCR_CLKRP_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_PCR_CLKRP,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_PCR_CLKXP\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_PCR_CLKXP_MASK (0x00000002)\r
- #define HMCBSP_PCR_CLKXP_SHIFT (0x00000001)\r
-\r
- #define HMCBSP_PCR_CLKXP_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_PCR_CLKXP)\r
-\r
- #define HMCBSP_PCR_CLKXP_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_PCR_CLKXP,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_PCR_FSRP\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_PCR_FSRP_MASK (0x00000004)\r
- #define HMCBSP_PCR_FSRP_SHIFT (0x00000002)\r
-\r
- #define HMCBSP_PCR_FSRP_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_PCR_FSRP)\r
-\r
- #define HMCBSP_PCR_FSRP_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_PCR_FSRP,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_PCR_FSXP\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_PCR_FSXP_MASK (0x00000008)\r
- #define HMCBSP_PCR_FSXP_SHIFT (0x00000003)\r
-\r
- #define HMCBSP_PCR_FSXP_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_PCR_FSXP)\r
-\r
- #define HMCBSP_PCR_FSXP_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_PCR_FSXP,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (R) HMCBSP_PCR_DTSTAT\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_PCR_DRSTAT_MASK (0x00000010)\r
- #define HMCBSP_PCR_DRSTAT_SHIFT (0x00000004)\r
-\r
- #define HMCBSP_PCR_DRSTAT_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_PCR_DRSTAT)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_PCR_DXSTAT\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_PCR_DXSTAT_MASK (0x00000020)\r
- #define HMCBSP_PCR_DXSTAT_SHIFT (0x00000005)\r
-\r
- #define HMCBSP_PCR_DXSTAT_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_PCR_DXSTAT)\r
-\r
- #define HMCBSP_PCR_DXSTAT_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_PCR_DXSTAT,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_PCR_CLKSSTAT\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_PCR_CLKSSTAT_MASK (0x00000040)\r
- #define HMCBSP_PCR_CLKSSTAT_SHIFT (0x00000006)\r
-\r
- #define HMCBSP_PCR_CLKSSTAT_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_PCR_CLKSSTAT)\r
-\r
- #define HMCBSP_PCR_CLKSSTAT_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_PCR_CLKSSTAT,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_PCR_CLKRM\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_PCR_CLKRM_MASK (0x00000100)\r
- #define HMCBSP_PCR_CLKRM_SHIFT (0x00000008)\r
-\r
- #define HMCBSP_PCR_CLKRM_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_PCR_CLKRM)\r
-\r
- #define HMCBSP_PCR_CLKRM_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_PCR_CLKRM,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_PCR_CLKXM\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_PCR_CLKXM_MASK (0x00000200)\r
- #define HMCBSP_PCR_CLKXM_SHIFT (0x00000009)\r
-\r
- #define HMCBSP_PCR_CLKXM_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_PCR_CLKXM)\r
-\r
- #define HMCBSP_PCR_CLKXM_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_PCR_CLKXM,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_PCR_FSRM\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_PCR_FSRM_MASK (0x00000400)\r
- #define HMCBSP_PCR_FSRM_SHIFT (0x0000000A)\r
-\r
- #define HMCBSP_PCR_FSRM_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_PCR_FSRM)\r
-\r
- #define HMCBSP_PCR_FSRM_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_PCR_FSRM,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_PCR_FSXM\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_PCR_FSXM_MASK (0x00000800)\r
- #define HMCBSP_PCR_FSXM_SHIFT (0x0000000B)\r
-\r
- #define HMCBSP_PCR_FSXM_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_PCR_FSXM)\r
-\r
- #define HMCBSP_PCR_FSXM_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_PCR_FSXM,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_PCR_RIOEN\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_PCR_RIOEN_MASK (0x00001000)\r
- #define HMCBSP_PCR_RIOEN_SHIFT (0x0000000C)\r
-\r
- #define HMCBSP_PCR_RIOEN_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_PCR_RIOEN)\r
-\r
- #define HMCBSP_PCR_RIOEN_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_PCR_RIOEN,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_PCR_XIOEN\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_PCR_XIOEN_MASK (0x00002000)\r
- #define HMCBSP_PCR_XIOEN_SHIFT (0x0000000D)\r
-\r
- #define HMCBSP_PCR_XIOEN_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HMCBSP_PCR_XIOEN)\r
-\r
- #define HMCBSP_PCR_XIOEN_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HMCBSP_PCR_XIOEN,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HMCBSP_PCR\r
-\*----------------------------------------------------------------------------*/\r
- #define HMCBSP_PCR_GET(RegAddr) HREG32_GET(RegAddr)\r
- #define HMCBSP_PCR_SET(RegAddr,Val) HREG32_SET(RegAddr,Val)\r
-\r
- #define HMCBSP_PCR_CFG(RegAddr,clkrp,clkxp,fsrp,fsxp,dxstat,clksstat,clkrm,\\r
- clkxm,fsrm,fsxm,rioen,xioen) REG32(RegAddr)=(UINT32)(\\r
- HFIELD_SHIFT(HMCBSP_PCR_CLKRP , clkrp )|\\r
- HFIELD_SHIFT(HMCBSP_PCR_CLKXP , clkxp )|\\r
- HFIELD_SHIFT(HMCBSP_PCR_FSRP , fsrp )|\\r
- HFIELD_SHIFT(HMCBSP_PCR_FSXP , fsxp )|\\r
- HFIELD_SHIFT(HMCBSP_PCR_DXSTAT , dxstat )|\\r
- HFIELD_SHIFT(HMCBSP_PCR_CLKSSTAT, clksstat)|\\r
- HFIELD_SHIFT(HMCBSP_PCR_CLKRM , clkrm )|\\r
- HFIELD_SHIFT(HMCBSP_PCR_CLKXM , clkxm )|\\r
- HFIELD_SHIFT(HMCBSP_PCR_FSRM , fsrm )|\\r
- HFIELD_SHIFT(HMCBSP_PCR_FSXM , fsxm )|\\r
- HFIELD_SHIFT(HMCBSP_PCR_RIOEN , rioen )|\\r
- HFIELD_SHIFT(HMCBSP_PCR_XIOEN , xioen ) \\r
- )\r
-\r
-/******************************************************************************/\r
-\r
-#endif /* MCBSP_SUPPORT */\r
-#endif /* _MCBSPHAL_H_ */\r
-/******************************************************************************\\r
-* End of mcbsphal.h\r
-\******************************************************************************/\r
-\r
-/******************************************************************************\\r
-* Copyright (C) 1999-2000 Texas Instruments Incorporated.\r
-* All Rights Reserved\r
-*------------------------------------------------------------------------------\r
-* FILENAME...... pwrhal.h\r
-* DATE CREATED.. 11/11/1999 \r
-* LAST MODIFIED. 03/08/2000\r
-*\r
-*------------------------------------------------------------------------------\r
-* DESCRIPTION: (HAL interface file for the PWR module)\r
-*\r
-* Registers Covered:\r
-* (RW) HPWR_PDCTL - power down control register (1)\r
-\r
-* (1) only on CHIP_6202, CHIP_6203\r
-*\r
-\******************************************************************************/\r
-#ifndef _PWRHAL_H_\r
-#define _PWRHAL_H_\r
-\r
-#if (PWR_SUPPORT)\r
- #define HPWR_BASE_ADDR (HCHIP_PERBASE_ADDR+0x001C0000)\r
-\r
-/******************************************************************************\\r
-* HPWR_PDCTL - power down control register (1)\r
-*\r
-* Fields:\r
-* (RW) HPWR_PDCTL_DMA\r
-* (RW) HPWR_PDCTL_EMIF\r
-* (RW) HPWR_PDCTL_MCBSP0\r
-* (RW) HPWR_PDCTL_MCBSP1\r
-* (RW) HPWR_PDCTL_MCBSP2\r
-*\r
-\******************************************************************************/\r
-#if (CHIP_6202)\r
- #define HPWR_PDCTL_ADDR (HPWR_BASE_ADDR+0x0200)\r
- #define HPWR_PDCTL REG32(HPWR_PDCTL_ADDR)\r
-#else\r
- #define HPWR_PDCTL_ADDR (HCHIP_NULL_ADDR)\r
- #define HPWR_PDCTL REG32(HPWR_PDCTL_ADDR)\r
-#endif\r
- \r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HPWR_PDCTL_DMA\r
-\*----------------------------------------------------------------------------*/\r
- #define HPWR_PDCTL_DMA_MASK (0x00000001)\r
- #define HPWR_PDCTL_DMA_SHIFT (0x00000000)\r
-\r
- #define HPWR_PDCTL_DMA_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HPWR_PDCTL_DMA)\r
-\r
- #define HPWR_PDCTL_DMA_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HPWR_PDCTL_DMA,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HPWR_PDCTL_EMIF\r
-\*----------------------------------------------------------------------------*/\r
- #define HPWR_PDCTL_EMIF_MASK (0x00000002)\r
- #define HPWR_PDCTL_EMIF_SHIFT (0x00000001)\r
-\r
- #define HPWR_PDCTL_EMIF_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HPWR_PDCTL_EMIF)\r
-\r
- #define HPWR_PDCTL_EMIF_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HPWR_PDCTL_EMIF,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HPWR_PDCTL_MCBSP0\r
-\*----------------------------------------------------------------------------*/\r
- #define HPWR_PDCTL_MCBSP0_MASK (0x00000004)\r
- #define HPWR_PDCTL_MCBSP0_SHIFT (0x00000002)\r
- \r
- #define HPWR_PDCTL_MCBSP0_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HPWR_PDCTL_MCBSP0)\r
-\r
- #define HPWR_PDCTL_MCBSP0_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HPWR_PDCTL_MCBSP0,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HPWR_PDCTL_MCBSP1\r
-\*----------------------------------------------------------------------------*/\r
- #define HPWR_PDCTL_MCBSP1_MASK (0x00000008)\r
- #define HPWR_PDCTL_MCBSP1_SHIFT (0x00000003)\r
- \r
- #define HPWR_PDCTL_MCBSP1_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HPWR_PDCTL_MCBSP1)\r
-\r
- #define HPWR_PDCTL_MCBSP1_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HPWR_PDCTL_MCBSP1,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HPWR_PDCTL_MCBSP2\r
-\*----------------------------------------------------------------------------*/\r
- #define HPWR_PDCTL_MCBSP2_MASK (0x00000010)\r
- #define HPWR_PDCTL_MCBSP2_SHIFT (0x00000004)\r
- \r
- #define HPWR_PDCTL_MCBSP2_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HPWR_PDCTL_MCBSP2)\r
-\r
- #define HPWR_PDCTL_MCBSP2_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HPWR_PDCTL_MCBSP2,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) HPWR_PDCTL\r
-\*----------------------------------------------------------------------------*/\r
- #define HPWR_PDCTL_GET(RegAddr) HREG32_GET(RegAddr)\r
- #define HPWR_PDCTL_SET(RegAddr,Val) HREG32_SET(RegAddr,Val)\r
- \r
- #define HPWR_PDCTL_CFG(RegAddr,dma,emif,mcbsp0,mcbsp1,mcbsp2)\\r
- REG32(RegAddr) = (\\r
- HFIELD_SHIFT(HPWR_PDCTL_DMA,dma)|\\r
- HFIELD_SHIFT(HPWR_PDCTL_EMIF,emif)|\\r
- HFIELD_SHIFT(HPWR_PDCTL_MCBSP0,mcbsp0)|\\r
- HFIELD_SHIFT(HPWR_PDCTL_MCBSP1,mcbsp1)|\\r
- HFIELD_SHIFT(HPWR_PDCTL_MCBSP2,mcbsp2)\\r
- )\r
-\r
-/*----------------------------------------------------------------------------*/\r
-\r
-#endif /* PWR_SUPPORT */\r
-#endif /* _PWRHAL_H_ */\r
-/******************************************************************************\\r
-* End of pwrhal.h\r
-\******************************************************************************/\r
-\r
-/******************************************************************************\\r
-* Copyright (C) 1999-2000 Texas Instruments Incorporated.\r
-* All Rights Reserved\r
-*------------------------------------------------------------------------------\r
-* FILENAME...... timerhal.h\r
-* DATE CREATED.. 06/20/1999 \r
-* LAST MODIFIED. 03/08/2000\r
-* \r
-*------------------------------------------------------------------------------\r
-* DESCRIPTION: (HAL interface file for the TIMER module)\r
-*\r
-* Registers Covered:\r
-* (RW) HTIMER_CTL0 - timer 0 control register\r
-* (RW) HTIMER_CTL1 - timer 1 control register\r
-* (RW) HTIMER_PRD0 - timer 0 period register\r
-* (RW) HTIMER_PRD1 - timer 1 perid register\r
-* (RW) HTIMER_CNT0 - timer 0 count register\r
-* (RW) HTIMER_CNT1 - timer 1 count register\r
-*\r
-\******************************************************************************/\r
-#ifndef _TIMERHAL_H_\r
-#define _TIMERHAL_H_\r
-\r
-#if (TIMER_SUPPORT)\r
-/*============================================================================*\\r
-* misc declarations\r
-\*============================================================================*/\r
-#define HTIMER_BASE0_ADDR (HCHIP_PERBASE_ADDR+0x00140000)\r
-#define HTIMER_BASE1_ADDR (HCHIP_PERBASE_ADDR+0x00180000)\r
-\r
-#define HTIMER_DEVICE_CNT (2)\r
-\r
-/******************************************************************************\\r
-* HTIMER_CTL0 - timer 0 control register\r
-* HTIMER_CTL1 - timer 1 control register\r
-*\r
-* Fields:\r
-* (RW) HTIMER_CTL_FUNC\r
-* (RW) HTIMER_CTL_INVOUT\r
-* (RW) HTIMER_CTL_DATOUT\r
-* (RW) HTIMER_CTL_DATIN\r
-* (RW) HTIMER_CTL_PWID\r
-* (RW) HTIMER_CTL_GO\r
-* (RW) HTIMER_CTL_HLD\r
-* (RW) HTIMER_CTL_CP\r
-* (RW) HTIMER_CTL_CLKSRC\r
-* (RW) HTIMER_CTL_INVINP\r
-* (R) HTIMER_CTL_TSTAT\r
-*\r
-\******************************************************************************/\r
- #define HTIMER_CTL0_ADDR (HTIMER_BASE0_ADDR+0x0000)\r
- #define HTIMER_CTL1_ADDR (HTIMER_BASE1_ADDR+0x0000)\r
-\r
- #define HTIMER_CTL0 REG32(HTIMER_CTL0_ADDR)\r
- #define HTIMER_CTL1 REG32(HTIMER_CTL1_ADDR)\r
- \r
-/*----------------------------------------------------------------------------*\\r
-* (RW) TIMER_CTL_FUNC\r
-\*----------------------------------------------------------------------------*/\r
- #define HTIMER_CTL_FUNC_MASK (0x00000001)\r
- #define HTIMER_CTL_FUNC_SHIFT (0x00000000)\r
- \r
- #define HTIMER_CTL_FUNC_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HTIMER_CTL_FUNC)\r
-\r
- #define HTIMER_CTL_FUNC_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HTIMER_CTL_FUNC,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) TIMER_CTL_INVOUT\r
-\*----------------------------------------------------------------------------*/\r
- #define HTIMER_CTL_INVOUT_MASK (0x00000002)\r
- #define HTIMER_CTL_INVOUT_SHIFT (0x00000001)\r
-\r
- #define HTIMER_CTL_INVOUT_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HTIMER_CTL_INVOUT)\r
-\r
- #define HTIMER_CTL_INVOUT_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HTIMER_CTL_INVOUT,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) TIMER_CTL_DATOUT\r
-\*----------------------------------------------------------------------------*/\r
- #define HTIMER_CTL_DATOUT_MASK (0x00000004)\r
- #define HTIMER_CTL_DATOUT_SHIFT (0x00000002)\r
-\r
- #define HTIMER_CTL_DATOUT_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HTIMER_CTL_DATOUT)\r
-\r
- #define HTIMER_CTL_DATOUT_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HTIMER_CTL_DATOUT,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) TIMER_CTL_DATIN\r
-\*----------------------------------------------------------------------------*/\r
- #define HTIMER_CTL_DATIN_MASK (0x00000008)\r
- #define HTIMER_CTL_DATIN_SHIFT (0x00000003)\r
-\r
- #define HTIMER_CTL_DATIN_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HTIMER_CTL_DATIN)\r
-\r
- #define HTIMER_CTL_DATIN_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HTIMER_CTL_DATIN,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) TIMER_CTL_PWID\r
-\*----------------------------------------------------------------------------*/\r
- #define HTIMER_CTL_PWID_MASK (0x00000010)\r
- #define HTIMER_CTL_PWID_SHIFT (0x00000004)\r
-\r
- #define HTIMER_CTL_PWID_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HTIMER_CTL_PWID)\r
-\r
- #define HTIMER_CTL_PWID_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HTIMER_CTL_PWID,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) TIMER_CTL_GO\r
-\*----------------------------------------------------------------------------*/\r
- #define HTIMER_CTL_GO_MASK (0x00000040)\r
- #define HTIMER_CTL_GO_SHIFT (0x00000006)\r
-\r
- #define HTIMER_CTL_GO_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HTIMER_CTL_GO)\r
-\r
- #define HTIMER_CTL_GO_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HTIMER_CTL_GO,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) TIMER_CTL_HLD\r
-\*----------------------------------------------------------------------------*/\r
- #define HTIMER_CTL_HLD_MASK (0x00000080)\r
- #define HTIMER_CTL_HLD_SHIFT (0x00000007)\r
-\r
- #define HTIMER_CTL_HLD_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HTIMER_CTL_HLD)\r
-\r
- #define HTIMER_CTL_HLD_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HTIMER_CTL_HLD,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) TIMER_CTL_CP\r
-\*----------------------------------------------------------------------------*/\r
- #define HTIMER_CTL_CP_MASK (0x00000100)\r
- #define HTIMER_CTL_CP_SHIFT (0x00000008)\r
-\r
- #define HTIMER_CTL_CP_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HTIMER_CTL_CP)\r
-\r
- #define HTIMER_CTL_CP_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HTIMER_CTL_CP,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) TIMER_CTL_CLKSRC\r
-\*----------------------------------------------------------------------------*/\r
- #define HTIMER_CTL_CLKSRC_MASK (0x00000200)\r
- #define HTIMER_CTL_CLKSRC_SHIFT (0x00000009)\r
-\r
- #define HTIMER_CTL_CLKSRC_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HTIMER_CTL_CLKSRC)\r
-\r
- #define HTIMER_CTL_CLKSRC_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HTIMER_CTL_CLKSRC,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) TIMER_CTL_INVINP\r
-\*----------------------------------------------------------------------------*/\r
- #define HTIMER_CTL_INVINP_MASK (0x00000400)\r
- #define HTIMER_CTL_INVINP_SHIFT (0x0000000A)\r
-\r
- #define HTIMER_CTL_INVINP_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HTIMER_CTL_INVINP)\r
-\r
- #define HTIMER_CTL_INVINP_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HTIMER_CTL_INVINP,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (R) TIMER_CTL_TSTAT\r
-\*----------------------------------------------------------------------------*/\r
- #define HTIMER_CTL_TSTAT_MASK (0x00000800)\r
- #define HTIMER_CTL_TSTAT_SHIFT (0x0000000B)\r
-\r
- #define HTIMER_CTL_TSTAT_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HTIMER_CTL_TSTAT)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) TIMER_CTL\r
-\*----------------------------------------------------------------------------*/\r
- #define HTIMER_CTL_GET(RegAddr) HREG32_GET(RegAddr)\r
-\r
- #define HTIMER_CTL_SET(RegAddr,Val) HREG32_SET(RegAddr,Val)\r
- \r
- #define HTIMER_CTL_CFG(RegAddr,func,invout,datout,datin,pwid,go,hld,cp,\\r
- clksrc,invinp) REG32(RegAddr) = (\\r
- HFIELD_SHIFT(HTIMER_CTL_FUNC, func) |\\r
- HFIELD_SHIFT(HTIMER_CTL_DATOUT, datout) |\\r
- HFIELD_SHIFT(HTIMER_CTL_DATIN, datin) |\\r
- HFIELD_SHIFT(HTIMER_CTL_GO, go) |\\r
- HFIELD_SHIFT(HTIMER_CTL_HLD, hld) |\\r
- HFIELD_SHIFT(HTIMER_CTL_CP, cp) |\\r
- HFIELD_SHIFT(HTIMER_CTL_PWID, pwid) |\\r
- HFIELD_SHIFT(HTIMER_CTL_CLKSRC, clksrc) |\\r
- HFIELD_SHIFT(HTIMER_CTL_INVINP, invinp) |\\r
- HFIELD_SHIFT(HTIMER_CTL_INVOUT, invout) \\r
- )\r
-\r
-/******************************************************************************\\r
-* HTIMER_PRD0 - timer 0 period register\r
-* HTIMER_PRD1 - timer 1 period register\r
-*\r
-* Fields:\r
-* (RW) PRD\r
-*\r
-\******************************************************************************/\r
- #define HTIMER_PRD0_ADDR (HTIMER_BASE0_ADDR+0x0004)\r
- #define HTIMER_PRD1_ADDR (HTIMER_BASE1_ADDR+0x0004)\r
-\r
- #define HTIMER_PRD0 REG32(HTIMER_PRD0_ADDR)\r
- #define HTIMER_PRD1 REG32(HTIMER_PRD1_ADDR)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) TIMER_PRD_PRD\r
-\*----------------------------------------------------------------------------*/\r
- #define HTIMER_PRD_PRD_MASK (0xFFFFFFFF)\r
- #define HTIMER_PRD_PRD_SHIFT (0x00000000)\r
- \r
- #define HTIMER_PRD_PRD_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HTIMER_PRD_PRD)\r
-\r
- #define HTIMER_PRD_PRD_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HTIMER_PRD_PRD,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) TIMER_PRD\r
-\*----------------------------------------------------------------------------*/\r
- #define HTIMER_PRD_GET(RegAddr) HREG32_GET(RegAddr)\r
-\r
- #define HTIMER_PRD_SET(RegAddr,Val) HREG32_SET(RegAddr,Val)\r
- \r
- #define HTIMER_PRD_CFG(RegAddr,Prd) REG32(RegAddr) = (UINT32)( \\r
- HFIELD_SHIFT(HTIMER_PRD_RRD,prd) \\r
- )\r
-\r
-/******************************************************************************\\r
-* HTIMER_CNT0 - timer 0 count register\r
-* HTIMER_CNT1 - timer 1 count register\r
-*\r
-* Fields:\r
-* (RW) CNT\r
-*\r
-\******************************************************************************/\r
- #define HTIMER_CNT0_ADDR (HTIMER_BASE0_ADDR+0x0008)\r
- #define HTIMER_CNT1_ADDR (HTIMER_BASE1_ADDR+0x0008)\r
-\r
- #define HTIMER_CNT0 REG32(HTIMER_CNT0_ADDR)\r
- #define HTIMER_CNT1 REG32(HTIMER_CNT1_ADDR)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) TIMER_CNT_CNT\r
-\*----------------------------------------------------------------------------*/\r
- #define HTIMER_CNT_CNT_MASK (0xFFFFFFFF)\r
- #define HTIMER_CNT_CNT_SHIFT (0x00000000)\r
-\r
- #define HTIMER_CNT_CNT_GET(RegAddr) \\r
- HFIELD_GET(RegAddr,HTIMER_CNT_CNT)\r
-\r
- #define HTIMER_CNT_CNT_SET(RegAddr,Val) \\r
- HFIELD_SET(RegAddr,HTIMER_CNT_CNT,Val)\r
-\r
-/*----------------------------------------------------------------------------*\\r
-* (RW) TIMER_CNT\r
-\*----------------------------------------------------------------------------*/\r
- #define HTIMER_CNT_GET(RegAddr) HREG32_GET(RegAddr)\r
-\r
- #define HTIMER_CNT_SET(RegAddr,Val) HREG32_SET(RegAddr,Val)\r
- \r
- #define HTIMER_CNT_CFG(RegAddr,Cnt) REG32(RegAddr) = (UINT32)( \\r
- HFIELD_SHIFT(HTIMER_CNT_CNT,cnt) \\r
- )\r
-\r
-/*----------------------------------------------------------------------------*/\r
-\r
-#endif /* TIMER_SUPPORT */\r
-#endif /* _TIMERHAL_H_ */\r
-/******************************************************************************\\r
-* End of timerhal.h\r
-\******************************************************************************/\r
-\r
-\r
-\r
-#endif /* _CSL_LEGACYHAL_H_ */\r
-/******************************************************************************\\r
-* End of csl_legacyhal.h\r
-\******************************************************************************/\r
-\r