diff --git a/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_pll.h b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_pll.h
+++ /dev/null
@@ -1,376 +0,0 @@
-/******************************************************************************\\r
-* Step 1. Copyright (C) 2001 Texas Instruments Incorporated.\r
-* All Rights Reserved\r
-*------------------------------------------------------------------------------\r
-* FILENAME...... csl_pll.h\r
-* DATE CREATED.. 10/29/2001 \r
-* LAST MODIFIED. 11/30/2001\r
-* 11/30/2003 Modified PLL_init() sequence to fix the PLL \r
-* initialization problem\r
-* 4/13/2005 Modified the sequence of the plldiv1 and plldiv2 \r
-* according to the data sheet in PLL_config() and\r
-* PLL_configArgs().\r
-\******************************************************************************/\r
-\r
-/******************************************************************************\\r
-* Step 2. Private Macros - Include files - PLL_SUPPORT\r
-\******************************************************************************/\r
-#ifndef _CSL_PLL_H_\r
-#define _CSL_PLL_H_\r
-\r
-#include <csl_stdinc.h>\r
-#include <csl_chip.h>\r
-#include <csl_pllhal.h>\r
-\r
-#if (PLL_SUPPORT)\r
-/******************************************************************************\\r
-* Step 3. scope and inline control macros \r
-\******************************************************************************/\r
-#ifdef __cplusplus\r
-#define CSLAPI extern "C" far \r
-#else\r
-#define CSLAPI extern far\r
-#endif\r
-\r
-#undef USEDEFS\r
-#undef IDECL\r
-#undef IDEF\r
-\r
-#ifdef _PLL_MOD_\r
- #define IDECL CSLAPI\r
- #define USEDEFS\r
- #define IDEF\r
-#else\r
- #ifdef _INLINE\r
- #define IDECL static inline\r
- #define USEDEFS\r
- #define IDEF static inline\r
- #else\r
- #define IDECL CSLAPI\r
- #endif\r
-#endif\r
-\r
-/******************************************************************************\\r
-* Step 4. global macro declarations\r
-\******************************************************************************/\r
-#define PLL_DIV0 0\r
-#define PLL_DIV1 1\r
-#define PLL_DIV2 2\r
-#define PLL_DIV3 3\r
-\r
-\r
-/*****************************************************************************\\r
-* Step 5. global typedef declarations\r
-* Example : Config structure \r
-* typedef struct {\r
-* Uint32 rg1;\r
-* Uint32 rg2;\r
-* } PLL_Config;\r
-\******************************************************************************/\r
-typedef struct{\r
- Uint32 pllcsr;\r
- Uint32 pllm;\r
- Uint32 plldiv0;\r
- Uint32 plldiv1;\r
- Uint32 plldiv2;\r
- Uint32 plldiv3;\r
- Uint32 oscdiv1;\r
-}PLL_Config;\r
- \r
- \r
-typedef struct {\r
- Uint32 mdiv;\r
- Uint32 d0ratio;\r
- Uint32 d1ratio;\r
- Uint32 d2ratio;\r
- Uint32 d3ratio;\r
- Uint32 od1ratio;\r
- }PLL_Init; \r
-\r
-/******************************************************************************\\r
-* Step 6. global variable declarations\r
-\******************************************************************************/\r
-/* private vars */\r
-extern far Uint32 _PLL_divAddr[4];\r
-\r
-\r
-/******************************************************************************\\r
-* Step 7. global function declarations\r
-\******************************************************************************/\r
-\r
-/* Private functions (If applicable)*/\r
-\r
-static void plldelay(Uint32 count);\r
-\r
-/* API functions (Non-Inline function : Source file) */\r
-CSLAPI void PLL_wait100();\r
-CSLAPI Uint32 PLL_wait1();\r
-\r
-/******************************************************************************\\r
-* Step 8. inline function declarations ( IDECL keyword)\r
-\******************************************************************************/\r
-IDECL void PLL_config(PLL_Config *config);\r
-IDECL void PLL_configArgs(Uint32 pllcsr, Uint32 pllm, Uint32 plldiv0, Uint32 plldiv1, Uint32 plldiv2, Uint32 plldiv3,Uint32 oscdiv1);\r
-IDECL void PLL_getConfig(PLL_Config *config);\r
-\r
-IDECL void PLL_init(PLL_Init *init);\r
-\r
-IDECL void PLL_pwrdwn();\r
-IDECL void PLL_operational();\r
-IDECL void PLL_enable();\r
-IDECL void PLL_bypass();\r
-IDECL void PLL_reset();\r
-IDECL void PLL_deassert();\r
-\r
-\r
-IDECL Uint32 PLL_clkTest();\r
-\r
-IDECL void PLL_enablePllDiv(Uint32 divId);\r
-IDECL void PLL_disablePllDiv(Uint32 divId);\r
-\r
-IDECL void PLL_enableOscDiv();\r
-IDECL void PLL_disableOscDiv();\r
-\r
-IDECL void PLL_setMultiplier(Uint32 val);\r
-IDECL void PLL_setPllRatio(Uint32 divId,Uint32 val);\r
-IDECL void PLL_setOscRatio(Uint32 val);\r
-\r
-IDECL Uint32 PLL_getMultiplier();\r
-IDECL Uint32 PLL_getPllRatio(Uint32 divnum);\r
-IDECL Uint32 PLL_getOscRatio();\r
-\r
-/******************************************************************************\\r
-* Step 9. inline function definitions ( #if USEDEF - IDEF keywords)\r
-\******************************************************************************/\r
-\r
-#ifdef USEDEFS\r
-/*----------------------------------------------------------------------------*/\r
-IDEF void PLL_pwrdwn(){ \r
- PLL_FSETS(PLLCSR,PLLEN,BYPASS); /* Bypass mode PLLEN = 0 */ \r
- PLL_FSETS(PLLCSR,PLLPWRDN,YES); /* PwrDwn mode */\r
-\r
-}\r
-/*----------------------------------------------------------------------------*/\r
-IDEF void PLL_operational(){ \r
- PLL_FSETS(PLLCSR,PLLPWRDN,NO); /* Operational mode */\r
- PLL_FSETS(PLLDIV0,D0EN,ENABLE); /* Enable D0 path */\r
- PLL_FSETS(PLLCSR,PLLEN,ENABLE); /* Enable PLLEN = 1 */ \r
-}\r
-/*----------------------------------------------------------------------------*/\r
-IDEF void PLL_enable(){\r
- PLL_FSETS(PLLCSR,PLLEN,ENABLE); /* Bypass mode PLLEN = 1 */ \r
-}\r
-/*----------------------------------------------------------------------------*/\r
-IDEF void PLL_bypass(){\r
- PLL_FSETS(PLLCSR,PLLEN,BYPASS); /* Bypass mode PLLEN = 0 */ \r
-}\r
-/*----------------------------------------------------------------------------*/\r
-IDEF Uint32 PLL_clkTest(){ \r
- return(PLL_FGET(PLLCSR,STABLE)); \r
-}\r
-/*----------------------------------------------------------------------------*/\r
-IDEF void PLL_reset(){ \r
- PLL_FSETS(PLLCSR,PLLRST,1); /* reset mode */\r
-}\r
-/*----------------------------------------------------------------------------*/\r
-IDEF void PLL_deassert(){ \r
- PLL_FSETS(PLLCSR,PLLRST,0); /* deassert PLL */ \r
-}\r
-/*----------------------------------------------------------------------------*/\r
-IDEF void PLL_enablePllDiv(Uint32 divId){\r
- (*(volatile Uint32*) _PLL_divAddr[divId]) |=(0x00008000u);\r
-}\r
-/*----------------------------------------------------------------------------*/\r
-IDEF void PLL_disablePllDiv(Uint32 divId){\r
- (*(volatile Uint32*) _PLL_divAddr[divId]) &=~(0x00008000u);\r
-}\r
-/*----------------------------------------------------------------------------*/\r
-IDEF void PLL_enableOscDiv(){\r
- PLL_FSET(OSCDIV1,OD1EN,1);\r
-}\r
-/*----------------------------------------------------------------------------*/\r
-IDEF void PLL_disableOscDiv(){\r
- PLL_FSET(OSCDIV1,OD1EN,0);\r
-}\r
-/*----------------------------------------------------------------------------*/\r
-IDEF void PLL_setPllRatio(Uint32 divId, Uint32 val){\r
- Uint32 tmp= ((*(volatile Uint32*) _PLL_divAddr[divId]) & 0xFFFFFFE0u);\r
- (*(volatile Uint32*) _PLL_divAddr[divId]) =(val | tmp );\r
-}\r
-/*----------------------------------------------------------------------------*/\r
-IDEF void PLL_setOscRatio(Uint32 val){\r
- PLL_FSET(OSCDIV1,RATIO,val);\r
-}\r
-/*----------------------------------------------------------------------------*/\r
-IDEF void PLL_setMultiplier(Uint32 val){\r
- PLL_FSET(PLLM,PLLM,val);\r
-}\r
-/*----------------------------------------------------------------------------*/\r
-IDEF Uint32 PLL_getPllRatio(Uint32 divId){\r
- return (Uint32)((*(volatile Uint32*) _PLL_divAddr[divId]) & 0x0000001Fu);\r
-}\r
-/*----------------------------------------------------------------------------*/\r
-IDEF Uint32 PLL_getOscRatio(){\r
- return(PLL_FGET(OSCDIV1,RATIO));\r
-}\r
-/*----------------------------------------------------------------------------*/\r
-IDEF Uint32 PLL_getMultiplier(){\r
- return(PLL_FGET(PLLM,PLLM));\r
-}\r
-\r
-/*----------------------------------------------------------------------------*/\r
-IDEF void PLL_init(PLL_Init *init) {\r
-\r
- Uint32 gie ;\r
- gie = IRQ_globalDisable();\r
-\r
- PLL_FSETS(PLLCSR,PLLEN,BYPASS); /* Bypass mode PLLEN = 0 */ \r
-\r
- plldelay(20);\r
-\r
- PLL_FSETS(PLLCSR,PLLRST,1); /* reset mode */\r
- \r
- plldelay(20);\r
-\r
- // Set main multiplier/divisor \r
- PLL_RSET(PLLM,init->mdiv);\r
- PLL_RSET(PLLDIV0, PLL_PLLDIV0_RMK(0,init->d0ratio));\r
- PLL_RSET(OSCDIV1,PLL_OSCDIV1_RMK(0,init->od1ratio)); \r
- \r
- // Set DSP clock \r
- PLL_RSET(PLLDIV1,PLL_PLLDIV1_RMK(1,init->d1ratio));\r
- \r
- // Set EMIF clock \r
- PLL_RSET(PLLDIV3,PLL_PLLDIV3_RMK(0,init->d3ratio));\r
-\r
- plldelay(20);\r
-\r
- // Take PLL out of reset\r
- PLL_FSETS(PLLCSR,PLLRST,0);\r
- plldelay(1500);\r
-\r
- // Enable PLL\r
- PLL_FSETS(PLLCSR,PLLEN,ENABLE);\r
- plldelay(20);\r
- \r
- IRQ_globalRestore(gie);\r
-}\r
- \r
-\r
-/*----------------------------------------------------------------------------*/\r
-IDEF void PLL_config(PLL_Config *config) {\r
- Uint32 gie;\r
- volatile Uint32 *base;\r
- register Uint32 x0,x1,x2,x3,x4,x5,x6;\r
- \r
- gie = IRQ_globalDisable();\r
-\r
- x0 = config->pllcsr;\r
- x1 = config->pllm;\r
- x2 = config->plldiv0;\r
- x3 = config->plldiv1;\r
- x4 = config->plldiv2;\r
- x5 = config->plldiv3;\r
- x6 = config->oscdiv1;\r
-\r
-\r
- base = (volatile Uint32 *)(_PLL_BASE_ADDR);\r
-\r
- base[_PLL_PLLM_OFFSET] = x1;\r
- base[_PLL_PLLDIV0_OFFSET] = x2;\r
- if ( base[_PLL_PLLDIV1_OFFSET] > x3 ) {\r
- base[_PLL_PLLDIV1_OFFSET] = x3;\r
- base[_PLL_PLLDIV2_OFFSET] = x4;\r
- }\r
- else {\r
- base[_PLL_PLLDIV2_OFFSET] = x4;\r
- base[_PLL_PLLDIV1_OFFSET] = x3;\r
- }\r
- \r
- base[_PLL_PLLDIV3_OFFSET] = x5;\r
- base[_PLL_OSCDIV1_OFFSET] = x6;\r
- base[_PLL_PLLCSR_OFFSET] = x0;\r
-\r
- IRQ_globalRestore(gie);\r
- \r
-}\r
-\r
-/*----------------------------------------------------------------------------*/\r
-IDEF void PLL_configArgs(Uint32 pllcsr, Uint32 pllm, Uint32 plldiv0, Uint32 plldiv1, Uint32 plldiv2, Uint32 plldiv3,Uint32 oscdiv1){\r
-\r
- Uint32 gie;\r
- volatile Uint32 *base;\r
- gie = IRQ_globalDisable();\r
-\r
- base = (volatile Uint32 *)(_PLL_BASE_ADDR);\r
-\r
- base[_PLL_PLLM_OFFSET] = pllm;\r
- base[_PLL_PLLDIV0_OFFSET] = plldiv0;\r
- if ( base[_PLL_PLLDIV1_OFFSET] > plldiv1) { \r
- base[_PLL_PLLDIV1_OFFSET] = plldiv1;\r
- base[_PLL_PLLDIV2_OFFSET] = plldiv2;\r
- }\r
- else {\r
- base[_PLL_PLLDIV2_OFFSET] = plldiv2;\r
- base[_PLL_PLLDIV1_OFFSET] = plldiv1;\r
- }\r
- base[_PLL_PLLDIV3_OFFSET] = plldiv3;\r
- base[_PLL_OSCDIV1_OFFSET] = oscdiv1;\r
- base[_PLL_PLLCSR_OFFSET] = pllcsr;\r
-\r
- IRQ_globalRestore(gie);\r
-}\r
-\r
-\r
-/*----------------------------------------------------------------------------*/\r
-IDEF void PLL_getConfig(PLL_Config *config) {\r
- Uint32 gie;\r
- volatile Uint32 *base;\r
- register Uint32 x0,x1,x2,x3,x4,x5,x6;\r
- \r
- gie = IRQ_globalDisable();\r
-\r
- base = (volatile Uint32 *)(_PLL_BASE_ADDR);\r
- \r
- x0 = base[_PLL_PLLCSR_OFFSET];\r
- x1 = base[_PLL_PLLM_OFFSET];\r
- x2 = base[_PLL_PLLDIV0_OFFSET];\r
- x3 = base[_PLL_PLLDIV1_OFFSET];\r
- x4 = base[_PLL_PLLDIV2_OFFSET];\r
- x5 = base[_PLL_PLLDIV3_OFFSET];\r
- x6 = base[_PLL_OSCDIV1_OFFSET];\r
-\r
- config->pllcsr = x0;\r
- config->pllm = x1;\r
- config->plldiv0 = x2;\r
- config->plldiv1 = x3;\r
- config->plldiv2 = x4;\r
- config->plldiv3 = x5;\r
- config->oscdiv1 = x6;\r
-\r
- IRQ_globalRestore(gie);\r
- \r
-}\r
-\r
-\r
-\r
-/*----------------------------------------------------------------------------*/\r
-#endif /* USEDEFS */\r
-\r
-/* Local software delay function */\r
-\r
-static void plldelay(Uint32 count){\r
- Uint32 i = count;\r
- while(i--){\r
- asm(" NOP 1");\r
- }\r
-}\r
-\r
-/******************************************************************************\\r
-* Step 10. #endif for PLL_SUPPORT and CSL_PLL_H Macro + Footer\r
-\******************************************************************************/\r
-#endif /* PLL_SUPPORT */\r
-#endif /* _CSL_PLL_H_ */\r
-/******************************************************************************\\r
-* End of csl_module.h\r
-\******************************************************************************/\r