[keystone-rtos/edma3_lld.git] / examples / CSL2_DAT_DEMO / src / dat_edma3LLD / csl2_dat_edma3lld_config.h
diff --git a/examples/CSL2_DAT_DEMO/src/dat_edma3LLD/csl2_dat_edma3lld_config.h b/examples/CSL2_DAT_DEMO/src/dat_edma3LLD/csl2_dat_edma3lld_config.h
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@@ -0,0 +1,100 @@
+/*\r
+ * Copyright 2006\r
+ * Texas Instruments Incorporated\r
+ *\r
+ * All rights reserved. Property of Texas Instruments Incorporated\r
+ * Restricted rights to use, duplicate or disclose this code are\r
+ * granted through contract.\r
+ *\r
+ */\r
+/**\r
+ * @file csl2_dat_edma3lld_config.h\r
+ *\r
+ * @brief Defines the hardware specific parameters required by the\r
+ * CSL DAT2 EDMA3 Adapter\r
+ *\r
+ *\r
+ */\r
+\r
+#ifndef _CSL_DAT2_EDMA3LLD_CONFIG_H\r
+#define _CSL_DAT2_EDMA3LLD_CONFIG_H\r
+\r
+\r
+/*\r
+ * Settings to be used with the EDMA3 DRV APIs\r
+ */\r
+#define DAT_EDMA3LLD_HW_REGION_ID (0x1u) /* DSP mapped to region1 on Davinci */\r
+#define DAT_EDMA3LLD_HW_INST_ID (0u) /* Hardware instance id */\r
+#define DAT_EDMA3LLD_HW_EVT_QUEUE_ID (0u) /* Event queue number to be used */\r
+#define DAT_EDMA3LLD_HW_MAXPHYCHANNELS (32u) /* Max number of physical channels */\r
+\r
+/*\r
+ * Settings for the DAT adapter layer\r
+ * has to be double checked by system integrator\r
+ */\r
+#define DAT_QUEUEDEPTH (4u) /* Maximum number of QDMA channels/tcc(s)\r
+ * allocated to the DAT layer\r
+ */\r
+/*\r
+ * Convenience MACROs for use in DAT adapter layer\r
+ */\r
+/*\r
+ * Clear bit in 32-bit register (task context)\r
+ */\r
+#define CLEAR_REGISTER32_BIT(reg,bit) \\r
+ _dat_critical_section_enter(); (reg) &= (~(0x1 << (bit))); \\r
+ _dat_critical_section_exit();\r
+/*\r
+ * Clear bit in 32-bit register (ISR context)\r
+ */\r
+#define CLEAR_REGISTER32_BIT_DURING_INT(reg,bit) \\r
+ (reg) &= (~(0x1 << (bit)));\r
+\r
+/*\r
+ * Set bit in 32-bit register (task context)\r
+ */\r
+#define SET_REGISTER32_BIT(reg,bit) \\r
+ _dat_critical_section_enter(); ((reg) |= (0x1 << (bit))); \\r
+ _dat_critical_section_exit();\r
+/*\r
+ * Set bit in 32-bit register (ISR context) \r
+ */\r
+#define SET_REGISTER32_BIT_DURING_INT(reg,bit) \\r
+ ((reg) |= (0x1 << (bit)));\r
+\r
+/*\r
+ * Get bit from 32-bit register\r
+ */\r
+#define GET_REGISTER32_BIT(reg,bit) \\r
+ (( ((reg)<< (31 - (bit)) ) >> 31) == 0)?0:1\r
+\r
+/*\r
+ * Commented out section in csl_dat2.c references these macros\r
+ */\r
+#define DAT_OPT_DEFAULT (0x0010000C) /* Sets up OPT for TCC Interrupt enabling\r
+ * AB-sync transfers, static entry with TCC\r
+ * not yet set */\r
+#define DAT_OPT_TCC_POS_MASK (0xC) /* This mask marks the position of TCC in\r
+ * OPT\r
+ */\r
+#define DAT_INVALID_ID (0xFFFFFFFF) /* Invalid ID */\r
+#define DAT_NULL_LINK (0xFFFF) /* Null link in the OPT */\r
+\r
+\r
+/* OPT Field specific defines */\r
+#define OPT_SYNCDIM_SHIFT (0x00000002u)\r
+#define OPT_TCC_MASK (0x0003F000u)\r
+#define OPT_TCC_SHIFT (0x0000000Cu)\r
+#define OPT_ITCINTEN_SHIFT (0x00000015u)\r
+#define OPT_TCINTEN_SHIFT (0x00000014u)\r
+#define OPT_STATIC_SHIFT (0x00000003u)\r
+\r
+\r
+/*\r
+ * Set Tcc in OPT\r
+ */\r
+#define DAT_OPT_TCC(opt,tcc) \\r
+ ((unsigned int)(opt) | ((tcc)<<DAT_OPT_TCC_POS_MASK))\r
+\r
+#endif /* _CSL_DAT2_EDMA3LLD_CONFIG_H */\r
+\r