index a8deded8dd46ccc48f18b82640f9461cbfe44fdb..f1bd4db99116ee404f7e8493e531956d58db31bb 100644 (file)
-#include "sample.h"\r
-\r
-extern signed char _srcBuff1[MAX_BUFFER_SIZE];\r
-extern signed char _dstBuff1[MAX_BUFFER_SIZE];\r
-\r
-extern signed char *srcBuff1;\r
-extern signed char *dstBuff1;\r
-\r
-/**\r
- * Test case demonstrating the poll mode scenario.\r
- * A user has requested a data transfer without giving any\r
- * callback function. After programming and enabling the channel,\r
- * he uses different APIs (meant to be used in poll mode)\r
- * to check the status of ongoing transfer.\r
- * Interrupt will NOT occur in this case.\r
- */\r
-/**\r
- * \brief EDMA3 mem-to-mem data copy test case, using a DMA channel.\r
- * This test case doesnot rely on the callback mechanism.\r
- * Instead, it Polls the IPR register to check the transfer\r
- * completion status.\r
- *\r
- * \param acnt [IN] Number of bytes in an array\r
- * \param bcnt [IN] Number of arrays in a frame\r
- * \param ccnt [IN] Number of frames in a block\r
- * \param syncType [IN] Synchronization type (A/AB Sync)\r
- *\r
- * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code\r
- */\r
-EDMA3_DRV_Result edma3_test_poll_mode(\r
- unsigned int acnt,\r
- unsigned int bcnt,\r
- unsigned int ccnt,\r
- EDMA3_DRV_SyncType syncType)\r
- {\r
- EDMA3_DRV_Result result = EDMA3_DRV_SOK;\r
- unsigned int chId = 0;\r
- unsigned int tcc = 0;\r
- int i;\r
- unsigned int count;\r
- unsigned int Istestpassed = 0u;\r
- unsigned int numenabled = 0;\r
- unsigned int BRCnt = 0;\r
- int srcbidx = 0, desbidx = 0;\r
- int srccidx = 0, descidx = 0;\r
-\r
-\r
- srcBuff1 = (signed char*)_srcBuff1;\r
- dstBuff1 = (signed char*)_dstBuff1;\r
-\r
-\r
- /* Initalize source and destination buffers */\r
- for (count = 0u; count < (acnt*bcnt*ccnt); count++)\r
- {\r
- srcBuff1[count] = (int)count+5;\r
- /**\r
- * No need to initialize the destination buffer as it is being invalidated.\r
- dstBuff1[count] = initval;\r
- */\r
- }\r
-\r
-\r
-#ifdef EDMA3_ENABLE_DCACHE\r
- /*\r
- * Note: These functions are required if the buffer is in DDR.\r
- * For other cases, where buffer is NOT in DDR, user\r
- * may or may not require the below functions.\r
- */\r
- /* Flush the Source Buffer */\r
- if (result == EDMA3_DRV_SOK)\r
- {\r
- result = Edma3_CacheFlush((unsigned int)srcBuff1, (acnt*bcnt*ccnt));\r
- }\r
-\r
- /* Invalidate the Destination Buffer */\r
- if (result == EDMA3_DRV_SOK)\r
- {\r
- result = Edma3_CacheInvalidate((unsigned int)dstBuff1, (acnt*bcnt*ccnt));\r
- }\r
-#endif /* EDMA3_ENABLE_DCACHE */\r
-\r
-\r
- /* Set B count reload as B count. */\r
- BRCnt = bcnt;\r
-\r
- /* Setting up the SRC/DES Index */\r
- srcbidx = (int)acnt;\r
- desbidx = (int)acnt;\r
-\r
- if (syncType == EDMA3_DRV_SYNC_A)\r
- {\r
- /* A Sync Transfer Mode */\r
- srccidx = (int)acnt;\r
- descidx = (int)acnt;\r
- }\r
- else\r
- {\r
- /* AB Sync Transfer Mode */\r
- srccidx = ((int)acnt * (int)bcnt);\r
- descidx = ((int)acnt * (int)bcnt);\r
- }\r
-\r
-\r
- /* Setup for Channel 1*/\r
- tcc = EDMA3_DRV_TCC_ANY;\r
- chId = EDMA3_DRV_DMA_CHANNEL_ANY;\r
-\r
-\r
- /* Request any DMA channel and any TCC */\r
- if (result == EDMA3_DRV_SOK)\r
- {\r
- result = EDMA3_DRV_requestChannel (hEdma, &chId, &tcc,\r
- (EDMA3_RM_EventQueue)0,\r
- NULL, NULL);\r
- }\r
-\r
- if (result == EDMA3_DRV_SOK)\r
- {\r
- result = EDMA3_DRV_setSrcParams (hEdma, chId, (unsigned int)(srcBuff1),\r
- EDMA3_DRV_ADDR_MODE_INCR,\r
- EDMA3_DRV_W8BIT);\r
- }\r
-\r
- if (result == EDMA3_DRV_SOK)\r
- {\r
- result = EDMA3_DRV_setDestParams (hEdma, chId, (unsigned int)(dstBuff1),\r
- EDMA3_DRV_ADDR_MODE_INCR,\r
- EDMA3_DRV_W8BIT);\r
- }\r
-\r
- if (result == EDMA3_DRV_SOK)\r
- {\r
- result = EDMA3_DRV_setSrcIndex (hEdma, chId, srcbidx, srccidx);\r
- }\r
-\r
- if (result == EDMA3_DRV_SOK)\r
- {\r
- result = EDMA3_DRV_setDestIndex (hEdma, chId, desbidx, descidx);\r
- }\r
-\r
- if (result == EDMA3_DRV_SOK)\r
- {\r
- if (syncType == EDMA3_DRV_SYNC_A)\r
- {\r
- result = EDMA3_DRV_setTransferParams (hEdma, chId, acnt, bcnt, ccnt,\r
- BRCnt, EDMA3_DRV_SYNC_A);\r
- }\r
- else\r
- {\r
- result = EDMA3_DRV_setTransferParams (hEdma, chId, acnt, bcnt, ccnt,\r
- BRCnt, EDMA3_DRV_SYNC_AB);\r
- }\r
- }\r
-\r
- if (result == EDMA3_DRV_SOK)\r
- {\r
- result = EDMA3_DRV_setOptField (hEdma, chId,\r
- EDMA3_DRV_OPT_FIELD_TCINTEN, 1u);\r
- }\r
-\r
- if (result == EDMA3_DRV_SOK)\r
- {\r
- result = EDMA3_DRV_setOptField (hEdma, chId,\r
- EDMA3_DRV_OPT_FIELD_ITCINTEN, 1u);\r
- }\r
-\r
- /*\r
- * Since the transfer is going to happen in Manual mode of EDMA3\r
- * operation, we have to 'Enable the Transfer' multiple times.\r
- * Number of times depends upon the Mode (A/AB Sync)\r
- * and the different counts.\r
- */\r
- if (result == EDMA3_DRV_SOK)\r
- {\r
- /*Need to activate next param*/\r
- if (syncType == EDMA3_DRV_SYNC_A)\r
- {\r
- numenabled = bcnt * ccnt;\r
- }\r
- else\r
- {\r
- /* AB Sync Transfer Mode */\r
- numenabled = ccnt;\r
- }\r
-\r
-\r
- for (i = 0; i < numenabled; i++)\r
- {\r
- /*\r
- * Now enable the transfer as many times as calculated above.\r
- */\r
- result = EDMA3_DRV_enableTransfer (hEdma, chId,\r
- EDMA3_DRV_TRIG_MODE_MANUAL);\r
- if (result != EDMA3_DRV_SOK)\r
- {\r
-#ifdef EDMA3_DRV_DEBUG\r
- EDMA3_DRV_PRINTF ("edma3_test_poll_mode: EDMA3_DRV_enableTransfer " \\r
- "Failed, error code: %d\r\n", result);\r
-#endif /* EDMA3_DRV_DEBUG */\r
- break;\r
- }\r
-\r
-\r
- /* Wait for the Completion Bit to be SET in the IPR/IPRH register. */\r
- result = EDMA3_DRV_waitAndClearTcc (hEdma, tcc);\r
- if (result != EDMA3_DRV_SOK)\r
- {\r
-#ifdef EDMA3_DRV_DEBUG\r
- EDMA3_DRV_PRINTF ("edma3_test_poll_mode: EDMA3_DRV_waitAndClearTcc " \\r
- "Failed, error code: %d\r\n", result);\r
-#endif /* EDMA3_DRV_DEBUG */\r
- break;\r
- }\r
- }\r
- }\r
-\r
-\r
- /* Match the Source and Destination Buffers. */\r
- if (EDMA3_DRV_SOK == result)\r
- {\r
- for (i = 0; i < (acnt*bcnt*ccnt); i++)\r
- {\r
- if (srcBuff1[i] != dstBuff1[i])\r
- {\r
- Istestpassed = 0u;\r
-#ifdef EDMA3_DRV_DEBUG\r
- EDMA3_DRV_PRINTF("edma3_test_poll_mode: Data write-read matching" \\r
- "FAILED at i = %d\r\n", i);\r
-#endif /* EDMA3_DRV_DEBUG */\r
- break;\r
- }\r
- }\r
- if (i == (acnt*bcnt*ccnt))\r
- {\r
- Istestpassed = 1u;\r
- }\r
-\r
-\r
- /* Free the previously allocated channel. */\r
- result = EDMA3_DRV_freeChannel (hEdma, chId);\r
- if (result != EDMA3_DRV_SOK)\r
- {\r
-#ifdef EDMA3_DRV_DEBUG\r
- EDMA3_DRV_PRINTF("edma3_test_poll_mode: EDMA3_DRV_freeChannel() FAILED, " \\r
- "error code: %d\r\n", result);\r
-#endif /* EDMA3_DRV_DEBUG */\r
- }\r
- }\r
-\r
-\r
- if(Istestpassed == 1u)\r
- {\r
-#ifdef EDMA3_DRV_DEBUG\r
- EDMA3_DRV_PRINTF("edma3_test_poll_mode PASSED\r\n");\r
-#endif /* EDMA3_DRV_DEBUG */\r
- }\r
- else\r
- {\r
-#ifdef EDMA3_DRV_DEBUG\r
- EDMA3_DRV_PRINTF("edma3_test_poll_mode FAILED\r\n");\r
-#endif /* EDMA3_DRV_DEBUG */\r
- result = ((EDMA3_DRV_SOK == result) ?\r
- EDMA3_DATA_MISMATCH_ERROR : result);\r
- }\r
-\r
-\r
- return result;\r
-}\r
+#include "sample.h"
+
+extern signed char _srcBuff1[MAX_BUFFER_SIZE];
+extern signed char _dstBuff1[MAX_BUFFER_SIZE];
+
+extern signed char *srcBuff1;
+extern signed char *dstBuff1;
+
+/**
+ * Test case demonstrating the poll mode scenario.
+ * A user has requested a data transfer without giving any
+ * callback function. After programming and enabling the channel,
+ * he uses different APIs (meant to be used in poll mode)
+ * to check the status of ongoing transfer.
+ * Interrupt will NOT occur in this case.
+ */
+/**
+ * \brief EDMA3 mem-to-mem data copy test case, using a DMA channel.
+ * This test case doesnot rely on the callback mechanism.
+ * Instead, it Polls the IPR register to check the transfer
+ * completion status.
+ *
+ * \param acnt [IN] Number of bytes in an array
+ * \param bcnt [IN] Number of arrays in a frame
+ * \param ccnt [IN] Number of frames in a block
+ * \param syncType [IN] Synchronization type (A/AB Sync)
+ *
+ * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code
+ */
+EDMA3_DRV_Result edma3_test_poll_mode(
+ unsigned int acnt,
+ unsigned int bcnt,
+ unsigned int ccnt,
+ EDMA3_DRV_SyncType syncType)
+ {
+ EDMA3_DRV_Result result = EDMA3_DRV_SOK;
+ unsigned int chId = 0;
+ unsigned int tcc = 0;
+ int i;
+ unsigned int count;
+ unsigned int Istestpassed = 0u;
+ unsigned int numenabled = 0;
+ unsigned int BRCnt = 0;
+ int srcbidx = 0, desbidx = 0;
+ int srccidx = 0, descidx = 0;
+
+
+ srcBuff1 = (signed char*)_srcBuff1;
+ dstBuff1 = (signed char*)_dstBuff1;
+
+
+ /* Initalize source and destination buffers */
+ for (count = 0u; count < (acnt*bcnt*ccnt); count++)
+ {
+ srcBuff1[count] = (int)count+5;
+ /**
+ * No need to initialize the destination buffer as it is being invalidated.
+ dstBuff1[count] = initval;
+ */
+ }
+
+
+#ifdef EDMA3_ENABLE_DCACHE
+ /*
+ * Note: These functions are required if the buffer is in DDR.
+ * For other cases, where buffer is NOT in DDR, user
+ * may or may not require the below functions.
+ */
+ /* Flush the Source Buffer */
+ if (result == EDMA3_DRV_SOK)
+ {
+ result = Edma3_CacheFlush((unsigned int)srcBuff1, (acnt*bcnt*ccnt));
+ }
+
+ /* Invalidate the Destination Buffer */
+ if (result == EDMA3_DRV_SOK)
+ {
+ result = Edma3_CacheInvalidate((unsigned int)dstBuff1, (acnt*bcnt*ccnt));
+ }
+#endif /* EDMA3_ENABLE_DCACHE */
+
+
+ /* Set B count reload as B count. */
+ BRCnt = bcnt;
+
+ /* Setting up the SRC/DES Index */
+ srcbidx = (int)acnt;
+ desbidx = (int)acnt;
+
+ if (syncType == EDMA3_DRV_SYNC_A)
+ {
+ /* A Sync Transfer Mode */
+ srccidx = (int)acnt;
+ descidx = (int)acnt;
+ }
+ else
+ {
+ /* AB Sync Transfer Mode */
+ srccidx = ((int)acnt * (int)bcnt);
+ descidx = ((int)acnt * (int)bcnt);
+ }
+
+
+ /* Setup for Channel 1*/
+ tcc = EDMA3_DRV_TCC_ANY;
+ chId = EDMA3_DRV_DMA_CHANNEL_ANY;
+
+
+ /* Request any DMA channel and any TCC */
+ if (result == EDMA3_DRV_SOK)
+ {
+ result = EDMA3_DRV_requestChannel (hEdma, &chId, &tcc,
+ (EDMA3_RM_EventQueue)0,
+ NULL, NULL);
+ }
+
+ if (result == EDMA3_DRV_SOK)
+ {
+ result = EDMA3_DRV_setSrcParams (hEdma, chId, (unsigned int)(srcBuff1),
+ EDMA3_DRV_ADDR_MODE_INCR,
+ EDMA3_DRV_W8BIT);
+ }
+
+ if (result == EDMA3_DRV_SOK)
+ {
+ result = EDMA3_DRV_setDestParams (hEdma, chId, (unsigned int)(dstBuff1),
+ EDMA3_DRV_ADDR_MODE_INCR,
+ EDMA3_DRV_W8BIT);
+ }
+
+ if (result == EDMA3_DRV_SOK)
+ {
+ result = EDMA3_DRV_setSrcIndex (hEdma, chId, srcbidx, srccidx);
+ }
+
+ if (result == EDMA3_DRV_SOK)
+ {
+ result = EDMA3_DRV_setDestIndex (hEdma, chId, desbidx, descidx);
+ }
+
+ if (result == EDMA3_DRV_SOK)
+ {
+ if (syncType == EDMA3_DRV_SYNC_A)
+ {
+ result = EDMA3_DRV_setTransferParams (hEdma, chId, acnt, bcnt, ccnt,
+ BRCnt, EDMA3_DRV_SYNC_A);
+ }
+ else
+ {
+ result = EDMA3_DRV_setTransferParams (hEdma, chId, acnt, bcnt, ccnt,
+ BRCnt, EDMA3_DRV_SYNC_AB);
+ }
+ }
+
+ if (result == EDMA3_DRV_SOK)
+ {
+ result = EDMA3_DRV_setOptField (hEdma, chId,
+ EDMA3_DRV_OPT_FIELD_TCINTEN, 1u);
+ }
+
+ if (result == EDMA3_DRV_SOK)
+ {
+ result = EDMA3_DRV_setOptField (hEdma, chId,
+ EDMA3_DRV_OPT_FIELD_ITCINTEN, 1u);
+ }
+
+ /*
+ * Since the transfer is going to happen in Manual mode of EDMA3
+ * operation, we have to 'Enable the Transfer' multiple times.
+ * Number of times depends upon the Mode (A/AB Sync)
+ * and the different counts.
+ */
+ if (result == EDMA3_DRV_SOK)
+ {
+ /*Need to activate next param*/
+ if (syncType == EDMA3_DRV_SYNC_A)
+ {
+ numenabled = bcnt * ccnt;
+ }
+ else
+ {
+ /* AB Sync Transfer Mode */
+ numenabled = ccnt;
+ }
+
+
+ for (i = 0; i < numenabled; i++)
+ {
+ /*
+ * Now enable the transfer as many times as calculated above.
+ */
+ result = EDMA3_DRV_enableTransfer (hEdma, chId,
+ EDMA3_DRV_TRIG_MODE_MANUAL);
+ if (result != EDMA3_DRV_SOK)
+ {
+#ifdef EDMA3_DRV_DEBUG
+ EDMA3_DRV_PRINTF ("edma3_test_poll_mode: EDMA3_DRV_enableTransfer " \
+ "Failed, error code: %d\r\n", result);
+#endif /* EDMA3_DRV_DEBUG */
+ break;
+ }
+
+
+ /* Wait for the Completion Bit to be SET in the IPR/IPRH register. */
+ result = EDMA3_DRV_waitAndClearTcc (hEdma, tcc);
+ if (result != EDMA3_DRV_SOK)
+ {
+#ifdef EDMA3_DRV_DEBUG
+ EDMA3_DRV_PRINTF ("edma3_test_poll_mode: EDMA3_DRV_waitAndClearTcc " \
+ "Failed, error code: %d\r\n", result);
+#endif /* EDMA3_DRV_DEBUG */
+ break;
+ }
+ }
+ }
+
+
+ /* Match the Source and Destination Buffers. */
+ if (EDMA3_DRV_SOK == result)
+ {
+ for (i = 0; i < (acnt*bcnt*ccnt); i++)
+ {
+ if (srcBuff1[i] != dstBuff1[i])
+ {
+ Istestpassed = 0u;
+#ifdef EDMA3_DRV_DEBUG
+ EDMA3_DRV_PRINTF("edma3_test_poll_mode: Data write-read matching" \
+ "FAILED at i = %d\r\n", i);
+#endif /* EDMA3_DRV_DEBUG */
+ break;
+ }
+ }
+ if (i == (acnt*bcnt*ccnt))
+ {
+ Istestpassed = 1u;
+ }
+
+
+ /* Free the previously allocated channel. */
+ result = EDMA3_DRV_freeChannel (hEdma, chId);
+ if (result != EDMA3_DRV_SOK)
+ {
+#ifdef EDMA3_DRV_DEBUG
+ EDMA3_DRV_PRINTF("edma3_test_poll_mode: EDMA3_DRV_freeChannel() FAILED, " \
+ "error code: %d\r\n", result);
+#endif /* EDMA3_DRV_DEBUG */
+ }
+ }
+
+
+ if(Istestpassed == 1u)
+ {
+#ifdef EDMA3_DRV_DEBUG
+ EDMA3_DRV_PRINTF("edma3_test_poll_mode PASSED\r\n");
+#endif /* EDMA3_DRV_DEBUG */
+ }
+ else
+ {
+#ifdef EDMA3_DRV_DEBUG
+ EDMA3_DRV_PRINTF("edma3_test_poll_mode FAILED\r\n");
+#endif /* EDMA3_DRV_DEBUG */
+ result = ((EDMA3_DRV_SOK == result) ?
+ EDMA3_DATA_MISMATCH_ERROR : result);
+ }
+
+
+ return result;
+}