index a6d37c630a6b428ba78841d032c61ed871e42af0..a8b8910756e681f6bc0cb393b9119ab6bf5e21fa 100644 (file)
* This file contains the test / demo code to demonstrate the EDMA3 driver
* functionality on DSP/BIOS 6.
*
-* Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - http://www.ti.com/
*
*
* Redistribution and use in source and binary forms, with or without
extern const uint32_t numEdma3Instances;
#endif
+#ifdef SOC_AM335x
+#define WR_MEM_32(addr, data) *(unsigned int*)(addr) = (unsigned int)(data)
+
+#define PRCM_BASE_ADDR (0x44E00000)
+#define CM_PER_TPTC0_CLKCTRL (PRCM_BASE_ADDR +0x0024)
+#define CM_PER_TPCC_CLKCTRL (PRCM_BASE_ADDR +0x00BC)
+#define CM_PER_TPTC1_CLKCTRL (PRCM_BASE_ADDR +0x00FC)
+#define CM_PER_TPTC2_CLKCTRL (PRCM_BASE_ADDR +0x0100)
+
+/*To enable EDMA3 Clock Module */
+static void edma3PRCMEnable();
+#endif
+
/**
* DSP instance number on which the executable is running. Its value is
* determined by reading the processor specific register DNUM.
memset(hEdma,0,sizeof(hEdma));
+#ifdef SOC_AM335x
+ edma3PRCMEnable();
+#endif
+
/* Print the Welcome Message */
printWelcomeBanner();
counter++;
}
}
+
+#ifdef SOC_AM335x
+/*To enable EDMA3 Clock Module of AM335x*/
+static void edma3PRCMEnable()
+{
+ WR_MEM_32(CM_PER_TPCC_CLKCTRL, 2);
+ WR_MEM_32(CM_PER_TPTC0_CLKCTRL , 2);
+ WR_MEM_32(CM_PER_TPTC1_CLKCTRL , 2);
+ WR_MEM_32(CM_PER_TPTC2_CLKCTRL , 2);
+}
+#endif