index 877cc58b69f4c325fdc28096b1c22ecbe211da96..2295890a4768fee5a57c5f82d5fa102caf45361f 100755 (executable)
-/*\r
- * qdma_test.c\r
- *\r
- * EDMA3 mem-to-mem data copy test case, using a QDMA channel.\r
- *\r
- * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ \r
- * \r
- * \r
- * Redistribution and use in source and binary forms, with or without \r
- * modification, are permitted provided that the following conditions \r
- * are met:\r
- *\r
- * Redistributions of source code must retain the above copyright \r
- * notice, this list of conditions and the following disclaimer.\r
- *\r
- * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the \r
- * documentation and/or other materials provided with the \r
- * distribution.\r
- *\r
- * Neither the name of Texas Instruments Incorporated nor the names of\r
- * its contributors may be used to endorse or promote products derived\r
- * from this software without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \r
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT \r
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT \r
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \r
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT \r
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT \r
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE \r
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- *\r
-*/\r
-\r
-#include "sample.h"\r
-\r
-extern signed char _srcBuff1[MAX_BUFFER_SIZE];\r
-extern signed char _dstBuff1[MAX_BUFFER_SIZE];\r
-\r
-extern signed char *srcBuff1;\r
-extern signed char *dstBuff1;\r
-\r
-\r
-/**\r
- * \brief EDMA3 mem-to-mem data copy test case, using a QDMA channel.\r
- *\r
- *\r
- * \param acnt [IN] Number of bytes in an array\r
- * \param bcnt [IN] Number of arrays in a frame\r
- * \param ccnt [IN] Number of frames in a block\r
- * \param syncType [IN] Synchronization type (A/AB Sync)\r
- *\r
- * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code\r
- */\r
-EDMA3_DRV_Result qdma_test(\r
- EDMA3_DRV_Handle hEdma,\r
- unsigned int acnt,\r
- unsigned int bcnt,\r
- unsigned int ccnt,\r
- EDMA3_DRV_SyncType syncType)\r
- {\r
- EDMA3_DRV_Result result = EDMA3_DRV_SOK;\r
- unsigned int i;\r
- unsigned int count;\r
- unsigned int Istestpassed = 0u;\r
- unsigned int numenabled = 0;\r
- unsigned int qCh1Id=0;\r
- unsigned int qTcc1 = 0;\r
- unsigned int BRCnt = 0;\r
- int srcbidx = 0, desbidx = 0;\r
- int srccidx = 0, descidx = 0;\r
- static signed char* tmpSrcBuff1 = NULL;\r
- static signed char* tmpDstBuff1 = NULL;\r
-\r
- srcBuff1 = (signed char*) _srcBuff1;\r
- dstBuff1 = (signed char*) _dstBuff1;\r
-\r
- tmpSrcBuff1 = srcBuff1;\r
- tmpDstBuff1 = dstBuff1;\r
-\r
- /* Initalize source and destination buffers */\r
- for (count = 0u; count < (acnt*bcnt*ccnt); count++)\r
- {\r
- srcBuff1[count] = (int)count+2;\r
- /**\r
- * No need to initialize the destination buffer as it is being invalidated.\r
- dstBuff1[count] = initval;\r
- */\r
- }\r
-\r
-#ifdef EDMA3_ENABLE_DCACHE\r
- /*\r
- * Note: These functions are required if the buffer is in DDR.\r
- * For other cases, where buffer is NOT in DDR, user\r
- * may or may not require the below functions.\r
- */\r
- /* Flush the Source Buffer */\r
- if (result == EDMA3_DRV_SOK)\r
- {\r
- result = Edma3_CacheFlush((unsigned int)srcBuff1, (acnt*bcnt*ccnt));\r
- }\r
-\r
- /* Invalidate the Destination Buffer */\r
- if (result == EDMA3_DRV_SOK)\r
- {\r
- result = Edma3_CacheInvalidate((unsigned int)dstBuff1, (acnt*bcnt*ccnt));\r
- }\r
-#endif /* EDMA3_ENABLE_DCACHE */\r
-\r
-\r
- irqRaised1 = 0;\r
-\r
- /* Set B count reload as B count. */\r
- BRCnt = bcnt;\r
- /* Setting up the SRC/DES Index */\r
- srcbidx = (int)acnt;\r
- desbidx = (int)acnt;\r
-\r
- if (syncType == EDMA3_DRV_SYNC_A)\r
- {\r
- srccidx = (int)acnt;\r
- descidx = (int)acnt;\r
- }\r
- else\r
- {\r
- /* AB Sync Transfer Mode */\r
- srccidx = ((int)acnt * (int)bcnt);\r
- descidx = ((int)acnt * (int)bcnt);\r
- }\r
-\r
-\r
- /* Setup for any QDMA Channel */\r
- qCh1Id = EDMA3_DRV_QDMA_CHANNEL_ANY;\r
- qTcc1 = EDMA3_DRV_TCC_ANY;\r
-\r
- if (result == EDMA3_DRV_SOK)\r
- {\r
- result = EDMA3_DRV_requestChannel (hEdma, &qCh1Id, &qTcc1,\r
- (EDMA3_RM_EventQueue)0, &callback1,\r
- NULL);\r
- }\r
-\r
- if (result == EDMA3_DRV_SOK)\r
- {\r
- /* Set QDMA Trigger Word as Destination Address */\r
- result = EDMA3_DRV_setQdmaTrigWord (hEdma, qCh1Id,\r
- EDMA3_RM_QDMA_TRIG_DST);\r
- }\r
-\r
- if (result == EDMA3_DRV_SOK)\r
- {\r
- result = EDMA3_DRV_setSrcIndex (hEdma, qCh1Id, srcbidx, srccidx);\r
- }\r
-\r
- if (result == EDMA3_DRV_SOK)\r
- {\r
- result = EDMA3_DRV_setDestIndex (hEdma, qCh1Id, desbidx, descidx);\r
- }\r
-\r
- if (result == EDMA3_DRV_SOK)\r
- {\r
- if (syncType == EDMA3_DRV_SYNC_A)\r
- {\r
- result = EDMA3_DRV_setTransferParams (hEdma, qCh1Id, acnt, bcnt,\r
- ccnt, BRCnt, EDMA3_DRV_SYNC_A);\r
- }\r
- else\r
- {\r
- /* AB Sync Transfer Mode */\r
- result = EDMA3_DRV_setTransferParams (hEdma, qCh1Id, acnt, bcnt,\r
- ccnt, BRCnt, EDMA3_DRV_SYNC_AB);\r
- }\r
- }\r
-\r
- if (result == EDMA3_DRV_SOK)\r
- {\r
- /* Enable Transfer Completion Interrupt */\r
- result = EDMA3_DRV_setOptField (hEdma, qCh1Id,\r
- EDMA3_DRV_OPT_FIELD_TCINTEN, 1u);\r
- }\r
-\r
- if (result == EDMA3_DRV_SOK)\r
- {\r
- /* Enable Intermediate Transfer Completion Interrupt */\r
- result = EDMA3_DRV_setOptField (hEdma, qCh1Id,\r
- EDMA3_DRV_OPT_FIELD_ITCINTEN, 1u);\r
- }\r
-\r
- if (result == EDMA3_DRV_SOK)\r
- {\r
- /* Set Source Transfer Mode as Increment Mode. */\r
- result = EDMA3_DRV_setOptField (hEdma, qCh1Id, EDMA3_DRV_OPT_FIELD_SAM,\r
- EDMA3_DRV_ADDR_MODE_INCR);\r
- }\r
-\r
- if (result == EDMA3_DRV_SOK)\r
- {\r
- /* Set Destination Transfer Mode as Increment Mode. */\r
- result = EDMA3_DRV_setOptField (hEdma, qCh1Id, EDMA3_DRV_OPT_FIELD_DAM,\r
- EDMA3_DRV_ADDR_MODE_INCR);\r
- }\r
-\r
-\r
- /*\r
- * Since the transfer is going to happen in QDMA mode of EDMA3\r
- * operation, we have to "Trigger" the transfer multiple times.\r
- * Number of times depends upon the Mode (A/AB Sync)\r
- * and the different counts.\r
- */\r
- if (result == EDMA3_DRV_SOK)\r
- {\r
- /*Need to activate next param*/\r
- if (syncType == EDMA3_DRV_SYNC_A)\r
- {\r
- numenabled = bcnt * ccnt;\r
- }\r
- else\r
- {\r
- /* AB Sync Transfer Mode */\r
- numenabled = ccnt;\r
- }\r
-\r
- for (i = 0u; i < numenabled; i++)\r
- {\r
- irqRaised1 = 0u;\r
-\r
- if (i == (numenabled-1u))\r
- {\r
- /**\r
- * Since OPT.STATIC field should be SET for isolated QDMA\r
- * transfers or for the final transfer in a linked list of QDMA\r
- * transfers, do the needful for the last request.\r
- */\r
- result = EDMA3_DRV_setOptField (hEdma, qCh1Id,\r
- EDMA3_DRV_OPT_FIELD_STATIC, 1u);\r
- }\r
-\r
- /* Write to the Source Address */\r
- result = EDMA3_DRV_setSrcParams (hEdma, qCh1Id,\r
- (unsigned int)(srcBuff1),\r
- EDMA3_DRV_ADDR_MODE_INCR,\r
- EDMA3_DRV_W8BIT);\r
- /*\r
- * Now trigger the QDMA channel by writing to the Trigger\r
- * Word which is set as Destination Address.\r
- */\r
- if (result == EDMA3_DRV_SOK)\r
- {\r
- result = EDMA3_DRV_setPaRAMEntry (hEdma, qCh1Id,\r
- EDMA3_DRV_PARAM_ENTRY_DST,\r
- (unsigned int)(dstBuff1));\r
- if (result != EDMA3_DRV_SOK)\r
- {\r
- printf ("error from qdma_test\n\r\n");\r
- break;\r
- }\r
- }\r
-\r
- /* Wait for the Completion ISR. */\r
- while (irqRaised1 == 0)\r
- {\r
- /* Wait for the Completion ISR. */\r
- printf ("waiting for interrupt...\n"); \r
- }\r
-\r
- /* Check the status of the completed transfer */\r
- if (irqRaised1 < 0)\r
- {\r
- /* Some error occured, break from the FOR loop. */\r
- printf ("\r\nqdma_test: Event Miss Occured!!!\r\n");\r
-\r
- /* Clear the error bits first */\r
- result = EDMA3_DRV_clearErrorBits (hEdma, qCh1Id);\r
-\r
- break;\r
- }\r
-\r
- /**\r
- * Now, update the source and destination addresses for next\r
- * "Trigger".\r
- */\r
- srcBuff1 += srccidx;\r
- dstBuff1 += descidx;\r
- }\r
- }\r
-\r
- if (result == EDMA3_DRV_SOK)\r
- {\r
- /* Restore the src and dest buffers */\r
- srcBuff1 = tmpSrcBuff1;\r
- dstBuff1 = tmpDstBuff1;\r
-\r
- /* Match the Source and Destination Buffers. */\r
- for (i = 0u; i < (acnt*bcnt*ccnt); i++)\r
- {\r
- if (srcBuff1[i] != dstBuff1[i])\r
- {\r
- Istestpassed = 0u;\r
- printf("qdma_test: Data write-read matching FAILED" \\r
- " at i = %d\r\n", i);\r
- break;\r
- }\r
- }\r
- if (i == (acnt*bcnt*ccnt))\r
- {\r
- Istestpassed = 1u;\r
- }\r
-\r
- /* Free the previously allocated channel. */\r
- result = EDMA3_DRV_freeChannel (hEdma, qCh1Id);\r
- if (result != EDMA3_DRV_SOK)\r
- {\r
- printf("qdma_test: EDMA3_DRV_freeChannel() FAILED, error code: %d\r\n", result);\r
- }\r
- }\r
-\r
- if(Istestpassed == 1u)\r
- {\r
- printf("qdma_test PASSED\r\n");\r
- }\r
- else\r
- {\r
- printf("qdma_test FAILED\r\n");\r
- result = ((EDMA3_DRV_SOK == result) ?\r
- EDMA3_DATA_MISMATCH_ERROR : result);\r
- }\r
-\r
- return result;\r
- }\r
-\r
-\r
+/*
+ * qdma_test.c
+ *
+ * EDMA3 mem-to-mem data copy test case, using a QDMA channel.
+ *
+ * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+#include "sample.h"
+
+extern signed char _srcBuff1[MAX_BUFFER_SIZE];
+extern signed char _dstBuff1[MAX_BUFFER_SIZE];
+
+extern signed char *srcBuff1;
+extern signed char *dstBuff1;
+
+
+/**
+ * \brief EDMA3 mem-to-mem data copy test case, using a QDMA channel.
+ *
+ *
+ * \param acnt [IN] Number of bytes in an array
+ * \param bcnt [IN] Number of arrays in a frame
+ * \param ccnt [IN] Number of frames in a block
+ * \param syncType [IN] Synchronization type (A/AB Sync)
+ *
+ * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code
+ */
+EDMA3_DRV_Result qdma_test(
+ EDMA3_DRV_Handle hEdma,
+ unsigned int acnt,
+ unsigned int bcnt,
+ unsigned int ccnt,
+ EDMA3_DRV_SyncType syncType)
+ {
+ EDMA3_DRV_Result result = EDMA3_DRV_SOK;
+ unsigned int i;
+ unsigned int count;
+ unsigned int Istestpassed = 0u;
+ unsigned int numenabled = 0;
+ unsigned int qCh1Id=0;
+ unsigned int qTcc1 = 0;
+ unsigned int BRCnt = 0;
+ int srcbidx = 0, desbidx = 0;
+ int srccidx = 0, descidx = 0;
+ static signed char* tmpSrcBuff1 = NULL;
+ static signed char* tmpDstBuff1 = NULL;
+
+ srcBuff1 = (signed char*) GLOBAL_ADDR(_srcBuff1);
+ dstBuff1 = (signed char*) GLOBAL_ADDR(_dstBuff1);
+
+ tmpSrcBuff1 = srcBuff1;
+ tmpDstBuff1 = dstBuff1;
+
+ /* Initalize source and destination buffers */
+ for (count = 0u; count < (acnt*bcnt*ccnt); count++)
+ {
+ srcBuff1[count] = (int)count+2;
+ /**
+ * No need to initialize the destination buffer as it is being invalidated.
+ dstBuff1[count] = initval;
+ */
+ }
+
+#ifdef EDMA3_ENABLE_DCACHE
+ /*
+ * Note: These functions are required if the buffer is in DDR.
+ * For other cases, where buffer is NOT in DDR, user
+ * may or may not require the below functions.
+ */
+ /* Flush the Source Buffer */
+ if (result == EDMA3_DRV_SOK)
+ {
+ result = Edma3_CacheFlush((unsigned int)srcBuff1, (acnt*bcnt*ccnt));
+ }
+
+ /* Invalidate the Destination Buffer */
+ if (result == EDMA3_DRV_SOK)
+ {
+ result = Edma3_CacheInvalidate((unsigned int)dstBuff1, (acnt*bcnt*ccnt));
+ }
+#endif /* EDMA3_ENABLE_DCACHE */
+
+
+ irqRaised1 = 0;
+
+ /* Set B count reload as B count. */
+ BRCnt = bcnt;
+ /* Setting up the SRC/DES Index */
+ srcbidx = (int)acnt;
+ desbidx = (int)acnt;
+
+ if (syncType == EDMA3_DRV_SYNC_A)
+ {
+ srccidx = (int)acnt;
+ descidx = (int)acnt;
+ }
+ else
+ {
+ /* AB Sync Transfer Mode */
+ srccidx = ((int)acnt * (int)bcnt);
+ descidx = ((int)acnt * (int)bcnt);
+ }
+
+
+ /* Setup for any QDMA Channel */
+ qCh1Id = EDMA3_DRV_QDMA_CHANNEL_ANY;
+ qTcc1 = EDMA3_DRV_TCC_ANY;
+
+ if (result == EDMA3_DRV_SOK)
+ {
+ result = EDMA3_DRV_requestChannel (hEdma, &qCh1Id, &qTcc1,
+ (EDMA3_RM_EventQueue)0, &callback1,
+ NULL);
+ }
+
+ if (result == EDMA3_DRV_SOK)
+ {
+ /* Set QDMA Trigger Word as Destination Address */
+ result = EDMA3_DRV_setQdmaTrigWord (hEdma, qCh1Id,
+ EDMA3_RM_QDMA_TRIG_DST);
+ }
+
+ if (result == EDMA3_DRV_SOK)
+ {
+ result = EDMA3_DRV_setSrcIndex (hEdma, qCh1Id, srcbidx, srccidx);
+ }
+
+ if (result == EDMA3_DRV_SOK)
+ {
+ result = EDMA3_DRV_setDestIndex (hEdma, qCh1Id, desbidx, descidx);
+ }
+
+ if (result == EDMA3_DRV_SOK)
+ {
+ if (syncType == EDMA3_DRV_SYNC_A)
+ {
+ result = EDMA3_DRV_setTransferParams (hEdma, qCh1Id, acnt, bcnt,
+ ccnt, BRCnt, EDMA3_DRV_SYNC_A);
+ }
+ else
+ {
+ /* AB Sync Transfer Mode */
+ result = EDMA3_DRV_setTransferParams (hEdma, qCh1Id, acnt, bcnt,
+ ccnt, BRCnt, EDMA3_DRV_SYNC_AB);
+ }
+ }
+
+ if (result == EDMA3_DRV_SOK)
+ {
+ /* Enable Transfer Completion Interrupt */
+ result = EDMA3_DRV_setOptField (hEdma, qCh1Id,
+ EDMA3_DRV_OPT_FIELD_TCINTEN, 1u);
+ }
+
+ if (result == EDMA3_DRV_SOK)
+ {
+ /* Enable Intermediate Transfer Completion Interrupt */
+ result = EDMA3_DRV_setOptField (hEdma, qCh1Id,
+ EDMA3_DRV_OPT_FIELD_ITCINTEN, 1u);
+ }
+
+ if (result == EDMA3_DRV_SOK)
+ {
+ /* Set Source Transfer Mode as Increment Mode. */
+ result = EDMA3_DRV_setOptField (hEdma, qCh1Id, EDMA3_DRV_OPT_FIELD_SAM,
+ EDMA3_DRV_ADDR_MODE_INCR);
+ }
+
+ if (result == EDMA3_DRV_SOK)
+ {
+ /* Set Destination Transfer Mode as Increment Mode. */
+ result = EDMA3_DRV_setOptField (hEdma, qCh1Id, EDMA3_DRV_OPT_FIELD_DAM,
+ EDMA3_DRV_ADDR_MODE_INCR);
+ }
+
+
+ /*
+ * Since the transfer is going to happen in QDMA mode of EDMA3
+ * operation, we have to "Trigger" the transfer multiple times.
+ * Number of times depends upon the Mode (A/AB Sync)
+ * and the different counts.
+ */
+ if (result == EDMA3_DRV_SOK)
+ {
+ /*Need to activate next param*/
+ if (syncType == EDMA3_DRV_SYNC_A)
+ {
+ numenabled = bcnt * ccnt;
+ }
+ else
+ {
+ /* AB Sync Transfer Mode */
+ numenabled = ccnt;
+ }
+
+ for (i = 0u; i < numenabled; i++)
+ {
+ irqRaised1 = 0u;
+
+ if (i == (numenabled-1u))
+ {
+ /**
+ * Since OPT.STATIC field should be SET for isolated QDMA
+ * transfers or for the final transfer in a linked list of QDMA
+ * transfers, do the needful for the last request.
+ */
+ result = EDMA3_DRV_setOptField (hEdma, qCh1Id,
+ EDMA3_DRV_OPT_FIELD_STATIC, 1u);
+ }
+
+ /* Write to the Source Address */
+ result = EDMA3_DRV_setSrcParams (hEdma, qCh1Id,
+ (unsigned int)(srcBuff1),
+ EDMA3_DRV_ADDR_MODE_INCR,
+ EDMA3_DRV_W8BIT);
+ /*
+ * Now trigger the QDMA channel by writing to the Trigger
+ * Word which is set as Destination Address.
+ */
+ if (result == EDMA3_DRV_SOK)
+ {
+ result = EDMA3_DRV_setPaRAMEntry (hEdma, qCh1Id,
+ EDMA3_DRV_PARAM_ENTRY_DST,
+ (unsigned int)(dstBuff1));
+ if (result != EDMA3_DRV_SOK)
+ {
+ printf ("error from qdma_test\n\r\n");
+ break;
+ }
+ }
+
+ /* Wait for the Completion ISR. */
+ while (irqRaised1 == 0)
+ {
+ /* Wait for the Completion ISR. */
+ printf ("waiting for interrupt...\n");
+ }
+
+ /* Check the status of the completed transfer */
+ if (irqRaised1 < 0)
+ {
+ /* Some error occured, break from the FOR loop. */
+ printf ("\r\nqdma_test: Event Miss Occured!!!\r\n");
+
+ /* Clear the error bits first */
+ result = EDMA3_DRV_clearErrorBits (hEdma, qCh1Id);
+
+ break;
+ }
+
+ /**
+ * Now, update the source and destination addresses for next
+ * "Trigger".
+ */
+ srcBuff1 += srccidx;
+ dstBuff1 += descidx;
+ }
+ }
+
+ if (result == EDMA3_DRV_SOK)
+ {
+ /* Restore the src and dest buffers */
+ srcBuff1 = tmpSrcBuff1;
+ dstBuff1 = tmpDstBuff1;
+
+ /* Match the Source and Destination Buffers. */
+ for (i = 0u; i < (acnt*bcnt*ccnt); i++)
+ {
+ if (srcBuff1[i] != dstBuff1[i])
+ {
+ Istestpassed = 0u;
+ printf("qdma_test: Data write-read matching FAILED" \
+ " at i = %d\r\n", i);
+ break;
+ }
+ }
+ if (i == (acnt*bcnt*ccnt))
+ {
+ Istestpassed = 1u;
+ }
+
+ /* Free the previously allocated channel. */
+ result = EDMA3_DRV_freeChannel (hEdma, qCh1Id);
+ if (result != EDMA3_DRV_SOK)
+ {
+ printf("qdma_test: EDMA3_DRV_freeChannel() FAILED, error code: %d\r\n", result);
+ }
+ }
+
+ if(Istestpassed == 1u)
+ {
+ printf("qdma_test PASSED\r\n");
+ }
+ else
+ {
+ printf("qdma_test FAILED\r\n");
+ result = ((EDMA3_DRV_SOK == result) ?
+ EDMA3_DATA_MISMATCH_ERROR : result);
+ }
+
+ return result;
+ }
+
+