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-<h1>edma3_drv.h File Reference</h1>EDMA3 Controller. <a href="#_details">More...</a>
+<h1>edma3_drv.h File Reference</h1>EDMA3 Controller.
+<a href="#_details">More...</a>
<p>
<code>#include <ti/sdo/edma3/rm/edma3_rm.h></code><br>
<p>
-<a href="edma3__drv_8h-source.html">Go to the source code of this file.</a><table border="0" cellpadding="0" cellspacing="0">
+<a href="edma3__drv_8h_source.html">Go to the source code of this file.</a><table border="0" cellpadding="0" cellspacing="0">
<tr><td></td></tr>
<tr><td colspan="2"><br><h2>Data Structures</h2></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">struct </td><td class="memItemRight" valign="bottom"><a class="el" href="structEDMA3__DRV__GblConfigParams.html">EDMA3_DRV_GblConfigParams</a></td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Free the specified channel (DMA/QDMA/Link) and its associated resources (PaRAM Set, TCC etc) and removes various mappings. <a href="group__Edma3DrvChannelSetup.html#g0589ed9b15b42ecefc4a6ccd8e1758fc"></a><br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group__Edma3DrvChannelSetup.html#g35daa16c899b38d5af19d7d2d22777a5">EDMA3_DRV_clearErrorBits</a> (EDMA3_DRV_Handle hEdma, unsigned int channelId)</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">Clears Event Register and Error Register for a specific DMA channel and brings back EDMA3 to its initial state. <a href="group__Edma3DrvChannelSetup.html#g35daa16c899b38d5af19d7d2d22777a5"></a><br></td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">Disables the DMA Channel by clearing the Event Enable Register and clears Error Register & Secondary Event Register for a specific DMA channel. <a href="group__Edma3DrvChannelSetup.html#g35daa16c899b38d5af19d7d2d22777a5"></a><br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group__Edma3DrvChannelSetup.html#ga8561ee446bd1b9d0c5c4b106c9f40a9">EDMA3_DRV_linkChannel</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh1, unsigned int lCh2)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Link two logical channels. <a href="group__Edma3DrvChannelSetup.html#ga8561ee446bd1b9d0c5c4b106c9f40a9"></a><br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group__Edma3DrvTransferSetupType.html#gdb56f2a6d896c03a77f14c8fdf57a397">EDMA3_DRV_disableTransfer</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh, <a class="el" href="group__Edma3DrvTransferSetupType.html#g9a3d4fdcf4d2d089d4defebe3ef3880e">EDMA3_DRV_TrigMode</a> trigMode)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Disable DMA transfer on the specified channel. <a href="group__Edma3DrvTransferSetupType.html#gdb56f2a6d896c03a77f14c8fdf57a397"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group__Edma3DrvTransferSetupType.html#g11070a2e9fb80e16fe96e8ad210e0b59">EDMA3_DRV_disableLogicalChannel</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh, <a class="el" href="group__Edma3DrvTransferSetupType.html#g9a3d4fdcf4d2d089d4defebe3ef3880e">EDMA3_DRV_TrigMode</a> trigMode)</td></tr>
+
+<tr><td class="mdescLeft"> </td><td class="mdescRight">Disable the event driven DMA channel or QDMA channel. <a href="group__Edma3DrvTransferSetupType.html#g11070a2e9fb80e16fe96e8ad210e0b59"></a><br></td></tr>
<tr><td class="memItemLeft" nowrap align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group__Edma3DrvTransferSetupOpt.html#g669ea0f2097604af17b9213a28985191">EDMA3_DRV_setQdmaTrigWord</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_RM_QdmaTrigWord trigWord)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Assign a Trigger Word to the specified QDMA channel. <a href="group__Edma3DrvTransferSetupOpt.html#g669ea0f2097604af17b9213a28985191"></a><br></td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Return the previously opened EDMA3 Driver Instance handle. <a href="group__Edma3DrvTransferSetupOpt.html#g866c17eaf78a3e0ddc83a397b91fe850"></a><br></td></tr>
</table>
-<hr><a name="_details"></a><h2>Detailed Description</h2>
+<hr><h2>Detailed Description</h2>
EDMA3 Controller.
<p>
This file contains Application Interface for the EDMA3 Driver. EDMA3 Driver uses the EDMA3 Resource Manager internally for resource allocation, interrupt handling and EDMA3 registers programming.<p>
@@ -547,8 +557,8 @@ This file contains Application Interface for the EDMA3 Driver. EDMA3 Driver uses
<li>Added documentation</li><li>Moved SoC specific defines to SoC specific header. 0.2.0 Anuj Aggarwal - Modified it for EDMA3 package</li><li>Added multiple instances capability 0.2.1 Anuj Aggarwal - Modified it for more run time configuration.</li><li>Made EDMA3 package OS independent. 0.2.2 Anuj Aggarwal - Critical section handling code modification. Uses semaphore and interrupts disabling mechanism for resource sharing. 0.3.0 Anuj Aggarwal - Renamed EDMA3_DVR to EDMA3_DRV</li><li>IPR bit clearing in RM ISR issue fixed.</li><li>Sample application made generic 0.3.1 Anuj Aggarwal - Added DMA/QDMA Channel to TCC mapping, to fix QDMA missed event issue. 0.3.2 Anuj Aggarwal - Added support for POLL mode</li><li>Added a new API to modify the CC Register. 1.0.0 Anuj Aggarwal - Fixed resource allocation related bugs. 1.0.0.1 Anuj Aggarwal - Fixed spurious missed event generation related bug. 1.0.0.2 Anuj Aggarwal - Made the EDMA3 package RTSC compliant. 1.0.0.3 Anuj Aggarwal - Changed the directory structure as per RTSC standard. 1.01.00.01 Anuj Aggarwal - a) Added new APIs to allocate logical channels b) Created EDMA3 config files for different platforms c) Misc changes 1.02.00.01 Anuj Aggarwal - a) Added DM6467 support b) Fixed some MRs 1.03.00.01 Anuj Aggarwal - a) Added non-RTSC PJT files b) IOCTL Interface added. c) Fixed some MRs. 1.04 Anuj Aggarwal - a) Header files modified to have extern "C" declarations. b) Implemented ECNs DPSP00009815 & DPSP00010035. </li></ul>
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