Revert "Revert "Merge branch 'master' into edma3_keystone2""

[keystone-rtos/edma3_lld.git] / packages / ti / sdo / edma3 / drv / edma3_drv.h

diff --git a/packages/ti/sdo/edma3/drv/edma3_drv.h b/packages/ti/sdo/edma3/drv/edma3_drv.h
index 8a58fee47813ee0db0c7ec0e7c3653af441a7f1b..bf0dba1a07975593fa2c95d0f6e7273f13db2845 100755 (executable)
--- a/packages/ti/sdo/edma3/drv/edma3_drv.h
+++ b/packages/ti/sdo/edma3/drv/edma3_drv.h
@@ -102,13 +102,13 @@ extern "C" {
   * format:
   *  0xAABBCCDD -> Arch (AA); API Changes (BB); Major (CC); Minor (DD) 
   */
-#define EDMA3_LLD_DRV_VERSION_ID                   (0x020B0B0D)
+#define EDMA3_LLD_DRV_VERSION_ID                   (0x020B0C10)
 
 /**
  * @brief   This is the version string which describes the EDMA3 LLD along with the
  * date and build information.
  */
-#define EDMA3_LLD_DRV_VERSION_STR                  "EDMA3 LLD Revision: 02.11.11.15"
+#define EDMA3_LLD_DRV_VERSION_STR                  "EDMA3 LLD Revision: 02.11.12.16"
 
 
 /** @brief EDMA3 Driver Error Codes Base define */
@@ -682,7 +682,7 @@ EDMA3_DRV_Result EDMA3_DRV_close (EDMA3_DRV_Handle hEdma,
  * DMA channel from the pool of (owned && non_reserved && available_right_now)
  * DMA channels will be chosen and returned.
  */
-#define EDMA3_DRV_DMA_CHANNEL_ANY                   1002u
+#define EDMA3_DRV_DMA_CHANNEL_ANY                   1002U
 
 /**
  * Used to specify any available QDMA Channel while requesting
@@ -690,7 +690,7 @@ EDMA3_DRV_Result EDMA3_DRV_close (EDMA3_DRV_Handle hEdma,
  * QDMA channel from the pool of (owned && non_reserved && available_right_now)
  * QDMA channels will be chosen and returned.
  */
-#define EDMA3_DRV_QDMA_CHANNEL_ANY                  1003u
+#define EDMA3_DRV_QDMA_CHANNEL_ANY                  1003U
 
 /**
  * Used to specify any available TCC while requesting
@@ -699,7 +699,7 @@ EDMA3_DRV_Result EDMA3_DRV_close (EDMA3_DRV_Handle hEdma,
  * TCC from the pool of (owned && non_reserved && available_right_now)
  * TCCs will be chosen and returned.
  */
-#define EDMA3_DRV_TCC_ANY                           1004u
+#define EDMA3_DRV_TCC_ANY                           1004U
 
 /**
  * Used to specify any available PaRAM Set while requesting
@@ -707,7 +707,7 @@ EDMA3_DRV_Result EDMA3_DRV_close (EDMA3_DRV_Handle hEdma,
  * PaRAM Set from the pool of (owned && non_reserved && available_right_now)
  * PaRAM Sets will be chosen and returned.
  */
-#define EDMA3_DRV_LINK_CHANNEL                      1005u
+#define EDMA3_DRV_LINK_CHANNEL                      1005U
 
 /**
  * Used to specify any available PaRAM Set while requesting one. Used in the
@@ -717,7 +717,7 @@ EDMA3_DRV_Result EDMA3_DRV_close (EDMA3_DRV_Handle hEdma,
  * PaRAM Set from the pool of (owned && non_reserved && available_right_now)
  * PaRAM Sets will be chosen and returned.
  */
-#define EDMA3_DRV_LINK_CHANNEL_WITH_TCC                                1006u
+#define EDMA3_DRV_LINK_CHANNEL_WITH_TCC                                1006U
 
 /**
 @}
@@ -895,19 +895,19 @@ typedef enum
 /** QDMA Channel 0 */
 #define EDMA3_DRV_QDMA_CHANNEL_0    (EDMA3_MAX_DMA_CH + EDMA3_MAX_PARAM_SETS)
 /** QDMA Channel 1 */
-#define EDMA3_DRV_QDMA_CHANNEL_1    (EDMA3_DRV_QDMA_CHANNEL_0+1u)
+#define EDMA3_DRV_QDMA_CHANNEL_1    (EDMA3_DRV_QDMA_CHANNEL_0+1U)
 /** QDMA Channel 2 */
-#define EDMA3_DRV_QDMA_CHANNEL_2    (EDMA3_DRV_QDMA_CHANNEL_0+2u)
+#define EDMA3_DRV_QDMA_CHANNEL_2    (EDMA3_DRV_QDMA_CHANNEL_0+2U)
 /** QDMA Channel 3 */
-#define EDMA3_DRV_QDMA_CHANNEL_3    (EDMA3_DRV_QDMA_CHANNEL_0+3u)
+#define EDMA3_DRV_QDMA_CHANNEL_3    (EDMA3_DRV_QDMA_CHANNEL_0+3U)
 /** QDMA Channel 4 */
-#define EDMA3_DRV_QDMA_CHANNEL_4    (EDMA3_DRV_QDMA_CHANNEL_0+4u)
+#define EDMA3_DRV_QDMA_CHANNEL_4    (EDMA3_DRV_QDMA_CHANNEL_0+4U)
 /** QDMA Channel 5 */
-#define EDMA3_DRV_QDMA_CHANNEL_5    (EDMA3_DRV_QDMA_CHANNEL_0+5u)
+#define EDMA3_DRV_QDMA_CHANNEL_5    (EDMA3_DRV_QDMA_CHANNEL_0+5U)
 /** QDMA Channel 6 */
-#define EDMA3_DRV_QDMA_CHANNEL_6    (EDMA3_DRV_QDMA_CHANNEL_0+6u)
+#define EDMA3_DRV_QDMA_CHANNEL_6    (EDMA3_DRV_QDMA_CHANNEL_0+6U)
 /** QDMA Channel 7 */
-#define EDMA3_DRV_QDMA_CHANNEL_7    (EDMA3_DRV_QDMA_CHANNEL_0+7u)
+#define EDMA3_DRV_QDMA_CHANNEL_7    (EDMA3_DRV_QDMA_CHANNEL_0+7U)
 
 /**
 @}
@@ -2983,13 +2983,13 @@ EDMA3_DRV_Result EDMA3_DRV_setTcErrorInt(uint32_t phyCtrllerInstId,
  * are used while returning the channel status from EDMA3_DRV_getChannelStatus().
  */
 /** Channel is clean; no pending event, completion interrupt and event miss interrupt */
-#define EDMA3_DRV_CHANNEL_CLEAN                                0x0000u
+#define EDMA3_DRV_CHANNEL_CLEAN                                0x0000U
 /** Pending event is detected on the DMA channel */
-#define EDMA3_DRV_CHANNEL_EVENT_PENDING                0x0001u
+#define EDMA3_DRV_CHANNEL_EVENT_PENDING                0x0001U
 /** Transfer completion interrupt is detected on the DMA/QDMA channel */
-#define EDMA3_DRV_CHANNEL_XFER_COMPLETE                0x0002u
+#define EDMA3_DRV_CHANNEL_XFER_COMPLETE                0x0002U
 /** Event miss error interrupt is detected on the DMA/QDMA channel */
-#define EDMA3_DRV_CHANNEL_ERR                          0x0004u
+#define EDMA3_DRV_CHANNEL_ERR                          0x0004U
 
 /**
 @}
@@ -3044,7 +3044,7 @@ EDMA3_DRV_Result EDMA3_DRV_mapTccLinkCh (EDMA3_DRV_Handle hEdma,
                                                 uint32_t linkCh,
                                                 uint32_t tcc);
 
-#define EDMA3_DRV_MAX_XBAR_EVENTS (63u)
+#define EDMA3_DRV_MAX_XBAR_EVENTS (63U)
 
 /**\struct  EDMA3_DRV_GblXbarToChanConfigParams
  * \brief   Init-time Configuration structure for EDMA3