index 56c07c27009ad859b28ddd55f66be55e5889c5ef..2c77bf8f2211657403fcd5e8252f35e5c0277807 100755 (executable)
* scheduling and synchronizing with EDMA transfers and many more.
*/
-#ifndef _EDMA3_DRV_H_
-#define _EDMA3_DRV_H_
+#ifndef EDMA3_DRV_H_
+#define EDMA3_DRV_H_
#include <stdint.h>
* format:
* 0xAABBCCDD -> Arch (AA); API Changes (BB); Major (CC); Minor (DD)
*/
-#define EDMA3_LLD_DRV_VERSION_ID (0x020B0C10)
+#define EDMA3_LLD_DRV_VERSION_ID (0x020C0118U)
/**
* @brief This is the version string which describes the EDMA3 LLD along with the
* date and build information.
*/
-#define EDMA3_LLD_DRV_VERSION_STR "EDMA3 LLD Revision: 02.11.13.17"
+#define EDMA3_LLD_DRV_VERSION_STR "EDMA3 LLD Revision: 02.12.01.25"
/** @brief EDMA3 Driver Error Codes Base define */
* This value should mandatorily be used to mark DMA channels with no initial
* mapping to specific PaRAM Sets.
*/
-#define EDMA3_DRV_CH_NO_PARAM_MAP EDMA3_RM_CH_NO_PARAM_MAP
+#define EDMA3_DRV_CH_NO_PARAM_MAP (EDMA3_RM_CH_NO_PARAM_MAP)
/**
* This define is used to specify that the DMA/QDMA channel is not tied to any
* This value should mandatorily be used to mark DMA channels with no initial
* mapping to specific TCCs.
*/
-#define EDMA3_DRV_CH_NO_TCC_MAP EDMA3_RM_CH_NO_TCC_MAP
+#define EDMA3_DRV_CH_NO_TCC_MAP (EDMA3_RM_CH_NO_TCC_MAP)
/**
@}
/**
* The OPT field (Offset Address 0x0 Bytes)
*/
- EDMA3_DRV_PARAM_ENTRY_OPT = 0,
+ EDMA3_DRV_PARAM_ENTRY_OPT = 0U,
/**
* The SRC field (Offset Address 0x4 Bytes)
*/
- EDMA3_DRV_PARAM_ENTRY_SRC = 1,
+ EDMA3_DRV_PARAM_ENTRY_SRC = 1U,
/**
* The (ACNT+BCNT) field (Offset Address 0x8 Bytes)
*/
- EDMA3_DRV_PARAM_ENTRY_ACNT_BCNT = 2,
+ EDMA3_DRV_PARAM_ENTRY_ACNT_BCNT = 2U,
/**
* The DST field (Offset Address 0xC Bytes)
*/
- EDMA3_DRV_PARAM_ENTRY_DST = 3,
+ EDMA3_DRV_PARAM_ENTRY_DST = 3U,
/**
* The (SRCBIDX+DSTBIDX) field (Offset Address 0x10 Bytes)
*/
- EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX = 4,
+ EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX = 4U,
/**
* The (LINK+BCNTRLD) field (Offset Address 0x14 Bytes)
*/
- EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD = 5,
+ EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD = 5U,
/**
* The (SRCCIDX+DSTCIDX) field (Offset Address 0x18 Bytes)
*/
- EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX = 6,
+ EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX = 6U,
/**
* The (CCNT+RSVD) field (Offset Address 0x1C Bytes)
*/
- EDMA3_DRV_PARAM_ENTRY_CCNT = 7
+ EDMA3_DRV_PARAM_ENTRY_CCNT = 7U
} EDMA3_DRV_PaRAMEntry;
* This is a mapping of the EDMA3 PaRAM set provided to the user
* for ease of modification of the individual fields
*/
-#ifndef _BIG_ENDIAN
+#if defined(EDMA_MODE_LITTLE_ENDIAN)
/* LITTLE_ENDIAN_MODE */
typedef struct {
/** OPT field of PaRAM Set */
*/
volatile uint16_t cCnt;
} EDMA3_DRV_PaRAMRegs;
-#endif /* #ifndef _BIG_ENDIAN */
+#endif
/**
* \brief Event queue priorities setup