Merge pull request #18 in PROCESSOR-SDK/edma3_lld from edma_fix_v2_PRSDK-3197 to...

[keystone-rtos/edma3_lld.git] / packages / ti / sdo / edma3 / drv / edma3_drv.h

diff --git a/packages/ti/sdo/edma3/drv/edma3_drv.h b/packages/ti/sdo/edma3/drv/edma3_drv.h
index ca099bc4b7ea208ff4933352d27b16e61fbe5321..2c77bf8f2211657403fcd5e8252f35e5c0277807 100755 (executable)
--- a/packages/ti/sdo/edma3/drv/edma3_drv.h
+++ b/packages/ti/sdo/edma3/drv/edma3_drv.h
@@ -47,8 +47,8 @@
  *  scheduling and synchronizing with EDMA transfers and many more.
  */
 
-#ifndef _EDMA3_DRV_H_
-#define _EDMA3_DRV_H_
+#ifndef EDMA3_DRV_H_
+#define EDMA3_DRV_H_
 
 #include <stdint.h>
 
@@ -102,13 +102,13 @@ extern "C" {
   * format:
   *  0xAABBCCDD -> Arch (AA); API Changes (BB); Major (CC); Minor (DD) 
   */
-#define EDMA3_LLD_DRV_VERSION_ID                   (0x020B0B0D)
+#define EDMA3_LLD_DRV_VERSION_ID                   (0x020C0118U)
 
 /**
  * @brief   This is the version string which describes the EDMA3 LLD along with the
  * date and build information.
  */
-#define EDMA3_LLD_DRV_VERSION_STR                  "EDMA3 LLD Revision: 02.11.11.15"
+#define EDMA3_LLD_DRV_VERSION_STR                  "EDMA3 LLD Revision: 02.12.01.25"
 
 
 /** @brief EDMA3 Driver Error Codes Base define */
@@ -189,7 +189,7 @@ extern "C" {
  * This value should mandatorily be used to mark DMA channels with no initial
  * mapping to specific PaRAM Sets.
  */
-#define EDMA3_DRV_CH_NO_PARAM_MAP           EDMA3_RM_CH_NO_PARAM_MAP
+#define EDMA3_DRV_CH_NO_PARAM_MAP           (EDMA3_RM_CH_NO_PARAM_MAP)
 
 /**
  * This define is used to specify that the DMA/QDMA channel is not tied to any
@@ -200,7 +200,7 @@ extern "C" {
  * This value should mandatorily be used to mark DMA channels with no initial
  * mapping to specific TCCs.
  */
-#define EDMA3_DRV_CH_NO_TCC_MAP             EDMA3_RM_CH_NO_TCC_MAP
+#define EDMA3_DRV_CH_NO_TCC_MAP             (EDMA3_RM_CH_NO_TCC_MAP)
 
 /**
 @}
@@ -1998,42 +1998,42 @@ typedef enum
     /**
      * The OPT field (Offset Address 0x0 Bytes)
      */
-    EDMA3_DRV_PARAM_ENTRY_OPT                       = 0,
+    EDMA3_DRV_PARAM_ENTRY_OPT                       = 0U,
 
     /**
      * The SRC field (Offset Address 0x4 Bytes)
      */
-    EDMA3_DRV_PARAM_ENTRY_SRC                       = 1,
+    EDMA3_DRV_PARAM_ENTRY_SRC                       = 1U,
 
     /**
      * The (ACNT+BCNT) field (Offset Address 0x8 Bytes)
      */
-    EDMA3_DRV_PARAM_ENTRY_ACNT_BCNT                 = 2,
+    EDMA3_DRV_PARAM_ENTRY_ACNT_BCNT                 = 2U,
 
     /**
      * The DST field (Offset Address 0xC Bytes)
      */
-    EDMA3_DRV_PARAM_ENTRY_DST                       = 3,
+    EDMA3_DRV_PARAM_ENTRY_DST                       = 3U,
 
     /**
      * The (SRCBIDX+DSTBIDX) field (Offset Address 0x10 Bytes)
      */
-    EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX              = 4,
+    EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX              = 4U,
 
     /**
      * The (LINK+BCNTRLD) field (Offset Address 0x14 Bytes)
      */
-    EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD              = 5,
+    EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD              = 5U,
 
     /**
      * The (SRCCIDX+DSTCIDX) field (Offset Address 0x18 Bytes)
      */
-    EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX              = 6,
+    EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX              = 6U,
 
     /**
      * The (CCNT+RSVD) field (Offset Address 0x1C Bytes)
      */
-    EDMA3_DRV_PARAM_ENTRY_CCNT                      = 7
+    EDMA3_DRV_PARAM_ENTRY_CCNT                      = 7U
 
 } EDMA3_DRV_PaRAMEntry;
 
@@ -2194,7 +2194,7 @@ typedef struct  {
  * This is a mapping of the EDMA3 PaRAM set provided to the user
  * for ease of modification of the individual fields
  */
-#ifndef _BIG_ENDIAN
+#if defined(EDMA_MODE_LITTLE_ENDIAN)
 /* LITTLE_ENDIAN_MODE */
 typedef struct  {
         /** OPT field of PaRAM Set */
@@ -2350,7 +2350,7 @@ typedef struct  {
          */
         volatile uint16_t cCnt;
 } EDMA3_DRV_PaRAMRegs;
-#endif         /* #ifndef _BIG_ENDIAN */
+#endif
 
 /**
  * \brief Event queue priorities setup