index 3cf4875b3c161076eafe4f2dc27dcd5e0051b518..8e760e0ae7c8eb183e72d7903d286df46a72f40f 100755 (executable)
* uses the EDMA3 Resource Manager internally for resource allocation, interrupt
* handling and EDMA3 registers programming.
*
- * Copyright (C) 2009-2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2009-2013 Texas Instruments Incorporated - http://www.ti.com/
*
*
* Redistribution and use in source and binary forms, with or without
* scheduling and synchronizing with EDMA transfers and many more.
*/
-#ifndef _EDMA3_DRV_H_
-#define _EDMA3_DRV_H_
+#ifndef EDMA3_DRV_H_
+#define EDMA3_DRV_H_
#include <stdint.h>
* format:
* 0xAABBCCDD -> Arch (AA); API Changes (BB); Major (CC); Minor (DD)
*/
-#define EDMA3_LLD_DRV_VERSION_ID (0x020B0601)
+#define EDMA3_LLD_DRV_VERSION_ID (0x020C0118U)
/**
* @brief This is the version string which describes the EDMA3 LLD along with the
* date and build information.
*/
-#define EDMA3_LLD_DRV_VERSION_STR "EDMA3 LLD Revision: 02.11.06.01"
+#define EDMA3_LLD_DRV_VERSION_STR "EDMA3 LLD Revision: 02.12.01.24"
/** @brief EDMA3 Driver Error Codes Base define */
* This value should mandatorily be used to mark DMA channels with no initial
* mapping to specific PaRAM Sets.
*/
-#define EDMA3_DRV_CH_NO_PARAM_MAP EDMA3_RM_CH_NO_PARAM_MAP
+#define EDMA3_DRV_CH_NO_PARAM_MAP (EDMA3_RM_CH_NO_PARAM_MAP)
/**
* This define is used to specify that the DMA/QDMA channel is not tied to any
* This value should mandatorily be used to mark DMA channels with no initial
* mapping to specific TCCs.
*/
-#define EDMA3_DRV_CH_NO_TCC_MAP EDMA3_RM_CH_NO_TCC_MAP
+#define EDMA3_DRV_CH_NO_TCC_MAP (EDMA3_RM_CH_NO_TCC_MAP)
/**
@}
* DMA channel from the pool of (owned && non_reserved && available_right_now)
* DMA channels will be chosen and returned.
*/
-#define EDMA3_DRV_DMA_CHANNEL_ANY 1002u
+#define EDMA3_DRV_DMA_CHANNEL_ANY 1002U
/**
* Used to specify any available QDMA Channel while requesting
* QDMA channel from the pool of (owned && non_reserved && available_right_now)
* QDMA channels will be chosen and returned.
*/
-#define EDMA3_DRV_QDMA_CHANNEL_ANY 1003u
+#define EDMA3_DRV_QDMA_CHANNEL_ANY 1003U
/**
* Used to specify any available TCC while requesting
* TCC from the pool of (owned && non_reserved && available_right_now)
* TCCs will be chosen and returned.
*/
-#define EDMA3_DRV_TCC_ANY 1004u
+#define EDMA3_DRV_TCC_ANY 1004U
/**
* Used to specify any available PaRAM Set while requesting
* PaRAM Set from the pool of (owned && non_reserved && available_right_now)
* PaRAM Sets will be chosen and returned.
*/
-#define EDMA3_DRV_LINK_CHANNEL 1005u
+#define EDMA3_DRV_LINK_CHANNEL 1005U
/**
* Used to specify any available PaRAM Set while requesting one. Used in the
* PaRAM Set from the pool of (owned && non_reserved && available_right_now)
* PaRAM Sets will be chosen and returned.
*/
-#define EDMA3_DRV_LINK_CHANNEL_WITH_TCC 1006u
+#define EDMA3_DRV_LINK_CHANNEL_WITH_TCC 1006U
/**
@}
/** QDMA Channel 0 */
#define EDMA3_DRV_QDMA_CHANNEL_0 (EDMA3_MAX_DMA_CH + EDMA3_MAX_PARAM_SETS)
/** QDMA Channel 1 */
-#define EDMA3_DRV_QDMA_CHANNEL_1 (EDMA3_DRV_QDMA_CHANNEL_0+1u)
+#define EDMA3_DRV_QDMA_CHANNEL_1 (EDMA3_DRV_QDMA_CHANNEL_0+1U)
/** QDMA Channel 2 */
-#define EDMA3_DRV_QDMA_CHANNEL_2 (EDMA3_DRV_QDMA_CHANNEL_0+2u)
+#define EDMA3_DRV_QDMA_CHANNEL_2 (EDMA3_DRV_QDMA_CHANNEL_0+2U)
/** QDMA Channel 3 */
-#define EDMA3_DRV_QDMA_CHANNEL_3 (EDMA3_DRV_QDMA_CHANNEL_0+3u)
+#define EDMA3_DRV_QDMA_CHANNEL_3 (EDMA3_DRV_QDMA_CHANNEL_0+3U)
/** QDMA Channel 4 */
-#define EDMA3_DRV_QDMA_CHANNEL_4 (EDMA3_DRV_QDMA_CHANNEL_0+4u)
+#define EDMA3_DRV_QDMA_CHANNEL_4 (EDMA3_DRV_QDMA_CHANNEL_0+4U)
/** QDMA Channel 5 */
-#define EDMA3_DRV_QDMA_CHANNEL_5 (EDMA3_DRV_QDMA_CHANNEL_0+5u)
+#define EDMA3_DRV_QDMA_CHANNEL_5 (EDMA3_DRV_QDMA_CHANNEL_0+5U)
/** QDMA Channel 6 */
-#define EDMA3_DRV_QDMA_CHANNEL_6 (EDMA3_DRV_QDMA_CHANNEL_0+6u)
+#define EDMA3_DRV_QDMA_CHANNEL_6 (EDMA3_DRV_QDMA_CHANNEL_0+6U)
/** QDMA Channel 7 */
-#define EDMA3_DRV_QDMA_CHANNEL_7 (EDMA3_DRV_QDMA_CHANNEL_0+7u)
+#define EDMA3_DRV_QDMA_CHANNEL_7 (EDMA3_DRV_QDMA_CHANNEL_0+7U)
/**
@}
/**
* The OPT field (Offset Address 0x0 Bytes)
*/
- EDMA3_DRV_PARAM_ENTRY_OPT = 0,
+ EDMA3_DRV_PARAM_ENTRY_OPT = 0U,
/**
* The SRC field (Offset Address 0x4 Bytes)
*/
- EDMA3_DRV_PARAM_ENTRY_SRC = 1,
+ EDMA3_DRV_PARAM_ENTRY_SRC = 1U,
/**
* The (ACNT+BCNT) field (Offset Address 0x8 Bytes)
*/
- EDMA3_DRV_PARAM_ENTRY_ACNT_BCNT = 2,
+ EDMA3_DRV_PARAM_ENTRY_ACNT_BCNT = 2U,
/**
* The DST field (Offset Address 0xC Bytes)
*/
- EDMA3_DRV_PARAM_ENTRY_DST = 3,
+ EDMA3_DRV_PARAM_ENTRY_DST = 3U,
/**
* The (SRCBIDX+DSTBIDX) field (Offset Address 0x10 Bytes)
*/
- EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX = 4,
+ EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX = 4U,
/**
* The (LINK+BCNTRLD) field (Offset Address 0x14 Bytes)
*/
- EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD = 5,
+ EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD = 5U,
/**
* The (SRCCIDX+DSTCIDX) field (Offset Address 0x18 Bytes)
*/
- EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX = 6,
+ EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX = 6U,
/**
* The (CCNT+RSVD) field (Offset Address 0x1C Bytes)
*/
- EDMA3_DRV_PARAM_ENTRY_CCNT = 7
+ EDMA3_DRV_PARAM_ENTRY_CCNT = 7U
} EDMA3_DRV_PaRAMEntry;
* are used while returning the channel status from EDMA3_DRV_getChannelStatus().
*/
/** Channel is clean; no pending event, completion interrupt and event miss interrupt */
-#define EDMA3_DRV_CHANNEL_CLEAN 0x0000u
+#define EDMA3_DRV_CHANNEL_CLEAN 0x0000U
/** Pending event is detected on the DMA channel */
-#define EDMA3_DRV_CHANNEL_EVENT_PENDING 0x0001u
+#define EDMA3_DRV_CHANNEL_EVENT_PENDING 0x0001U
/** Transfer completion interrupt is detected on the DMA/QDMA channel */
-#define EDMA3_DRV_CHANNEL_XFER_COMPLETE 0x0002u
+#define EDMA3_DRV_CHANNEL_XFER_COMPLETE 0x0002U
/** Event miss error interrupt is detected on the DMA/QDMA channel */
-#define EDMA3_DRV_CHANNEL_ERR 0x0004u
+#define EDMA3_DRV_CHANNEL_ERR 0x0004U
/**
@}
uint32_t linkCh,
uint32_t tcc);
-#define EDMA3_DRV_MAX_XBAR_EVENTS (63u)
+#define EDMA3_DRV_MAX_XBAR_EVENTS (63U)
/**\struct EDMA3_DRV_GblXbarToChanConfigParams
* \brief Init-time Configuration structure for EDMA3