index 6343122f461ef3653ec3de3c5d51ee14c746413d..8e760e0ae7c8eb183e72d7903d286df46a72f40f 100755 (executable)
* uses the EDMA3 Resource Manager internally for resource allocation, interrupt
* handling and EDMA3 registers programming.
*
- * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2009-2013 Texas Instruments Incorporated - http://www.ti.com/
*
*
* Redistribution and use in source and binary forms, with or without
*
*/
-#ifndef _EDMA3_DRV_H_
-#define _EDMA3_DRV_H_
+/** @defgroup EDMA3_LLD_DRV_API EDMA3 Driver
+ *
+ * @section Introduction
+ *
+ * @subsection xxx Overview
+ * EDMA3 Driver is a functional library providing APIs for programming,
+ * scheduling and synchronizing with EDMA transfers and many more.
+ */
+#ifndef EDMA3_DRV_H_
+#define EDMA3_DRV_H_
+
+#include <stdint.h>
/* Include the Resource Manager header file */
#include <ti/sdo/edma3/rm/edma3_rm.h>
#endif
/**
- * \defgroup Edma3DrvMain EDMA3 Driver Interface Definition
- *
- * Top-level Encapsulation of all documentation for EDMA3 Driver
- *
- * @{
- */
-
-
-/*---------------------------------------------------------------------------*/
-/*------------------Usage Guidelines Start-----------------------------------*/
-/*---------------------------------------------------------------------------*/
+@defgroup EDMA3_LLD_DRV_SYMBOL EDMA3 Driver Symbols
+@ingroup EDMA3_LLD_DRV_API
+*/
+/**
+@defgroup EDMA3_LLD_DRV_DATASTRUCT EDMA3 Driver Data Structures
+@ingroup EDMA3_LLD_DRV_API
+*/
+/**
+@defgroup EDMA3_LLD_DRV_FUNCTION EDMA3 Driver APIs
+@ingroup EDMA3_LLD_DRV_API
+*/
/**
- * \defgroup Edma3DrvUsage EDMA3 Driver Usage Guidelines
- *
- * Guidelines for typical usage of EDMA3 Driver.
- *
- * @{
- */
-
-
-/**
- \brief Usage of EDMA3 Driver.
-
- -# Create EDMA3 Driver Object (one for each EDMA3 hardware instance)
- - EDMA3_DRV_Result result = EDMA3_DRV_SOK;
- - unsigned int edma3HwInstanceId = 0;
- - EDMA3_DRV_GblConfigParams *gblCfgParams = NULL;
- - Init-time Configuration structure for EDMA3 controller, to provide
- Global SoC specific Information. This could be NULL also. In that
- case, static configuration will be taken.
- - result = EDMA3_DRV_create (edma3HwInstanceId, gblCfgParams, NULL);
-
- -# Open EDMA3 driver Instance
- - Steps
- - EDMA3_DRV_InitConfig initCfg;
- - EDMA3_DRV_Handle hEdma = NULL;
- - EDMA3_OS_SemAttrs semAttrs = {EDMA3_OS_SEMTYPE_FIFO, NULL};
- - EDMA3_DRV_Result edmaResult;
- -To get the error code while opening driver instance
-
- -# initCfg.regionId = One of the possible regions available
- for eg, (EDMA3_RM_RegionId)0 or (EDMA3_RM_RegionId)1 etc, for
- different masters.
-
- -# initCfg.isMaster = TRUE/FALSE (Whether this EDMA3
- DRV instance is Master or not. The EDMA3 Shadow Region tied to
- the Master DRV Instance will ONLY receive the EDMA3 interrupts
- (error or completion), if enabled).
-
- -# initCfg.drvSemHandle =
- EDMA3 DRV Instance specific semaphore handle. It should
- be provided by the user for proper sharing of resources.
- - edma3Result = edma3OsSemCreate(1, &semAttrs,
- &initCfg.drvSemHandle);
-
- -# initCfg.drvInstInitConfig =
- Init-time Region Specific Configuration Structure. It can be
- provided by the user at run-time. If not provided by the user,
- this info would be taken from the platform specific config file,
- if it exists.
-
- -# initCfg.drvInstInitConfig->ownDmaChannels[] =
- The bitmap(s) which indicate the DMA channels owned by this
- instance of the EDMA3 Driver\n
- E.g. A '1' at bit position 24 indicates that this instance of
- the EDMA3 Driver owns DMA Channel Id 24\n
- Later when a request is made based on a particular Channel Id,
- the EDMA3 Driver will check first if it owns that channel.
- If it doesnot own it, EDMA3 Driver returns error.
- -# initCfg.drvInstInitConfig->ownQdmaChannels[] =
- The bitmap(s) which indicate the QDMA channels owned by this
- instance of the EDMA3 Driver \n
- -# initCfg.drvInstInitConfig->ownPaRAMSets[] =
- The bitmap(s) which indicate the PaRAM Sets owned by this
- instance of the EDMA3 Driver \n
- -# initCfg.drvInstInitConfig->ownTccs[] =
- The bitmap(s) which indicate the TCCs owned by this
- instance of the EDMA3 Driver \n
-
- -# initCfg.drvInstInitConfig->resvdDmaChannels[] =
- The bitmap(s) which indicate the DMA channels reserved by this
- instance of the EDMA3 Driver \n
- E.g. A '1' at bit position 24 indicates that this instance of
- the EDMA3 Driver reserves Channel Id 24\n
- These channels are reserved and may be mapped to HW events,
- these are not given to 'EDMA3_DRV_DMA_CHANNEL_ANY' requests.\n
- -# initCfg.drvInstInitConfig->resvdQdmaChannels[] =
- The bitmap(s) which indicate the QDMA channels reserved by this
- instance of the EDMA3 Driver \n
- E.g. A '1' at bit position 1 indicates that this instance of
- the EDMA3 Driver reserves QDMA Channel Id 1\n
- These channels are reserved for some specific purpose,
- these are not given to 'EDMA3_DRV_QDMA_CHANNEL_ANY' request\n
- -# initCfg.drvInstInitConfig->resvdPaRAMSets[] =
- PaRAM Sets which are reserved by this Region;
- -# initCfg.drvInstInitConfig->resvdTccs[] =
- TCCs which are reserved by this Region;
-
-
- -# initCfg.gblerrCb =
- Instance wide callback function to catch non-channel specific
- errors;
- -# initCfg.gblerrData =
- Application data to be passed back to the callback function;
-
- -# hEdma = EDMA3_DRV_open(edma3HwInstanceId, &initCfg, &edmaResult);
-
- -# EDMA3 driver APIs
- - EDMA3_RM_ResDesc resObj;
- - EDMA3_DRV_Result result;
- - unsigned int ch1Id = 0;
- - unsigned int ch2Id = 0;
- - unsigned int tcc1 = 0;
- - unsigned int tcc2 = 0;
- - unsigned int qCh1Id = 0;
- - unsigned int qTcc1 = 0;
- - unsigned int qCh2Id = 0;
- - unsigned int qTcc2 = 0;
- - unsigned int paRAMId;
- - int srcbidx = 0;
- - int desbidx = 0;
- - int srccidx = 0;
- - int descidx = 0;
- - unsigned int acnt = 0;
- - unsigned int bcnt = 0;
- - unsigned int ccnt = 0;
- - unsigned int bcntreload = 0;
- - EDMA3_DRV_SyncType synctype;
- - EDMA3_RM_TccCallback tccCb;
- - void *cbData;
- -
- - Use Case 1: Memory to memory transfer on any available
- - DMA Channel\n\n
- - tcc1 = EDMA3_DRV_TCC_ANY;
- - ch1Id = EDMA3_DRV_DMA_CHANNEL_ANY;
- - result = EDMA3_DRV_requestChannel (hEdma, &ch1Id, &tcc1,
- (EDMA3_RM_EventQueue)0, &callback1, NULL);
-
- - result = EDMA3_DRV_setSrcParams (hEdma, ch1Id,
- (unsigned int)(srcBuff1),
- EDMA3_DRV_ADDR_MODE_INCR,
- EDMA3_DRV_W8BIT);
- - result = EDMA3_DRV_setDestParams (hEdma, ch1Id,
- (unsigned int)(dstBuff1),
- EDMA3_DRV_ADDR_MODE_INCR,
- EDMA3_DRV_W8BIT);
-
- - Set EDMA transfer parameters (aCnt, bCnt, cCnt, bCntReload,
- SyncType)
- acnt = 256; bcnt = 1; ccnt = 1, bcntreload = 0;
- synctype = EDMA3_DRV_SYNC_A;
- - result = EDMA3_DRV_setTransferParams (hEdma, ch1Id, acnt, bcnt,
- ccnt, bcntreload, synctype);
-
- - Set srcbidx and srccidx to the appropriate values
- - srcbidx = acnt; srccidx = acnt;
- - result = EDMA3_DRV_setSrcIndex (hEdma, ch1Id, srcbidx, srccidx);
-
- - Set desbidx and descidx to the appropriate values
- - desbidx = acnt; descidx = acnt;
- - result = EDMA3_DRV_setDestIndex (hEdma, ch1Id, desbidx, descidx);
-
- - Enable the final completion interrupt.
- - result = EDMA3_DRV_setOptField (hEdma, ch1Id,
- EDMA3_DRV_OPT_FIELD_TCINTEN, 1);
-
- - Enable the transfer
- - result = EDMA3_DRV_enableTransfer (hEdma, ch1Id,
- EDMA3_DRV_TRIG_MODE_MANUAL);
-
- - Use Case 2: Linked memory to memory transfer on any available
- - DMA Channel\n\n
- - Perform steps as for Use Case 1 for the Master logical channel
- ch1Id for configuration. DONOT enable the transfer for ch1Id.
- - Configure link channel, ch2Id.
- - tcc2 = EDMA3_DRV_TCC_ANY;
- - ch2Id = EDMA3_DRV_LINK_CHANNEL;
- - result = EDMA3_DRV_requestChannel (hEdma, &ch2Id, &tcc2,
- (EDMA3_RM_EventQueue)0, &callback2, NULL);
-
- - result = EDMA3_DRV_setSrcParams (hEdma, ch2Id,
- (unsigned int)(srcBuff2),
- EDMA3_DRV_ADDR_MODE_INCR,
- EDMA3_DRV_W8BIT);
- - result = EDMA3_DRV_setDestParams (hEdma, ch2Id,(
- unsigned int)(dstBuff2),
- EDMA3_DRV_ADDR_MODE_INCR,
- EDMA3_DRV_W8BIT);
-
- - result = EDMA3_DRV_setSrcIndex (hEdma, ch2Id, srcbidx, srccidx);
- - result = EDMA3_DRV_setDestIndex (hEdma, ch2Id, desbidx, descidx);
-
- - result = EDMA3_DRV_setTransferParams (hEdma, ch2Id, acnt, bcnt,
- ccnt, bcntreload, synctype);
-
- - Link both the channels
- - result = EDMA3_DRV_linkChannel (hEdma, ch1Id, ch2Id);
-
- - Enable the final completion interrupts on both the channels
- - result = EDMA3_DRV_setOptField (hEdma, ch1Id,
- EDMA3_DRV_OPT_FIELD_TCINTEN, 1);
- - result = EDMA3_DRV_setOptField (hEdma, ch2Id,
- EDMA3_DRV_OPT_FIELD_TCINTEN, 1);
-
- - Enable the transfer on channel 1.
- - result = EDMA3_DRV_enableTransfer (hEdma, ch1Id,
- EDMA3_DRV_TRIG_MODE_MANUAL);
- - Wait for the completion interrupt on Ch1 and then enable the
- transfer again for the LINK channel, to provide the required
- sync event.
- - result = EDMA3_DRV_enableTransfer (hEdma, ch1Id,
- EDMA3_DRV_TRIG_MODE_MANUAL);
-
- - Note: Enabling of transfers on channel 1 (for master and link
- channel) is required as many number of times as the sync events
- are required. For ASync mode, number of sync events=(bcnt * ccnt)
- and for ABSync mode, number of sync events = ccnt.
-
- - Use Case 3: Memory to memory transfer on any available
- - QDMA Channel\n\n
- - qTcc1 = EDMA3_DRV_TCC_ANY;
- - qCh1Id = EDMA3_DRV_QDMA_CHANNEL_ANY;
-
- - result = EDMA3_DRV_requestChannel (hEdma, &qCh1Id, &qTcc1,
- (EDMA3_RM_EventQueue)0, &callback1, NULL);
-
- - Set the QDMA trigger word.
- - result = EDMA3_DRV_setQdmaTrigWord (hEdma, qCh1Id,
- EDMA3_RM_QDMA_TRIG_DST);
- - Note: DONOT write the destination address (trigger word) before
- completing the configuration as it will trigger the
- transfer. Also, DONOT use EDMA3_DRV_setDestParams() to set
- the destination address as it also sets other parameters.
- Use EDMA3_DRV_setPaRAMEntry() to set the destination address
-
- - result = EDMA3_DRV_setSrcParams (hEdma, qCh1Id,
- (unsigned int)(srcBuff1),
- EDMA3_DRV_ADDR_MODE_INCR,
- EDMA3_DRV_W8BIT);
-
- - Set QDMA transfer parameters (aCnt, bCnt, cCnt, bCntReload,
- SyncType)
- acnt = 256; bcnt = 1; ccnt = 1, bcntreload = 0;
- synctype = EDMA3_DRV_SYNC_A;
- - result = EDMA3_DRV_setTransferParams (hEdma, qCh1Id, acnt, bcnt,
- ccnt, bcntreload, synctype);
-
- - srcbidx = acnt; srccidx = acnt; desbidx = acnt; descidx = acnt;
- - result = EDMA3_DRV_setSrcIndex (hEdma, qCh1Id, srcbidx, srccidx);
- - result = EDMA3_DRV_setDestIndex (hEdma, qCh1Id, desbidx, descidx);
-
- - Enable the final completion interrupt.
- - result = EDMA3_DRV_setOptField (hEdma, qCh1Id,
- EDMA3_DRV_OPT_FIELD_TCINTEN, 1);
-
- - Set the Destination Addressing Mode as Increment
- - result = EDMA3_DRV_setOptField (hEdma, qCh1Id,
- EDMA3_DRV_OPT_FIELD_DAM,
- EDMA3_DRV_ADDR_MODE_INCR);
-
- - Trigger the QDMA channel by writing the destination address
- - result = EDMA3_DRV_setPaRAMEntry (hEdma, qCh1Id,
- EDMA3_DRV_PARAM_ENTRY_DST,
- (unsigned int)(dstBuff1));
-
- -
- - Use Case 4: Linked memory to memory transfer on any available
- - QDMA Channel\n\n
- - Setup for any QDMA Channel
- - qTcc1 = EDMA3_DRV_TCC_ANY;
- - qCh1Id = EDMA3_DRV_QDMA_CHANNEL_ANY;
- - result = EDMA3_DRV_requestChannel (hEdma, &qCh1Id, &qTcc1,
- (EDMA3_RM_EventQueue)0, &callback1, NULL);
-
- - Setup for Channel 2
- - qCh2Id = EDMA3_DRV_LINK_CHANNEL;
- - qTcc2 = EDMA3_DRV_TCC_ANY;
- - result = EDMA3_DRV_requestChannel (hEdma, &qCh2Id, &qTcc2,
- (EDMA3_RM_EventQueue)0,
- &callback2, NULL);
-
- - result = EDMA3_DRV_setSrcParams (hEdma, qCh2Id,
- (unsigned int)(srcBuff2),
- EDMA3_DRV_ADDR_MODE_INCR,
- EDMA3_DRV_W8BIT);
- - result = EDMA3_DRV_setDestParams(hEdma, qCh2Id,
- (unsigned int)(dstBuff2),
- EDMA3_DRV_ADDR_MODE_INCR,
- EDMA3_DRV_W8BIT);
-
- - acnt = 256; bcnt = 1; ccnt = 1, bcntreload = 0;
- synctype = EDMA3_DRV_SYNC_A;
- - result = EDMA3_DRV_setTransferParams (hEdma, qCh2Id, acnt, bcnt,
- ccnt, BRCnt,
- EDMA3_DRV_SYNC_A);
-
- - srcbidx = acnt; srccidx = acnt; desbidx = acnt; descidx = acnt;
- - result = EDMA3_DRV_setSrcIndex (hEdma, qCh2Id, srcbidx, srccidx);
- - result = EDMA3_DRV_setDestIndex (hEdma, qCh2Id, desbidx, descidx);
-
- - result = EDMA3_DRV_setOptField (hEdma, qCh2Id,
- EDMA3_DRV_OPT_FIELD_TCINTEN, 1);
-
- - Make the PaRAM Set associated with qCh2Id as Static
- - result = EDMA3_DRV_setOptField (hEdma, qCh2Id,
- EDMA3_DRV_OPT_FIELD_STATIC, 1u);
-
- - Link both the channels
- - result = EDMA3_DRV_linkChannel (hEdma,qCh1Id,qCh2Id);
-
- - Set the QDMA trigger word.
- - result = EDMA3_DRV_setQdmaTrigWord (hEdma, qCh1Id,
- EDMA3_DRV_QDMA_TRIG_DST);
- - Note: DONOT write the destination address (trigger word) before
- completing the configuration as it'll trigger the transfer.
- Also, DONOT use EDMA3_DRV_setDestParams () function to set
- the destination address as it also sets other parameters.
- Use EDMA3_DRV_setPaRAMEntry() to set the dest address.
-
- - result = EDMA3_DRV_setSrcParams (hEdma, qCh1Id,
- (unsigned int)(srcBuff1),
- EDMA3_DRV_ADDR_MODE_INCR,
- EDMA3_DRV_W8BIT);
-
- - Set QDMA transfer parameters (aCnt, bCnt, cCnt, bCntReload,
- SyncType)
- acnt = 256; bcnt = 1; ccnt = 1, bcntreload = 0;
- synctype = EDMA3_DRV_SYNC_A;
- - result = EDMA3_DRV_setTransferParams (hEdma, qCh1Id, acnt, bcnt,
- ccnt, bcntreload, synctype);
-
- - srcbidx = acnt; srccidx = acnt; desbidx = acnt; descidx = acnt;
- - result = EDMA3_DRV_setSrcIndex (hEdma, qCh1Id, srcbidx, srccidx);
- - result = EDMA3_DRV_setDestIndex (hEdma, qCh1Id, desbidx, descidx);
-
- - result = EDMA3_DRV_setOptField (hEdma, qCh1Id,
- EDMA3_DRV_OPT_FIELD_TCINTEN, 1);
-
- - Set the Destination Addressing Mode as Increment
- - result = EDMA3_DRV_setOptField (hEdma, qCh1Id,
- EDMA3_DRV_OPT_FIELD_DAM,
- EDMA3_DRV_ADDR_MODE_INCR);
-
- - Trigger the QDMA channel by writing the destination address
- - result = EDMA3_DRV_setPaRAMEntry (hEdma, qCh1Id,
- EDMA3_DRV_PARAM_ENTRY_DST,
- (unsigned int)(dstBuff1));
+@defgroup EDMA3_LLD_DRV_SYMBOL_DEFINE EDMA3 Driver Defines
+@ingroup EDMA3_LLD_DRV_SYMBOL
+*/
+/**
+@defgroup EDMA3_LLD_DRV_SYMBOL_ENUM EDMA3 Driver Enums
+@ingroup EDMA3_LLD_DRV_SYMBOL
+*/
+/**
+@defgroup EDMA3_LLD_DRV_FUNCTION_INIT EDMA3 Driver Initialization APIs
+@ingroup EDMA3_LLD_DRV_FUNCTION
+*/
+/**
+@defgroup EDMA3_LLD_DRV_FUNCTION_BASIC EDMA3 Driver Basic APIs
+@ingroup EDMA3_LLD_DRV_FUNCTION
+*/
+/**
+@defgroup EDMA3_LLD_DRV_FUNCTION_ADVANCED EDMA3 Driver Advanced APIs
+@ingroup EDMA3_LLD_DRV_FUNCTION
*/
-/* @} Edma3DrvUsage */
-/*---------------------------------------------------------------------------*/
-/*------------------Usage Guidelines End-------------------------------------*/
-/*---------------------------------------------------------------------------*/
+/** @addtogroup EDMA3_LLD_DRV_SYMBOL_DEFINE
+ @{ */
+ /**
+ * @brief This is the EDMA3 LLD Version. Versions numbers are encoded in the following
+ * format:
+ * 0xAABBCCDD -> Arch (AA); API Changes (BB); Major (CC); Minor (DD)
+ */
+#define EDMA3_LLD_DRV_VERSION_ID (0x020C0118U)
/**
- * \defgroup Edma3DrvErrorCode EDMA3 Driver Error Codes
- *
- * Error Codes returned by the EDMA3 Driver
- *
- * @{
+ * @brief This is the version string which describes the EDMA3 LLD along with the
+ * date and build information.
*/
-/** EDMA3 Driver Error Codes Base define */
+#define EDMA3_LLD_DRV_VERSION_STR "EDMA3 LLD Revision: 02.12.01.24"
+
+
+/** @brief EDMA3 Driver Error Codes Base define */
#define EDMA3_DRV_E_BASE (-128)
/**
/** EDMA3 Driver Instance does not exist, it is not opened yet */
#define EDMA3_DRV_E_INST_NOT_OPENED (EDMA3_DRV_E_BASE-16)
-/* @} Edma3DrvErrorCode */
-
-
/**
* This define is used to specify that a DMA channel is NOT tied to any PaRAM
* Set and hence any available PaRAM Set could be used for that DMA channel.
* This value should mandatorily be used to mark DMA channels with no initial
* mapping to specific PaRAM Sets.
*/
-#define EDMA3_DRV_CH_NO_PARAM_MAP EDMA3_RM_CH_NO_PARAM_MAP
+#define EDMA3_DRV_CH_NO_PARAM_MAP (EDMA3_RM_CH_NO_PARAM_MAP)
/**
* This define is used to specify that the DMA/QDMA channel is not tied to any
* This value should mandatorily be used to mark DMA channels with no initial
* mapping to specific TCCs.
*/
-#define EDMA3_DRV_CH_NO_TCC_MAP EDMA3_RM_CH_NO_TCC_MAP
+#define EDMA3_DRV_CH_NO_TCC_MAP (EDMA3_RM_CH_NO_TCC_MAP)
+/**
+@}
+*/
+/** @addtogroup EDMA3_LLD_DRV_DATASTRUCT
+ @{ */
/**\struct EDMA3_DRV_GblConfigParams
* \brief Init-time Configuration structure for EDMA3
*/
typedef struct {
/** Number of DMA Channels supported by the underlying EDMA3 Controller. */
- unsigned int numDmaChannels;
+ uint32_t numDmaChannels;
/** Number of QDMA Channels supported by the underlying EDMA3 Controller */
- unsigned int numQdmaChannels;
+ uint32_t numQdmaChannels;
/**
* Number of Interrupt Channels supported by the underlying EDMA3
* Controller
*/
- unsigned int numTccs;
+ uint32_t numTccs;
/** Number of PaRAM Sets supported by the underlying EDMA3 Controller */
- unsigned int numPaRAMSets;
+ uint32_t numPaRAMSets;
/** Number of Event Queues in the underlying EDMA3 Controller */
- unsigned int numEvtQueue;
+ uint32_t numEvtQueue;
/**
* Number of Transfer Controllers (TCs) in the underlying EDMA3 Controller
*/
- unsigned int numTcs;
+ uint32_t numTcs;
/** Number of Regions in the underlying EDMA3 Controller */
- unsigned int numRegions;
+ uint32_t numRegions;
/**
* \brief Channel mapping existence
* any PaRAM Set. In other words, ANY PaRAM Set can be used for ANY DMA
* channel (like QDMA Channels).
*/
- unsigned int dmaChPaRAMMapExists;
+ uint32_t dmaChPaRAMMapExists;
/** Existence of memory protection feature */
- unsigned int memProtectionExists;
+ uint32_t memProtectionExists;
/** Base address of EDMA3 CC memory mapped registers. */
void *globalRegs;
* EDMA3 transfer completion interrupt line (could be different for ARM
* and DSP)
*/
- unsigned int xferCompleteInt;
+ uint32_t xferCompleteInt;
/** EDMA3 CC error interrupt line (could be different for ARM and DSP) */
- unsigned int ccError;
+ uint32_t ccError;
/** EDMA3 TCs error interrupt line (could be different for ARM and DSP) */
- unsigned int tcError[EDMA3_MAX_TC];
+ uint32_t tcError[EDMA3_MAX_TC];
/**
* \brief EDMA3 TC priority setting
* relative to IO initiated by the other bus masters on the
* device (ARM, DSP, USB, etc)
*/
- unsigned int evtQPri [EDMA3_MAX_EVT_QUE];
+ uint32_t evtQPri [EDMA3_MAX_EVT_QUE];
/**
* \brief Event Queues Watermark Levels
* or equals the threshold/watermark value that is set
* in the queue watermark threshold register (QWMTHRA).
*/
- unsigned int evtQueueWaterMarkLvl [EDMA3_MAX_EVT_QUE];
+ uint32_t evtQueueWaterMarkLvl [EDMA3_MAX_EVT_QUE];
/**
* \brief Default Burst Size (DBS) of TCs.
* default burst size (DBS). Different TCs can have different
* DBS values. It is defined in Bytes.
*/
- unsigned int tcDefaultBurstSize[EDMA3_MAX_TC];
+ uint32_t tcDefaultBurstSize[EDMA3_MAX_TC];
/**
* \brief Mapping from DMA channels to PaRAM Sets
* automatically uses the right PaRAM Set for that DMA channel.
* Useful only if mapping exists, otherwise of no use.
*/
- unsigned int dmaChannelPaRAMMap [EDMA3_MAX_DMA_CH];
+ uint32_t dmaChannelPaRAMMap [EDMA3_MAX_DMA_CH];
/**
* \brief Mapping from DMA channels to TCCs
* TCC code will be returned when the transfer is completed
* on the mapped DMA channel.
*/
- unsigned int dmaChannelTccMap [EDMA3_MAX_DMA_CH];
+ uint32_t dmaChannelTccMap [EDMA3_MAX_DMA_CH];
/**
* \brief Mapping from DMA channels to Hardware Events
* channel.
* All channels need not be mapped, some can be free also.
*/
- unsigned int dmaChannelHwEvtMap [EDMA3_MAX_DMA_CHAN_DWRDS];
+ uint32_t dmaChannelHwEvtMap [EDMA3_MAX_DMA_CHAN_DWRDS];
} EDMA3_DRV_GblConfigParams;
-
-
/**\struct EDMA3_DRV_InstanceInitConfig
* \brief Init-time Region Specific Configuration structure for
* EDMA3 Driver, to provide region specific Information.
typedef struct
{
/** PaRAM Sets owned by the EDMA3 Driver Instance. */
- unsigned int ownPaRAMSets[EDMA3_MAX_PARAM_DWRDS];
+ uint32_t ownPaRAMSets[EDMA3_MAX_PARAM_DWRDS];
/** DMA Channels owned by the EDMA3 Driver Instance. */
- unsigned int ownDmaChannels[EDMA3_MAX_DMA_CHAN_DWRDS];
+ uint32_t ownDmaChannels[EDMA3_MAX_DMA_CHAN_DWRDS];
/** QDMA Channels owned by the EDMA3 Driver Instance. */
- unsigned int ownQdmaChannels[EDMA3_MAX_QDMA_CHAN_DWRDS];
+ uint32_t ownQdmaChannels[EDMA3_MAX_QDMA_CHAN_DWRDS];
/** TCCs owned by the EDMA3 Driver Instance. */
- unsigned int ownTccs[EDMA3_MAX_TCC_DWRDS];
+ uint32_t ownTccs[EDMA3_MAX_TCC_DWRDS];
/**
* \brief Reserved PaRAM Sets
* be given when user requests for ANY available PaRAM Set for linking
* using 'EDMA3_DRV_LINK_CHANNEL' as channel id.
*/
- unsigned int resvdPaRAMSets[EDMA3_MAX_PARAM_DWRDS];
+ uint32_t resvdPaRAMSets[EDMA3_MAX_PARAM_DWRDS];
/**
* \brief Reserved DMA channels
* not be given when user requests for ANY available DMA channel using
* 'EDMA3_DRV_DMA_CHANNEL_ANY' as channel id.
*/
- unsigned int resvdDmaChannels[EDMA3_MAX_DMA_CHAN_DWRDS];
+ uint32_t resvdDmaChannels[EDMA3_MAX_DMA_CHAN_DWRDS];
/**
* \brief Reserved QDMA channels
* not be given when user requests for ANY available QDMA channel using
* 'EDMA3_DRV_QDMA_CHANNEL_ANY' as channel id.
*/
- unsigned int resvdQdmaChannels[EDMA3_MAX_QDMA_CHAN_DWRDS];
+ uint32_t resvdQdmaChannels[EDMA3_MAX_QDMA_CHAN_DWRDS];
/**
* \brief Reserved TCCs
* be given when user requests for ANY available TCC using
* 'EDMA3_DRV_TCC_ANY' as resource id.
*/
- unsigned int resvdTccs[EDMA3_MAX_TCC_DWRDS];
+ uint32_t resvdTccs[EDMA3_MAX_TCC_DWRDS];
}EDMA3_DRV_InstanceInitConfig;
-
-
/**\struct EDMA3_DRV_InitConfig
* \brief Used to Initialize the EDMA3 Driver Instance
*
* region associated with this master instance will receive the EDMA3
* interrupts (if enabled).
*/
- unsigned int isMaster;
+ uint32_t isMaster;
/**
* EDMA3 resources related shadow region specific information. Which all
void *gblerrData;
} EDMA3_DRV_InitConfig;
-
-
/**\struct EDMA3_DRV_MiscParam
* \brief Used to specify the miscellaneous options during EDMA3 Driver
* Initialization.
* program the global EDMA3 registers (like Queue priority, Queue water-
* mark level, error registers etc).
*/
- unsigned short isSlave;
+ uint16_t isSlave;
/** For future use **/
- unsigned short param;
+ uint16_t param;
}EDMA3_DRV_MiscParam;
+/**
+@}
+*/
+
+/** @addtogroup EDMA3_LLD_DRV_FUNCTION_INIT
+ @{ */
/**
* \brief Create EDMA3 Driver Object
*
* \return EDMA3_DRV_SOK or EDMA3_DRV Error code
*/
-EDMA3_DRV_Result EDMA3_DRV_create (unsigned int phyCtrllerInstId,
+EDMA3_DRV_Result EDMA3_DRV_create (uint32_t phyCtrllerInstId,
const EDMA3_DRV_GblConfigParams *gblCfgParams,
const void *miscParam);
-
-
/**
* \brief Delete EDMA3 Driver Object
*
*
* \return EDMA3_DRV_SOK or EDMA3_DRV Error code
*/
-EDMA3_DRV_Result EDMA3_DRV_delete (unsigned int phyCtrllerInstId,
+EDMA3_DRV_Result EDMA3_DRV_delete (uint32_t phyCtrllerInstId,
const void *param);
-
-
/**
* \brief Open EDMA3 Driver Instance
*
* EDMA3_OS_PROTECT_INTERRUPT) while modifying the global data
* structures, to make it re-entrant.
*/
-EDMA3_DRV_Handle EDMA3_DRV_open (unsigned int phyCtrllerInstId,
+EDMA3_DRV_Handle EDMA3_DRV_open (uint32_t phyCtrllerInstId,
const EDMA3_DRV_InitConfig *initCfg,
EDMA3_DRV_Result *errorCode);
-
/**
* \brief Close the EDMA3 Driver Instance.
*
EDMA3_DRV_Result EDMA3_DRV_close (EDMA3_DRV_Handle hEdma,
const void *param);
-
-
/**
- * \defgroup Edma3DrvChannelSetup EDMA3 Driver Channel Setup
- *
- * Channel related Interface of the EDMA3 Driver
- *
- * @{
- */
+@}
+*/
+
+/** @addtogroup EDMA3_LLD_DRV_SYMBOL_DEFINE
+ @{ */
/* Defines for Logical Channel Values */
/*---------------------------------------------------------------------------*/
* DMA channel from the pool of (owned && non_reserved && available_right_now)
* DMA channels will be chosen and returned.
*/
-#define EDMA3_DRV_DMA_CHANNEL_ANY 1002u
+#define EDMA3_DRV_DMA_CHANNEL_ANY 1002U
/**
* Used to specify any available QDMA Channel while requesting
* QDMA channel from the pool of (owned && non_reserved && available_right_now)
* QDMA channels will be chosen and returned.
*/
-#define EDMA3_DRV_QDMA_CHANNEL_ANY 1003u
+#define EDMA3_DRV_QDMA_CHANNEL_ANY 1003U
/**
* Used to specify any available TCC while requesting
* TCC from the pool of (owned && non_reserved && available_right_now)
* TCCs will be chosen and returned.
*/
-#define EDMA3_DRV_TCC_ANY 1004u
+#define EDMA3_DRV_TCC_ANY 1004U
/**
* Used to specify any available PaRAM Set while requesting
* PaRAM Set from the pool of (owned && non_reserved && available_right_now)
* PaRAM Sets will be chosen and returned.
*/
-#define EDMA3_DRV_LINK_CHANNEL 1005u
+#define EDMA3_DRV_LINK_CHANNEL 1005U
/**
- * Used to specify any available PaRAM Set while requesting
- * one. Used in the API EDMA3_DRV_requestChannel(), for Link channels.
+ * Used to specify any available PaRAM Set while requesting one. Used in the
+ * API EDMA3_DRV_requestChannel(), for Link channels.
+ * TCC code should also be specified and it will be used to populate the LINK
+ * field of the PaRAM Set. Without TCC code, the call will fail.
* PaRAM Set from the pool of (owned && non_reserved && available_right_now)
* PaRAM Sets will be chosen and returned.
*/
-#define EDMA3_DRV_LINK_CHANNEL_WITH_TCC 1006u
-/*---------------------------------------------------------------------------*/
+#define EDMA3_DRV_LINK_CHANNEL_WITH_TCC 1006U
+
+/**
+@}
+*/
+/** @addtogroup EDMA3_LLD_DRV_SYMBOL_ENUM
+ @{ */
/**
* \brief DMA Channels assigned to different Hardware Events.
+ *
* They should be used while requesting a specific DMA channel.
* One possible usage is to maintain a SoC specific file, which will
* contain the mapping of these hardware events to the respective
* peripherals for better understanding and lesser probability of
* errors. Also, if any event associated with a particular peripheral
* gets changed, only that SoC specific file needs to be changed.
- *
* for eg, the sample SoC specific file "soc.h" can have these defines:
*
* #define EDMA3_DRV_HW_CHANNEL_MCBSP_TX EDMA3_DRV_HW_CHANNEL_EVENT_2
EDMA3_DRV_HW_CHANNEL_EVENT_63
} EDMA3_DRV_HW_CHANNEL_EVENT;
+/**
+@}
+*/
+
+/** @addtogroup EDMA3_LLD_DRV_SYMBOL_DEFINE
+ @{ */
/**
* \brief QDMA Channel defines
- * They should be used while requesting a specific QDMA channel.
+ *
+ * They should be used while requesting a specific QDMA channel in API
+ * EDMA3_DRV_requestChannel() as the argument (*pLch). Please note that
+ * these defines should ONLY be used in the API EDMA3_DRV_requestChannel() and
+ * not in any other API to perform further operations. They are only provided
+ * to allow user allocate specific QDMA channels.
*/
/** QDMA Channel 0 */
#define EDMA3_DRV_QDMA_CHANNEL_0 (EDMA3_MAX_DMA_CH + EDMA3_MAX_PARAM_SETS)
/** QDMA Channel 1 */
-#define EDMA3_DRV_QDMA_CHANNEL_1 (EDMA3_DRV_QDMA_CHANNEL_0+1u)
+#define EDMA3_DRV_QDMA_CHANNEL_1 (EDMA3_DRV_QDMA_CHANNEL_0+1U)
/** QDMA Channel 2 */
-#define EDMA3_DRV_QDMA_CHANNEL_2 (EDMA3_DRV_QDMA_CHANNEL_0+2u)
+#define EDMA3_DRV_QDMA_CHANNEL_2 (EDMA3_DRV_QDMA_CHANNEL_0+2U)
/** QDMA Channel 3 */
-#define EDMA3_DRV_QDMA_CHANNEL_3 (EDMA3_DRV_QDMA_CHANNEL_0+3u)
+#define EDMA3_DRV_QDMA_CHANNEL_3 (EDMA3_DRV_QDMA_CHANNEL_0+3U)
/** QDMA Channel 4 */
-#define EDMA3_DRV_QDMA_CHANNEL_4 (EDMA3_DRV_QDMA_CHANNEL_0+4u)
+#define EDMA3_DRV_QDMA_CHANNEL_4 (EDMA3_DRV_QDMA_CHANNEL_0+4U)
/** QDMA Channel 5 */
-#define EDMA3_DRV_QDMA_CHANNEL_5 (EDMA3_DRV_QDMA_CHANNEL_0+5u)
+#define EDMA3_DRV_QDMA_CHANNEL_5 (EDMA3_DRV_QDMA_CHANNEL_0+5U)
/** QDMA Channel 6 */
-#define EDMA3_DRV_QDMA_CHANNEL_6 (EDMA3_DRV_QDMA_CHANNEL_0+6u)
+#define EDMA3_DRV_QDMA_CHANNEL_6 (EDMA3_DRV_QDMA_CHANNEL_0+6U)
/** QDMA Channel 7 */
-#define EDMA3_DRV_QDMA_CHANNEL_7 (EDMA3_DRV_QDMA_CHANNEL_0+7u)
+#define EDMA3_DRV_QDMA_CHANNEL_7 (EDMA3_DRV_QDMA_CHANNEL_0+7U)
+/**
+@}
+*/
+/** @addtogroup EDMA3_LLD_DRV_FUNCTION_BASIC
+ @{ */
/**
* \brief Request a DMA/QDMA/Link channel.
*
* This API is used to allocate a logical channel (DMA/QDMA/Link) along with
* the associated resources. For DMA and QDMA channels, TCC and PaRAM Set are
- * also allocated along with the requested channel. For Link channel, ONLY a
- * PaRAM Set is allocated.
+ * also allocated along with the requested channel. User can also specify a
+ * specific TCC which needs to be allocated with the DMA/QDMA channel or else
+ * can request any available TCC.
+ *
+ * For Link channels, ONLY a PaRAM Set is allocated and the allocated PaRAM Set
+ * number is returned as the logical channel no. A TCC code can also be
+ * specified while making the request. This TCC code will be copied to the
+ * LINK field of the allocated PaRAM Set and will be associated with the Link
+ * channel.
*
- * User can request a specific logical channel by passing the channel id in
- * 'pLCh'. Note that the channel id is the same as the actual resource id in
- * case of DMA channels. To allocate specific QDMA channels, user SHOULD use the
- * defines EDMA3_DRV_QDMA_CHANNEL_X mentioned above.
+ * User can request a specific logical channel - DMA, QDMA and Link, by passing
+ * the channel id in 'pLCh'. Note that the channel id is the same as the actual
+ * resource id in case of DMA channels and Link channels. For DMA channels,
+ * channel id lies between 0 and (max dma channels - 1). For Link channels,
+ * channel id lies between (max dma channels) and (max param sets - 1). To
+ * allocate specific QDMA channels, user SHOULD use the defines
+ * EDMA3_DRV_QDMA_CHANNEL_X mentioned above.
*
- * User can also request ANY available logical channel also by specifying the
+ * User can also request ANY available logical channel by specifying the
* below mentioned values in '*pLCh':
* a) EDMA3_DRV_DMA_CHANNEL_ANY: For DMA channels
* b) EDMA3_DRV_QDMA_CHANNEL_ANY: For QDMA channels, and
* value to request link channels (PaRAM Sets used for linking purpose
* only), unless he wants to use some specific link channels (PaRAM Sets)
* which is also allowed.
+ * d) EDMA3_DRV_LINK_CHANNEL_WITH_TCC: For Link channels. User should
+ * use this value to request link channels with TCC code.
*
* This API internally uses EDMA3_RM_allocResource () to allocate the desired
* resources (DMA/QDMA channel, PaRAM Set and TCC).
*
- * This API also registers a specific callback function against the allocated
- * TCC.
+ * This API also registers a specific callback function, in case the same is
+ * provided, against the allocated TCC. To do this, this API calls
+ * EDMA3_RM_registerTccCb(), which is a part of the Resource Manager. Please
+ * note that the interrupts are enabled for the specific TCC only if callback
+ * function is provided. In the absence of this, the API assumes that the
+ * requested logical channel is going to be used in Poll mode environment.
*
* For DMA/QDMA channels, after allocating all the EDMA3 resources, this API
* sets the TCC field of the OPT PaRAM Word with the allocated TCC. It also sets
* - to be linked to some other Master
* - channel.
*
+ * - EDMA3_DRV_LINK_CHANNEL_WITH_TCC
+ * - For requesting a DMA Slave Channel,
+ * - to be linked to some other Master
+ * - channel, with a TCC associated with it.
+ *
* In case user passes a specific channel
* Id, pLCh value is left unchanged. In
* case user requests ANY available
* \note To request a PaRAM Set for the purpose of
* linking to another channel, call the function with
*
- * *pLCh = EDMA3_DRV_LINK_CHANNEL;
+ * *pLCh = EDMA3_DRV_LINK_CHANNEL or EDMA3_DRV_LINK_CHANNEL_WITH_TCC
*
* This function will update *pLCh with the allocated Link channel
- * handle. This handle could be DIFFERENT from the actual PaRAM Set
- * allocated by the Resource Manager internally. So user SHOULD NOT
- * assume the handle as the PaRAM Set Id.
+ * handle.
*
* \param pTcc [IN/OUT] The channel number on which the
* completion/error interrupt is generated.
* function (ISR context).
*/
EDMA3_DRV_Result EDMA3_DRV_requestChannel (EDMA3_DRV_Handle hEdma,
- unsigned int *pLCh,
- unsigned int *pTcc,
+ uint32_t *pLCh,
+ uint32_t *pTcc,
EDMA3_RM_EventQueue evtQueue,
EDMA3_RM_TccCallback tccCb,
void *cbData);
-
/**
* \brief Free the specified channel (DMA/QDMA/Link) and its associated
* resources (PaRAM Set, TCC etc) and removes various mappings.
* de-allocation. It is re-entrant.
*/
EDMA3_DRV_Result EDMA3_DRV_freeChannel (EDMA3_DRV_Handle hEdma,
- unsigned int channelId);
-
-
+ uint32_t channelId);
/**
* \brief Disables the DMA Channel by clearing the Event Enable Register and
* re-entrant for same channelId value.
*/
EDMA3_DRV_Result EDMA3_DRV_clearErrorBits (EDMA3_DRV_Handle hEdma,
- unsigned int channelId);
+ uint32_t channelId);
+/**
+@}
+*/
+
+/** @addtogroup EDMA3_LLD_DRV_FUNCTION_ADVANCED
+ @{ */
/**
* \brief Link two logical channels.
* channel (lCh1) to point it to the PaRAM set associated with second logical
* channel (lCh2).
*
- * It also sets the TCC field of PaRAM set associated with second logical
- * channel to the same as that of the first logical channel.
- *
- * After linking the channels, user should not update any PaRAM Set of the
- * channel.
+ * It also sets the TCC field of PaRAM set of second logical channel to the
+ * same as that of the first logical channel, only if the TCC field doesnot
+ * contain a valid TCC code. In case the second logical channel has its own TCC,
+ * the TCC field remains unchanged.
*
* \param hEdma [IN] Handle to the EDMA Driver Instance.
* \param lCh1 [IN] Logical Channel to which particular channel
* non-re-entrant for same lCh1 & lCh2 values.
*/
EDMA3_DRV_Result EDMA3_DRV_linkChannel ( EDMA3_DRV_Handle hEdma,
- unsigned int lCh1,
- unsigned int lCh2);
-
-
+ uint32_t lCh1,
+ uint32_t lCh2);
/**
* \brief Unlink the channel from the earlier linked logical channel.
* re-entrant for same lCh value.
*/
EDMA3_DRV_Result EDMA3_DRV_unlinkChannel (EDMA3_DRV_Handle hEdma,
- unsigned int lCh);
-
-/* @} Edma3DrvChannelSetup */
-
-
+ uint32_t lCh);
/**
- * \defgroup Edma3DrvTransferSetupType EDMA3 Driver Typical EDMA Transfer Setup
- *
- * The typical EDMA transfer related Interface of the EDMA3 Driver
- *
- * @{
- */
+@}
+*/
+
+/** @addtogroup EDMA3_LLD_DRV_SYMBOL_ENUM
+ @{ */
/**
* \brief OPT Field Offset.
} EDMA3_DRV_OptField;
-
/**
* \brief EDMA Addressing modes
*
} EDMA3_DRV_AddrMode;
-
-
/**
* \brief EDMA Transfer Synchronization type.
*
} EDMA3_DRV_SyncType;
-
-
/**
* \brief True/False: PaRAM set is Static or not. A Static PaRAM set
* is updated or linked after TR is submitted.
EDMA3_DRV_STATIC_EN = 1
} EDMA3_DRV_StaticMode;
-
/**
* \brief EDMA3 FIFO width.
*
} EDMA3_DRV_FifoWidth;
-
-
-
/**
* \brief Transfer complete code mode.
* Indicates the point at which a transfer is considered completed for
EDMA3_DRV_TCCMODE_EARLY = 1
} EDMA3_DRV_TccMode;
-
/**
* \brief Transfer complete interrupt enable.
*/
EDMA3_DRV_TCINTEN_EN = 1
} EDMA3_DRV_TcintEn;
-
/**
* \brief Intermediate Transfer complete interrupt enable.
*/
EDMA3_DRV_ITCINTEN_EN = 1
} EDMA3_DRV_ItcintEn;
-
/**
* \brief Transfer complete chaining enable.
*/
EDMA3_DRV_TCCHEN_EN = 1
} EDMA3_DRV_TcchEn;
-
/**
* \brief Intermediate Transfer complete chaining enable.
*/
EDMA3_DRV_ITCCHEN_EN = 1
} EDMA3_DRV_ItcchEn;
+/**
+@}
+*/
+
+/** @addtogroup EDMA3_LLD_DRV_DATASTRUCT
+ @{ */
/**
* \brief Structure to be used to configure interrupt generation
EDMA3_DRV_ItcintEn itcintEn;
} EDMA3_DRV_ChainOptions;
+/**
+@}
+*/
+/** @addtogroup EDMA3_LLD_DRV_FUNCTION_BASIC
+ @{ */
/**
* \brief Set a particular OPT field in the PaRAM set associated with the
* re-entrant for same lCh value.
*/
EDMA3_DRV_Result EDMA3_DRV_setOptField (EDMA3_DRV_Handle hEdma,
- unsigned int lCh,
+ uint32_t lCh,
EDMA3_DRV_OptField optField,
- unsigned int newOptFieldVal);
-
+ uint32_t newOptFieldVal);
/**
* \brief Get a particular OPT field in the PaRAM set associated with the
* \note This function is re-entrant.
*/
EDMA3_DRV_Result EDMA3_DRV_getOptField (EDMA3_DRV_Handle hEdma,
- unsigned int lCh,
+ uint32_t lCh,
EDMA3_DRV_OptField optField,
- unsigned int *optFieldVal);
-
+ uint32_t *optFieldVal);
/**
* \brief DMA source parameters setup
* re-entrant for same lCh value.
*/
EDMA3_DRV_Result EDMA3_DRV_setSrcParams ( EDMA3_DRV_Handle hEdma,
- unsigned int lCh,
- unsigned int srcAddr,
+ uint32_t lCh,
+ uint32_t srcAddr,
EDMA3_DRV_AddrMode addrMode,
EDMA3_DRV_FifoWidth fifoWidth);
-
-
/**
* \brief DMA Destination parameters setup
*
* re-entrant for same lCh value.
*/
EDMA3_DRV_Result EDMA3_DRV_setDestParams ( EDMA3_DRV_Handle hEdma,
- unsigned int lCh,
- unsigned int destAddr,
+ uint32_t lCh,
+ uint32_t destAddr,
EDMA3_DRV_AddrMode addrMode,
EDMA3_DRV_FifoWidth fifoWidth );
-
-
/**
* \brief DMA source index setup
*
* re-entrant for same lCh value.
*/
EDMA3_DRV_Result EDMA3_DRV_setSrcIndex ( EDMA3_DRV_Handle hEdma,
- unsigned int lCh,
- int srcBIdx,
- int srcCIdx );
-
-
+ uint32_t lCh,
+ int32_t srcBIdx,
+ int32_t srcCIdx );
/**
* \brief DMA destination index setup
* re-entrant for same lCh value.
*/
EDMA3_DRV_Result EDMA3_DRV_setDestIndex (EDMA3_DRV_Handle hEdma,
- unsigned int lCh,
- int destBIdx,
- int destCIdx);
-
+ uint32_t lCh,
+ int32_t destBIdx,
+ int32_t destCIdx);
/**
* \brief DMA transfer parameters setup
*/
EDMA3_DRV_Result EDMA3_DRV_setTransferParams (
EDMA3_DRV_Handle hEdma,
- unsigned int lCh,
- unsigned int aCnt,
- unsigned int bCnt,
- unsigned int cCnt,
- unsigned int bCntReload,
+ uint32_t lCh,
+ uint32_t aCnt,
+ uint32_t bCnt,
+ uint32_t cCnt,
+ uint32_t bCntReload,
EDMA3_DRV_SyncType syncType);
+/**
+@}
+*/
+/** @addtogroup EDMA3_LLD_DRV_FUNCTION_ADVANCED
+ @{ */
/**
* \brief Chain the two specified channels.
* non-re-entrant for same lCh1 & lCh2 values.
*/
EDMA3_DRV_Result EDMA3_DRV_chainChannel (EDMA3_DRV_Handle hEdma,
- unsigned int lCh1,
- unsigned int lCh2,
+ uint32_t lCh1,
+ uint32_t lCh2,
const EDMA3_DRV_ChainOptions *chainOptions);
-
/**
* \brief Unchain the two channels.
*
* re-entrant for same lCh value.
*/
EDMA3_DRV_Result EDMA3_DRV_unchainChannel (EDMA3_DRV_Handle hEdma,
- unsigned int lCh);
+ uint32_t lCh);
+
+/**
+@}
+*/
+/** @addtogroup EDMA3_LLD_DRV_SYMBOL_ENUM
+ @{ */
/**
* \brief EDMA Trigger Mode Selection
EDMA3_DRV_TRIG_MODE_NONE = 3
} EDMA3_DRV_TrigMode;
+/**
+@}
+*/
+
+/** @addtogroup EDMA3_LLD_DRV_FUNCTION_BASIC
+ @{ */
+
+/**
+ * \brief Version information
+ *
+ * The function is used to get the version information of the EDMA LLD.
+ *
+ * \return Version Information.
+ */
+uint32_t EDMA3_DRV_getVersion (void);
+
+/**
+ * \brief Version string querry
+ *
+ * The function is used to get the version string for the EDMA LLD.
+ *
+ * \return Version Information.
+ */
+const char* EDMA3_DRV_getVersionStr (void);
/**
* \brief Start EDMA transfer on the specified channel.
* Manual or QDMA.
*
* In event triggered, a peripheral or an externally generated event triggers
- * the transfer. This API clears the Event and Event Miss Register and then
- * enables the DMA channel by writing to the EESR.
+ * the transfer. This API clears the Secondary Event Register and Event Miss
+ * Register and then enables the DMA channel by writing to the EESR.
*
* In manual triggered mode, CPU manually triggers a transfer by writing a 1
* in the Event Set Register (ESR/ESRH). This API writes to the ESR/ESRH to
* re-entrant for same lCh value.
*/
EDMA3_DRV_Result EDMA3_DRV_enableTransfer (EDMA3_DRV_Handle hEdma,
- unsigned int lCh,
+ uint32_t lCh,
EDMA3_DRV_TrigMode trigMode);
-
/**
* \brief Disable DMA transfer on the specified channel
*
* API clears the QDMA Event Enable Register, for the specific QDMA channel.
*
* To disable a channel which was previously triggered in event mode, this API
- * clears the Event Enable Register, Event Register, Secondary Event Register
- * and Event Miss Register, if set, for the specific DMA channel.
+ * clears the Event Enable Register. It also clears Event Register, Secondary
+ * Event Register and Event Miss Register, if set, for the specific DMA channel.
*
* \param hEdma [IN] Handle to the EDMA Driver Instance
* \param lCh [IN] Channel on which transfer has to be stopped
* re-entrant for same lCh value.
*/
EDMA3_DRV_Result EDMA3_DRV_disableTransfer (EDMA3_DRV_Handle hEdma,
- unsigned int lCh,
+ uint32_t lCh,
EDMA3_DRV_TrigMode trigMode);
/**
* \note This function is re-entrant for unique lCh values. It is non-
* re-entrant for same lCh value.
*/
-EDMA3_DRV_Result EDMA3_DRV_disableLogicalChannel (EDMA3_DRV_Handle hEdma,
- unsigned int lCh,
+EDMA3_DRV_Result EDMA3_DRV_disableLogicalChannel (
+ EDMA3_DRV_Handle hEdma,
+ uint32_t lCh,
EDMA3_DRV_TrigMode trigMode);
-
-/* @} Edma3DrvTransferSetupType */
-
-
-
/**
- * \defgroup Edma3DrvTransferSetupOpt EDMA3 Driver Optional Setup for EDMA
- * Transfer.
- *
- * The Optional EDMA transfer related Interface of the EDMA3 Driver
- *
- * @{
- */
+@}
+*/
+
+/** @addtogroup EDMA3_LLD_DRV_SYMBOL_ENUM
+ @{ */
/**
* \brief PaRAM Set Entry type
*
* Use this enum to set or get any of the
- * 8 DWords(unsigned int) within a Parameter RAM set
+ * 8 DWords(uint32_t) within a Parameter RAM set
*/
typedef enum
{
/**
* The OPT field (Offset Address 0x0 Bytes)
*/
- EDMA3_DRV_PARAM_ENTRY_OPT = 0,
+ EDMA3_DRV_PARAM_ENTRY_OPT = 0U,
/**
* The SRC field (Offset Address 0x4 Bytes)
*/
- EDMA3_DRV_PARAM_ENTRY_SRC = 1,
+ EDMA3_DRV_PARAM_ENTRY_SRC = 1U,
/**
* The (ACNT+BCNT) field (Offset Address 0x8 Bytes)
*/
- EDMA3_DRV_PARAM_ENTRY_ACNT_BCNT = 2,
+ EDMA3_DRV_PARAM_ENTRY_ACNT_BCNT = 2U,
/**
* The DST field (Offset Address 0xC Bytes)
*/
- EDMA3_DRV_PARAM_ENTRY_DST = 3,
+ EDMA3_DRV_PARAM_ENTRY_DST = 3U,
/**
* The (SRCBIDX+DSTBIDX) field (Offset Address 0x10 Bytes)
*/
- EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX = 4,
+ EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX = 4U,
/**
* The (LINK+BCNTRLD) field (Offset Address 0x14 Bytes)
*/
- EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD = 5,
+ EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD = 5U,
/**
* The (SRCCIDX+DSTCIDX) field (Offset Address 0x18 Bytes)
*/
- EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX = 6,
+ EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX = 6U,
/**
* The (CCNT+RSVD) field (Offset Address 0x1C Bytes)
*/
- EDMA3_DRV_PARAM_ENTRY_CCNT = 7
+ EDMA3_DRV_PARAM_ENTRY_CCNT = 7U
} EDMA3_DRV_PaRAMEntry;
-
-
/**
* \brief PaRAM Set Field type
*
} EDMA3_DRV_PaRAMField;
+/**
+@}
+*/
+/** @addtogroup EDMA3_LLD_DRV_DATASTRUCT
+ @{ */
/**
* \brief EDMA3 PaRAM Set
*/
typedef struct {
/** OPT field of PaRAM Set */
- volatile unsigned int OPT;
+ volatile uint32_t OPT;
/**
* \brief Starting byte address of Source
* For FIFO mode, srcAddr must be a 256-bit aligned address.
*/
- volatile unsigned int SRC;
+ volatile uint32_t SRC;
/**
* Number of bytes in each Array (ACNT) (16 bits) and
* Number of Arrays in each Frame (BCNT) (16 bits).
*/
- volatile unsigned int A_B_CNT;
+ volatile uint32_t A_B_CNT;
/**
* \brief Starting byte address of destination
* For FIFO mode, destAddr must be a 256-bit aligned address.
* i.e. 5 LSBs should be 0.
*/
- volatile unsigned int DST;
+ volatile uint32_t DST;
/**
* Index between consec. arrays of a Source Frame (SRCBIDX) (16 bits) and
* If DAM is set to 1 (via channelOptions) then destInterArrIndex should
* be an even multiple of 32 bytes
*/
- volatile unsigned int SRC_DST_BIDX;
+ volatile uint32_t SRC_DST_BIDX;
/**
* \brief Address for linking (AutoReloading of a PaRAM Set) (16 bits)
*
* B count reload field is relevant only for A-sync transfers.
*/
- volatile unsigned int LINK_BCNTRLD;
+ volatile uint32_t LINK_BCNTRLD;
/**
* \brief Index between consecutive frames of a Source Block (SRCCIDX)
* (16 bits) and Index between consecutive frames of a Dest Block
* (DSTCIDX) (16 bits).
*/
- volatile unsigned int SRC_DST_CIDX;
+ volatile uint32_t SRC_DST_CIDX;
/**
* \brief Number of Frames in a block (CCNT) (16 bits).
*/
- volatile unsigned int CCNT;
+ volatile uint32_t CCNT;
} EDMA3_DRV_ParamentryRegs;
-
-
/**
* \brief EDMA3 Parameter RAM Set in User Configurable format
*
/* LITTLE_ENDIAN_MODE */
typedef struct {
/** OPT field of PaRAM Set */
- volatile unsigned int opt;
+ volatile uint32_t opt;
/**
* \brief Starting byte address of Source
* For FIFO mode, srcAddr must be a 256-bit aligned address.
*/
- volatile unsigned int srcAddr;
+ volatile uint32_t srcAddr;
/**
* \brief Number of bytes in each Array (ACNT)
*/
- volatile unsigned short aCnt;
+ volatile uint16_t aCnt;
/**
* \brief Number of Arrays in each Frame (BCNT)
*/
- volatile unsigned short bCnt;
+ volatile uint16_t bCnt;
/**
* \brief Starting byte address of destination
* For FIFO mode, destAddr must be a 256-bit aligned address.
* i.e. 5 LSBs should be 0.
*/
- volatile unsigned int destAddr;
+ volatile uint32_t destAddr;
/**
* \brief Index between consec. arrays of a Source Frame (SRCBIDX)
* If SAM is set to 1 (via channelOptions) then srcInterArrIndex should
* be an even multiple of 32 bytes.
*/
- volatile short srcBIdx;
+ volatile int16_t srcBIdx;
/**
* \brief Index between consec. arrays of a Destination Frame (DSTBIDX)
* If DAM is set to 1 (via channelOptions) then destInterArrIndex should
* be an even multiple of 32 bytes
*/
- volatile short destBIdx;
+ volatile int16_t destBIdx;
/**
* \brief Address for linking (AutoReloading of a PaRAM Set)
* Linking is especially useful for use with ping-pong buffers and
* circular buffers
*/
- volatile unsigned short linkAddr;
+ volatile uint16_t linkAddr;
/**
* \brief Reload value of the numArrInFrame (BCNT)
* Relevant only for A-sync transfers
*/
- volatile unsigned short bCntReload;
+ volatile uint16_t bCntReload;
/**
* \brief Index between consecutive frames of a Source Block (SRCCIDX)
*/
- volatile short srcCIdx;
+ volatile int16_t srcCIdx;
/**
* \brief Index between consecutive frames of a Dest Block (DSTCIDX)
*/
- volatile short destCIdx;
+ volatile int16_t destCIdx;
/**
* \brief Number of Frames in a block (CCNT)
*/
- volatile unsigned short cCnt;
+ volatile uint16_t cCnt;
/**
* \brief Reserved
*/
- volatile short reserved;
+ volatile int16_t reserved;
} EDMA3_DRV_PaRAMRegs;
#else
/* BIG_ENDIAN_MODE */
typedef struct {
/** OPT field of PaRAM Set */
- volatile unsigned int opt;
+ volatile uint32_t opt;
/**
* \brief Starting byte address of Source
* For FIFO mode, srcAddr must be a 256-bit aligned address.
*/
- volatile unsigned int srcAddr;
+ volatile uint32_t srcAddr;
/**
* \brief Number of Arrays in each Frame (BCNT)
*/
- volatile unsigned short bCnt;
+ volatile uint16_t bCnt;
/**
* \brief Number of bytes in each Array (ACNT)
*/
- volatile unsigned short aCnt;
+ volatile uint16_t aCnt;
/**
* \brief Starting byte address of destination
* For FIFO mode, destAddr must be a 256-bit aligned address.
* i.e. 5 LSBs should be 0.
*/
- volatile unsigned int destAddr;
+ volatile uint32_t destAddr;
/**
* \brief Index between consec. arrays of a Destination Frame (DSTBIDX)
* If DAM is set to 1 (via channelOptions) then destInterArrIndex should
* be an even multiple of 32 bytes
*/
- volatile short destBIdx;
+ volatile int16_t destBIdx;
/**
* \brief Index between consec. arrays of a Source Frame (SRCBIDX)
* If SAM is set to 1 (via channelOptions) then srcInterArrIndex should
* be an even multiple of 32 bytes.
*/
- volatile short srcBIdx;
+ volatile int16_t srcBIdx;
/**
* \brief Reload value of the numArrInFrame (BCNT)
* Relevant only for A-sync transfers
*/
- volatile unsigned short bCntReload;
+ volatile uint16_t bCntReload;
/**
* \brief Address for linking (AutoReloading of a PaRAM Set)
* Linking is especially useful for use with ping-pong buffers and
* circular buffers
*/
- volatile unsigned short linkAddr;
+ volatile uint16_t linkAddr;
/**
* \brief Index between consecutive frames of a Dest Block (DSTCIDX)
*/
- volatile short destCIdx;
+ volatile int16_t destCIdx;
/**
* \brief Index between consecutive frames of a Source Block (SRCCIDX)
*/
- volatile short srcCIdx;
+ volatile int16_t srcCIdx;
/**
* \brief Reserved
*/
- volatile short reserved;
+ volatile int16_t reserved;
/**
* \brief Number of Frames in a block (CCNT)
*/
- volatile unsigned short cCnt;
+ volatile uint16_t cCnt;
} EDMA3_DRV_PaRAMRegs;
#endif /* #ifndef _BIG_ENDIAN */
/**
* \brief Event Queue Priorities
*/
- unsigned int evtQPri[EDMA3_MAX_EVT_QUE];
+ uint32_t evtQPri[EDMA3_MAX_EVT_QUE];
}EDMA3_DRV_EvtQuePriority;
+/**
+@}
+*/
+/** @addtogroup EDMA3_LLD_DRV_FUNCTION_ADVANCED
+ @{ */
/**
* \brief Assign a Trigger Word to the specified QDMA channel
* re-entrant for same lCh value.
*/
EDMA3_DRV_Result EDMA3_DRV_setQdmaTrigWord (EDMA3_DRV_Handle hEdma,
- unsigned int lCh,
+ uint32_t lCh,
EDMA3_RM_QdmaTrigWord trigWord);
-
/**
* \brief Copy the user specified PaRAM Set onto the PaRAM Set
* associated with the logical channel (DMA/QDMA/Link).
* re-entrant for same lCh value.
*/
EDMA3_DRV_Result EDMA3_DRV_setPaRAM ( EDMA3_DRV_Handle hEdma,
- unsigned int lCh,
+ uint32_t lCh,
const EDMA3_DRV_PaRAMRegs *newPaRAM);
-
/**
* \brief Retrieve existing PaRAM set associated with specified logical
* channel (DMA/QDMA/Link).
* \note This function is re-entrant.
*/
EDMA3_DRV_Result EDMA3_DRV_getPaRAM (EDMA3_DRV_Handle hEdma,
- unsigned int lCh,
+ uint32_t lCh,
EDMA3_DRV_PaRAMRegs *currPaRAM);
-
-
/**
* \brief Set a particular PaRAM set entry of the specified PaRAM set
*
* re-entrant for same lCh value.
*/
EDMA3_DRV_Result EDMA3_DRV_setPaRAMEntry (EDMA3_DRV_Handle hEdma,
- unsigned int lCh,
+ uint32_t lCh,
EDMA3_DRV_PaRAMEntry paRAMEntry,
- unsigned int newPaRAMEntryVal);
-
+ uint32_t newPaRAMEntryVal);
/**
* \brief Get a particular PaRAM set entry of the specified PaRAM set
* \note This function is re-entrant.
*/
EDMA3_DRV_Result EDMA3_DRV_getPaRAMEntry (EDMA3_DRV_Handle hEdma,
- unsigned int lCh,
+ uint32_t lCh,
EDMA3_DRV_PaRAMEntry paRAMEntry,
- unsigned int *paRAMEntryVal);
-
+ uint32_t *paRAMEntryVal);
/**
* \brief Set a particular PaRAM set field of the specified PaRAM set
* re-entrant for same lCh value.
*/
EDMA3_DRV_Result EDMA3_DRV_setPaRAMField (EDMA3_DRV_Handle hEdma,
- unsigned int lCh,
+ uint32_t lCh,
EDMA3_DRV_PaRAMField paRAMField,
- unsigned int newPaRAMFieldVal);
-
+ uint32_t newPaRAMFieldVal);
/**
* \brief Get a particular PaRAM set field of the specified PaRAM set
* \note This function is re-entrant.
*/
EDMA3_DRV_Result EDMA3_DRV_getPaRAMField (EDMA3_DRV_Handle hEdma,
- unsigned int lCh,
+ uint32_t lCh,
EDMA3_DRV_PaRAMField paRAMField,
- unsigned int *currPaRAMFieldVal);
-
+ uint32_t *currPaRAMFieldVal);
/**
* \brief Sets EDMA TC priority
EDMA3_DRV_Result EDMA3_DRV_setEvtQPriority (EDMA3_DRV_Handle hEdma,
const EDMA3_DRV_EvtQuePriority *evtQPriObj);
-
/**
* \brief Associate Channel to Event Queue
*
* the global CC Registers, to make it re-entrant.
*/
EDMA3_DRV_Result EDMA3_DRV_mapChToEvtQ (EDMA3_DRV_Handle hEdma,
- unsigned int channelId,
+ uint32_t channelId,
EDMA3_RM_EventQueue eventQ);
-
/**
* \brief Get the Event Queue mapped to the specified DMA/QDMA channel.
*
* \note This function is re-entrant.
*/
EDMA3_DRV_Result EDMA3_DRV_getMapChToEvtQ (EDMA3_DRV_Handle hEdma,
- unsigned int channelId,
- unsigned int *mappedEvtQ);
-
-
+ uint32_t channelId,
+ uint32_t *mappedEvtQ);
/**
* \brief Set the Channel Controller (CC) Register value
* EDMA handles, this function is re-entrant.
*/
EDMA3_DRV_Result EDMA3_DRV_setCCRegister (EDMA3_DRV_Handle hEdma,
- unsigned int regOffset,
- unsigned int newRegValue);
-
+ uint32_t regOffset,
+ uint32_t newRegValue);
/**
* \brief Get the Channel Controller (CC) Register value
* \note This function is re-entrant.
*/
EDMA3_DRV_Result EDMA3_DRV_getCCRegister (EDMA3_DRV_Handle hEdma,
- unsigned int regOffset,
- unsigned int *regValue);
-
-
+ uint32_t regOffset,
+ uint32_t *regValue);
/**
* \brief Wait for a transfer completion interrupt to occur and clear it.
* \note This function is re-entrant for different tccNo.
*/
EDMA3_DRV_Result EDMA3_DRV_waitAndClearTcc (EDMA3_DRV_Handle hEdma,
- unsigned int tccNo);
-
-
-
+ uint32_t tccNo);
/**
* \brief Returns the status of a previously initiated transfer.
* \note This function is re-entrant for different tccNo.
*/
EDMA3_DRV_Result EDMA3_DRV_checkAndClearTcc (EDMA3_DRV_Handle hEdma,
- unsigned int tccNo,
- unsigned short *tccStatus);
-
-
+ uint32_t tccNo,
+ uint16_t *tccStatus);
/**
* \brief Get the PaRAM Set Physical Address associated with a logical channel
* \note This function is re-entrant.
*/
EDMA3_DRV_Result EDMA3_DRV_getPaRAMPhyAddr(EDMA3_DRV_Handle hEdma,
- unsigned int lCh,
- unsigned int *paramPhyAddr);
+ uint32_t lCh,
+ uint32_t *paramPhyAddr);
+/**
+@}
+*/
+
+/** @addtogroup EDMA3_LLD_DRV_SYMBOL_ENUM
+ @{ */
/**\enum EDMA3_DRV_IoctlCmd
* \brief EDMA3 Driver IOCTL commands
* during allocation.
* If the value read is '0', it means that PaRAM Sets are NOT getting cleared
* during allocation.
- *
* For e.g.,
- * unsigned short isParamClearingDone;
+ * uint16_t isParamClearingDone;
* cmdArg = ¶mClearingRequired;
*/
EDMA3_DRV_IOCTL_GET_PARAM_CLEAR_OPTION,
EDMA3_DRV_IOCTL_MAX_IOCTL
} EDMA3_DRV_IoctlCmd;
+/**
+@}
+*/
+
+/** @addtogroup EDMA3_LLD_DRV_FUNCTION_ADVANCED
+ @{ */
/**
* \brief EDMA3 Driver IOCTL
void *param
);
-
/**
* \brief Return the previously opened EDMA3 Driver Instance handle
*
*
* 2) This function is re-entrant.
*/
-EDMA3_DRV_Handle EDMA3_DRV_getInstHandle(unsigned int phyCtrllerInstId,
+EDMA3_DRV_Handle EDMA3_DRV_getInstHandle(uint32_t phyCtrllerInstId,
EDMA3_RM_RegionId regionId,
EDMA3_DRV_Result *errorCode);
-
/**
* \brief Registers a transfer completion handler for a specific DMA/QDMA
* channel
*
* This function registers a non-NULL callback function for a specific DMA or QDMA
* channel and enables the completion interrupt for the TCC associated with
- * the underlying channel in the IER/IERH register. If user enables the transfer
- * completion interrupts (intermediate or final) in the associated PaRAM Set,
- * the registered callback function will be called by the EDMA3 driver.
+ * the underlying channel in the IER/IERH register. It also sets the DRAE/DRAEH
+ * register for the TCC associated with the specified DMA/QDMA channel. If user
+ * enables the transfer completion interrupts (intermediate or final) in the OPT
+ * field of the associated PaRAM Set, the registered callback function will be
+ * called by the EDMA3 Resource Manager.
*
* If a call-back function is already registered for the channel, the API fails
* with the error code EDMA3_RM_E_CALLBACK_ALREADY_REGISTERED.
* re-entrant for same channelId value.
*/
EDMA3_DRV_Result EDMA3_DRV_registerTccCb(EDMA3_DRV_Handle hEdma,
- const unsigned int channelId,
+ const uint32_t channelId,
EDMA3_RM_TccCallback tccCb,
void *cbData);
* \brief Un-register the previously registered callback function against a
* DMA/QDMA channel.
*
- * This function unregisters the previously registered callback function against
- * a DMA/QDMA channel by removing any stored callback function. Moreover, it
- * clears the interrupt enable register (IER/IERH) by writing to the IECR/
- * IECRH register, for the TCC associated with that particular channel.
+ * This function un-registers the previously registered callback function for
+ * the DMA/QDMA channel by removing any stored callback function. Moreover, it
+ * clears the:
+ * Interrupt Enable Register (IER/IERH) by writing to the IECR/IECRH
+ * register, for the TCC associated with that particular channel,
+ * DRA/DRAEH register for the TCC associated with the specified DMA/QDMA
+ * channel
*
* \param hEdma [IN] Handle to the EDMA Driver Instance.
* \param channelId [IN] DMA/QDMA channel for which the callback
* function needs to be un-registered.
*
- * \return EDMA3_RM_SOK or EDMA3_RM Error Code.
+ * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code
*
* \note This function is re-entrant for unique channelId. It is
* non-re-entrant for same channelId.
*/
EDMA3_DRV_Result EDMA3_DRV_unregisterTccCb(EDMA3_DRV_Handle hEdma,
- const unsigned int channelId);
+ const uint32_t channelId);
+
+/**
+@}
+*/
+/** @addtogroup EDMA3_LLD_DRV_SYMBOL_ENUM
+ @{ */
/**\enum EDMA3_DRV_Tc_Err
* \brief TC Error Enablers
*
* Use this enum to enable/disable the specific EDMA3 Transfer Controller
- * Interrupt.
+ * Interrupts.
*/
typedef enum
{
EDMA3_DRV_TC_ERR_EN
} EDMA3_DRV_Tc_Err;
+/**
+@}
+*/
+
+/** @addtogroup EDMA3_LLD_DRV_FUNCTION_ADVANCED
+ @{ */
/**
- * \brief Un-register the previously registered callback function against a
- * DMA/QDMA channel.
+ * \brief Enable/disable specific EDMA3 Transfer Controller Interrupts
*
- * This function unregisters the previously registered callback function against
- * a DMA/QDMA channel by removing any stored callback function. Moreover, it
- * clears the interrupt enable register (IER/IERH) by writing to the IECR/
- * IECRH register, for the TCC associated with that particular channel.
+ * This function allows one to enable/disable specific EDMA3 Transfer Controller
+ * Interrupts. Since these interrupts don't get enabled by default, this API can
+ * be used to achieve the same.
*
- * \param hEdma [IN] Handle to the EDMA Driver Instance.
- * \param channelId [IN] DMA/QDMA channel for which the callback
- * function needs to be un-registered.
+ * \param phyCtrllerInstId [IN] EDMA3 Controller Instance Id
+ * (Hardware instance id, starting from 0).
+ * \param tcId [IN] Transfer Controller Id. It starts from 0
+ * for each EDMA3 hardware and can go upto
+ * (TCs available on EDMA3 Hardware - 1).
+ * \param tcErr [IN] TC Error Interrupts which need to be
+ * enabled/disabled.
*
- * \return EDMA3_RM_SOK or EDMA3_RM Error Code.
+ * \return EDMA3_DRV_SOK or EDMA3_DRV Error code
*
- * \note This function is re-entrant for unique channelId. It is
- * non-re-entrant for same channelId.
+ * \note This function is re-entrant for unique combination of EDMA3 hw and
+ * TC. It is non-re-entrant for same combination.
*/
-EDMA3_DRV_Result EDMA3_DRV_setTcErrorInt(unsigned int phyCtrllerInstId,
- unsigned int tcId,
+EDMA3_DRV_Result EDMA3_DRV_setTcErrorInt(uint32_t phyCtrllerInstId,
+ uint32_t tcId,
EDMA3_DRV_Tc_Err tcErr);
+/**
+@}
+*/
-#define EDMA3_DRV_CHANNEL_CLEAN 0x0000u
-#define EDMA3_DRV_CHANNEL_EVENT_PENDING 0x0001u
-#define EDMA3_DRV_CHANNEL_XFER_COMPLETE 0x0002u
-#define EDMA3_DRV_CHANNEL_ERR 0x0004u
+/** @addtogroup EDMA3_LLD_DRV_SYMBOL_DEFINE
+ @{ */
/**
- * \brief Un-register the previously registered callback function against a
- * DMA/QDMA channel.
+ * \brief Channel status defines
+ * These defines suggest the current state of the DMA / QDMA channel. They
+ * are used while returning the channel status from EDMA3_DRV_getChannelStatus().
+ */
+/** Channel is clean; no pending event, completion interrupt and event miss interrupt */
+#define EDMA3_DRV_CHANNEL_CLEAN 0x0000U
+/** Pending event is detected on the DMA channel */
+#define EDMA3_DRV_CHANNEL_EVENT_PENDING 0x0001U
+/** Transfer completion interrupt is detected on the DMA/QDMA channel */
+#define EDMA3_DRV_CHANNEL_XFER_COMPLETE 0x0002U
+/** Event miss error interrupt is detected on the DMA/QDMA channel */
+#define EDMA3_DRV_CHANNEL_ERR 0x0004U
+
+/**
+@}
+*/
+
+/** @addtogroup EDMA3_LLD_DRV_FUNCTION_ADVANCED
+ @{ */
+
+/**
+ * \brief Get the current status of the DMA/QDMA channel
*
- * This function unregisters the previously registered callback function against
- * a DMA/QDMA channel by removing any stored callback function. Moreover, it
- * clears the interrupt enable register (IER/IERH) by writing to the IECR/
- * IECRH register, for the TCC associated with that particular channel.
+ * This function returns the current status of the specific DMA/QDMA channel.
+ * For a DMA channel, it checks whether an event is pending in ER, transfer
+ * completion interrupt is pending in IPR and event miss error interrupt is
+ * pending in EMR or not. For a QDMA channel, it checks whether a transfer
+ * completion interrupt is pending in IPR and event miss error interrupt is
+ * pending in QEMR or not.
*
* \param hEdma [IN] Handle to the EDMA Driver Instance.
- * \param channelId [IN] DMA/QDMA channel for which the callback
- * function needs to be un-registered.
+ * \param lCh [IN] DMA/QDMA channel for which the current
+ * status is required.
+ * \param lchStatus [IN/OUT]Status of the channel. Defines mentioned
+ * above are used (and may be combined) to
+ * return the actual status.
*
- * \return EDMA3_RM_SOK or EDMA3_RM Error Code.
+ * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code
*
- * \note This function is re-entrant for unique channelId. It is
- * non-re-entrant for same channelId.
+ * \note This function is re-entrant.
*/
EDMA3_DRV_Result EDMA3_DRV_getChannelStatus(EDMA3_DRV_Handle hEdma,
- unsigned int lCh, unsigned int *lchStatus);
+ uint32_t lCh, uint32_t *lchStatus);
/**
* \brief Associates a link channel and a TCC
*
* This API is used to map a TCC to a LINK channel. It should be used with LINK
- * channels ONLY else it will fail.
+ * channels ONLY else it will fail. It will copy the TCC code in the OPT field
+ * of the param set associated with the link channel.
*
* \param hEdma [IN] Handle to the EDMA Driver Instance.
* \param linkCh [IN] Link Channel to which a particular TCC
* needs to be mapped.
- * \param tcc [IN] TCC which needs to be mapped
+ * \param tcc [IN] TCC which needs to be mapped.
*
* \return EDMA3_DRV_SOK or EDMA3_DRV Error Code
*
* \note This function is re-entrant for unique linkCh values. It is
* non-re-entrant for same linkCh values.
*/
-EDMA3_DRV_Result EDMA3_DRV_mapTccLinkCh ( EDMA3_DRV_Handle hEdma,
- unsigned int linkCh,
- unsigned int tcc);
+EDMA3_DRV_Result EDMA3_DRV_mapTccLinkCh (EDMA3_DRV_Handle hEdma,
+ uint32_t linkCh,
+ uint32_t tcc);
+
+#define EDMA3_DRV_MAX_XBAR_EVENTS (63U)
+
+/**\struct EDMA3_DRV_GblXbarToChanConfigParams
+ * \brief Init-time Configuration structure for EDMA3
+ * controller, to provide Global SoC specific Information.
+ *
+ * This configuration structure is used to specify the EDMA3 Driver
+ * global settings, specific to the SoC.
+ * This configuraion structure provides the details of the mapping of cross bar
+ * events to available channels.
+ * This configuration information is SoC specific and could be provided by the
+ * user at run-time while creating the EDMA3 Driver Object, using API
+ * EDMA3_DRV_initXbarEventMap. In case user doesn't provide it,
+ * this information could be taken from the SoC specific configuration
+ * file edma3_<SOC_NAME>_cfg.c, incase it is available.
+ */
+typedef struct {
+ /**
+ * \brief Mapping from DMA channels to Hardware Events
+ *
+ * Each element in this array corresponds to one cross bar event and tells
+ * whether this event is mapped to any DMA channel. That is whether any
+ * free or unused DMA channel can be mapped to this event.
+ * -1 means the cross bar event is not mapped to any DMA channel;
+ * Any number from 0 to 63 means this event is mapped to specified channel.
+ * All channels need not be mapped, some can be free also.
+ * For the cross bar event mapped to DMA channel, appropriate Control Config
+ * register of TPCC event mux register should be configured.
+ */
+ int32_t dmaMapXbarToChan [EDMA3_DRV_MAX_XBAR_EVENTS];
+ } EDMA3_DRV_GblXbarToChanConfigParams;
+
+
+/**
+ * \brief Associates cross bar mapped event to channel
+ *
+ * This function have to be defined in the configuration file.
+ * This function will be called only if the channel requested for is beyond the
+ * maximum number of channels.
+ * This function should read from the global cross bar mapped configuration
+ * data structure and return the mapped channel number to this event.
+ *
+ * \param eventNum [IN] Event number
+ * \param chanNum [IN/OUT]Return the channel number to which the
+ * request event is mapped to.
+ * \param edmaGblXbarConfig [IN] This is the configuration data structure
+ * for mapping the events to the channel
+ *
+ * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code
+ *
+ * \note This function is re-entrant for unique event values. It is
+ * non-re-entrant for same event values.
+ */
+typedef EDMA3_DRV_Result (*EDMA3_DRV_mapXbarEvtToChan) (uint32_t eventNum,
+ uint32_t *chanNum,
+ const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig);
+/**
+ * \brief Writes to the cross bar mapped event to channel to system
+ * configuration register
+ *
+ * This function have to be defined in the configuration file.
+ * This function will be called only if the event number requested for is
+ * beyond the maximum number of channels and if any channel is allocated to this
+ * event.
+ * This function should read the cross bar mapped event number and write the
+ * allocated channel number in Control Config Event Mux registers.
+ *
+ * \param eventNum [IN] Event number
+ * \param chanNum [IN/OUT]Return the channel number to which the
+ * request event is mapped to.
+ *
+ * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code
+ *
+ * \note This function is re-entrant for unique event values. It is
+ * non-re-entrant for same event values.
+ */
+typedef EDMA3_DRV_Result (*EDMA3_DRV_xbarConfigScr) (uint32_t eventNum,
+ uint32_t chanNum);
-/* @} Edma3DrvTransferSetupOpt */
+/**
+ * \brief Initialize the cross bar mapped event to channel function
+ *
+ * This API provides interface to associate the cross bar mapped event to edma
+ * channel in the driver.
+ * This function will called by the application during initilization.
+ * User could pass the application specific configuration structure
+ * during init-time. In case user doesn't provide it, this information could
+ * be taken from the SoC specific configuration file edma3_<SOC_NAME>_cfg.c,
+ * in case it is available.
+ * \param hEdma [IN] Handle to the EDMA Driver Instance.
+ * \param edmaGblXbarConfig [IN] This is the configuration data structure
+ * for mapping the events to the channel
+ * \param mapXbarEvtFunc [IN] This is the user defined function for
+ * mapping the cross bar event to channel.
+ *
+ * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code
+ *
+ * \note This function disables the global interrupts (by calling API
+ * edma3OsProtectEntry with protection level
+ * EDMA3_OS_PROTECT_INTERRUPT) while modifying the global data
+ * structures, to make it re-entrant.
+ */
+EDMA3_DRV_Result EDMA3_DRV_initXbarEventMap (EDMA3_DRV_Handle hEdma,
+ const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig,
+ EDMA3_DRV_mapXbarEvtToChan mapXbarEvtFunc,
+ EDMA3_DRV_xbarConfigScr configXbarScr);
-/* @} Edma3DrvMain */
+
+/**
+@}
+*/
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif /* _EDMA3_DRV_H_ */
-