Added Vayu support in edma3lld

[keystone-rtos/edma3_lld.git] / packages / ti / sdo / edma3 / drv / sample / src / platforms / sample_tda2xx_arm_int_reg.c

diff --git a/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_tda2xx_arm_int_reg.c b/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_tda2xx_arm_int_reg.c
index 84dd33f6e2c1646125fcc8f1ec9d90ee908ab760..cae613892d2f7e9e8f2cbbec36af92d6d1c65f6e 100644 (file)
--- a/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_tda2xx_arm_int_reg.c
+++ b/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_tda2xx_arm_int_reg.c
@@ -94,39 +94,22 @@ extern EDMA3_DRV_GblXbarToChanConfigParams
                                                                sampleXbarChanInitConfig[][EDMA3_MAX_REGIONS];\r
 \r
 typedef struct  {\r
-    volatile Uint32 DSP_INTMUX[21];\r
-    volatile Uint32 DUCATI_INTMUX[15];\r
-    volatile Uint32 TPCC_EVTMUX[16];\r
-    volatile Uint32 TIMER_EVTCAPT;\r
-    volatile Uint32 GPIO_MUX;\r
+    volatile Uint32 TPCC_EVTMUX[32];\r
 } CSL_IntmuxRegs;\r
 \r
 typedef volatile CSL_IntmuxRegs     *CSL_IntmuxRegsOvly;\r
 \r
-\r
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_MASK (0x3F000000u)\r
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_SHIFT (0x00000018u)\r
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_RESETVAL (0x00000000u)\r
-\r
-\r
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_MASK (0x003F0000u)\r
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_SHIFT (0x00000010u)\r
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_RESETVAL (0x00000000u)\r
-\r
-\r
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK (0x00003F00u)\r
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT (0x00000008u)\r
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK (0x00FF0000u)\r
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT (0x00000010u)\r
 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_RESETVAL (0x00000000u)\r
 \r
-\r
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK (0x0000003Fu)\r
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK (0x000000FFu)\r
 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_SHIFT (0x00000000u)\r
 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_RESETVAL (0x00000000u)\r
 \r
 \r
-#define EDMA3_MAX_CROSS_BAR_EVENTS_TI814X (95u)\r
+#define EDMA3_MAX_CROSS_BAR_EVENTS_TI814X (127u)\r
 #define EDMA3_NUM_TCC                     (64u)\r
-\r
 /*\r
  * Forward decleration\r
  */\r
@@ -149,8 +132,6 @@ void registerEdma3Interrupts (unsigned int edma3Id)
        IntXbar_connect(tcErrorIntXbarInstNo[edma3Id][0], tcErrEdmaXbarIndex[edma3Id][0]);\r
        IntXbar_connect(tcErrorIntXbarInstNo[edma3Id][1], tcErrEdmaXbarIndex[edma3Id][1]);\r
        \r
-//     *((volatile UInt32 *) 0x4A002544U) = (UInt32) 0xF757FDC0;\r
-\r
     Hwi_Params hwiParams; \r
     Error_Block      eb;\r
 \r
@@ -176,7 +157,7 @@ void registerEdma3Interrupts (unsigned int edma3Id)
     {\r
         System_printf("HWI Create Failed\n",Error_getCode(&eb));\r
     }\r
-#if 0\r
+\r
     /* Initialize the HWI parameters with user specified values */\r
     Hwi_Params_init(&hwiParams);\r
     /* argument for the ISR */\r
@@ -213,7 +194,7 @@ void registerEdma3Interrupts (unsigned int edma3Id)
         }\r
         numTc++;\r
        }\r
-#endif\r
+\r
    /**\r
     * Enabling the HWI_ID.\r
     * EDMA3 interrupts (transfer completion, CC error etc.)\r
@@ -226,7 +207,6 @@ void registerEdma3Interrupts (unsigned int edma3Id)
     * API C64_enableIER(), in which the YYY bit is SET.\r
     */\r
     Hwi_enableInterrupt(ccErrorInt[edma3Id]);\r
-#if 0\r
     Hwi_enableInterrupt(ccXferCompInt[edma3Id][dsp_num]);\r
     numTc = 0;\r
     while (numTc < numEdma3Tc[edma3Id])\r
@@ -234,7 +214,6 @@ void registerEdma3Interrupts (unsigned int edma3Id)
         Hwi_enableInterrupt(tcErrorInt[edma3Id][numTc]);\r
         numTc++;\r
        }\r
-#endif\r
     /* Restore interrupts */\r
     Hwi_restore(cookie);\r
     }\r
@@ -306,14 +285,14 @@ EDMA3_DRV_Result sampleConfigScr (unsigned int eventNum,
     unsigned int scrChanOffset = 0;\r
     unsigned int scrRegOffset  = 0;\r
     unsigned int xBarEvtNum    = 0;\r
-    CSL_IntmuxRegsOvly scrEvtMux = (CSL_IntmuxRegsOvly)(0x48140F00);\r
+    CSL_IntmuxRegsOvly scrEvtMux = (CSL_IntmuxRegsOvly)(0x4a002c78);\r
 \r
 \r
        if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_TI814X) &&\r
                (chanNum < EDMA3_NUM_TCC))\r
                {\r
-               scrRegOffset = chanNum / 4;\r
-               scrChanOffset = chanNum - (scrRegOffset * 4);\r
+               scrRegOffset = chanNum / 2;\r
+               scrChanOffset = chanNum - (scrRegOffset * 2);\r
                xBarEvtNum = (eventNum - EDMA3_NUM_TCC) + 1;\r
                \r
                switch(scrChanOffset)\r
@@ -327,16 +306,6 @@ EDMA3_DRV_Result sampleConfigScr (unsigned int eventNum,
                                        ((xBarEvtNum << CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT) & \r
                                        (CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK));\r
                                break;\r
-                       case 2:\r
-                               scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=\r
-                                       ((xBarEvtNum << CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_SHIFT) & \r
-                                       (CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_MASK));\r
-                               break;\r
-                       case 3:\r
-                               scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=\r
-                                       ((xBarEvtNum << CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_SHIFT) & \r
-                                       (CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_MASK));\r
-                               break;\r
                        default:\r
                                edma3Result = EDMA3_DRV_E_INVALID_PARAM;\r
                                break;\r