[keystone-rtos/edma3_lld.git] / packages / ti / sdo / edma3 / drv / sample / src / platforms / sample_tda2xx_cfg.c
diff --git a/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_tda2xx_cfg.c b/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_tda2xx_cfg.c
index 6026d9d5a62c40dc6624c11dce9bfe186a35c93f..f9220cbb1be15a0c24197be8c6882617a67c2ca4 100644 (file)
#endif\r
\r
/* Number of EDMA3 controllers present in the system */\r
-#define NUM_EDMA3_INSTANCES 2u\r
-const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;\r
+#define NUM_EDMA3_INSTANCES 3U\r
+const uint32_t numEdma3Instances = NUM_EDMA3_INSTANCES;\r
\r
/* Number of DSPs present in the system */\r
-#define NUM_DSPS 1u\r
-const unsigned int numDsps = NUM_DSPS;\r
+#define NUM_DSPS 1U\r
+const uint32_t numDsps = NUM_DSPS;\r
\r
/* Determine the processor id by reading DNUM register. */\r
/* Statically allocate the region numbers with cores. */\r
-int myCoreNum;\r
-#define PID0_ADDRESS 0xE00FFFE0\r
-#define CORE_ID_C0 0x0\r
-#define CORE_ID_C1 0x1\r
+volatile int32_t myCoreNum;\r
+#define PID0_ADDRESS 0xE00FFFE0U\r
+#define CORE_ID_C0 0x0U\r
+#define CORE_ID_C1 0x1U\r
\r
-unsigned short determineProcId()\r
-{\r
-unsigned short regionNo;\r
#ifdef BUILD_TDA2XX_MPU\r
-\r
+static inline void readProcFeatureReg(void);\r
+static inline void readProcFeatureReg(void)\r
+{\r
asm (" push {r0-r2} \n\t"\r
" MRC p15, 0, r0, c0, c0, 5\n\t"\r
" LDR r1, =myCoreNum\n\t"\r
" STR r0, [r1]\n\t"\r
" pop {r0-r2}\n\t");\r
- if((myCoreNum & 0x03) == 1)\r
- regionNo = 1;\r
- else\r
- regionNo = 0;\r
-#elif defined(BUILD_TDA2XX_IPU)\r
-myCoreNum = (*(unsigned int *)(PID0_ADDRESS));\r
-if(Core_getIpuId() == 1){\r
- if(myCoreNum == CORE_ID_C0)\r
- regionNo = 4;\r
- else if (myCoreNum == CORE_ID_C1)\r
- regionNo = 5;\r
-}\r
-if(Core_getIpuId() == 2){\r
- if(myCoreNum == CORE_ID_C0)\r
- regionNo = 6;\r
- else if (myCoreNum == CORE_ID_C1)\r
- regionNo = 7;\r
}\r
-#elif defined BUILD_TDA2XX_DSP\r
-extern __cregister volatile unsigned int DNUM;\r
- myCoreNum = DNUM;\r
+#endif\r
+\r
+uint16_t determineProcId(void);\r
+\r
+int8_t* getGlobalAddr(int8_t* addr);\r
+\r
+uint16_t isGblConfigRequired(uint32_t dspNum);\r
+\r
+uint16_t determineProcId(void)\r
+{\r
+ uint16_t regionNo = (uint16_t)numEdma3Instances;\r
+#ifdef BUILD_TDA2XX_DSP\r
+ extern __cregister volatile uint32_t DNUM;\r
+#endif\r
+\r
+ myCoreNum = (int32_t)numDsps;\r
+\r
+#ifdef BUILD_TDA2XX_MPU\r
+ readProcFeatureReg();\r
+/* myCoreNum is always 1 here, fix for klocwork error(Unreachable code) */\r
+ regionNo = 0U;\r
+ if(((uint32_t)myCoreNum & 0x03U) == 1U)\r
+ {\r
+ regionNo = 1U;\r
+ }\r
+#elif defined(BUILD_TDA2XX_IPU)\r
+ myCoreNum = (*(volatile uint32_t *)(PID0_ADDRESS));\r
+ if(Core_getIpuId() == 1U){\r
+ if(myCoreNum == (int32_t)CORE_ID_C0)\r
+ {\r
+ regionNo = 4U;\r
+ }\r
+ else if (myCoreNum == (int32_t)CORE_ID_C1)\r
+ {\r
+ regionNo = 5U;\r
+ }\r
+ else\r
+ {\r
+ /* Nothing to be done here*/\r
+ }\r
+ }\r
+ if(Core_getIpuId() == 2U){\r
+ if(myCoreNum == (int32_t)CORE_ID_C0)\r
+ {\r
+ regionNo = 6U;\r
+ }\r
+ else if (myCoreNum == (int32_t)CORE_ID_C1)\r
+ {\r
+ regionNo = 7U;\r
+ }\r
+ else\r
+ {\r
+ /* Nothing to be done here*/\r
+ }\r
+ }\r
+#elif defined(BUILD_TDA2XX_DSP)\r
+\r
+ myCoreNum = (int32_t)DNUM;\r
if(myCoreNum == 0)\r
- regionNo = 2;\r
+ {\r
+ regionNo = 2U;\r
+ }\r
else\r
- regionNo = 3;\r
+ {\r
+ regionNo = 3U;\r
+ }\r
+#elif defined(BUILD_TDA2XX_EVE)\r
+ regionNo = 1U;\r
#endif\r
return regionNo;\r
}\r
\r
-signed char* getGlobalAddr(signed char* addr)\r
+int8_t* getGlobalAddr(int8_t* addr)\r
{\r
return (addr); /* The address is already a global address */\r
}\r
-unsigned short isGblConfigRequired(unsigned int dspNum)\r
+uint16_t isGblConfigRequired(uint32_t dspNum)\r
{\r
(void) dspNum;\r
- return 1;\r
+ return 1U;\r
}\r
\r
/* Semaphore handles */\r
EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};\r
\r
/** Number of PaRAM Sets available */\r
-#define EDMA3_NUM_PARAMSET (512u)\r
+#define EDMA3_NUM_PARAMSET (512U)\r
+\r
+/** Number of TCCS available */\r
+#define EDMA3_NUM_TCC (64U)\r
+\r
+/** Number of DMA Channels available */\r
+#define EDMA3_NUM_DMA_CHANNELS (64U)\r
+\r
+/** Number of QDMA Channels available */\r
+#define EDMA3_NUM_QDMA_CHANNELS (8U)\r
+\r
+/** Number of Event Queues available */\r
+#define EDMA3_NUM_EVTQUE (4U)\r
+\r
+/** Number of Transfer Controllers available */\r
+#define EDMA3_NUM_TC (2U)\r
+\r
+/** Number of Regions */\r
+#define EDMA3_NUM_REGIONS (8U)\r
+\r
+/* EDMA3 configuaration for EVE */\r
+\r
+/** Number of PaRAM Sets available */\r
+#define EDMA3_NUM_PARAMSET_EVE (64U)\r
\r
/** Number of TCCS available */\r
-#define EDMA3_NUM_TCC (64u)\r
+#define EDMA3_NUM_TCC_EVE (16U)\r
\r
/** Number of DMA Channels available */\r
-#define EDMA3_NUM_DMA_CHANNELS (64u)\r
+#define EDMA3_NUM_DMA_CHANNELS_EVE (16U)\r
\r
/** Number of QDMA Channels available */\r
-#define EDMA3_NUM_QDMA_CHANNELS (8u)\r
+#define EDMA3_NUM_QDMA_CHANNELS_EVE (8U)\r
\r
/** Number of Event Queues available */\r
-#define EDMA3_NUM_EVTQUE (4u)\r
+#define EDMA3_NUM_EVTQUE_EVE (2U)\r
\r
/** Number of Transfer Controllers available */\r
-#define EDMA3_NUM_TC (2u)\r
+#define EDMA3_NUM_TC_EVE (2U)\r
\r
/** Number of Regions */\r
-#define EDMA3_NUM_REGIONS (8u)\r
+#define EDMA3_NUM_REGIONS_EVE (8U)\r
+\r
\r
/** Interrupt no. for Transfer Completion */\r
-#define EDMA3_CC_XFER_COMPLETION_INT_A15 (66u)\r
-#define EDMA3_CC_XFER_COMPLETION_INT_DSP (38u)\r
-#define EDMA3_CC_XFER_COMPLETION_INT_IPU_C0 (34u)\r
-#define EDMA3_CC_XFER_COMPLETION_INT_IPU_C1 (33u)\r
+#define EDMA3_CC_XFER_COMPLETION_INT_A15 (66U)\r
+#define EDMA3_CC_XFER_COMPLETION_INT_DSP (38U)\r
+#define EDMA3_CC_XFER_COMPLETION_INT_IPU_C0 (34U)\r
+#define EDMA3_CC_XFER_COMPLETION_INT_IPU_C1 (33U)\r
+#define EDMA3_CC_XFER_COMPLETION_INT_EVE (8U)\r
+\r
/** Based on the interrupt number to be mapped define the XBAR instance number */\r
-#define COMPLETION_INT_A15_XBAR_INST_NO (29u)\r
-#define COMPLETION_INT_DSP_XBAR_INST_NO (7u)\r
-#define COMPLETION_INT_IPU_C0_XBAR_INST_NO (12u)\r
-#define COMPLETION_INT_IPU_C1_XBAR_INST_NO (11u)\r
+#define COMPLETION_INT_A15_XBAR_INST_NO (29U)\r
+#define COMPLETION_INT_DSP_XBAR_INST_NO (7U)\r
+#define COMPLETION_INT_IPU_C0_XBAR_INST_NO (12U)\r
+#define COMPLETION_INT_IPU_C1_XBAR_INST_NO (11U)\r
\r
/** Interrupt no. for CC Error */\r
-#define EDMA3_CC_ERROR_INT_A15 (67u)\r
-#define EDMA3_CC_ERROR_INT_DSP (39u)\r
-#define EDMA3_CC_ERROR_INT_IPU (35u)\r
+#define EDMA3_CC_ERROR_INT_A15 (67U)\r
+#define EDMA3_CC_ERROR_INT_DSP (39U)\r
+#define EDMA3_CC_ERROR_INT_IPU (35U)\r
+#define EDMA3_CC_ERROR_INT_EVE (23U)\r
\r
/** Based on the interrupt number to be mapped define the XBAR instance number */\r
-#define CC_ERROR_INT_A15_XBAR_INST_NO (30u)\r
-#define CC_ERROR_INT_DSP_XBAR_INST_NO (8u)\r
-#define CC_ERROR_INT_IPU_XBAR_INST_NO (13u)\r
+#define CC_ERROR_INT_A15_XBAR_INST_NO (30U)\r
+#define CC_ERROR_INT_DSP_XBAR_INST_NO (8U)\r
+#define CC_ERROR_INT_IPU_XBAR_INST_NO (13U)\r
\r
/** Interrupt no. for TCs Error */\r
-#define EDMA3_TC0_ERROR_INT_A15 (68u)\r
-#define EDMA3_TC0_ERROR_INT_DSP (40u)\r
-#define EDMA3_TC0_ERROR_INT_IPU (36u)\r
-#define EDMA3_TC1_ERROR_INT_A15 (69u)\r
-#define EDMA3_TC1_ERROR_INT_DSP (41u)\r
-#define EDMA3_TC1_ERROR_INT_IPU (37u)\r
+#define EDMA3_TC0_ERROR_INT_A15 (68U)\r
+#define EDMA3_TC0_ERROR_INT_DSP (40U)\r
+#define EDMA3_TC0_ERROR_INT_IPU (36U)\r
+#define EDMA3_TC0_ERROR_INT_EVE (24U)\r
+#define EDMA3_TC1_ERROR_INT_A15 (69U)\r
+#define EDMA3_TC1_ERROR_INT_DSP (41U)\r
+#define EDMA3_TC1_ERROR_INT_IPU (37U)\r
+#define EDMA3_TC1_ERROR_INT_EVE (25U)\r
+\r
/** Based on the interrupt number to be mapped define the XBAR instance number */\r
-#define TC0_ERROR_INT_A15_XBAR_INST_NO (31u)\r
-#define TC0_ERROR_INT_DSP_XBAR_INST_NO (9u)\r
-#define TC0_ERROR_INT_IPU_XBAR_INST_NO (14u)\r
-#define TC1_ERROR_INT_A15_XBAR_INST_NO (32u)\r
-#define TC1_ERROR_INT_DSP_XBAR_INST_NO (10u)\r
-#define TC1_ERROR_INT_IPU_XBAR_INST_NO (15u)\r
+#define TC0_ERROR_INT_A15_XBAR_INST_NO (31U)\r
+#define TC0_ERROR_INT_DSP_XBAR_INST_NO (9U) \r
+#define TC0_ERROR_INT_IPU_XBAR_INST_NO (14U)\r
+#define TC1_ERROR_INT_A15_XBAR_INST_NO (32U)\r
+#define TC1_ERROR_INT_DSP_XBAR_INST_NO (10U)\r
+#define TC1_ERROR_INT_IPU_XBAR_INST_NO (15U)\r
\r
#ifdef BUILD_TDA2XX_MPU\r
-#define EDMA3_CC_XFER_COMPLETION_INT EDMA3_CC_XFER_COMPLETION_INT_A15\r
-#define EDMA3_CC_ERROR_INT EDMA3_CC_ERROR_INT_A15\r
-#define CC_ERROR_INT_XBAR_INST_NO CC_ERROR_INT_A15_XBAR_INST_NO\r
-#define EDMA3_TC0_ERROR_INT EDMA3_TC0_ERROR_INT_A15\r
-#define EDMA3_TC1_ERROR_INT EDMA3_TC1_ERROR_INT_A15\r
-#define TC0_ERROR_INT_XBAR_INST_NO TC0_ERROR_INT_A15_XBAR_INST_NO\r
-#define TC1_ERROR_INT_XBAR_INST_NO TC1_ERROR_INT_A15_XBAR_INST_NO\r
+#define EDMA3_CC_XFER_COMPLETION_INT (EDMA3_CC_XFER_COMPLETION_INT_A15)\r
+#define EDMA3_CC_ERROR_INT (EDMA3_CC_ERROR_INT_A15)\r
+#define CC_ERROR_INT_XBAR_INST_NO (CC_ERROR_INT_A15_XBAR_INST_NO)\r
+#define EDMA3_TC0_ERROR_INT (EDMA3_TC0_ERROR_INT_A15)\r
+#define EDMA3_TC1_ERROR_INT (EDMA3_TC1_ERROR_INT_A15)\r
+#define TC0_ERROR_INT_XBAR_INST_NO (TC0_ERROR_INT_A15_XBAR_INST_NO)\r
+#define TC1_ERROR_INT_XBAR_INST_NO (TC1_ERROR_INT_A15_XBAR_INST_NO)\r
\r
#elif defined BUILD_TDA2XX_DSP\r
-#define EDMA3_CC_XFER_COMPLETION_INT EDMA3_CC_XFER_COMPLETION_INT_DSP\r
-#define EDMA3_CC_ERROR_INT EDMA3_CC_ERROR_INT_DSP\r
-#define CC_ERROR_INT_XBAR_INST_NO CC_ERROR_INT_DSP_XBAR_INST_NO\r
-#define EDMA3_TC0_ERROR_INT EDMA3_TC0_ERROR_INT_DSP\r
-#define EDMA3_TC1_ERROR_INT EDMA3_TC1_ERROR_INT_DSP\r
-#define TC0_ERROR_INT_XBAR_INST_NO TC0_ERROR_INT_DSP_XBAR_INST_NO\r
-#define TC1_ERROR_INT_XBAR_INST_NO TC1_ERROR_INT_DSP_XBAR_INST_NO\r
+#define EDMA3_CC_XFER_COMPLETION_INT (EDMA3_CC_XFER_COMPLETION_INT_DSP)\r
+#define EDMA3_CC_ERROR_INT (EDMA3_CC_ERROR_INT_DSP)\r
+#define CC_ERROR_INT_XBAR_INST_NO (CC_ERROR_INT_DSP_XBAR_INST_NO)\r
+#define EDMA3_TC0_ERROR_INT (EDMA3_TC0_ERROR_INT_DSP)\r
+#define EDMA3_TC1_ERROR_INT (EDMA3_TC1_ERROR_INT_DSP)\r
+#define TC0_ERROR_INT_XBAR_INST_NO (TC0_ERROR_INT_DSP_XBAR_INST_NO)\r
+#define TC1_ERROR_INT_XBAR_INST_NO (TC1_ERROR_INT_DSP_XBAR_INST_NO)\r
\r
#elif defined BUILD_TDA2XX_IPU\r
-#define EDMA3_CC_XFER_COMPLETION_INT EDMA3_CC_XFER_COMPLETION_INT_IPU_C0\r
-#define EDMA3_CC_ERROR_INT EDMA3_CC_ERROR_INT_IPU\r
-#define CC_ERROR_INT_XBAR_INST_NO CC_ERROR_INT_IPU_XBAR_INST_NO\r
-#define EDMA3_TC0_ERROR_INT EDMA3_TC0_ERROR_INT_IPU\r
-#define EDMA3_TC1_ERROR_INT EDMA3_TC1_ERROR_INT_IPU\r
-#define TC0_ERROR_INT_XBAR_INST_NO TC0_ERROR_INT_IPU_XBAR_INST_NO\r
-#define TC1_ERROR_INT_XBAR_INST_NO TC1_ERROR_INT_IPU_XBAR_INST_NO\r
+#define EDMA3_CC_XFER_COMPLETION_INT (EDMA3_CC_XFER_COMPLETION_INT_IPU_C0)\r
+#define EDMA3_CC_ERROR_INT (EDMA3_CC_ERROR_INT_IPU)\r
+#define CC_ERROR_INT_XBAR_INST_NO (CC_ERROR_INT_IPU_XBAR_INST_NO)\r
+#define EDMA3_TC0_ERROR_INT (EDMA3_TC0_ERROR_INT_IPU)\r
+#define EDMA3_TC1_ERROR_INT (EDMA3_TC1_ERROR_INT_IPU)\r
+#define TC0_ERROR_INT_XBAR_INST_NO (TC0_ERROR_INT_IPU_XBAR_INST_NO)\r
+#define TC1_ERROR_INT_XBAR_INST_NO (TC1_ERROR_INT_IPU_XBAR_INST_NO)\r
+\r
+#elif defined BUILD_TDA2XX_EVE\r
+#define EDMA3_CC_XFER_COMPLETION_INT (EDMA3_CC_XFER_COMPLETION_INT_EVE)\r
+#define EDMA3_CC_ERROR_INT (EDMA3_CC_ERROR_INT_EVE)\r
+#define EDMA3_TC0_ERROR_INT (EDMA3_TC0_ERROR_INT_EVE)\r
+#define EDMA3_TC1_ERROR_INT (EDMA3_TC1_ERROR_INT_EVE)\r
+/* For accessing EVE internal edma, there is no need to configure Xbar */\r
+#define CC_ERROR_INT_XBAR_INST_NO (0U)\r
+#define TC0_ERROR_INT_XBAR_INST_NO (0U)\r
+#define TC1_ERROR_INT_XBAR_INST_NO (0U)\r
\r
#else\r
-#define EDMA3_CC_XFER_COMPLETION_INT (0u)\r
-#define EDMA3_CC_ERROR_INT (0u)\r
-#define CC_ERROR_INT_XBAR_INST_NO (0u)\r
-#define EDMA3_TC0_ERROR_INT (0u)\r
-#define EDMA3_TC1_ERROR_INT (0u)\r
-#define TC0_ERROR_INT_XBAR_INST_NO TC0_ERROR_INT_A15_XBAR_INST_NO\r
-#define TC1_ERROR_INT_XBAR_INST_NO TC1_ERROR_INT_A15_XBAR_INST_NO\r
+#define EDMA3_CC_XFER_COMPLETION_INT (0U)\r
+#define EDMA3_CC_ERROR_INT (0U)\r
+#define CC_ERROR_INT_XBAR_INST_NO (0U)\r
+#define EDMA3_TC0_ERROR_INT (0U)\r
+#define EDMA3_TC1_ERROR_INT (0U)\r
+#define TC0_ERROR_INT_XBAR_INST_NO (TC0_ERROR_INT_A15_XBAR_INST_NO)\r
+#define TC1_ERROR_INT_XBAR_INST_NO (TC1_ERROR_INT_A15_XBAR_INST_NO)\r
#endif\r
\r
-#define EDMA3_TC2_ERROR_INT (0u)\r
-#define EDMA3_TC3_ERROR_INT (0u)\r
-#define EDMA3_TC4_ERROR_INT (0u)\r
-#define EDMA3_TC5_ERROR_INT (0u)\r
-#define EDMA3_TC6_ERROR_INT (0u)\r
-#define EDMA3_TC7_ERROR_INT (0u)\r
+#define EDMA3_TC2_ERROR_INT (0U)\r
+#define EDMA3_TC3_ERROR_INT (0U)\r
+#define EDMA3_TC4_ERROR_INT (0U)\r
+#define EDMA3_TC5_ERROR_INT (0U)\r
+#define EDMA3_TC6_ERROR_INT (0U)\r
+#define EDMA3_TC7_ERROR_INT (0U)\r
\r
-#define DSP1_EDMA3_CC_XFER_COMPLETION_INT (19u)\r
-#define DSP2_EDMA3_CC_XFER_COMPLETION_INT (20u)\r
-#define DSP1_EDMA3_CC_ERROR_INT (27u)\r
-#define DSP1_EDMA3_TC0_ERROR_INT (28u)\r
-#define DSP1_EDMA3_TC1_ERROR_INT (29u)\r
+#define DSP1_EDMA3_CC_XFER_COMPLETION_INT (19U)\r
+#define DSP2_EDMA3_CC_XFER_COMPLETION_INT (20U)\r
+#define DSP1_EDMA3_CC_ERROR_INT (27U)\r
+#define DSP1_EDMA3_TC0_ERROR_INT (28U)\r
+#define DSP1_EDMA3_TC1_ERROR_INT (29U)\r
\r
/** XBAR interrupt source index numbers for EDMA interrupts */\r
-#define XBAR_EDMA_TPCC_IRQ_REGION0 (361u)\r
-#define XBAR_EDMA_TPCC_IRQ_REGION1 (362u)\r
-#define XBAR_EDMA_TPCC_IRQ_REGION2 (363u)\r
-#define XBAR_EDMA_TPCC_IRQ_REGION3 (364u)\r
-#define XBAR_EDMA_TPCC_IRQ_REGION4 (365u)\r
-#define XBAR_EDMA_TPCC_IRQ_REGION5 (366u)\r
-#define XBAR_EDMA_TPCC_IRQ_REGION6 (367u)\r
-#define XBAR_EDMA_TPCC_IRQ_REGION7 (368u)\r
-\r
-#define XBAR_EDMA_TPCC_IRQ_ERR (359u)\r
-#define XBAR_EDMA_TC0_IRQ_ERR (370u)\r
-#define XBAR_EDMA_TC1_IRQ_ERR (371u)\r
+#define XBAR_EDMA_TPCC_IRQ_REGION0 (361U)\r
+#define XBAR_EDMA_TPCC_IRQ_REGION1 (362U)\r
+#define XBAR_EDMA_TPCC_IRQ_REGION2 (363U)\r
+#define XBAR_EDMA_TPCC_IRQ_REGION3 (364U)\r
+#define XBAR_EDMA_TPCC_IRQ_REGION4 (365U)\r
+#define XBAR_EDMA_TPCC_IRQ_REGION5 (366U)\r
+#define XBAR_EDMA_TPCC_IRQ_REGION6 (367U)\r
+#define XBAR_EDMA_TPCC_IRQ_REGION7 (368U)\r
+\r
+#define XBAR_EDMA_TPCC_IRQ_ERR (359U)\r
+#define XBAR_EDMA_TC0_IRQ_ERR (370U)\r
+#define XBAR_EDMA_TC1_IRQ_ERR (371U)\r
\r
/**\r
* EDMA3 interrupts (transfer completion, CC error etc.) correspond to different\r
*/\r
/* EDMA 0 */\r
\r
-#define EDMA3_HWI_INT_XFER_COMP (7u)\r
-#define EDMA3_HWI_INT_CC_ERR (7u)\r
-#define EDMA3_HWI_INT_TC0_ERR (10u)\r
-#define EDMA3_HWI_INT_TC1_ERR (10u)\r
-#define EDMA3_HWI_INT_TC2_ERR (10u)\r
-#define EDMA3_HWI_INT_TC3_ERR (10u)\r
+#define EDMA3_HWI_INT_XFER_COMP (7U)\r
+#define EDMA3_HWI_INT_CC_ERR (7U)\r
+#define EDMA3_HWI_INT_TC0_ERR (10U)\r
+#define EDMA3_HWI_INT_TC1_ERR (10U)\r
+#define EDMA3_HWI_INT_TC2_ERR (10U)\r
+#define EDMA3_HWI_INT_TC3_ERR (10U)\r
\r
/**\r
* \brief Mapping of DMA channels 0-31 to Hardware Events from\r
* various peripherals, which use EDMA for data transfer.\r
* All channels need not be mapped, some can be free also.\r
* 1: Mapped\r
- * 0: Not mapped\r
+ * 0: Not mapped (channel available)\r
*\r
* This mapping will be used to allocate DMA channels when user passes\r
* EDMA3_DRV_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory\r
* To allocate more DMA channels or TCCs, one has to modify the event mapping.\r
*/\r
/* 31 0 */\r
-#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA (0x3FC0C06Eu) /* TBD */\r
-#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_DSPEDMA (0x000FFFFFu) /* TBD */\r
-\r
+#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA (0x3FC0C06EU) /* TBD */\r
+#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_DSPEDMA (0x000FFFFFU) /* TBD */\r
+#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_EVEEDMA (0x00000000U) /* TBD */\r
\r
/**\r
* \brief Mapping of DMA channels 32-63 to Hardware Events from\r
* various peripherals, which use EDMA for data transfer.\r
* All channels need not be mapped, some can be free also.\r
* 1: Mapped\r
- * 0: Not mapped\r
+ * 0: Not mapped (channel available)\r
*\r
* This mapping will be used to allocate DMA channels when user passes\r
* EDMA3_DRV_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory\r
*\r
* To allocate more DMA channels or TCCs, one has to modify the event mapping.\r
*/\r
-#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA (0xF3FFFFF8u) /* TBD */\r
-#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_DSPEDMA (0x00000000u) /* TBD */\r
+#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA (0xF3FFFFFCU) /* TBD */\r
+#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_DSPEDMA (0x00000000U) /* TBD */\r
+#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_EVEEDMA (0x00000000U) /* TBD */\r
\r
\r
/* Variable which will be used internally for referring number of Event Queues*/\r
-unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] = {\r
+uint32_t numEdma3EvtQue[NUM_EDMA3_INSTANCES] = {\r
EDMA3_NUM_EVTQUE,\r
+ EDMA3_NUM_EVTQUE,\r
+ EDMA3_NUM_EVTQUE\r
};\r
\r
/* Variable which will be used internally for referring number of TCs. */\r
-unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] = {\r
+uint32_t numEdma3Tc[NUM_EDMA3_INSTANCES] = {\r
+ EDMA3_NUM_TC,\r
EDMA3_NUM_TC,\r
+ EDMA3_NUM_TC\r
};\r
\r
/**\r
* Variable which will be used internally for referring transfer completion\r
* interrupt.\r
*/\r
-unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
+uint32_t ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
{\r
+ /* EDMA3 INSTANCE# 0 */\r
{\r
- EDMA3_CC_XFER_COMPLETION_INT_A15, EDMA3_CC_XFER_COMPLETION_INT_A15,\r
- EDMA3_CC_XFER_COMPLETION_INT_DSP, EDMA3_CC_XFER_COMPLETION_INT_DSP,\r
- EDMA3_CC_XFER_COMPLETION_INT_IPU_C0, EDMA3_CC_XFER_COMPLETION_INT_IPU_C1,\r
- EDMA3_CC_XFER_COMPLETION_INT_IPU_C0, EDMA3_CC_XFER_COMPLETION_INT_IPU_C1,\r
+ EDMA3_CC_XFER_COMPLETION_INT_A15,\r
+ EDMA3_CC_XFER_COMPLETION_INT_A15,\r
+ EDMA3_CC_XFER_COMPLETION_INT_DSP,\r
+ EDMA3_CC_XFER_COMPLETION_INT_DSP,\r
+ EDMA3_CC_XFER_COMPLETION_INT_IPU_C0,\r
+ EDMA3_CC_XFER_COMPLETION_INT_IPU_C1,\r
+ EDMA3_CC_XFER_COMPLETION_INT_IPU_C0,\r
+ EDMA3_CC_XFER_COMPLETION_INT_IPU_C1\r
},\r
+ /* EDMA3 INSTANCE# 1 */\r
{\r
- 0u, 0u, DSP1_EDMA3_CC_XFER_COMPLETION_INT, DSP2_EDMA3_CC_XFER_COMPLETION_INT,\r
- 0u, 0u, 0u, 0u,\r
+ 0U,\r
+ 0U,\r
+ DSP1_EDMA3_CC_XFER_COMPLETION_INT,\r
+ DSP2_EDMA3_CC_XFER_COMPLETION_INT,\r
+ 0U,\r
+ 0U,\r
+ 0U,\r
+ 0U\r
},\r
+ /* EDMA3 INSTANCE# 2 */\r
+ {\r
+ 0U,\r
+ /* Region 1 (Associated to EVE core)*/\r
+ EDMA3_CC_XFER_COMPLETION_INT_EVE,\r
+ 0U,\r
+ 0U,\r
+ 0U,\r
+ 0U,\r
+ 0U,\r
+ 0U,\r
+ }\r
};\r
/** These are the Xbar instance numbers corresponding to interrupt numbers */\r
-unsigned int ccXferCompIntXbarInstNo[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
+uint32_t ccXferCompIntXbarInstNo[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
{\r
+ /* EDMA3 INSTANCE# 0 */\r
+ {\r
+ COMPLETION_INT_A15_XBAR_INST_NO,\r
+ COMPLETION_INT_A15_XBAR_INST_NO,\r
+ COMPLETION_INT_DSP_XBAR_INST_NO,\r
+ COMPLETION_INT_DSP_XBAR_INST_NO,\r
+ COMPLETION_INT_IPU_C0_XBAR_INST_NO,\r
+ COMPLETION_INT_IPU_C1_XBAR_INST_NO,\r
+ COMPLETION_INT_IPU_C0_XBAR_INST_NO,\r
+ COMPLETION_INT_IPU_C1_XBAR_INST_NO,\r
+ },\r
+ /* EDMA3 INSTANCE# 1 */\r
{\r
- COMPLETION_INT_A15_XBAR_INST_NO, COMPLETION_INT_A15_XBAR_INST_NO,\r
- COMPLETION_INT_DSP_XBAR_INST_NO, COMPLETION_INT_DSP_XBAR_INST_NO,\r
- COMPLETION_INT_IPU_C0_XBAR_INST_NO, COMPLETION_INT_IPU_C1_XBAR_INST_NO,\r
- COMPLETION_INT_IPU_C0_XBAR_INST_NO, COMPLETION_INT_IPU_C1_XBAR_INST_NO,\r
+ 0U,\r
+ 0U,\r
+ 0U,\r
+ 0U,\r
+ 0U,\r
+ 0U,\r
+ 0U,\r
+ 0U\r
},\r
+ /* EDMA3 INSTANCE# 2 */\r
+ {\r
+ /* \r
+ * For accessing EVE internal edma,\r
+ * there is no need to configure Xbar.\r
+ * So getting to zero.\r
+ */\r
+ 0U,\r
+ 0U,\r
+ 0U,\r
+ 0U,\r
+ 0U,\r
+ 0U,\r
+ 0U,\r
+ 0U\r
+ }\r
};\r
\r
/** These are the Interrupt Crossbar Index For EDMA Completion for different regions */\r
-unsigned int ccCompEdmaXbarIndex[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
+uint32_t ccCompEdmaXbarIndex[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
{\r
+ /* EDMA3 INSTANCE# 0 */\r
{\r
- XBAR_EDMA_TPCC_IRQ_REGION0, XBAR_EDMA_TPCC_IRQ_REGION1, XBAR_EDMA_TPCC_IRQ_REGION2, XBAR_EDMA_TPCC_IRQ_REGION3,\r
- XBAR_EDMA_TPCC_IRQ_REGION4, XBAR_EDMA_TPCC_IRQ_REGION5, XBAR_EDMA_TPCC_IRQ_REGION6, XBAR_EDMA_TPCC_IRQ_REGION7,\r
+ XBAR_EDMA_TPCC_IRQ_REGION0,\r
+ XBAR_EDMA_TPCC_IRQ_REGION1,\r
+ XBAR_EDMA_TPCC_IRQ_REGION2,\r
+ XBAR_EDMA_TPCC_IRQ_REGION3,\r
+ XBAR_EDMA_TPCC_IRQ_REGION4,\r
+ XBAR_EDMA_TPCC_IRQ_REGION5,\r
+ XBAR_EDMA_TPCC_IRQ_REGION6,\r
+ XBAR_EDMA_TPCC_IRQ_REGION7\r
+ },\r
+ /* EDMA3 INSTANCE# 1 */\r
+ {\r
+ XBAR_EDMA_TPCC_IRQ_REGION0,\r
+ XBAR_EDMA_TPCC_IRQ_REGION1,\r
+ XBAR_EDMA_TPCC_IRQ_REGION2,\r
+ XBAR_EDMA_TPCC_IRQ_REGION3,\r
+ XBAR_EDMA_TPCC_IRQ_REGION4,\r
+ XBAR_EDMA_TPCC_IRQ_REGION5,\r
+ XBAR_EDMA_TPCC_IRQ_REGION6,\r
+ XBAR_EDMA_TPCC_IRQ_REGION7\r
+ },\r
+ /* EDMA3 INSTANCE# 2 */\r
+ {\r
+ /* \r
+ * For accessing EVE internal edma,\r
+ * there is no need to configure Xbar.\r
+ * So getting to zero.\r
+ */\r
+ 0U,\r
+ 0U,\r
+ 0U,\r
+ 0U,\r
+ 0U,\r
+ 0U,\r
+ 0U,\r
+ 0U\r
}\r
};\r
\r
* Variable which will be used internally for referring channel controller's\r
* error interrupt.\r
*/\r
-unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {\r
- EDMA3_CC_ERROR_INT,DSP1_EDMA3_CC_ERROR_INT,\r
- };\r
-unsigned int ccErrorIntXbarInstNo[NUM_EDMA3_INSTANCES] = {\r
- CC_ERROR_INT_XBAR_INST_NO,\r
- };\r
-unsigned int ccErrEdmaXbarIndex[NUM_EDMA3_INSTANCES] = \r
+uint32_t ccErrorInt[NUM_EDMA3_INSTANCES] = \r
+{\r
+ EDMA3_CC_ERROR_INT,\r
+ DSP1_EDMA3_CC_ERROR_INT,\r
+ EDMA3_CC_ERROR_INT\r
+};\r
+uint32_t ccErrorIntXbarInstNo[NUM_EDMA3_INSTANCES] =\r
+{\r
+ CC_ERROR_INT_XBAR_INST_NO,\r
+ CC_ERROR_INT_XBAR_INST_NO,\r
+ CC_ERROR_INT_XBAR_INST_NO\r
+};\r
+uint32_t ccErrEdmaXbarIndex[NUM_EDMA3_INSTANCES] = \r
{\r
XBAR_EDMA_TPCC_IRQ_ERR,\r
+ XBAR_EDMA_TPCC_IRQ_ERR,\r
+ XBAR_EDMA_TPCC_IRQ_ERR\r
};\r
\r
/**\r
* Variable which will be used internally for referring transfer controllers'\r
* error interrupts.\r
*/\r
-unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][8] =\r
+uint32_t tcErrorInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
{\r
- {\r
- EDMA3_TC0_ERROR_INT, EDMA3_TC1_ERROR_INT,\r
- EDMA3_TC2_ERROR_INT, EDMA3_TC3_ERROR_INT,\r
- EDMA3_TC4_ERROR_INT, EDMA3_TC5_ERROR_INT,\r
- EDMA3_TC6_ERROR_INT, EDMA3_TC7_ERROR_INT,\r
- },\r
- {\r
- EDMA3_TC0_ERROR_INT, EDMA3_TC1_ERROR_INT,\r
- EDMA3_TC2_ERROR_INT, EDMA3_TC3_ERROR_INT,\r
- EDMA3_TC4_ERROR_INT, EDMA3_TC5_ERROR_INT,\r
- DSP1_EDMA3_TC0_ERROR_INT, DSP1_EDMA3_TC1_ERROR_INT,\r
- }\r
+ /* EDMA3 INSTANCE# 0 */\r
+ {\r
+ EDMA3_TC0_ERROR_INT, EDMA3_TC1_ERROR_INT,\r
+ EDMA3_TC2_ERROR_INT, EDMA3_TC3_ERROR_INT,\r
+ EDMA3_TC4_ERROR_INT, EDMA3_TC5_ERROR_INT,\r
+ EDMA3_TC6_ERROR_INT, EDMA3_TC7_ERROR_INT,\r
+ },\r
+ /* EDMA3 INSTANCE# 1 */\r
+ {\r
+ DSP1_EDMA3_TC0_ERROR_INT, DSP1_EDMA3_TC1_ERROR_INT,\r
+ EDMA3_TC0_ERROR_INT, EDMA3_TC1_ERROR_INT,\r
+ EDMA3_TC2_ERROR_INT, EDMA3_TC3_ERROR_INT,\r
+ EDMA3_TC4_ERROR_INT, EDMA3_TC5_ERROR_INT,\r
+ },\r
+ /* EDMA3 INSTANCE# 2 */\r
+ {\r
+ EDMA3_TC0_ERROR_INT, EDMA3_TC1_ERROR_INT,\r
+ EDMA3_TC2_ERROR_INT, EDMA3_TC3_ERROR_INT,\r
+ EDMA3_TC4_ERROR_INT, EDMA3_TC5_ERROR_INT,\r
+ EDMA3_TC6_ERROR_INT, EDMA3_TC7_ERROR_INT,\r
+ }\r
};\r
-unsigned int tcErrorIntXbarInstNo[NUM_EDMA3_INSTANCES][8] =\r
+uint32_t tcErrorIntXbarInstNo[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
{\r
- {\r
+ /* EDMA3 INSTANCE# 0 */\r
+ {\r
+ TC0_ERROR_INT_XBAR_INST_NO, TC1_ERROR_INT_XBAR_INST_NO,\r
+ 0U, 0U,\r
+ 0U, 0U,\r
+ 0U, 0U,\r
+ },\r
+ /* EDMA3 INSTANCE# 1 */\r
+ {\r
+ TC0_ERROR_INT_XBAR_INST_NO, TC1_ERROR_INT_XBAR_INST_NO,\r
+ 0U, 0U,\r
+ 0U, 0U,\r
+ 0U, 0U,\r
+ },\r
+ /* EDMA3 INSTANCE# 2 */\r
+ {\r
TC0_ERROR_INT_XBAR_INST_NO, TC1_ERROR_INT_XBAR_INST_NO,\r
- 0u, 0u,\r
- 0u, 0u,\r
- 0u, 0u,\r
- }\r
+ 0U, 0U,\r
+ 0U, 0U,\r
+ 0U, 0U,\r
+ }\r
};\r
\r
-unsigned int tcErrEdmaXbarIndex[NUM_EDMA3_INSTANCES][8] =\r
+uint32_t tcErrEdmaXbarIndex[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
{\r
- {\r
+ /* EDMA3 INSTANCE# 0 */\r
+ {\r
XBAR_EDMA_TC0_IRQ_ERR, XBAR_EDMA_TC1_IRQ_ERR,\r
- 0u, 0u,\r
- 0u, 0u, 0u, 0u,\r
- }\r
+ 0U, 0U,\r
+ 0U, 0U, 0U, 0U,\r
+ },\r
+ /* EDMA3 INSTANCE# 1 */\r
+ {\r
+ XBAR_EDMA_TC0_IRQ_ERR, XBAR_EDMA_TC1_IRQ_ERR,\r
+ 0U, 0U,\r
+ 0U, 0U, 0U, 0U,\r
+ },\r
+ /* EDMA3 INSTANCE# 2 */\r
+ {\r
+ XBAR_EDMA_TC0_IRQ_ERR, XBAR_EDMA_TC1_IRQ_ERR,\r
+ 0U, 0U,\r
+ 0U, 0U, 0U, 0U,\r
+ }\r
};\r
\r
\r
* Variables which will be used internally for referring the hardware interrupt\r
* for various EDMA3 interrupts.\r
*/\r
-unsigned int hwIntXferComp[NUM_EDMA3_INSTANCES] = {\r
- EDMA3_HWI_INT_XFER_COMP, EDMA3_HWI_INT_XFER_COMP,\r
- };\r
-\r
-unsigned int hwIntCcErr[NUM_EDMA3_INSTANCES] = {\r
- EDMA3_HWI_INT_CC_ERR, EDMA3_HWI_INT_CC_ERR,\r
- };\r
-\r
-unsigned int hwIntTcErr[NUM_EDMA3_INSTANCES][8] = {\r
- {\r
- EDMA3_HWI_INT_TC0_ERR,\r
- EDMA3_HWI_INT_TC1_ERR,\r
- EDMA3_HWI_INT_TC2_ERR,\r
- EDMA3_HWI_INT_TC3_ERR\r
- },\r
- {\r
- EDMA3_HWI_INT_TC0_ERR,\r
- EDMA3_HWI_INT_TC1_ERR,\r
- EDMA3_HWI_INT_TC2_ERR,\r
- EDMA3_HWI_INT_TC3_ERR\r
- }\r
- };\r
+uint32_t hwIntXferComp[NUM_EDMA3_INSTANCES] =\r
+{\r
+ EDMA3_HWI_INT_XFER_COMP,\r
+ EDMA3_HWI_INT_XFER_COMP,\r
+ EDMA3_CC_XFER_COMPLETION_INT\r
+};\r
+\r
+uint32_t hwIntCcErr[NUM_EDMA3_INSTANCES] =\r
+{\r
+ EDMA3_HWI_INT_CC_ERR,\r
+ EDMA3_HWI_INT_CC_ERR,\r
+ EDMA3_CC_ERROR_INT\r
+};\r
+\r
+uint32_t hwIntTcErr[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
+{\r
+ /* EDMA3 INSTANCE# 0 */\r
+ {\r
+ EDMA3_HWI_INT_TC0_ERR ,\r
+ EDMA3_HWI_INT_TC1_ERR ,\r
+ EDMA3_HWI_INT_TC2_ERR ,\r
+ EDMA3_HWI_INT_TC3_ERR ,\r
+ 0U ,\r
+ 0U ,\r
+ 0U ,\r
+ 0U \r
+ },\r
+ /* EDMA3 INSTANCE# 1 */\r
+ {\r
+ EDMA3_HWI_INT_TC0_ERR ,\r
+ EDMA3_HWI_INT_TC1_ERR ,\r
+ EDMA3_HWI_INT_TC2_ERR ,\r
+ EDMA3_HWI_INT_TC3_ERR ,\r
+ 0U ,\r
+ 0U ,\r
+ 0U ,\r
+ 0U \r
+ },\r
+ /* EDMA3 INSTANCE# 2 */\r
+ {\r
+ EDMA3_TC0_ERROR_INT ,\r
+ EDMA3_TC1_ERROR_INT ,\r
+ EDMA3_TC2_ERROR_INT ,\r
+ EDMA3_TC3_ERROR_INT ,\r
+ 0U ,\r
+ 0U ,\r
+ 0U ,\r
+ 0U \r
+ }\r
+};\r
\r
/**\r
* \brief Base address as seen from the different cores may be different\r
#define EDMA3_CC_BASE_ADDR ((void *)(0x63300000))\r
#define EDMA3_TC0_BASE_ADDR ((void *)(0x63400000))\r
#define EDMA3_TC1_BASE_ADDR ((void *)(0x63500000))\r
+#elif (defined BUILD_TDA2XX_EVE)\r
+#define EDMA3_CC_BASE_ADDR ((void *)(0x400A0000))\r
+#define EDMA3_TC0_BASE_ADDR ((void *)(0x40086000))\r
+#define EDMA3_TC1_BASE_ADDR ((void *)(0x40087000))\r
#else\r
#define EDMA3_CC_BASE_ADDR ((void *)(0x0))\r
#define EDMA3_TC0_BASE_ADDR ((void *)(0x0))\r
* for a channel number to a parameter entry number or, in other words,\r
* PaRAM entry n corresponds to channel n.\r
*/\r
- 1u,\r
+ 1U,\r
\r
/** Existence of memory protection feature */\r
- 0u,\r
+ 0U,\r
\r
/** Global Register Region of CC Registers */\r
EDMA3_CC_BASE_ADDR,\r
* device (ARM, DSP, USB, etc)\r
*/\r
{\r
- 0u,\r
- 1u,\r
- 0u,\r
- 0u,\r
- 0u,\r
- 0u,\r
- 0u,\r
- 0u\r
+ 0U,\r
+ 1U,\r
+ 0U,\r
+ 0U,\r
+ 0U,\r
+ 0U,\r
+ 0U,\r
+ 0U\r
},\r
/**\r
* \brief To Configure the Threshold level of number of events\r
* in the queue watermark threshold register (QWMTHRA).\r
*/\r
{\r
- 16u,\r
- 16u,\r
- 0u,\r
- 0u,\r
- 0u,\r
- 0u,\r
- 0u,\r
- 0u\r
+ 16U,\r
+ 16U,\r
+ 0U,\r
+ 0U,\r
+ 0U,\r
+ 0U,\r
+ 0U,\r
+ 0U\r
},\r
\r
/**\r
* DBS values. It is defined in Bytes.\r
*/\r
{\r
- 16u,\r
- 16u,\r
- 0u,\r
- 0u,\r
- 0u,\r
- 0u,\r
- 0u,\r
- 0u\r
+ 16U,\r
+ 16U,\r
+ 0U,\r
+ 0U,\r
+ 0U,\r
+ 0U,\r
+ 0U,\r
+ 0U\r
},\r
\r
/**\r
* All channels need not be mapped, some can be free also.\r
*/\r
{\r
- EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA,\r
- EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA\r
+ EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA,\r
+ EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA\r
}\r
},\r
{\r
* for a channel number to a parameter entry number or, in other words,\r
* PaRAM entry n corresponds to channel n.\r
*/\r
- 1u,\r
+ 1U,\r
\r
/** Existence of memory protection feature */\r
- 0u,\r
+ 0U,\r
\r
/** Global Register Region of CC Registers */\r
DSP1_EDMA3_CC_BASE_ADDR,\r
* device (ARM, DSP, USB, etc)\r
*/\r
{\r
- 0u,\r
- 1u,\r
- 0u,\r
- 0u,\r
- 0u,\r
- 0u,\r
- 0u,\r
- 0u\r
+ 0U,\r
+ 1U,\r
+ 0U,\r
+ 0U,\r
+ 0U,\r
+ 0U,\r
+ 0U,\r
+ 0U\r
},\r
/**\r
* \brief To Configure the Threshold level of number of events\r
* in the queue watermark threshold register (QWMTHRA).\r
*/\r
{\r
- 16u,\r
- 16u,\r
- 0u,\r
- 0u,\r
- 0u,\r
- 0u,\r
- 0u,\r
- 0u\r
+ 16U,\r
+ 16U,\r
+ 0U,\r
+ 0U,\r
+ 0U,\r
+ 0U,\r
+ 0U,\r
+ 0U\r
},\r
\r
/**\r
* DBS values. It is defined in Bytes.\r
*/\r
{\r
- 16u,\r
- 16u,\r
- 0u,\r
- 0u,\r
- 0u,\r
- 0u,\r
- 0u,\r
- 0u\r
+ 16U,\r
+ 16U,\r
+ 0U,\r
+ 0U,\r
+ 0U,\r
+ 0U,\r
+ 0U,\r
+ 0U\r
},\r
\r
/**\r
@@ -809,793 +1064,1549 @@ EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
},\r
\r
- /**\r
- * \brief Mapping of DMA channels to Hardware Events from\r
- * various peripherals, which use EDMA for data transfer.\r
- * All channels need not be mapped, some can be free also.\r
- */\r
- {\r
- EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_DSPEDMA,\r
- EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_DSPEDMA\r
- }\r
- },\r
-};\r
+ /**\r
+ * \brief Mapping of DMA channels to Hardware Events from\r
+ * various peripherals, which use EDMA for data transfer.\r
+ * All channels need not be mapped, some can be free also.\r
+ */\r
+ {\r
+ EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_DSPEDMA,\r
+ EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_DSPEDMA\r
+ }\r
+ },\r
+ {\r
+ /* EDMA3 INSTANCE# 2 */\r
+ /** Total number of DMA Channels supported by the EDMA3 Controller */\r
+ EDMA3_NUM_DMA_CHANNELS_EVE,\r
+ /** Total number of QDMA Channels supported by the EDMA3 Controller */\r
+ EDMA3_NUM_QDMA_CHANNELS_EVE,\r
+ /** Total number of TCCs supported by the EDMA3 Controller */\r
+ EDMA3_NUM_TCC_EVE,\r
+ /** Total number of PaRAM Sets supported by the EDMA3 Controller */\r
+ EDMA3_NUM_PARAMSET_EVE,\r
+ /** Total number of Event Queues in the EDMA3 Controller */\r
+ EDMA3_NUM_EVTQUE_EVE,\r
+ /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller*/\r
+ EDMA3_NUM_TC_EVE,\r
+ /** Number of Regions on this EDMA3 controller */\r
+ EDMA3_NUM_REGIONS_EVE,\r
+\r
+ /**\r
+ * \brief Channel mapping existence\r
+ * A value of 0 (No channel mapping) implies that there is fixed association\r
+ * for a channel number to a parameter entry number or, in other words,\r
+ * PaRAM entry n corresponds to channel n.\r
+ */\r
+ 1U,\r
+\r
+ /** Existence of memory protection feature */\r
+ 0U,\r
+\r
+ /** Global Register Region of CC Registers */\r
+ EDMA3_CC_BASE_ADDR,\r
+ /** Transfer Controller (TC) Registers */\r
+ {\r
+ EDMA3_TC0_BASE_ADDR,\r
+ EDMA3_TC1_BASE_ADDR,\r
+ (void *)NULL,\r
+ (void *)NULL,\r
+ (void *)NULL,\r
+ (void *)NULL,\r
+ (void *)NULL,\r
+ (void *)NULL\r
+ },\r
+ /** Interrupt no. for Transfer Completion */\r
+ EDMA3_CC_XFER_COMPLETION_INT,\r
+ /** Interrupt no. for CC Error */\r
+ EDMA3_CC_ERROR_INT,\r
+ /** Interrupt no. for TCs Error */\r
+ {\r
+ EDMA3_TC0_ERROR_INT,\r
+ EDMA3_TC1_ERROR_INT,\r
+ EDMA3_TC2_ERROR_INT,\r
+ EDMA3_TC3_ERROR_INT,\r
+ EDMA3_TC4_ERROR_INT,\r
+ EDMA3_TC5_ERROR_INT,\r
+ EDMA3_TC6_ERROR_INT,\r
+ EDMA3_TC7_ERROR_INT\r
+ },\r
+\r
+ /**\r
+ * \brief EDMA3 TC priority setting\r
+ *\r
+ * User can program the priority of the Event Queues\r
+ * at a system-wide level. This means that the user can set the\r
+ * priority of an IO initiated by either of the TCs (Transfer Controllers)\r
+ * relative to IO initiated by the other bus masters on the\r
+ * device (ARM, DSP, USB, etc)\r
+ */\r
+ {\r
+ 0U,\r
+ 1U,\r
+ 0U,\r
+ 0U,\r
+ 0U,\r
+ 0U,\r
+ 0U,\r
+ 0U\r
+ },\r
+ /**\r
+ * \brief To Configure the Threshold level of number of events\r
+ * that can be queued up in the Event queues. EDMA3CC error register\r
+ * (CCERR) will indicate whether or not at any instant of time the\r
+ * number of events queued up in any of the event queues exceeds\r
+ * or equals the threshold/watermark value that is set\r
+ * in the queue watermark threshold register (QWMTHRA).\r
+ */\r
+ {\r
+ 16U,\r
+ 16U,\r
+ 0U,\r
+ 0U,\r
+ 0U,\r
+ 0U,\r
+ 0U,\r
+ 0U\r
+ },\r
+\r
+ /**\r
+ * \brief To Configure the Default Burst Size (DBS) of TCs.\r
+ * An optimally-sized command is defined by the transfer controller\r
+ * default burst size (DBS). Different TCs can have different\r
+ * DBS values. It is defined in Bytes.\r
+ */\r
+ {\r
+ 16U,\r
+ 16U,\r
+ 0U,\r
+ 0U,\r
+ 0U,\r
+ 0U,\r
+ 0U,\r
+ 0U\r
+ },\r
+\r
+ /**\r
+ * \brief Mapping from each DMA channel to a Parameter RAM set,\r
+ * if it exists, otherwise of no use.\r
+ */\r
+ {\r
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP\r
+ },\r
+\r
+ /**\r
+ * \brief Mapping from each DMA channel to a TCC. This specific\r
+ * TCC code will be returned when the transfer is completed\r
+ * on the mapped channel.\r
+ */\r
+ {\r
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+ },\r
+\r
+ /**\r
+ * \brief Mapping of DMA channels to Hardware Events from\r
+ * various peripherals, which use EDMA for data transfer.\r
+ * All channels need not be mapped, some can be free also.\r
+ */\r
+ {\r
+ EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_EVEEDMA,\r
+ EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_EVEEDMA\r
+ }\r
+ },\r
+\r
+};\r
+\r
+/**\r
+ * \brief Resource splitting defines for Own/Reserved DMA/QDMA channels and TCCs\r
+ * For PaRAMs explicit defines are not present but should be replaced in the structure sampleInstInitConfig\r
+ * Default configuration has all resources owned by all cores and none reserved except for first 64 PaRAMs corrosponding to DMA channels\r
+ * Resources to be Split properly by application and rebuild the sample library to avoid resource conflict\r
+ *\r
+ * Only Resources owned by a perticular core are allocated by Driver\r
+ * Reserved resources are not allocated if requested for any available resource\r
+ */\r
+ \r
+/* Driver Instance Initialization Configuration */\r
+EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
+ {\r
+ /* EDMA3 INSTANCE# 0 */\r
+ {\r
+ /* Resources owned/reserved by region 0 (Associated to MPU core 0)*/\r
+ {\r
+ /* ownPaRAMSets */\r
+ /* 31 0 63 32 95 64 127 96 */\r
+ {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
+ /* 159 128 191 160 223 192 255 224 */\r
+ 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
+ /* 287 256 319 288 351 320 383 352 */\r
+ 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
+ /* 415 384 447 416 479 448 511 480 */\r
+ 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},\r
+\r
+ /* ownDmaChannels */\r
+ /* 31 0 63 32 */\r
+ {0xFFFFFFFFU, 0xFFFFFFFFU},\r
+\r
+ /* ownQdmaChannels */\r
+ /* 31 0 */\r
+ {0x000000FFU},\r
+\r
+ /* ownTccs */\r
+ /* 31 0 63 32 */\r
+ {0xFFFFFFFFU, 0xFFFFFFFFU},\r
+\r
+ /* resvdPaRAMSets */\r
+ /* 31 0 63 32 95 64 127 96 */\r
+ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+ /* 159 128 191 160 223 192 255 224 */\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+ /* 287 256 319 288 351 320 383 352 */\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+ /* 415 384 447 416 479 448 511 480 */\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
+\r
+ /* resvdDmaChannels */\r
+ /* 31 0 63 32 */\r
+ {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA},\r
+\r
+ /* resvdQdmaChannels */\r
+ /* 31 0 */\r
+ {0x00U},\r
+\r
+ /* resvdTccs */\r
+ /* 31 0 63 32 */\r
+ {0x00U, 0x00U},\r
+ },\r
+\r
+ /* Resources owned/reserved by region 1 (Associated to MPU core 1) */\r
+ {\r
+ /* ownPaRAMSets */\r
+ /* 31 0 63 32 95 64 127 96 */\r
+ {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
+ /* 159 128 191 160 223 192 255 224 */\r
+ 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
+ /* 287 256 319 288 351 320 383 352 */\r
+ 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
+ /* 415 384 447 416 479 448 511 480 */\r
+ 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},\r
+/* \r
+ * This instance 0 and region 1 is only accessible to MPU core 1.\r
+ * So other cores should not be access.\r
+ */\r
+#ifdef BUILD_TDA2XX_MPU\r
+ /* ownDmaChannels */\r
+ /* 31 0 63 32 */\r
+ {0xFFFFFFFFU, 0xFFFFFFFFU},\r
+#else\r
+ /* ownDmaChannels */\r
+ /* 31 0 63 32 */\r
+ {0x00000000U, 0x00000000U},\r
+#endif\r
+ /* ownQdmaChannels */\r
+ /* 31 0 */\r
+ {0x000000FFU},\r
+\r
+ /* ownTccs */\r
+ /* 31 0 63 32 */\r
+ {0xFFFFFFFFU, 0xFFFFFFFFU},\r
+\r
+ /* resvdPaRAMSets */\r
+ /* 31 0 63 32 95 64 127 96 */\r
+ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+ /* 159 128 191 160 223 192 255 224 */\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+ /* 287 256 319 288 351 320 383 352 */\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+ /* 415 384 447 416 479 448 511 480 */\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
+\r
+ /* resvdDmaChannels */\r
+ /* 31 0 63 32 */\r
+ {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA},\r
+\r
+ /* resvdQdmaChannels */\r
+ /* 31 0 */\r
+ {0x00U},\r
+\r
+ /* resvdTccs */\r
+ /* 31 0 63 32 */\r
+ {0x00U, 0x00U},\r
+ },\r
+\r
+ /* Resources owned/reserved by region 2 (Associated to any DSP1)*/\r
+ {\r
+ /* ownPaRAMSets */\r
+ /* 31 0 63 32 95 64 127 96 */\r
+ {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
+ /* 159 128 191 160 223 192 255 224 */\r
+ 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
+ /* 287 256 319 288 351 320 383 352 */\r
+ 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
+ /* 415 384 447 416 479 448 511 480 */\r
+ 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},\r
+\r
+ /* ownDmaChannels */\r
+ /* 31 0 63 32 */\r
+ {0xFFFFFFFFU, 0xFFFFFFFFU},\r
+\r
+ /* ownQdmaChannels */\r
+ /* 31 0 */\r
+ {0x000000FFU},\r
+\r
+ /* ownTccs */\r
+ /* 31 0 63 32 */\r
+ {0xFFFFFFFFU, 0xFFFFFFFFU},\r
+\r
+ /* resvdPaRAMSets */\r
+ /* 31 0 63 32 95 64 127 96 */\r
+ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+ /* 159 128 191 160 223 192 255 224 */\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+ /* 287 256 319 288 351 320 383 352 */\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+ /* 415 384 447 416 479 448 511 480 */\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
+\r
+ /* resvdDmaChannels */\r
+ /* 31 0 63 32 */\r
+ {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA},\r
+\r
+ /* resvdQdmaChannels */\r
+ /* 31 0 */\r
+ {0x00U},\r
+\r
+ /* resvdTccs */\r
+ /* 31 0 63 32 */\r
+ {0x00U, 0x00U},\r
+ },\r
+\r
+ /* Resources owned/reserved by region 3 (Associated to any DSP2)*/\r
+ {\r
+ /* ownPaRAMSets */\r
+ /* 31 0 63 32 95 64 127 96 */\r
+ {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
+ /* 159 128 191 160 223 192 255 224 */\r
+ 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
+ /* 287 256 319 288 351 320 383 352 */\r
+ 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
+ /* 415 384 447 416 479 448 511 480 */\r
+ 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},\r
+\r
+ /* ownDmaChannels */\r
+ /* 31 0 63 32 */\r
+ {0xFFFFFFFFU, 0xFFFFFFFFU},\r
+\r
+ /* ownQdmaChannels */\r
+ /* 31 0 */\r
+ {0x000000FFU},\r
+\r
+ /* ownTccs */\r
+ /* 31 0 63 32 */\r
+ {0xFFFFFFFFU, 0xFFFFFFFFU},\r
+\r
+ /* resvdPaRAMSets */\r
+ /* 31 0 63 32 95 64 127 96 */\r
+ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+ /* 159 128 191 160 223 192 255 224 */\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+ /* 287 256 319 288 351 320 383 352 */\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+ /* 415 384 447 416 479 448 511 480 */\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
+\r
+ /* resvdDmaChannels */\r
+ /* 31 0 63 32 */\r
+ {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA},\r
+\r
+ /* resvdQdmaChannels */\r
+ /* 31 0 */\r
+ {0x00U},\r
+\r
+ /* resvdTccs */\r
+ /* 31 0 63 32 */\r
+ {0x00U, 0x00U},\r
+ },\r
+\r
+ /* Resources owned/reserved by region 4 (Associated to any IPU1 core 0)*/\r
+ {\r
+ /* ownPaRAMSets */\r
+ /* 31 0 63 32 95 64 127 96 */\r
+ {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
+ /* 159 128 191 160 223 192 255 224 */\r
+ 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
+ /* 287 256 319 288 351 320 383 352 */\r
+ 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
+ /* 415 384 447 416 479 448 511 480 */\r
+ 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},\r
+\r
+ /* ownDmaChannels */\r
+ /* 31 0 63 32 */\r
+ {0xFFFFFFFFU, 0xFFFFFFFFU},\r
+\r
+ /* ownQdmaChannels */\r
+ /* 31 0 */\r
+ {0x000000FFU},\r
+\r
+ /* ownTccs */\r
+ /* 31 0 63 32 */\r
+ {0xFFFFFFFFU, 0xFFFFFFFFU},\r
+\r
+ /* resvdPaRAMSets */\r
+ /* 31 0 63 32 95 64 127 96 */\r
+ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+ /* 159 128 191 160 223 192 255 224 */\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+ /* 287 256 319 288 351 320 383 352 */\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+ /* 415 384 447 416 479 448 511 480 */\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
+\r
+ /* resvdDmaChannels */\r
+ /* 31 0 63 32 */\r
+ {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA},\r
+\r
+ /* resvdQdmaChannels */\r
+ /* 31 0 */\r
+ {0x00U},\r
+\r
+ /* resvdTccs */\r
+ /* 31 0 63 32 */\r
+ {0x00U, 0x00U},\r
+ },\r
+\r
+ /* Resources owned/reserved by region 5 (Associated to any IPU1 core 1)*/\r
+ {\r
+ /* ownPaRAMSets */\r
+ /* 31 0 63 32 95 64 127 96 */\r
+ {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
+ /* 159 128 191 160 223 192 255 224 */\r
+ 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
+ /* 287 256 319 288 351 320 383 352 */\r
+ 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
+ /* 415 384 447 416 479 448 511 480 */\r
+ 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},\r
+\r
+ /* ownDmaChannels */\r
+ /* 31 0 63 32 */\r
+ {0xFFFFFFFFU, 0xFFFFFFFFU},\r
+\r
+ /* ownQdmaChannels */\r
+ /* 31 0 */\r
+ {0x000000FFU},\r
+\r
+ /* ownTccs */\r
+ /* 31 0 63 32 */\r
+ {0xFFFFFFFFU, 0xFFFFFFFFU},\r
+\r
+ /* resvdPaRAMSets */\r
+ /* 31 0 63 32 95 64 127 96 */\r
+ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+ /* 159 128 191 160 223 192 255 224 */\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+ /* 287 256 319 288 351 320 383 352 */\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+ /* 415 384 447 416 479 448 511 480 */\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
+\r
+ /* resvdDmaChannels */\r
+ /* 31 0 63 32 */\r
+ {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA},\r
+\r
+ /* resvdQdmaChannels */\r
+ /* 31 0 */\r
+ {0x00U},\r
+\r
+ /* resvdTccs */\r
+ /* 31 0 63 32 */\r
+ {0x00U, 0x00U},\r
+ },\r
+\r
+ /* Resources owned/reserved by region 6 (Associated to any IPU2 core 0)*/\r
+ {\r
+ /* ownPaRAMSets */\r
+ /* 31 0 63 32 95 64 127 96 */\r
+ {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
+ /* 159 128 191 160 223 192 255 224 */\r
+ 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
+ /* 287 256 319 288 351 320 383 352 */\r
+ 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
+ /* 415 384 447 416 479 448 511 480 */\r
+ 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},\r
+\r
+ /* ownDmaChannels */\r
+ /* 31 0 63 32 */\r
+ {0xFFFFFFFFU, 0xFFFFFFFFU},\r
+\r
+ /* ownQdmaChannels */\r
+ /* 31 0 */\r
+ {0x000000FFU},\r
+\r
+ /* ownTccs */\r
+ /* 31 0 63 32 */\r
+ {0xFFFFFFFFU, 0xFFFFFFFFU},\r
+\r
+ /* resvdPaRAMSets */\r
+ /* 31 0 63 32 95 64 127 96 */\r
+ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+ /* 159 128 191 160 223 192 255 224 */\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+ /* 287 256 319 288 351 320 383 352 */\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+ /* 415 384 447 416 479 448 511 480 */\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
+\r
+ /* resvdDmaChannels */\r
+ /* 31 0 63 32 */\r
+ {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA},\r
+\r
+ /* resvdQdmaChannels */\r
+ /* 31 0 */\r
+ {0x00U},\r
+\r
+ /* resvdTccs */\r
+ /* 31 0 63 32 */\r
+ {0x00U, 0x00U},\r
+ },\r
+\r
+ /* Resources owned/reserved by region 7 (Associated to any IPU2 core 1)*/\r
+ {\r
+ /* ownPaRAMSets */\r
+ /* 31 0 63 32 95 64 127 96 */\r
+ {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
+ /* 159 128 191 160 223 192 255 224 */\r
+ 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
+ /* 287 256 319 288 351 320 383 352 */\r
+ 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
+ /* 415 384 447 416 479 448 511 480 */\r
+ 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},\r
+\r
+ /* ownDmaChannels */\r
+ /* 31 0 63 32 */\r
+ {0xFFFFFFFFU, 0xFFFFFFFFU},\r
\r
-/**\r
- * \brief Resource splitting defines for Own/Reserved DMA/QDMA channels and TCCs\r
- * For PaRAMs explicit defines are not present but should be replaced in the structure sampleInstInitConfig\r
- * Default configuration has all resources owned by all cores and none reserved except for first 64 PaRAMs corrosponding to DMA channels\r
- * Resources to be Split properly by application and rebuild the sample library to avoid resource conflict\r
- *\r
- * Only Resources owned by a perticular core are allocated by Driver\r
- * Reserved resources are not allocated if requested for any available resource\r
- */\r
- \r
-/* Driver Instance Initialization Configuration */\r
-EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
- {\r
- /* EDMA3 INSTANCE# 0 */\r
+ /* ownQdmaChannels */\r
+ /* 31 0 */\r
+ {0x000000FFU},\r
+\r
+ /* ownTccs */\r
+ /* 31 0 63 32 */\r
+ {0xFFFFFFFFU, 0xFFFFFFFFU},\r
+\r
+ /* resvdPaRAMSets */\r
+ /* 31 0 63 32 95 64 127 96 */\r
+ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+ /* 159 128 191 160 223 192 255 224 */\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+ /* 287 256 319 288 351 320 383 352 */\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+ /* 415 384 447 416 479 448 511 480 */\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
+\r
+ /* resvdDmaChannels */\r
+ /* 31 0 63 32 */\r
+ {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA},\r
+\r
+ /* resvdQdmaChannels */\r
+ /* 31 0 */\r
+ {0x00U},\r
+\r
+ /* resvdTccs */\r
+ /* 31 0 63 32 */\r
+ {0x00U, 0x00U},\r
+ },\r
+ },\r
+ /* EDMA3 INSTANCE# 1 DSP1 EDMA*/\r
{\r
- /* Resources owned/reserved by region 0 (Associated to MPU core 0)*/\r
+ /* Resources owned/reserved by region 0 (Not Associated to any core supported)*/\r
{\r
/* ownPaRAMSets */\r
/* 31 0 63 32 95 64 127 96 */\r
- {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
/* 159 128 191 160 223 192 255 224 */\r
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
/* 287 256 319 288 351 320 383 352 */\r
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
/* 415 384 447 416 479 448 511 480 */\r
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
\r
/* ownDmaChannels */\r
/* 31 0 63 32 */\r
- {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+ {0x00000000U, 0x00000000U},\r
\r
/* ownQdmaChannels */\r
/* 31 0 */\r
- {0x000000FFu},\r
+ {0x00000000U},\r
\r
/* ownTccs */\r
/* 31 0 63 32 */\r
- {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+ {0x00000000U, 0x00000000U},\r
\r
/* resvdPaRAMSets */\r
/* 31 0 63 32 95 64 127 96 */\r
- {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
+ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
/* 159 128 191 160 223 192 255 224 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
/* 287 256 319 288 351 320 383 352 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
/* 415 384 447 416 479 448 511 480 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
\r
/* resvdDmaChannels */\r
/* 31 0 63 32 */\r
- {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA},\r
+ {0x00000000U, 0x00000000U},\r
\r
/* resvdQdmaChannels */\r
/* 31 0 */\r
- {0x00u},\r
+ {0x00000000U},\r
\r
/* resvdTccs */\r
/* 31 0 63 32 */\r
- {0x00u, 0x00u},\r
+ {0x00000000U, 0x00000000U},\r
},\r
\r
- /* Resources owned/reserved by region 1 (Associated to MPU core 1) */\r
+ /* Resources owned/reserved by region 1 (Not Associated to any core supported) */\r
{\r
/* ownPaRAMSets */\r
/* 31 0 63 32 95 64 127 96 */\r
- {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
/* 159 128 191 160 223 192 255 224 */\r
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
/* 287 256 319 288 351 320 383 352 */\r
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
/* 415 384 447 416 479 448 511 480 */\r
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
\r
/* ownDmaChannels */\r
/* 31 0 63 32 */\r
- {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+ {0x00000000U, 0x00000000U},\r
\r
/* ownQdmaChannels */\r
/* 31 0 */\r
- {0x000000FFu},\r
+ {0x00000000U},\r
\r
/* ownTccs */\r
/* 31 0 63 32 */\r
- {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+ {0x00000000U, 0x00000000U},\r
\r
/* resvdPaRAMSets */\r
/* 31 0 63 32 95 64 127 96 */\r
- {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
+ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
/* 159 128 191 160 223 192 255 224 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
/* 287 256 319 288 351 320 383 352 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
/* 415 384 447 416 479 448 511 480 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
\r
/* resvdDmaChannels */\r
/* 31 0 63 32 */\r
- {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA},\r
+ {0x00000000U, 0x00000000U},\r
\r
/* resvdQdmaChannels */\r
/* 31 0 */\r
- {0x00u},\r
+ {0x00000000U},\r
\r
/* resvdTccs */\r
/* 31 0 63 32 */\r
- {0x00u, 0x00u},\r
+ {0x00000000U, 0x00000000U},\r
},\r
\r
- /* Resources owned/reserved by region 2 (Associated to any DSP1)*/\r
+ /* Resources owned/reserved by region 2 (Associated to any DSP core 0)*/\r
{\r
/* ownPaRAMSets */\r
/* 31 0 63 32 95 64 127 96 */\r
- {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+ {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
/* 159 128 191 160 223 192 255 224 */\r
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+ 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
/* 287 256 319 288 351 320 383 352 */\r
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+ 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
/* 415 384 447 416 479 448 511 480 */\r
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
+ 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},\r
\r
/* ownDmaChannels */\r
/* 31 0 63 32 */\r
- {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+ {0xFFFFFFFFU, 0xFFFFFFFFU},\r
\r
/* ownQdmaChannels */\r
/* 31 0 */\r
- {0x000000FFu},\r
+ {0x000000FFU},\r
\r
/* ownTccs */\r
/* 31 0 63 32 */\r
- {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+ {0xFFFFFFFFU, 0xFFFFFFFFU},\r
\r
/* resvdPaRAMSets */\r
/* 31 0 63 32 95 64 127 96 */\r
- {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
+ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
/* 159 128 191 160 223 192 255 224 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
/* 287 256 319 288 351 320 383 352 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
/* 415 384 447 416 479 448 511 480 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
\r
/* resvdDmaChannels */\r
/* 31 0 63 32 */\r
- {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA},\r
+ {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_DSPEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_DSPEDMA},\r
\r
/* resvdQdmaChannels */\r
/* 31 0 */\r
- {0x00u},\r
+ {0x00U},\r
\r
/* resvdTccs */\r
/* 31 0 63 32 */\r
- {0x00u, 0x00u},\r
+ {0x00U, 0x00U},\r
},\r
\r
- /* Resources owned/reserved by region 3 (Associated to any DSP2)*/\r
+ /* Resources owned/reserved by region 3 (Associated to any DSP core 1)*/\r
{\r
/* ownPaRAMSets */\r
/* 31 0 63 32 95 64 127 96 */\r
- {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+ {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
/* 159 128 191 160 223 192 255 224 */\r
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+ 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
/* 287 256 319 288 351 320 383 352 */\r
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+ 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
/* 415 384 447 416 479 448 511 480 */\r
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
+ 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},\r
\r
/* ownDmaChannels */\r
/* 31 0 63 32 */\r
- {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+ {0xFFFFFFFFU, 0xFFFFFFFFU},\r
\r
/* ownQdmaChannels */\r
/* 31 0 */\r
- {0x000000FFu},\r
+ {0x000000FFU},\r
\r
/* ownTccs */\r
/* 31 0 63 32 */\r
- {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+ {0xFFFFFFFFU, 0xFFFFFFFFU},\r
\r
/* resvdPaRAMSets */\r
/* 31 0 63 32 95 64 127 96 */\r
- {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
+ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
/* 159 128 191 160 223 192 255 224 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
/* 287 256 319 288 351 320 383 352 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
/* 415 384 447 416 479 448 511 480 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
\r
/* resvdDmaChannels */\r
/* 31 0 63 32 */\r
- {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA},\r
+ {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_DSPEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_DSPEDMA},\r
\r
/* resvdQdmaChannels */\r
/* 31 0 */\r
- {0x00u},\r
+ {0x00U},\r
\r
/* resvdTccs */\r
/* 31 0 63 32 */\r
- {0x00u, 0x00u},\r
+ {0x00U, 0x00U},\r
},\r
\r
- /* Resources owned/reserved by region 4 (Associated to any IPU1 core 0)*/\r
+ /* Resources owned/reserved by region 4 (Not Associated to any core supported)*/\r
{\r
/* ownPaRAMSets */\r
/* 31 0 63 32 95 64 127 96 */\r
- {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
/* 159 128 191 160 223 192 255 224 */\r
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
/* 287 256 319 288 351 320 383 352 */\r
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
/* 415 384 447 416 479 448 511 480 */\r
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
\r
/* ownDmaChannels */\r
/* 31 0 63 32 */\r
- {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+ {0x00000000U, 0x00000000U},\r
\r
/* ownQdmaChannels */\r
/* 31 0 */\r
- {0x000000FFu},\r
+ {0x00000000U},\r
\r
/* ownTccs */\r
/* 31 0 63 32 */\r
- {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+ {0x00000000U, 0x00000000U},\r
\r
/* resvdPaRAMSets */\r
/* 31 0 63 32 95 64 127 96 */\r
- {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
+ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
/* 159 128 191 160 223 192 255 224 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
/* 287 256 319 288 351 320 383 352 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
/* 415 384 447 416 479 448 511 480 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
\r
/* resvdDmaChannels */\r
/* 31 0 63 32 */\r
- {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA},\r
+ {0x00000000U, 0x00000000U},\r
\r
/* resvdQdmaChannels */\r
/* 31 0 */\r
- {0x00u},\r
+ {0x00000000U},\r
\r
/* resvdTccs */\r
/* 31 0 63 32 */\r
- {0x00u, 0x00u},\r
+ {0x00000000U, 0x00000000U},\r
},\r
\r
- /* Resources owned/reserved by region 5 (Associated to any IPU1 core 1)*/\r
+ /* Resources owned/reserved by region 5 (Not Associated to any core supported)*/\r
{\r
/* ownPaRAMSets */\r
/* 31 0 63 32 95 64 127 96 */\r
- {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
/* 159 128 191 160 223 192 255 224 */\r
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
/* 287 256 319 288 351 320 383 352 */\r
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
/* 415 384 447 416 479 448 511 480 */\r
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
\r
/* ownDmaChannels */\r
/* 31 0 63 32 */\r
- {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+ {0x00000000U, 0x00000000U},\r
\r
/* ownQdmaChannels */\r
/* 31 0 */\r
- {0x000000FFu},\r
+ {0x00000000U},\r
\r
/* ownTccs */\r
/* 31 0 63 32 */\r
- {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+ {0x00000000U, 0x00000000U},\r
\r
/* resvdPaRAMSets */\r
/* 31 0 63 32 95 64 127 96 */\r
- {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
+ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
/* 159 128 191 160 223 192 255 224 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
/* 287 256 319 288 351 320 383 352 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
/* 415 384 447 416 479 448 511 480 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
\r
/* resvdDmaChannels */\r
/* 31 0 63 32 */\r
- {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA},\r
+ {0x00000000U, 0x00000000U},\r
\r
/* resvdQdmaChannels */\r
/* 31 0 */\r
- {0x00u},\r
+ {0x00000000U},\r
\r
/* resvdTccs */\r
/* 31 0 63 32 */\r
- {0x00u, 0x00u},\r
+ {0x00000000U, 0x00000000U},\r
},\r
\r
- /* Resources owned/reserved by region 6 (Associated to any IPU2 core 0)*/\r
+ /* Resources owned/reserved by region 6 (Not Associated to any core supported)*/\r
{\r
/* ownPaRAMSets */\r
/* 31 0 63 32 95 64 127 96 */\r
- {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
/* 159 128 191 160 223 192 255 224 */\r
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
/* 287 256 319 288 351 320 383 352 */\r
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
/* 415 384 447 416 479 448 511 480 */\r
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
\r
/* ownDmaChannels */\r
/* 31 0 63 32 */\r
- {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+ {0x00000000U, 0x00000000U},\r
\r
/* ownQdmaChannels */\r
/* 31 0 */\r
- {0x000000FFu},\r
+ {0x00000000U},\r
\r
/* ownTccs */\r
/* 31 0 63 32 */\r
- {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+ {0x00000000U, 0x00000000U},\r
\r
/* resvdPaRAMSets */\r
/* 31 0 63 32 95 64 127 96 */\r
- {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
+ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
/* 159 128 191 160 223 192 255 224 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
/* 287 256 319 288 351 320 383 352 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
/* 415 384 447 416 479 448 511 480 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
\r
/* resvdDmaChannels */\r
/* 31 0 63 32 */\r
- {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA},\r
+ {0x00000000U, 0x00000000U},\r
\r
/* resvdQdmaChannels */\r
/* 31 0 */\r
- {0x00u},\r
+ {0x00000000U},\r
\r
/* resvdTccs */\r
/* 31 0 63 32 */\r
- {0x00u, 0x00u},\r
+ {0x00000000U, 0x00000000U},\r
},\r
\r
- /* Resources owned/reserved by region 7 (Associated to any IPU2 core 1)*/\r
+ /* Resources owned/reserved by region 7 (Not Associated to any core supported)*/\r
{\r
/* ownPaRAMSets */\r
/* 31 0 63 32 95 64 127 96 */\r
- {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
/* 159 128 191 160 223 192 255 224 */\r
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
/* 287 256 319 288 351 320 383 352 */\r
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
/* 415 384 447 416 479 448 511 480 */\r
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
\r
/* ownDmaChannels */\r
/* 31 0 63 32 */\r
- {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+ {0x00000000U, 0x00000000U},\r
\r
/* ownQdmaChannels */\r
/* 31 0 */\r
- {0x000000FFu},\r
+ {0x00000000U},\r
\r
/* ownTccs */\r
/* 31 0 63 32 */\r
- {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+ {0x00000000U, 0x00000000U},\r
\r
/* resvdPaRAMSets */\r
/* 31 0 63 32 95 64 127 96 */\r
- {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
+ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
/* 159 128 191 160 223 192 255 224 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
/* 287 256 319 288 351 320 383 352 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
/* 415 384 447 416 479 448 511 480 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
\r
/* resvdDmaChannels */\r
/* 31 0 63 32 */\r
- {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA},\r
+ {0x00000000U, 0x00000000U},\r
\r
/* resvdQdmaChannels */\r
/* 31 0 */\r
- {0x00u},\r
+ {0x00000000U},\r
\r
/* resvdTccs */\r
/* 31 0 63 32 */\r
- {0x00u, 0x00u},\r
+ {0x00000000U, 0x00000000U},\r
},\r
},\r
- /* EDMA3 INSTANCE# 1 DSP1 EDMA*/\r
+ /* EDMA3 INSTANCE# 2 EVE EDMA*/\r
{\r
/* Resources owned/reserved by region 0 (Not Associated to any core supported)*/\r
{\r
/* ownPaRAMSets */\r
/* 31 0 63 32 95 64 127 96 */\r
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
/* 159 128 191 160 223 192 255 224 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
/* 287 256 319 288 351 320 383 352 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
/* 415 384 447 416 479 448 511 480 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
\r
/* ownDmaChannels */\r
/* 31 0 63 32 */\r
- {0x00000000u, 0x00000000u},\r
+ {0x00000000U, 0x00000000U},\r
\r
/* ownQdmaChannels */\r
/* 31 0 */\r
- {0x00000000u},\r
+ {0x00000000U},\r
\r
/* ownTccs */\r
/* 31 0 63 32 */\r
- {0x00000000u, 0x00000000u},\r
+ {0x00000000U, 0x00000000U},\r
\r
/* resvdPaRAMSets */\r
/* 31 0 63 32 95 64 127 96 */\r
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
/* 159 128 191 160 223 192 255 224 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
/* 287 256 319 288 351 320 383 352 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
/* 415 384 447 416 479 448 511 480 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
\r
/* resvdDmaChannels */\r
/* 31 0 63 32 */\r
- {0x00000000u, 0x00000000u},\r
+ {0x00000000U, 0x00000000U},\r
\r
/* resvdQdmaChannels */\r
/* 31 0 */\r
- {0x00000000u},\r
+ {0x00000000U},\r
\r
/* resvdTccs */\r
/* 31 0 63 32 */\r
- {0x00000000u, 0x00000000u},\r
+ {0x00000000U, 0x00000000U},\r
},\r
\r
- /* Resources owned/reserved by region 1 (Not Associated to any core supported) */\r
+ /* Resources owned/reserved by region 1 (Associated to any EVE core)*/\r
{\r
/* ownPaRAMSets */\r
/* 31 0 63 32 95 64 127 96 */\r
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+ {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
/* 159 128 191 160 223 192 255 224 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
/* 287 256 319 288 351 320 383 352 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
/* 415 384 447 416 479 448 511 480 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,},\r
\r
/* ownDmaChannels */\r
/* 31 0 63 32 */\r
- {0x00000000u, 0x00000000u},\r
+ {0xFFFFFFFFU, 0xFFFFFFFFU},\r
\r
/* ownQdmaChannels */\r
/* 31 0 */\r
- {0x00000000u},\r
+ {0x000000FFU},\r
\r
/* ownTccs */\r
/* 31 0 63 32 */\r
- {0x00000000u, 0x00000000u},\r
+ {0xFFFFFFFFU, 0xFFFFFFFFU},\r
\r
/* resvdPaRAMSets */\r
/* 31 0 63 32 95 64 127 96 */\r
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
/* 159 128 191 160 223 192 255 224 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
/* 287 256 319 288 351 320 383 352 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
/* 415 384 447 416 479 448 511 480 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
\r
/* resvdDmaChannels */\r
/* 31 0 63 32 */\r
- {0x00000000u, 0x00000000u},\r
+ {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_EVEEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_EVEEDMA},\r
\r
/* resvdQdmaChannels */\r
/* 31 0 */\r
- {0x00000000u},\r
+ {0x00U},\r
\r
/* resvdTccs */\r
/* 31 0 63 32 */\r
- {0x00000000u, 0x00000000u},\r
+ {0x00U, 0x00U},\r
},\r
\r
- /* Resources owned/reserved by region 2 (Associated to any DSP core 0)*/\r
+ /* Resources owned/reserved by region 2 (Not Associated to any core supported)*/\r
{\r
/* ownPaRAMSets */\r
/* 31 0 63 32 95 64 127 96 */\r
- {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
/* 159 128 191 160 223 192 255 224 */\r
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
/* 287 256 319 288 351 320 383 352 */\r
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
/* 415 384 447 416 479 448 511 480 */\r
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
\r
/* ownDmaChannels */\r
/* 31 0 63 32 */\r
- {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+ {0x00000000U, 0x00000000U},\r
\r
/* ownQdmaChannels */\r
/* 31 0 */\r
- {0x000000FFu},\r
+ {0x00000000U},\r
\r
/* ownTccs */\r
/* 31 0 63 32 */\r
- {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+ {0x00000000U, 0x00000000U},\r
\r
/* resvdPaRAMSets */\r
/* 31 0 63 32 95 64 127 96 */\r
- {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
+ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
/* 159 128 191 160 223 192 255 224 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
/* 287 256 319 288 351 320 383 352 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
/* 415 384 447 416 479 448 511 480 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
\r
/* resvdDmaChannels */\r
/* 31 0 63 32 */\r
- {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_DSPEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_DSPEDMA},\r
+ {0x00000000U, 0x00000000U},\r
\r
/* resvdQdmaChannels */\r
/* 31 0 */\r
- {0x00u},\r
+ {0x00000000U},\r
\r
/* resvdTccs */\r
/* 31 0 63 32 */\r
- {0x00u, 0x00u},\r
+ {0x00000000U, 0x00000000U},\r
},\r
\r
- /* Resources owned/reserved by region 3 (Associated to any DSP core 1)*/\r
+ /* Resources owned/reserved by region 3 (Not Associated to any core supported)*/\r
{\r
/* ownPaRAMSets */\r
/* 31 0 63 32 95 64 127 96 */\r
- {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
/* 159 128 191 160 223 192 255 224 */\r
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
/* 287 256 319 288 351 320 383 352 */\r
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
/* 415 384 447 416 479 448 511 480 */\r
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
\r
/* ownDmaChannels */\r
/* 31 0 63 32 */\r
- {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+ {0x00000000U, 0x00000000U},\r
\r
/* ownQdmaChannels */\r
/* 31 0 */\r
- {0x000000FFu},\r
+ {0x00000000U},\r
\r
/* ownTccs */\r
/* 31 0 63 32 */\r
- {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+ {0x00000000U, 0x00000000U},\r
\r
/* resvdPaRAMSets */\r
/* 31 0 63 32 95 64 127 96 */\r
- {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
+ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
/* 159 128 191 160 223 192 255 224 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
/* 287 256 319 288 351 320 383 352 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
/* 415 384 447 416 479 448 511 480 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
\r
/* resvdDmaChannels */\r
/* 31 0 63 32 */\r
- {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_DSPEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_DSPEDMA},\r
+ {0x00000000U, 0x00000000U},\r
\r
/* resvdQdmaChannels */\r
/* 31 0 */\r
- {0x00u},\r
+ {0x00000000U},\r
\r
/* resvdTccs */\r
/* 31 0 63 32 */\r
- {0x00u, 0x00u},\r
+ {0x00000000U, 0x00000000U},\r
},\r
\r
/* Resources owned/reserved by region 4 (Not Associated to any core supported)*/\r
{\r
/* ownPaRAMSets */\r
/* 31 0 63 32 95 64 127 96 */\r
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
/* 159 128 191 160 223 192 255 224 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
/* 287 256 319 288 351 320 383 352 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
/* 415 384 447 416 479 448 511 480 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
\r
/* ownDmaChannels */\r
/* 31 0 63 32 */\r
- {0x00000000u, 0x00000000u},\r
+ {0x00000000U, 0x00000000U},\r
\r
/* ownQdmaChannels */\r
/* 31 0 */\r
- {0x00000000u},\r
+ {0x00000000U},\r
\r
/* ownTccs */\r
/* 31 0 63 32 */\r
- {0x00000000u, 0x00000000u},\r
+ {0x00000000U, 0x00000000U},\r
\r
/* resvdPaRAMSets */\r
/* 31 0 63 32 95 64 127 96 */\r
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
/* 159 128 191 160 223 192 255 224 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
/* 287 256 319 288 351 320 383 352 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
/* 415 384 447 416 479 448 511 480 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
\r
/* resvdDmaChannels */\r
/* 31 0 63 32 */\r
- {0x00000000u, 0x00000000u},\r
+ {0x00000000U, 0x00000000U},\r
\r
/* resvdQdmaChannels */\r
/* 31 0 */\r
- {0x00000000u},\r
+ {0x00000000U},\r
\r
/* resvdTccs */\r
/* 31 0 63 32 */\r
- {0x00000000u, 0x00000000u},\r
+ {0x00000000U, 0x00000000U},\r
},\r
\r
/* Resources owned/reserved by region 5 (Not Associated to any core supported)*/\r
{\r
/* ownPaRAMSets */\r
/* 31 0 63 32 95 64 127 96 */\r
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
/* 159 128 191 160 223 192 255 224 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
/* 287 256 319 288 351 320 383 352 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
/* 415 384 447 416 479 448 511 480 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
\r
/* ownDmaChannels */\r
/* 31 0 63 32 */\r
- {0x00000000u, 0x00000000u},\r
+ {0x00000000U, 0x00000000U},\r
\r
/* ownQdmaChannels */\r
/* 31 0 */\r
- {0x00000000u},\r
+ {0x00000000U},\r
\r
/* ownTccs */\r
/* 31 0 63 32 */\r
- {0x00000000u, 0x00000000u},\r
+ {0x00000000U, 0x00000000U},\r
\r
/* resvdPaRAMSets */\r
/* 31 0 63 32 95 64 127 96 */\r
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
/* 159 128 191 160 223 192 255 224 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
/* 287 256 319 288 351 320 383 352 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
/* 415 384 447 416 479 448 511 480 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
\r
/* resvdDmaChannels */\r
/* 31 0 63 32 */\r
- {0x00000000u, 0x00000000u},\r
+ {0x00000000U, 0x00000000U},\r
\r
/* resvdQdmaChannels */\r
/* 31 0 */\r
- {0x00000000u},\r
+ {0x00000000U},\r
\r
/* resvdTccs */\r
/* 31 0 63 32 */\r
- {0x00000000u, 0x00000000u},\r
+ {0x00000000U, 0x00000000U},\r
},\r
\r
/* Resources owned/reserved by region 6 (Not Associated to any core supported)*/\r
{\r
/* ownPaRAMSets */\r
/* 31 0 63 32 95 64 127 96 */\r
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
/* 159 128 191 160 223 192 255 224 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
/* 287 256 319 288 351 320 383 352 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
/* 415 384 447 416 479 448 511 480 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
\r
/* ownDmaChannels */\r
/* 31 0 63 32 */\r
- {0x00000000u, 0x00000000u},\r
+ {0x00000000U, 0x00000000U},\r
\r
/* ownQdmaChannels */\r
/* 31 0 */\r
- {0x00000000u},\r
+ {0x00000000U},\r
\r
/* ownTccs */\r
/* 31 0 63 32 */\r
- {0x00000000u, 0x00000000u},\r
+ {0x00000000U, 0x00000000U},\r
\r
/* resvdPaRAMSets */\r
/* 31 0 63 32 95 64 127 96 */\r
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
/* 159 128 191 160 223 192 255 224 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
/* 287 256 319 288 351 320 383 352 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
/* 415 384 447 416 479 448 511 480 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
\r
/* resvdDmaChannels */\r
/* 31 0 63 32 */\r
- {0x00000000u, 0x00000000u},\r
+ {0x00000000U, 0x00000000U},\r
\r
/* resvdQdmaChannels */\r
/* 31 0 */\r
- {0x00000000u},\r
+ {0x00000000U},\r
\r
/* resvdTccs */\r
/* 31 0 63 32 */\r
- {0x00000000u, 0x00000000u},\r
+ {0x00000000U, 0x00000000U},\r
},\r
\r
/* Resources owned/reserved by region 7 (Not Associated to any core supported)*/\r
{\r
/* ownPaRAMSets */\r
/* 31 0 63 32 95 64 127 96 */\r
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
/* 159 128 191 160 223 192 255 224 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
/* 287 256 319 288 351 320 383 352 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
/* 415 384 447 416 479 448 511 480 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
\r
/* ownDmaChannels */\r
/* 31 0 63 32 */\r
- {0x00000000u, 0x00000000u},\r
+ {0x00000000U, 0x00000000U},\r
\r
/* ownQdmaChannels */\r
/* 31 0 */\r
- {0x00000000u},\r
+ {0x00000000U},\r
\r
/* ownTccs */\r
/* 31 0 63 32 */\r
- {0x00000000u, 0x00000000u},\r
+ {0x00000000U, 0x00000000U},\r
\r
/* resvdPaRAMSets */\r
/* 31 0 63 32 95 64 127 96 */\r
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
/* 159 128 191 160 223 192 255 224 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
/* 287 256 319 288 351 320 383 352 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
/* 415 384 447 416 479 448 511 480 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
\r
/* resvdDmaChannels */\r
/* 31 0 63 32 */\r
- {0x00000000u, 0x00000000u},\r
+ {0x00000000U, 0x00000000U},\r
\r
/* resvdQdmaChannels */\r
/* 31 0 */\r
- {0x00000000u},\r
+ {0x00000000U},\r
\r
/* resvdTccs */\r
/* 31 0 63 32 */\r
- {0x00000000u, 0x00000000u},\r
+ {0x00000000U, 0x00000000U},\r
},\r
},\r
- };\r
+};\r
\r
/* Driver Instance Cross bar event to channel map Initialization Configuration */\r
EDMA3_DRV_GblXbarToChanConfigParams sampleXbarChanInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
{\r
/* EDMA3 INSTANCE# 0 */\r
+ {\r
+ /* Event to channel map for region 0 */\r
+ {\r
+ {-1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1}\r
+ },\r
+ /* Event to channel map for region 1 */\r
+ {\r
+ {-1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1}\r
+ },\r
+ /* Event to channel map for region 2 */\r
+ {\r
+ {-1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1}\r
+ },\r
+ /* Event to channel map for region 3 */\r
+ {\r
+ {-1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1}\r
+ },\r
+ /* Event to channel map for region 4 */\r
+ {\r
+ {-1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1}\r
+ },\r
+ /* Event to channel map for region 5 */\r
+ {\r
+ {-1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1}\r
+ },\r
+ /* Event to channel map for region 6 */\r
+ {\r
+ {-1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1}\r
+ },\r
+ /* Event to channel map for region 7 */\r
+ {\r
+ {-1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1}\r
+ },\r
+ },\r
+ \r
+ /* EDMA3 INSTANCE# 1 */\r
+ {\r
+ /* Event to channel map for region 0 */\r
+ {\r
+ {-1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1}\r
+ },\r
+ /* Event to channel map for region 1 */\r
+ {\r
+ {-1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1}\r
+ },\r
+ /* Event to channel map for region 2 */\r
+ {\r
+ {-1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1}\r
+ },\r
+ /* Event to channel map for region 3 */\r
+ {\r
+ {-1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1}\r
+ },\r
+ /* Event to channel map for region 4 */\r
+ {\r
+ {-1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1}\r
+ },\r
+ /* Event to channel map for region 5 */\r
+ {\r
+ {-1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1}\r
+ },\r
+ /* Event to channel map for region 6 */\r
+ {\r
+ {-1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1}\r
+ },\r
+ /* Event to channel map for region 7 */\r
+ {\r
+ {-1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1}\r
+ },\r
+ },\r
+ \r
+ /* EDMA3 INSTANCE# 2 */\r
{\r
/* Event to channel map for region 0 */\r
{\r