[keystone-rtos/edma3_lld.git] / packages / ti / sdo / edma3 / drv / sample / src / platforms / sample_ti814x_cfg.c
diff --git a/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_ti814x_cfg.c b/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_ti814x_cfg.c
index 49a4471012ee7bc667e4b0085346cf12f41511f4..f88f5562812b463777c91c2950bbccb7f273bcc0 100755 (executable)
#define NUM_DSPS 1U
const uint32_t numDsps = NUM_DSPS;
+int8_t* getGlobalAddr(int8_t* addr);
+
+uint16_t isGblConfigRequired(uint32_t dspNum);
+
+/* Determine the processor id by reading DNUM register. */
+uint16_t determineProcId(void);
+
/* Determine the processor id by reading DNUM register. */
-uint16_t determineProcId()
+uint16_t determineProcId(void)
{
#ifdef BUILD_CENTAURUS_A8
- return 0;
+ return 0U;
#elif defined BUILD_CENTAURUS_DSP
- return 1;
+ return 1U;
#elif defined BUILD_CENTAURUS_M3VPSS
- return 5;
+ return 5U;
#elif defined BUILD_CENTAURUS_M3VIDEO
- return 4;
+ return 4U;
#else
- return 1;
+ return 1U;
#endif
}
{
(void) dspNum;
#ifdef BUILD_CENTAURUS_DSP
- return 1;
+ return 1U;
#else
- return 0;
+ return 0U;
#endif
}
#define EDMA3_CC_XFER_COMPLETION_INT_M3VIDEO (62U)
#ifdef BUILD_CENTAURUS_A8
-#define EDMA3_CC_XFER_COMPLETION_INT EDMA3_CC_XFER_COMPLETION_INT_A8
+#define EDMA3_CC_XFER_COMPLETION_INT (EDMA3_CC_XFER_COMPLETION_INT_A8)
#elif defined BUILD_CENTAURUS_DSP
-#define EDMA3_CC_XFER_COMPLETION_INT EDMA3_CC_XFER_COMPLETION_INT_DSP
+#define EDMA3_CC_XFER_COMPLETION_INT (EDMA3_CC_XFER_COMPLETION_INT_DSP)
#elif defined BUILD_CENTAURUS_M3VIDEO
-#define EDMA3_CC_XFER_COMPLETION_INT EDMA3_CC_XFER_COMPLETION_INT_M3VIDEO
+#define EDMA3_CC_XFER_COMPLETION_INT (EDMA3_CC_XFER_COMPLETION_INT_M3VIDEO)
#elif defined BUILD_CENTAURUS_M3VPSS
-#define EDMA3_CC_XFER_COMPLETION_INT EDMA3_CC_XFER_COMPLETION_INT_M3VPSS
+#define EDMA3_CC_XFER_COMPLETION_INT (EDMA3_CC_XFER_COMPLETION_INT_M3VPSS)
#else
#define EDMA3_CC_XFER_COMPLETION_INT {0U}
#endif
#define EDMA3_CC_ERROR_INT_DSP (21U)
#ifdef BUILD_CENTAURUS_A8
-#define EDMA3_CC_ERROR_INT EDMA3_CC_ERROR_INT_A8
+#define EDMA3_CC_ERROR_INT (EDMA3_CC_ERROR_INT_A8)
#elif defined BUILD_CENTAURUS_DSP
-#define EDMA3_CC_ERROR_INT EDMA3_CC_ERROR_INT_DSP
+#define EDMA3_CC_ERROR_INT (EDMA3_CC_ERROR_INT_DSP)
#else
#define EDMA3_CC_ERROR_INT (0U)
#endif
#define EDMA3_TC3_ERROR_INT_A8 (115U)
#ifdef BUILD_CENTAURUS_A8
-#define EDMA3_TC0_ERROR_INT EDMA3_TC0_ERROR_INT_A8
-#define EDMA3_TC1_ERROR_INT EDMA3_TC1_ERROR_INT_A8
-#define EDMA3_TC2_ERROR_INT EDMA3_TC2_ERROR_INT_A8
-#define EDMA3_TC3_ERROR_INT EDMA3_TC3_ERROR_INT_A8
+#define EDMA3_TC0_ERROR_INT (EDMA3_TC0_ERROR_INT_A8)
+#define EDMA3_TC1_ERROR_INT (EDMA3_TC1_ERROR_INT_A8)
+#define EDMA3_TC2_ERROR_INT (EDMA3_TC2_ERROR_INT_A8)
+#define EDMA3_TC3_ERROR_INT (EDMA3_TC3_ERROR_INT_A8)
#elif defined BUILD_CENTAURUS_DSP
-#define EDMA3_TC0_ERROR_INT EDMA3_TC0_ERROR_INT_DSP
-#define EDMA3_TC1_ERROR_INT EDMA3_TC1_ERROR_INT_DSP
-#define EDMA3_TC2_ERROR_INT EDMA3_TC2_ERROR_INT_DSP
-#define EDMA3_TC3_ERROR_INT EDMA3_TC3_ERROR_INT_DSP
+#define EDMA3_TC0_ERROR_INT (EDMA3_TC0_ERROR_INT_DSP)
+#define EDMA3_TC1_ERROR_INT (EDMA3_TC1_ERROR_INT_DSP)
+#define EDMA3_TC2_ERROR_INT (EDMA3_TC2_ERROR_INT_DSP)
+#define EDMA3_TC3_ERROR_INT (EDMA3_TC3_ERROR_INT_DSP)
#else
#define EDMA3_TC0_ERROR_INT (0U)
#define EDMA3_TC1_ERROR_INT (0U)
EDMA3_HWI_INT_TC0_ERR,
EDMA3_HWI_INT_TC1_ERR,
EDMA3_HWI_INT_TC2_ERR,
- EDMA3_HWI_INT_TC3_ERR
+ EDMA3_HWI_INT_TC3_ERR,
+ 0,
+ 0,
+ 0,
+ 0
}
};