[keystone-rtos/edma3_lld.git] / packages / ti / sdo / edma3 / drv / sample / src / platforms / sample_ti814x_cfg.c
diff --git a/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_ti814x_cfg.c b/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_ti814x_cfg.c
index d731b4af43c094583ee75ddc7cb697ae4a9ac984..07aa75b5af751ff5a5fa061ff2e975fe94ffd223 100755 (executable)
/* Determine the processor id by reading DNUM register. */
unsigned short determineProcId()
{
/* Determine the processor id by reading DNUM register. */
unsigned short determineProcId()
{
- return 1;
+#ifdef BUILD_CENTAURUS_A8
+ return 0;
+#elif defined BUILD_CENTAURUS_DSP
+ return 1;
+#elif defined BUILD_CENTAURUS_M3VPSS
+ return 5;
+#elif defined BUILD_CENTAURUS_M3VIDEO
+ return 4;
+#else
+ return 1;
+#endif
}
signed char* getGlobalAddr(signed char* addr)
}
signed char* getGlobalAddr(signed char* addr)
unsigned short isGblConfigRequired(unsigned int dspNum)
{
(void) dspNum;
unsigned short isGblConfigRequired(unsigned int dspNum)
{
(void) dspNum;
-
- return 1;
+#ifdef BUILD_CENTAURUS_DSP
+ return 1;
+#else
+ return 0;
+#endif
}
/* Semaphore handles */
}
/* Semaphore handles */
#define EDMA3_NUM_QDMA_CHANNELS (8u)
/** Number of Event Queues available */
#define EDMA3_NUM_QDMA_CHANNELS (8u)
/** Number of Event Queues available */
-#define EDMA3_0_NUM_EVTQUE (4u)
+#define EDMA3_NUM_EVTQUE (4u)
/** Number of Transfer Controllers available */
/** Number of Transfer Controllers available */
-#define EDMA3_0_NUM_TC (4u)
+#define EDMA3_NUM_TC (4u)
/** Number of Regions */
/** Number of Regions */
-#define EDMA3_0_NUM_REGIONS (2u)
-
-
-/** Interrupt no. for Transfer Completion */
-#define EDMA3_0_CC_XFER_COMPLETION_INT (20u)
-/** Interrupt no. for CC Error */
-#define EDMA3_0_CC_ERROR_INT (21u)
-/** Interrupt no. for TCs Error */
-#define EDMA3_0_TC0_ERROR_INT (22u)
-#define EDMA3_0_TC1_ERROR_INT (27u)
-#define EDMA3_0_TC2_ERROR_INT (28u)
-#define EDMA3_0_TC3_ERROR_INT (29u)
-#define EDMA3_0_TC4_ERROR_INT (0u)
-#define EDMA3_0_TC5_ERROR_INT (0u)
-#define EDMA3_0_TC6_ERROR_INT (0u)
-#define EDMA3_0_TC7_ERROR_INT (0u)
+#define EDMA3_NUM_REGIONS (6u)
+
+
+/** Interrupt no. for Transfer Completion */
+#define EDMA3_CC_XFER_COMPLETION_INT_A8 (12u)
+#define EDMA3_CC_XFER_COMPLETION_INT_DSP (20u)
+#define EDMA3_CC_XFER_COMPLETION_INT_M3VPSS (63u)
+#define EDMA3_CC_XFER_COMPLETION_INT_M3VIDEO (62u)
+
+#ifdef BUILD_CENTAURUS_A8
+#define EDMA3_CC_XFER_COMPLETION_INT EDMA3_CC_XFER_COMPLETION_INT_A8
+#elif defined BUILD_CENTAURUS_DSP
+#define EDMA3_CC_XFER_COMPLETION_INT EDMA3_CC_XFER_COMPLETION_INT_DSP
+#elif defined BUILD_CENTAURUS_M3VIDEO
+#define EDMA3_CC_XFER_COMPLETION_INT EDMA3_CC_XFER_COMPLETION_INT_M3VIDEO
+#elif defined BUILD_CENTAURUS_M3VPSS
+#define EDMA3_CC_XFER_COMPLETION_INT EDMA3_CC_XFER_COMPLETION_INT_M3VPSS
+#else
+#define EDMA3_CC_XFER_COMPLETION_INT {0u}
+#endif
+
+/** Interrupt no. for CC Error */
+#define EDMA3_CC_ERROR_INT_A8 (14u)
+#define EDMA3_CC_ERROR_INT_DSP (21u)
+
+#ifdef BUILD_CENTAURUS_A8
+#define EDMA3_CC_ERROR_INT EDMA3_CC_ERROR_INT_A8
+#elif defined BUILD_CENTAURUS_DSP
+#define EDMA3_CC_ERROR_INT EDMA3_CC_ERROR_INT_DSP
+#else
+#define EDMA3_CC_ERROR_INT (0u)
+#endif
+
+/** Interrupt no. for TCs Error */
+#define EDMA3_TC0_ERROR_INT_DSP (22u)
+#define EDMA3_TC1_ERROR_INT_DSP (27u)
+#define EDMA3_TC2_ERROR_INT_DSP (28u)
+#define EDMA3_TC3_ERROR_INT_DSP (29u)
+#define EDMA3_TC0_ERROR_INT_A8 (112u)
+#define EDMA3_TC1_ERROR_INT_A8 (113u)
+#define EDMA3_TC2_ERROR_INT_A8 (114u)
+#define EDMA3_TC3_ERROR_INT_A8 (115u)
+
+#ifdef BUILD_CENTAURUS_A8
+#define EDMA3_TC0_ERROR_INT EDMA3_TC0_ERROR_INT_A8
+#define EDMA3_TC1_ERROR_INT EDMA3_TC1_ERROR_INT_A8
+#define EDMA3_TC2_ERROR_INT EDMA3_TC2_ERROR_INT_A8
+#define EDMA3_TC3_ERROR_INT EDMA3_TC3_ERROR_INT_A8
+#elif defined BUILD_CENTAURUS_DSP
+#define EDMA3_TC0_ERROR_INT EDMA3_TC0_ERROR_INT_DSP
+#define EDMA3_TC1_ERROR_INT EDMA3_TC1_ERROR_INT_DSP
+#define EDMA3_TC2_ERROR_INT EDMA3_TC2_ERROR_INT_DSP
+#define EDMA3_TC3_ERROR_INT EDMA3_TC3_ERROR_INT_DSP
+#else
+#define EDMA3_TC0_ERROR_INT (0u)
+#define EDMA3_TC1_ERROR_INT (0u)
+#define EDMA3_TC2_ERROR_INT (0u)
+#define EDMA3_TC3_ERROR_INT (0u)
+#endif
+
+#define EDMA3_TC4_ERROR_INT (0u)
+#define EDMA3_TC5_ERROR_INT (0u)
+#define EDMA3_TC6_ERROR_INT (0u)
+#define EDMA3_TC7_ERROR_INT (0u)
/**
* EDMA3 interrupts (transfer completion, CC error etc.) correspond to different
/**
* EDMA3 interrupts (transfer completion, CC error etc.) correspond to different
*/
/* EDMA 0 */
*/
/* EDMA 0 */
-#define EDMA3_0_HWI_INT_XFER_COMP (7u)
-#define EDMA3_0_HWI_INT_CC_ERR (7u)
-#define EDMA3_0_HWI_INT_TC0_ERR (7u)
-#define EDMA3_0_HWI_INT_TC1_ERR (7u)
-#define EDMA3_0_HWI_INT_TC2_ERR (7u)
-#define EDMA3_0_HWI_INT_TC3_ERR (7u)
+#define EDMA3_HWI_INT_XFER_COMP (7u)
+#define EDMA3_HWI_INT_CC_ERR (7u)
+#define EDMA3_HWI_INT_TC0_ERR (10u)
+#define EDMA3_HWI_INT_TC1_ERR (10u)
+#define EDMA3_HWI_INT_TC2_ERR (10u)
+#define EDMA3_HWI_INT_TC3_ERR (10u)
/**
/**
* To allocate more DMA channels or TCCs, one has to modify the event mapping.
*/
/* 31 0 */
* To allocate more DMA channels or TCCs, one has to modify the event mapping.
*/
/* 31 0 */
-#define EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0 (0xFCFF3F00u) /* TBD */
+#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0 (0xFCFF3F00u) /* TBD */
/**
/**
* To allocate more DMA channels or TCCs, one has to modify the event mapping.
*/
/* DMA channels 32-63 DOES NOT exist in omapl138. */
* To allocate more DMA channels or TCCs, one has to modify the event mapping.
*/
/* DMA channels 32-63 DOES NOT exist in omapl138. */
-#define EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1 (0xFF033C00u) /* TBD */
+#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1 (0xFF003C00u) /* TBD */
/* Variable which will be used internally for referring number of Event Queues*/
unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] = {
/* Variable which will be used internally for referring number of Event Queues*/
unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] = {
- EDMA3_0_NUM_EVTQUE,
+ EDMA3_NUM_EVTQUE,
};
/* Variable which will be used internally for referring number of TCs. */
unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] = {
};
/* Variable which will be used internally for referring number of TCs. */
unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] = {
- EDMA3_0_NUM_TC,
+ EDMA3_NUM_TC,
};
/**
};
/**
unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
{
{
unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
{
{
- 0u, EDMA3_0_CC_XFER_COMPLETION_INT, 0u, 0u, 0u, 0u, 0u, 0u,
+ EDMA3_CC_XFER_COMPLETION_INT_A8, EDMA3_CC_XFER_COMPLETION_INT_DSP, 0u, 0u,
+ EDMA3_CC_XFER_COMPLETION_INT_M3VIDEO, EDMA3_CC_XFER_COMPLETION_INT_M3VPSS, 0u, 0u,
},
};
},
};
* error interrupt.
*/
unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {
* error interrupt.
*/
unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {
- EDMA3_0_CC_ERROR_INT,
+ EDMA3_CC_ERROR_INT,
};
/**
};
/**
unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][8] =
{
{
unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][8] =
{
{
- EDMA3_0_TC0_ERROR_INT, EDMA3_0_TC1_ERROR_INT,
- EDMA3_0_TC2_ERROR_INT, EDMA3_0_TC3_ERROR_INT,
- EDMA3_0_TC4_ERROR_INT, EDMA3_0_TC5_ERROR_INT,
- EDMA3_0_TC6_ERROR_INT, EDMA3_0_TC7_ERROR_INT,
+ EDMA3_TC0_ERROR_INT, EDMA3_TC1_ERROR_INT,
+ EDMA3_TC2_ERROR_INT, EDMA3_TC3_ERROR_INT,
+ EDMA3_TC4_ERROR_INT, EDMA3_TC5_ERROR_INT,
+ EDMA3_TC6_ERROR_INT, EDMA3_TC7_ERROR_INT,
}
};
}
};
* for various EDMA3 interrupts.
*/
unsigned int hwIntXferComp[NUM_EDMA3_INSTANCES] = {
* for various EDMA3 interrupts.
*/
unsigned int hwIntXferComp[NUM_EDMA3_INSTANCES] = {
- EDMA3_0_HWI_INT_XFER_COMP
+ EDMA3_HWI_INT_XFER_COMP
};
unsigned int hwIntCcErr[NUM_EDMA3_INSTANCES] = {
};
unsigned int hwIntCcErr[NUM_EDMA3_INSTANCES] = {
- EDMA3_0_HWI_INT_CC_ERR
+ EDMA3_HWI_INT_CC_ERR
};
unsigned int hwIntTcErr[NUM_EDMA3_INSTANCES][8] = {
{
};
unsigned int hwIntTcErr[NUM_EDMA3_INSTANCES][8] = {
{
- EDMA3_0_HWI_INT_TC0_ERR,
- EDMA3_0_HWI_INT_TC1_ERR,
- EDMA3_0_HWI_INT_TC2_ERR,
- EDMA3_0_HWI_INT_TC3_ERR
+ EDMA3_HWI_INT_TC0_ERR,
+ EDMA3_HWI_INT_TC1_ERR,
+ EDMA3_HWI_INT_TC2_ERR,
+ EDMA3_HWI_INT_TC3_ERR
}
};
}
};
+/**
+ * \brief Base address as seen from the different cores may be different
+ * And is defined based on the core
+ */
+#ifdef BUILD_CENTAURUS_DSP
+#define EDMA3_CC_BASE_ADDR ((void *)(0x09000000))
+#define EDMA3_TC0_BASE_ADDR ((void *)(0x09800000))
+#define EDMA3_TC1_BASE_ADDR ((void *)(0x09900000))
+#define EDMA3_TC2_BASE_ADDR ((void *)(0x09A00000))
+#define EDMA3_TC3_BASE_ADDR ((void *)(0x09B00000))
+#else
+#define EDMA3_CC_BASE_ADDR ((void *)(0x49000000))
+#define EDMA3_TC0_BASE_ADDR ((void *)(0x49800000))
+#define EDMA3_TC1_BASE_ADDR ((void *)(0x49900000))
+#define EDMA3_TC2_BASE_ADDR ((void *)(0x49A00000))
+#define EDMA3_TC3_BASE_ADDR ((void *)(0x49B00000))
+#endif
+
/* Driver Object Initialization Configuration */
EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
{
/* Driver Object Initialization Configuration */
EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
{
/** Total number of PaRAM Sets supported by the EDMA3 Controller */
EDMA3_NUM_PARAMSET,
/** Total number of Event Queues in the EDMA3 Controller */
/** Total number of PaRAM Sets supported by the EDMA3 Controller */
EDMA3_NUM_PARAMSET,
/** Total number of Event Queues in the EDMA3 Controller */
- EDMA3_0_NUM_EVTQUE,
+ EDMA3_NUM_EVTQUE,
/** Total number of Transfer Controllers (TCs) in the EDMA3 Controller*/
/** Total number of Transfer Controllers (TCs) in the EDMA3 Controller*/
- EDMA3_0_NUM_TC,
+ EDMA3_NUM_TC,
/** Number of Regions on this EDMA3 controller */
/** Number of Regions on this EDMA3 controller */
- EDMA3_0_NUM_REGIONS,
+ EDMA3_NUM_REGIONS,
/**
* \brief Channel mapping existence
/**
* \brief Channel mapping existence
0u,
/** Global Register Region of CC Registers */
0u,
/** Global Register Region of CC Registers */
- (void *)0x09000000u,
+ EDMA3_CC_BASE_ADDR,
/** Transfer Controller (TC) Registers */
{
/** Transfer Controller (TC) Registers */
{
- (void *)0x09800000u,
- (void *)0x09900000u,
- (void *)0x09A00000u,
- (void *)0x09B00000u,
+ EDMA3_TC0_BASE_ADDR,
+ EDMA3_TC1_BASE_ADDR,
+ EDMA3_TC2_BASE_ADDR,
+ EDMA3_TC3_BASE_ADDR,
(void *)NULL,
(void *)NULL,
(void *)NULL,
(void *)NULL
},
/** Interrupt no. for Transfer Completion */
(void *)NULL,
(void *)NULL,
(void *)NULL,
(void *)NULL
},
/** Interrupt no. for Transfer Completion */
- EDMA3_0_CC_XFER_COMPLETION_INT,
+ EDMA3_CC_XFER_COMPLETION_INT,
/** Interrupt no. for CC Error */
/** Interrupt no. for CC Error */
- EDMA3_0_CC_ERROR_INT,
+ EDMA3_CC_ERROR_INT,
/** Interrupt no. for TCs Error */
{
/** Interrupt no. for TCs Error */
{
- EDMA3_0_TC0_ERROR_INT,
- EDMA3_0_TC1_ERROR_INT,
- EDMA3_0_TC2_ERROR_INT,
- EDMA3_0_TC3_ERROR_INT,
- EDMA3_0_TC4_ERROR_INT,
- EDMA3_0_TC5_ERROR_INT,
- EDMA3_0_TC6_ERROR_INT,
- EDMA3_0_TC7_ERROR_INT
+ EDMA3_TC0_ERROR_INT,
+ EDMA3_TC1_ERROR_INT,
+ EDMA3_TC2_ERROR_INT,
+ EDMA3_TC3_ERROR_INT,
+ EDMA3_TC4_ERROR_INT,
+ EDMA3_TC5_ERROR_INT,
+ EDMA3_TC6_ERROR_INT,
+ EDMA3_TC7_ERROR_INT
},
/**
},
/**
{
16u,
16u,
{
16u,
16u,
- 0u,
- 0u,
+ 16u,
+ 16u,
0u,
0u,
0u,
0u,
0u,
0u,
* All channels need not be mapped, some can be free also.
*/
{
* All channels need not be mapped, some can be free also.
*/
{
- EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0,
- EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1
+ EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0,
+ EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1
}
},
};
}
},
};
+/**
+ * \brief Resource splitting defines for Own/Reserved DMA/QDMA channels and TCCs
+ * For PaRAMs explicit defines are not present but should be replaced in the structure sampleInstInitConfig
+ * Default configuration has all resources owned by all cores and none reserved except for first 64 PaRAMs corrosponding to DMA channels
+ * Resources to be Split properly by application and rebuild the sample library to avoid resource conflict
+ *
+ * Only Resources owned by a perticular core are allocated by Driver
+ * Reserved resources are not allocated if requested for any available resource
+ */
+
+/* Defines for Own DMA channels For different cores */
+/* channels 0 to 31 */
+#define EDMA3_OWN_DMA_CHANNELS_0_A8 (0xFFFFFFFFu)
+#define EDMA3_OWN_DMA_CHANNELS_0_DSP (0xFFFFFFFFu)
+#define EDMA3_OWN_DMA_CHANNELS_0_M3VIDEO (0xFFFFFFFFu)
+#define EDMA3_OWN_DMA_CHANNELS_0_M3VPSS (0xFFFFFFFFu)
+/* Channels 32 to 63 */
+#define EDMA3_OWN_DMA_CHANNELS_1_A8 (0xFFFFFFFFu)
+#define EDMA3_OWN_DMA_CHANNELS_1_DSP (0xFFFFFFFFu)
+#define EDMA3_OWN_DMA_CHANNELS_1_M3VIDEO (0xFFFFFFFFu)
+#define EDMA3_OWN_DMA_CHANNELS_1_M3VPSS (0xFFFFFFFFu)
+
+/* Defines for Own QDMA channels For different cores */
+#define EDMA3_OWN_QDMA_CHANNELS_0_A8 (0x000000FFu)
+#define EDMA3_OWN_QDMA_CHANNELS_0_DSP (0x000000FFu)
+#define EDMA3_OWN_QDMA_CHANNELS_0_M3VIDEO (0x000000FFu)
+#define EDMA3_OWN_QDMA_CHANNELS_0_M3VPSS (0x000000FFu)
+
+/* Defines for Own TCCs For different cores */
+#define EDMA3_OWN_TCC_0_A8 (0xFFFFFFFFu)
+#define EDMA3_OWN_TCC_0_DSP (0xFFFFFFFFu)
+#define EDMA3_OWN_TCC_0_M3VIDEO (0xFFFFFFFFu)
+#define EDMA3_OWN_TCC_0_M3VPSS (0xFFFFFFFFu)
+/* Channels 32 to 63 */
+#define EDMA3_OWN_TCC_1_A8 (0xFFFFFFFFu)
+#define EDMA3_OWN_TCC_1_DSP (0xFFFFFFFFu)
+#define EDMA3_OWN_TCC_1_M3VIDEO (0xFFFFFFFFu)
+#define EDMA3_OWN_TCC_1_M3VPSS (0xFFFFFFFFu)
+
+/* Defines for Reserved DMA channels For different cores */
+/* channels 0 to 31 */
+#define EDMA3_RESERVED_DMA_CHANNELS_0_A8 (EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0)
+#define EDMA3_RESERVED_DMA_CHANNELS_0_DSP (EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0)
+#define EDMA3_RESERVED_DMA_CHANNELS_0_M3VIDEO (0x00u)
+#define EDMA3_RESERVED_DMA_CHANNELS_0_M3VPSS (0x00u)
+/* Channels 32 to 63 */
+#define EDMA3_RESERVED_DMA_CHANNELS_1_A8 (EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1)
+#define EDMA3_RESERVED_DMA_CHANNELS_1_DSP (EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1)
+#define EDMA3_RESERVED_DMA_CHANNELS_1_M3VIDEO (0x00u)
+#define EDMA3_RESERVED_DMA_CHANNELS_1_M3VPSS (0x00u)
+
+/* Defines for RESERVED QDMA channels For different cores */
+#define EDMA3_RESERVED_QDMA_CHANNELS_0_A8 (0x00u)
+#define EDMA3_RESERVED_QDMA_CHANNELS_0_DSP (0x00u)
+#define EDMA3_RESERVED_QDMA_CHANNELS_0_M3VIDEO (0x00u)
+#define EDMA3_RESERVED_QDMA_CHANNELS_0_M3VPSS (0x00u)
+
+/* Defines for RESERVED TCCs For different cores */
+#define EDMA3_RESERVED_TCC_0_A8 (EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0)
+#define EDMA3_RESERVED_TCC_0_DSP (EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0)
+#define EDMA3_RESERVED_TCC_0_M3VIDEO (0x00u)
+#define EDMA3_RESERVED_TCC_0_M3VPSS (0x00u)
+/* Channels 32 to 63 */
+#define EDMA3_RESERVED_TCC_1_A8 (EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1)
+#define EDMA3_RESERVED_TCC_1_DSP (EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1)
+#define EDMA3_RESERVED_TCC_1_M3VIDEO (0x00u)
+#define EDMA3_RESERVED_TCC_1_M3VPSS (0x00u)
/* Driver Instance Initialization Configuration */
EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
/* Driver Instance Initialization Configuration */
EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
-{
- /* EDMA3 INSTANCE# 0 */
{
{
- /* Resources owned/reserved by region 0 */
- {
- /* ownPaRAMSets */
- /* 31 0 63 32 95 64 127 96 */
- {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
- /* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
- /* ownDmaChannels */
- /* 31 0 63 32 */
- {0xFFFFFFFFu, 0x00000000u},
-
- /* ownQdmaChannels */
- /* 31 0 */
- {0x000000FFu},
-
- /* ownTccs */
- /* 31 0 63 32 */
- {0xFFFFFFFFu, 0x00000000u},
-
- /* Resources reserved by Region 1 */
- /* resvdPaRAMSets */
- /* 31 0 63 32 95 64 127 96 */
- {0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
- /* resvdDmaChannels */
- /* 31 0 */
- {0xFF3FF3FFu,
- /* 63..32 */
- 0x00000000u},
-
- /* resvdQdmaChannels */
- /* 31 0 */
- {0x00000000u},
-
- /* resvdTccs */
- /* 31 0 */
- {EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0,
- /* 63..32 */
- EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1},
- },
- /* Resources owned/reserved by region 1 */
- {
- /* ownPaRAMSets */
- /* 31 0 63 32 95 64 127 96 */
- {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
- /* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
- /* ownDmaChannels */
- /* 31 0 63 32 */
- {0xFFFFFFFFu, 0xFFFFFFFFu},
-
- /* ownQdmaChannels */
- /* 31 0 */
- {0x000000FFu},
-
- /* ownTccs */
- /* 31 0 63 32 */
- {0xFFFFFFFFu, 0xFFFFFFFFu},
-
- /* Resources reserved by Region 1 */
- /* resvdPaRAMSets */
- /* 31 0 63 32 95 64 127 96 */
- {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
- /* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
- /* resvdDmaChannels */
- /* 31 0 */
- {EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0,
- /* 63..32 */
- EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1},
-
- /* resvdQdmaChannels */
- /* 31 0 */
- {0x00000000u},
-
- /* resvdTccs */
- /* 31 0 */
- {EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0,
- /* 63..32 */
- EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1},
- },
- /* Resources owned/reserved by region 2 */
- {
- /* ownPaRAMSets */
- /* 31 0 63 32 95 64 127 96 */
- {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
- /* ownDmaChannels */
- /* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
-
- /* ownQdmaChannels */
- /* 31 0 */
- {0x00000000u},
-
- /* ownTccs */
- /* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
-
- /* resvdPaRAMSets */
- /* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
- /* resvdDmaChannels */
- /* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
-
- /* resvdQdmaChannels */
- /* 31 0 */
- {0x00000000u},
-
- /* resvdTccs */
- /* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
- },
-
- /* Resources owned/reserved by region 3 */
- {
- /* ownPaRAMSets */
- /* 31 0 63 32 95 64 127 96 */
- {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
- /* ownDmaChannels */
- /* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
-
- /* ownQdmaChannels */
- /* 31 0 */
- {0x00000000u},
-
- /* ownTccs */
- /* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
-
- /* resvdPaRAMSets */
- /* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
- /* resvdDmaChannels */
- /* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
-
- /* resvdQdmaChannels */
- /* 31 0 */
- {0x00000000u},
-
- /* resvdTccs */
- /* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
- },
-
- /* Resources owned/reserved by region 4 */
- {
- /* ownPaRAMSets */
- /* 31 0 63 32 95 64 127 96 */
- {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
- /* ownDmaChannels */
- /* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
-
- /* ownQdmaChannels */
- /* 31 0 */
- {0x00000000u},
-
- /* ownTccs */
- /* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
-
- /* resvdPaRAMSets */
- /* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
- /* resvdDmaChannels */
- /* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
-
- /* resvdQdmaChannels */
- /* 31 0 */
- {0x00000000u},
-
- /* resvdTccs */
- /* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
- },
-
- /* Resources owned/reserved by region 5 */
- {
- /* ownPaRAMSets */
- /* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
- /* ownDmaChannels */
- /* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
-
- /* ownQdmaChannels */
- /* 31 0 */
- {0x00000000u},
-
- /* ownTccs */
- /* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
-
- /* resvdPaRAMSets */
- /* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
- /* resvdDmaChannels */
- /* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
-
- /* resvdQdmaChannels */
- /* 31 0 */
- {0x00000000u},
-
- /* resvdTccs */
- /* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
- },
-
- /* Resources owned/reserved by region 6 */
- {
- /* ownPaRAMSets */
- /* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
- /* ownDmaChannels */
- /* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
-
- /* ownQdmaChannels */
- /* 31 0 */
- {0x00000000u},
-
- /* ownTccs */
- /* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
-
- /* resvdPaRAMSets */
- /* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
- /* resvdDmaChannels */
- /* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
-
- /* resvdQdmaChannels */
- /* 31 0 */
- {0x00000000u},
-
- /* resvdTccs */
- /* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
- },
-
- /* Resources owned/reserved by region 7 */
- {
- /* ownPaRAMSets */
- /* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
- /* ownDmaChannels */
- /* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
-
- /* ownQdmaChannels */
- /* 31 0 */
- {0x00000000u},
-
- /* ownTccs */
- /* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
-
- /* resvdPaRAMSets */
- /* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
- /* resvdDmaChannels */
- /* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
-
- /* resvdQdmaChannels */
- /* 31 0 */
- {0x00000000u},
-
- /* resvdTccs */
- /* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
- },
- }
-};
+ /* EDMA3 INSTANCE# 0 */
+ {
+ /* Resources owned/reserved by region 0 (Configuration for Centaurus A8 Core)*/
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ /* 159 128 191 160 223 192 255 224 */
+ 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ /* 287 256 319 288 351 320 383 352 */
+ 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ /* 415 384 447 416 479 448 511 480 */
+ 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {EDMA3_OWN_DMA_CHANNELS_0_A8, EDMA3_OWN_DMA_CHANNELS_1_A8},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {EDMA3_OWN_QDMA_CHANNELS_0_A8},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {EDMA3_OWN_TCC_0_A8, EDMA3_OWN_TCC_1_A8},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {EDMA3_RESERVED_DMA_CHANNELS_0_A8, EDMA3_RESERVED_DMA_CHANNELS_1_A8},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {EDMA3_RESERVED_QDMA_CHANNELS_0_A8},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {EDMA3_RESERVED_TCC_0_A8, EDMA3_RESERVED_TCC_1_A8},
+ },
+
+ /* Resources owned/reserved by region 1 (Configuration for Centaurus DSP Core)*/
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ /* 159 128 191 160 223 192 255 224 */
+ 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ /* 287 256 319 288 351 320 383 352 */
+ 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ /* 415 384 447 416 479 448 511 480 */
+ 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {EDMA3_OWN_DMA_CHANNELS_0_DSP, EDMA3_OWN_DMA_CHANNELS_1_DSP},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {EDMA3_OWN_QDMA_CHANNELS_0_DSP},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {EDMA3_OWN_TCC_0_DSP, EDMA3_OWN_TCC_1_DSP},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {EDMA3_RESERVED_DMA_CHANNELS_0_DSP, EDMA3_RESERVED_DMA_CHANNELS_1_DSP},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {EDMA3_RESERVED_QDMA_CHANNELS_0_DSP},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {EDMA3_RESERVED_TCC_0_DSP, EDMA3_RESERVED_TCC_1_DSP},
+ },
+
+ /* Resources owned/reserved by region 2 (Not Associated to any core supported)*/
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 3 (Not Associated to any core supported)*/
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 4 (Configuration for Centaurus M3VIDEO Core)*/
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ /* 159 128 191 160 223 192 255 224 */
+ 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ /* 287 256 319 288 351 320 383 352 */
+ 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ /* 415 384 447 416 479 448 511 480 */
+ 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {EDMA3_OWN_DMA_CHANNELS_0_M3VIDEO, EDMA3_OWN_DMA_CHANNELS_1_M3VIDEO},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {EDMA3_OWN_QDMA_CHANNELS_0_M3VIDEO},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {EDMA3_OWN_TCC_0_M3VIDEO, EDMA3_OWN_TCC_0_M3VIDEO},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {EDMA3_RESERVED_DMA_CHANNELS_0_M3VIDEO, EDMA3_RESERVED_DMA_CHANNELS_1_M3VIDEO},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {EDMA3_RESERVED_QDMA_CHANNELS_0_M3VIDEO},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {EDMA3_RESERVED_TCC_0_M3VIDEO, EDMA3_RESERVED_TCC_1_M3VIDEO},
+ },
+
+ /* Resources owned/reserved by region 5 (Configuration for Centaurus M3VPSS Core)*/
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ /* 159 128 191 160 223 192 255 224 */
+ 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ /* 287 256 319 288 351 320 383 352 */
+ 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ /* 415 384 447 416 479 448 511 480 */
+ 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {EDMA3_OWN_DMA_CHANNELS_0_M3VPSS, EDMA3_OWN_DMA_CHANNELS_1_M3VPSS},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {EDMA3_OWN_QDMA_CHANNELS_0_M3VPSS},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {EDMA3_OWN_TCC_0_M3VPSS, EDMA3_OWN_TCC_1_M3VPSS},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {EDMA3_RESERVED_DMA_CHANNELS_0_M3VPSS, EDMA3_RESERVED_DMA_CHANNELS_1_M3VPSS},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {EDMA3_RESERVED_QDMA_CHANNELS_0_M3VPSS},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {EDMA3_RESERVED_TCC_0_M3VPSS, EDMA3_RESERVED_TCC_1_M3VPSS},
+ },
+
+ /* Resources owned/reserved by region 6 (Not Associated to any core supported)*/
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 7 (Not Associated to any core supported)*/
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+ },
+ };
/* Driver Instance Cross bar event to channel map Initialization Configuration */
EDMA3_DRV_GblXbarToChanConfigParams sampleXbarChanInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
/* Driver Instance Cross bar event to channel map Initialization Configuration */
EDMA3_DRV_GblXbarToChanConfigParams sampleXbarChanInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
@@ -796,7 +935,7 @@ EDMA3_DRV_GblXbarToChanConfigParams sampleXbarChanInitConfig[NUM_EDMA3_INSTANCES
-1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1,
- -1, -1, -1, -1, -1, -1, -1
+ -1, 26, 27, -1, -1, -1, -1
},
/* Event to channel map for region 1 */
{
},
/* Event to channel map for region 1 */
{