Misra C fixes:

[keystone-rtos/edma3_lld.git] / packages / ti / sdo / edma3 / drv / src / edma3.h

diff --git a/packages/ti/sdo/edma3/drv/src/edma3.h b/packages/ti/sdo/edma3/drv/src/edma3.h
index 6c7ff02ddad3d83b97c23a2aec7c85dd64479f2c..4bcf4c0db0f8536d2e1b67b03dc2f9872de9503c 100755 (executable)
--- a/packages/ti/sdo/edma3/drv/src/edma3.h
+++ b/packages/ti/sdo/edma3/drv/src/edma3.h
@@ -36,8 +36,8 @@
  *
 */
 
-#ifndef _EDMA3_H_
-#define _EDMA3_H_
+#ifndef EDMA3_H_
+#define EDMA3_H_
 
 /** Include EDMA3 Driver header file */
 #include <ti/sdo/edma3/drv/edma3_drv.h>
@@ -107,36 +107,36 @@ extern "C" {
 #define EDMA3_DRV_OPT_ITCCHEN_SET_MASK(itcchen)     (((EDMA3_CCRL_OPT_ITCCHEN_MASK >> EDMA3_CCRL_OPT_ITCCHEN_SHIFT) & (itcchen)) << EDMA3_CCRL_OPT_ITCCHEN_SHIFT)
 
 /** OPT-SAM bit Get */
-#define EDMA3_DRV_OPT_SAM_GET_MASK(mode)            ((mode)&1u)
+#define EDMA3_DRV_OPT_SAM_GET_MASK(mode)            ((mode)&1U)
 /** OPT-DAM bit Get */
-#define EDMA3_DRV_OPT_DAM_GET_MASK(mode)            (((mode)&(1u<<1u))>>1u)
+#define EDMA3_DRV_OPT_DAM_GET_MASK(mode)            (((mode)&(1U<<1U))>>1U)
 /** OPT-SYNCDIM bit Get */
-#define EDMA3_DRV_OPT_SYNCDIM_GET_MASK(synctype)    (((synctype)&(1u<<2u))>>2u)
+#define EDMA3_DRV_OPT_SYNCDIM_GET_MASK(synctype)    (((synctype)&(1U<<2U))>>2U)
 /** OPT-STATIC bit Get */
-#define EDMA3_DRV_OPT_STATIC_GET_MASK(en)           (((en)&(1u<<3u))>>3u)
+#define EDMA3_DRV_OPT_STATIC_GET_MASK(en)           (((en)&(1U<<3U))>>3U)
 /** OPT-FWID bitfield Get */
-#define EDMA3_DRV_OPT_FWID_GET_MASK(width)          (((width)&(0x7u<<8u))>>8u)
+#define EDMA3_DRV_OPT_FWID_GET_MASK(width)          (((width)&(0x7U<<8U))>>8U)
 /** OPT-TCCMODE bit Get */
-#define EDMA3_DRV_OPT_TCCMODE_GET_MASK(early)       (((early)&(1u<<11u))>>11u)
+#define EDMA3_DRV_OPT_TCCMODE_GET_MASK(early)       (((early)&(1U<<11U))>>11U)
 /** OPT-TCC bitfield Get */
-#define EDMA3_DRV_OPT_TCC_GET_MASK(tcc)             (((tcc)&(0x3fu<<12u))>>12u)
+#define EDMA3_DRV_OPT_TCC_GET_MASK(tcc)             (((tcc)&((uint32_t)0x3fU<<12U))>>12U)
 /** OPT-TCINTEN bit Get */
-#define EDMA3_DRV_OPT_TCINTEN_GET_MASK(tcinten)     (((tcinten)&(1u<<20u))>>20u)
+#define EDMA3_DRV_OPT_TCINTEN_GET_MASK(tcinten)     (((tcinten)&(1U<<20U))>>20U)
 /** OPT-ITCINTEN bit Get */
-#define EDMA3_DRV_OPT_ITCINTEN_GET_MASK(itcinten)   (((itcinten)&(1u<<21u))>>21u)
+#define EDMA3_DRV_OPT_ITCINTEN_GET_MASK(itcinten)   (((itcinten)&(1U<<21U))>>21U)
 /** OPT-TCCHEN bit Get */
-#define EDMA3_DRV_OPT_TCCHEN_GET_MASK(tcchen)       (((tcchen)&(1u<<22u))>>22u)
+#define EDMA3_DRV_OPT_TCCHEN_GET_MASK(tcchen)       (((tcchen)&(1U<<22U))>>22U)
 /** OPT-ITCCHEN bit Get */
-#define EDMA3_DRV_OPT_ITCCHEN_GET_MASK(itcchen)     (((itcchen)&(1u<<23u))>>23u)
+#define EDMA3_DRV_OPT_ITCCHEN_GET_MASK(itcchen)     (((itcchen)&(1U<<23U))>>23U)
 
 /** DMAQNUM bits Clear */
-#define EDMA3_DRV_DMAQNUM_CLR_MASK(chNum)           (~(0x7u<<(((chNum)%8u)*4u)))
+#define EDMA3_DRV_DMAQNUM_CLR_MASK(chNum)           (~((uint32_t)0x7U<<(((chNum)%8U)*4U)))
 /** DMAQNUM bits Set */
-#define EDMA3_DRV_DMAQNUM_SET_MASK(chNum,queNum)    ((0x7u & (queNum)) << (((chNum)%8u)*4u))
+#define EDMA3_DRV_DMAQNUM_SET_MASK(chNum,queNum)    ((0x7U & (queNum)) << (((chNum)%8U)*4U))
 /** QDMAQNUM bits Clear */
-#define EDMA3_DRV_QDMAQNUM_CLR_MASK(chNum)          (~(0x7u<<((chNum)*4u)))
+#define EDMA3_DRV_QDMAQNUM_CLR_MASK(chNum)          (~((uint32_t)0x7U<<((chNum)*4U)))
 /** QDMAQNUM bits Set */
-#define EDMA3_DRV_QDMAQNUM_SET_MASK(chNum,queNum)   ((0x7u & (queNum)) << ((chNum)*4u))
+#define EDMA3_DRV_QDMAQNUM_SET_MASK(chNum,queNum)   ((0x7U & (queNum)) << ((chNum)*4U))
 
 
 /* Other Mask defines */
@@ -157,13 +157,13 @@ extern "C" {
 #define EDMA3_DRV_QCH_PARAM_TRWORD_CLR_MASK         (EDMA3_DRV_QCH_PARAM_CLR_MASK | EDMA3_DRV_QCH_TRWORD_CLR_MASK)
 
 /** Max value of ACnt */
-#define EDMA3_DRV_ACNT_MAX_VAL              (0xFFFFu)
+#define EDMA3_DRV_ACNT_MAX_VAL              (0xFFFFU)
 /** Max value of BCnt */
-#define EDMA3_DRV_BCNT_MAX_VAL              (0xFFFFu)
+#define EDMA3_DRV_BCNT_MAX_VAL              (0xFFFFU)
 /** Max value of CCnt */
-#define EDMA3_DRV_CCNT_MAX_VAL              (0xFFFFu)
+#define EDMA3_DRV_CCNT_MAX_VAL              (0xFFFFU)
 /** Max value of BCntReld */
-#define EDMA3_DRV_BCNTRELD_MAX_VAL          (0xFFFFu)
+#define EDMA3_DRV_BCNTRELD_MAX_VAL          (0xFFFFU)
 /** Max value of SrcBIdx */
 #define EDMA3_DRV_SRCBIDX_MAX_VAL           (0x7FFF)
 /** Min value of SrcBIdx */
@@ -181,9 +181,9 @@ extern "C" {
 /** Min value of DestCIdx */
 #define EDMA3_DRV_DSTCIDX_MIN_VAL           (-32768)
 /** Max value of Queue Priority */
-#define EDMA3_DRV_QPRIORITY_MAX_VAL         (7u)
+#define EDMA3_DRV_QPRIORITY_MAX_VAL         (7U)
 /** Min value of Queue Priority */
-#define EDMA3_DRV_QPRIORITY_MIN_VAL         (0u)
+#define EDMA3_DRV_QPRIORITY_MIN_VAL         (0U)
 
 
 /** To maintain the state of the EDMA3 Driver object */