diff --git a/packages/ti/sdo/edma3/drv/src/edma3_drv_basic.c b/packages/ti/sdo/edma3/drv/src/edma3_drv_basic.c
-/*******************************************************************************\r
-**+--------------------------------------------------------------------------+**\r
-**| **** |**\r
-**| **** |**\r
-**| ******o*** |**\r
-**| ********_///_**** |**\r
-**| ***** /_//_/ **** |**\r
-**| ** ** (__/ **** |**\r
-**| ********* |**\r
-**| **** |**\r
-**| *** |**\r
-**| |**\r
-**| Copyright (c) 1998-2006 Texas Instruments Incorporated |**\r
-**| ALL RIGHTS RESERVED |**\r
-**| |**\r
-**| Permission is hereby granted to licensees of Texas Instruments |**\r
-**| Incorporated (TI) products to use this computer program for the sole |**\r
-**| purpose of implementing a licensee product based on TI products. |**\r
-**| No other rights to reproduce, use, or disseminate this computer |**\r
-**| program, whether in part or in whole, are granted. |**\r
-**| |**\r
-**| TI makes no representation or warranties with respect to the |**\r
-**| performance of this computer program, and specifically disclaims |**\r
-**| any responsibility for any damages, special or consequential, |**\r
-**| connected with the use of this program. |**\r
-**| |**\r
-**+--------------------------------------------------------------------------+**\r
-*******************************************************************************/\r
-\r
-/**\r
-* \file edma3_drv_basic.c\r
-*\r
-* \brief EDMA3 Driver Basic Interface Implementation\r
-* This file contains beginner-level EDMA3 Driver APIs which are required\r
-* to:\r
-* a) Request/free a DMA, QDMA and Link channel.\r
-* b) Program various fields in the PaRAM Set like source/destination\r
-* parameters, transfer parameters etc.\r
-* c) Enable/disable a transfer.\r
-* These APIs are provided to program a DMA/QDMA channel for simple use-cases\r
-* and don't expose all the features of EDMA3 hardware. Users who want to go\r
-* beyond this and have complete control on the EDMA3 hardware are advised\r
-* to refer edma3_drv_adv.c source file.\r
-*\r
-* @author: PSP Team, TII\r
-*\r
-*/\r
-\r
-\r
-/* EDMa3 Driver Internal Header Files */\r
-#include <ti/sdo/edma3/drv/src/edma3.h>\r
-/* Resource Manager Internal Header Files */\r
-#include <ti/sdo/edma3/rm/src/edma3resmgr.h>\r
-\r
-/* Instrumentation Header File */\r
-#ifdef EDMA3_INSTRUMENTATION_ENABLED\r
-#include <ti/sdo/edma3/rm/src/edma3_log.h>\r
-#endif\r
-\r
-/* For assert() */\r
-/**\r
- * Define NDEBUG to ignore assert().\r
- * NDEBUG should be defined before including assert.h header file.\r
- */\r
-#include <assert.h>\r
-\r
-\r
-/* Externel Variables */\r
-/*---------------------------------------------------------------------------*/\r
-/**\r
- * Maximum Resource Manager Instances supported by the EDMA3 Package.\r
- */\r
-extern const unsigned int EDMA3_MAX_RM_INSTANCES;\r
-\r
-\r
-/**\r
- * \brief EDMA3 Resource Manager Objects, tied to each EDMA3 HW Controller.\r
- *\r
- * Typically one RM object will cater to one EDMA3 HW controller\r
- * and will have all the global config information.\r
- */\r
-extern EDMA3_RM_Obj resMgrObj[EDMA3_MAX_EDMA3_INSTANCES];\r
-\r
-\r
-/**\r
- * \brief Region Specific Configuration structure for\r
- * EDMA3 controller, to provide region specific Information.\r
- *\r
- * This configuration info can also be provided by the user at run-time,\r
- * while calling EDMA3_RM_open (). If not provided at run-time,\r
- * this info will be taken from the config file "edma3_<PLATFORM_NAME>_cfg.c",\r
- * for the specified platform.\r
- */\r
-extern EDMA3_RM_InstanceInitConfig *ptrInitCfgArray;\r
-\r
-\r
-/**\r
- * Handles of EDMA3 Resource Manager Instances.\r
- *\r
- * Used to maintain information of the EDMA3 RM Instances\r
- * for each HW controller.\r
- * There could be a maximum of EDMA3_MAX_RM_INSTANCES instances per\r
- * EDMA3 HW.\r
- */\r
-extern EDMA3_RM_Instance *ptrRMIArray;\r
-\r
-/** Local MemSet function */\r
-extern void edma3MemSet(void *dst, unsigned char data, unsigned int len);\r
-/** Local MemCpy function */\r
-extern void edma3MemCpy(void *dst, const void *src, unsigned int len);\r
-\r
-/**\r
- * \brief EDMA3 Driver Objects, tied to each EDMA3 HW Controller.\r
- *\r
- * Typically one object will cater to one EDMA3 HW controller\r
- * and will have all regions' (ARM, DSP etc) specific config information.\r
- */\r
-extern EDMA3_DRV_Object drvObj [EDMA3_MAX_EDMA3_INSTANCES];\r
-\r
-\r
-/**\r
- * Handles of EDMA3 Driver Instances.\r
- *\r
- * Used to maintain information of the EDMA3 Driver Instances for\r
- * each region, for each HW controller.\r
- * There could be as many Driver Instances as there are shadow\r
- * regions. Multiple EDMA3 Driver instances on the same shadow\r
- * region are NOT allowed.\r
- */\r
-extern EDMA3_DRV_Instance drvInstance [EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGIONS];\r
-\r
-\r
-/**\r
- * \brief Resources bound to a Channel\r
- *\r
- * When a request for a channel is made, the resources PaRAM Set and TCC\r
- * get bound to that channel. This information is needed internally by the\r
- * driver when a request is made to free the channel (Since it is the\r
- * responsibility of the driver to free up the channel-associated resources\r
- * from the Resource Manager layer).\r
- */\r
-extern EDMA3_DRV_ChBoundResources edma3DrvChBoundRes [EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_LOGICAL_CH];\r
-\r
-\r
-\r
-/* Local functions prototypes */\r
-/*---------------------------------------------------------------------------*/\r
-/** Remove various mappings and do cleanup for DMA/QDMA channels */\r
-static EDMA3_DRV_Result edma3RemoveMapping (EDMA3_DRV_Handle hEdma,\r
- unsigned int channelId);\r
-\r
-/*---------------------------------------------------------------------------*/\r
-\r
-\r
-/**\r
- * \brief Request a DMA/QDMA/Link channel.\r
- *\r
- * Each channel (DMA/QDMA/Link) must be requested before initiating a DMA\r
- * transfer on that channel.\r
- *\r
- * This API is used to allocate a logical channel (DMA/QDMA/Link) along with\r
- * the associated resources. For DMA and QDMA channels, TCC and PaRAM Set are\r
- * also allocated along with the requested channel. For Link channel, ONLY a\r
- * PaRAM Set is allocated.\r
- *\r
- * User can request a specific logical channel by passing the channel id in\r
- * 'pLCh'. Note that the channel id is the same as the actual resource id in\r
- * case of DMA channels. To allocate specific QDMA channels, user SHOULD use the\r
- * defines EDMA3_DRV_QDMA_CHANNEL_X mentioned above.\r
- *\r
- * User can also request ANY available logical channel also by specifying the\r
- * below mentioned values in '*pLCh':\r
- * a) EDMA3_DRV_DMA_CHANNEL_ANY: For DMA channels\r
- * b) EDMA3_DRV_QDMA_CHANNEL_ANY: For QDMA channels, and\r
- * c) EDMA3_DRV_LINK_CHANNEL: For Link channels. Normally user should use this\r
- * value to request link channels (PaRAM Sets used for linking purpose\r
- * only), unless he wants to use some specific link channels (PaRAM Sets)\r
- * which is also allowed.\r
- *\r
- * This API internally uses EDMA3_RM_allocResource () to allocate the desired\r
- * resources (DMA/QDMA channel, PaRAM Set and TCC).\r
- *\r
- * This API also registers a specific callback function against the allocated\r
- * TCC.\r
- *\r
- * For DMA/QDMA channels, after allocating all the EDMA3 resources, this API\r
- * sets the TCC field of the OPT PaRAM Word with the allocated TCC. It also sets\r
- * the event queue for the channel allocated. The event queue needs to be\r
- * specified by the user.\r
- *\r
- * For DMA channel, it also sets the DCHMAP register, if required.\r
- *\r
- * For QDMA channel, it sets the QCHMAP register and CCNT as trigger word and\r
- * enables the QDMA channel by writing to the QEESR register.\r
- *\r
- * \param hEdma [IN] Handle to the previously opened Driver\r
- * Instance.\r
- * \param pLCh [IN/OUT] Requested logical channel id.\r
- * Examples:\r
- * - EDMA3_DRV_HW_CHANNEL_EVENT_0\r
- * - To request a DMA Master Channel\r
- * mapped to EDMA Event 0.\r
- *\r
- * - EDMA3_DRV_DMA_CHANNEL_ANY\r
- * - For requesting any DMA Master channel\r
- * with no event mapping.\r
- *\r
- * - EDMA3_DRV_QDMA_CHANNEL_ANY\r
- * - For requesting any QDMA Master channel\r
- *\r
- * - EDMA3_DRV_QDMA_CHANNEL_0\r
- * - For requesting the QDMA Channel 0.\r
- *\r
- * - EDMA3_DRV_LINK_CHANNEL\r
- * - For requesting a DMA Slave Channel,\r
- * - to be linked to some other Master\r
- * - channel.\r
- *\r
- * In case user passes a specific channel\r
- * Id, pLCh value is left unchanged. In\r
- * case user requests ANY available\r
- * resource, the allocated channel id is\r
- * returned in pLCh.\r
- *\r
- * \note To request a PaRAM Set for the purpose of\r
- * linking to another channel, call the function with\r
- *\r
- * *pLCh = EDMA3_DRV_LINK_CHANNEL;\r
- *\r
- * This function will update *pLCh with the allocated Link channel\r
- * handle. This handle could be DIFFERENT from the actual PaRAM Set\r
- * allocated by the Resource Manager internally. So user SHOULD NOT\r
- * assume the handle as the PaRAM Set Id.\r
- *\r
- * \param pTcc [IN/OUT] The channel number on which the\r
- * completion/error interrupt is generated.\r
- * Not used if user requested for a Link\r
- * channel.\r
- * Examples:\r
- * - EDMA3_DRV_HW_CHANNEL_EVENT_0\r
- * - To request TCC associated with\r
- * - DMA Master Channel mapped to EDMA\r
- * - event 0.\r
- *\r
- * - EDMA3_DRV_TCC_ANY\r
- * - For requesting any TCC with no\r
- * - channel mapping.\r
- * In case user passes a specific TCC\r
- * value, pTcc value is left unchanged.\r
- * In case user requests ANY available TCC,\r
- * the allocated one is returned in pTcc\r
- *\r
- * \param evtQueue [IN] Event Queue Number to which the channel\r
- * will be mapped (valid only for the\r
- * Master Channel (DMA/QDMA) request)\r
- *\r
- * \param tccCb [IN] TCC callback - caters to channel-\r
- * specific events like "Event Miss Error"\r
- * or "Transfer Complete"\r
- *\r
- * \param cbData [IN] Data which will be passed directly to\r
- * the tccCb callback function\r
- *\r
- * \return EDMA3_DRV_SOK or EDMA3_DRV Error code\r
- *\r
- * \note This function internally uses EDMA3 Resource Manager, which\r
- * acquires a RM Instance specific semaphore\r
- * to prevent simultaneous access to the global pool of resources.\r
- * It also disables the global interrupts while modifying\r
- * the global CC registers.\r
- * It is re-entrant, but SHOULD NOT be called from the user callback\r
- * function (ISR context).\r
- */\r
-EDMA3_DRV_Result EDMA3_DRV_requestChannel (EDMA3_DRV_Handle hEdma,\r
- unsigned int *pLCh,\r
- unsigned int *pTcc,\r
- EDMA3_RM_EventQueue evtQueue,\r
- EDMA3_RM_TccCallback tccCb,\r
- void *cbData)\r
- {\r
- EDMA3_RM_ResDesc resObj;\r
- EDMA3_RM_ResDesc channelObj;\r
- EDMA3_DRV_Result result = EDMA3_DRV_SOK;\r
- unsigned int linkBcntReld = 0;\r
- EDMA3_DRV_Instance *drvInst = NULL;\r
- EDMA3_DRV_Object *drvObject = NULL;\r
- EDMA3_RM_ResType savedResType;\r
- unsigned int mappedTcc = EDMA3_DRV_CH_NO_TCC_MAP;\r
- int paRAMId = (int)EDMA3_RM_RES_ANY;\r
- EDMA3_DRV_ChannelType chType = EDMA3_DRV_CHANNEL_TYPE_QDMA;\r
- volatile EDMA3_CCRL_Regs *globalRegs = NULL;\r
- int mappedPaRAMId;\r
-\r
-#ifdef EDMA3_INSTRUMENTATION_ENABLED\r
- EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",\r
- EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,\r
- EDMA3_DVT_dCOUNTER,\r
- EDMA3_DVT_dNONE,\r
- EDMA3_DVT_dNONE));\r
-#endif /* EDMA3_INSTRUMENTATION_ENABLED */\r
-\r
- /* If parameter checking is enabled... */\r
-#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE\r
- if ((pLCh == NULL) || (hEdma == NULL))\r
- {\r
- result = EDMA3_DRV_E_INVALID_PARAM;\r
- }\r
-#endif\r
-\r
- /* Check if the parameters are OK. */\r
- if (EDMA3_DRV_SOK == result)\r
- {\r
- drvInst = (EDMA3_DRV_Instance *)hEdma;\r
- drvObject = drvInst->pDrvObjectHandle;\r
-\r
- if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL))\r
- {\r
- result = EDMA3_DRV_E_INVALID_PARAM;\r
- }\r
- else\r
- {\r
- globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);\r
-\r
- /* If parameter checking is enabled... */\r
-#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE\r
- if (((*pLCh) != EDMA3_DRV_LINK_CHANNEL) &&\r
- ((evtQueue >= drvObject->gblCfgParams.numEvtQueue) || (pTcc == NULL)))\r
- {\r
- result = EDMA3_DRV_E_INVALID_PARAM;\r
- }\r
-#endif\r
-\r
- /* Check if the parameters are OK. */\r
- if (EDMA3_DRV_SOK == result)\r
- {\r
- if ((*pLCh) == EDMA3_DRV_LINK_CHANNEL)\r
- {\r
- /*\r
- * Do nothing. Do not allocate channel.\r
- * Typically this option is for request\r
- * of a PaRAM Set for linking purpose.\r
- */\r
- result = EDMA3_DRV_SOK;\r
- }\r
- else if ((*pLCh) == EDMA3_DRV_DMA_CHANNEL_ANY)\r
- {\r
- /* First request for any available DMA channel */\r
- resObj.type = EDMA3_RM_RES_DMA_CHANNEL;\r
- resObj.resId = EDMA3_RM_RES_ANY;\r
- result = EDMA3_RM_allocResource(drvInst->resMgrInstance, (EDMA3_RM_ResDesc *)&resObj);\r
-\r
- if (result == EDMA3_RM_SOK)\r
- {\r
- *pLCh = resObj.resId;\r
- mappedPaRAMId = drvObject->gblCfgParams.dmaChannelPaRAMMap[*pLCh];\r
- mappedTcc = drvObject->gblCfgParams.dmaChannelTccMap[*pLCh];\r
- if (mappedPaRAMId != EDMA3_DRV_CH_NO_PARAM_MAP)\r
- {\r
- /*\r
- * There is a PaRAM Set statically mapped to the returned\r
- * channel number.\r
- * This imposes a constraint on the PaRAM Set which we\r
- * next request for.\r
- * We update the PaRAM Set number with the one statically\r
- * reserved for the afore-returned channel number.\r
- */\r
- paRAMId = mappedPaRAMId;\r
- }\r
- chType = EDMA3_DRV_CHANNEL_TYPE_DMA;\r
-\r
- /* Save the Resource Type for TCC registeration */\r
- channelObj.type = EDMA3_RM_RES_DMA_CHANNEL;\r
- }\r
- else\r
- {\r
- result = EDMA3_DRV_E_DMA_CHANNEL_UNAVAIL;\r
- }\r
- }\r
- else if ((*pLCh) == EDMA3_DRV_QDMA_CHANNEL_ANY)\r
- {\r
- /* First request for any available QDMA channel */\r
- resObj.type = EDMA3_RM_RES_QDMA_CHANNEL;\r
- resObj.resId = EDMA3_RM_RES_ANY;\r
- result = EDMA3_RM_allocResource(drvInst->resMgrInstance,\r
- (EDMA3_RM_ResDesc *)&resObj);\r
- if (result == EDMA3_DRV_SOK)\r
- {\r
- (*pLCh) = resObj.resId + EDMA3_DRV_QDMA_CH_MIN_VAL;\r
- chType = EDMA3_DRV_CHANNEL_TYPE_QDMA;\r
-\r
- /* Save the Resource Type for TCC registeration */\r
- channelObj.type = EDMA3_RM_RES_QDMA_CHANNEL;\r
- }\r
- else\r
- {\r
- result = EDMA3_DRV_E_QDMA_CHANNEL_UNAVAIL;\r
- }\r
- }\r
- else if ((*pLCh) <= EDMA3_DRV_DMA_CH_MAX_VAL)\r
- {\r
- /* Request for a specific DMA channel */\r
- resObj.type = EDMA3_RM_RES_DMA_CHANNEL;\r
- resObj.resId = *pLCh;\r
- result = EDMA3_RM_allocResource(drvInst->resMgrInstance, (EDMA3_RM_ResDesc *)&resObj);\r
- if (result != EDMA3_RM_SOK)\r
- {\r
- result = EDMA3_DRV_E_DMA_CHANNEL_UNAVAIL;\r
- }\r
- else\r
- {\r
- mappedPaRAMId = drvObject->gblCfgParams.dmaChannelPaRAMMap[*pLCh];\r
- mappedTcc = drvObject->gblCfgParams.dmaChannelTccMap[*pLCh];\r
- if (mappedPaRAMId != EDMA3_DRV_CH_NO_PARAM_MAP)\r
- {\r
- /*\r
- * There is a PaRAM Set statically mapped to the returned\r
- * channel number.\r
- * This imposes a constraint on the PaRAM Set which we\r
- * next request for.\r
- * We update the PaRAM Set number with the one statically\r
- * reserved for the afore-returned channel number.\r
- */\r
- paRAMId = mappedPaRAMId;\r
- }\r
- chType = EDMA3_DRV_CHANNEL_TYPE_DMA;\r
-\r
- /* Save the Resource Type for TCC registeration */\r
- channelObj.type = EDMA3_RM_RES_DMA_CHANNEL;\r
- }\r
- }\r
- else if (((*pLCh) >= EDMA3_DRV_QDMA_CH_MIN_VAL) && ((*pLCh) <= EDMA3_DRV_QDMA_CH_MAX_VAL))\r
- {\r
- /* Request for a specific QDMA channel */\r
- resObj.type = EDMA3_RM_RES_QDMA_CHANNEL;\r
- resObj.resId = (((*pLCh)) - EDMA3_DRV_QDMA_CH_MIN_VAL);\r
- result = EDMA3_RM_allocResource(drvInst->resMgrInstance, (EDMA3_RM_ResDesc *)&resObj);\r
- if (result != EDMA3_RM_SOK)\r
- {\r
- result = EDMA3_DRV_E_QDMA_CHANNEL_UNAVAIL;\r
- }\r
- else\r
- {\r
- chType = EDMA3_DRV_CHANNEL_TYPE_QDMA;\r
-\r
- /* Save the Resource Type for TCC registeration */\r
- channelObj.type = EDMA3_RM_RES_QDMA_CHANNEL;\r
- }\r
- }\r
- else\r
- {\r
- result = EDMA3_DRV_E_INVALID_PARAM;\r
- }\r
-\r
- if (result == EDMA3_DRV_SOK)\r
- {\r
- /* Request for a PaRAM Set */\r
- savedResType = resObj.type;\r
- resObj.type = EDMA3_RM_RES_PARAM_SET;\r
- resObj.resId = (unsigned int)paRAMId;\r
- result = EDMA3_RM_allocResource(drvInst->resMgrInstance, (EDMA3_RM_ResDesc *)&resObj);\r
-\r
- paRAMId = (int)resObj.resId;\r
- if ((*pLCh) == EDMA3_DRV_LINK_CHANNEL)\r
- {\r
- if (result == EDMA3_RM_SOK)\r
- {\r
- unsigned int linkCh = EDMA3_DRV_LINK_CH_MIN_VAL;\r
-\r
- /*\r
- * Search for the next Link channel handle available,\r
- * starting from EDMA3_DRV_LINK_CH_MIN_VAL.\r
- */\r
- while ((edma3DrvChBoundRes[drvObject->phyCtrllerInstId][linkCh].paRAMId != -1)\r
- && (linkCh <= EDMA3_DRV_LINK_CH_MAX_VAL))\r
- {\r
- /* Move to the next handle. */\r
- linkCh++;\r
- }\r
-\r
- /* Verify the returned handle, it should lie in the correct range */\r
- if (linkCh > EDMA3_DRV_LINK_CH_MAX_VAL)\r
- {\r
- result = EDMA3_DRV_E_INVALID_PARAM;\r
- }\r
- else\r
- {\r
- *pLCh = linkCh;\r
- }\r
- }\r
- }\r
- else\r
- {\r
- if (result != EDMA3_DRV_SOK)\r
- {\r
- /*\r
- * Free the already allocated channel\r
- * (only if channel is a Non-Link Channel)\r
- */\r
- resObj.type = savedResType;\r
- resObj.resId = *pLCh;\r
- EDMA3_RM_freeResource(drvInst->resMgrInstance, (EDMA3_RM_ResDesc *)&resObj);\r
- }\r
- else\r
- {\r
- /* Request for a TCC */\r
- resObj.type = EDMA3_RM_RES_TCC;\r
- if ((*pTcc) == EDMA3_DRV_TCC_ANY)\r
- {\r
- if (mappedTcc == EDMA3_DRV_CH_NO_TCC_MAP)\r
- {\r
- resObj.resId = EDMA3_RM_RES_ANY;\r
- }\r
- else\r
- {\r
- resObj.resId = mappedTcc;\r
- }\r
- }\r
- else\r
- {\r
- resObj.resId = *pTcc;\r
- }\r
-\r
- result = EDMA3_RM_allocResource(drvInst->resMgrInstance, (EDMA3_RM_ResDesc *)&resObj);\r
- if (result == EDMA3_DRV_SOK)\r
- {\r
- *pTcc = resObj.resId;\r
- }\r
- else\r
- {\r
- resObj.type = savedResType;\r
- resObj.resId = *pLCh;\r
- EDMA3_RM_freeResource(drvInst->resMgrInstance, (EDMA3_RM_ResDesc *)&resObj);\r
-\r
- resObj.type = EDMA3_RM_RES_PARAM_SET;\r
- resObj.resId = (unsigned int)paRAMId;\r
- EDMA3_RM_freeResource(drvInst->resMgrInstance, (EDMA3_RM_ResDesc *)&resObj);\r
- result = EDMA3_DRV_E_TCC_UNAVAIL;\r
- }\r
-\r
- if (result == EDMA3_DRV_SOK)\r
- {\r
- /* If callback function is not null, register it with the RM. */\r
- if (NULL != tccCb)\r
- {\r
- /**\r
- * Fill the resource id, whose associated TCC\r
- * needs to be registered.\r
- * For QDMA channels, pass the actual QDMA\r
- * channel no instead of (*pLCh).\r
- */\r
- if (((*pLCh) >= EDMA3_DRV_QDMA_CH_MIN_VAL)\r
- && ((*pLCh) <= EDMA3_DRV_QDMA_CH_MAX_VAL))\r
- {\r
- channelObj.resId = (*pLCh) - EDMA3_DRV_QDMA_CH_MIN_VAL;\r
- }\r
- else\r
- {\r
- channelObj.resId = (*pLCh);\r
- }\r
-\r
- result = EDMA3_RM_registerTccCb (\r
- drvInst->resMgrInstance,\r
- (EDMA3_RM_ResDesc *)&channelObj,\r
- *pTcc, tccCb, cbData);\r
-\r
- if (result != EDMA3_DRV_SOK)\r
- {\r
- EDMA3_DRV_freeChannel (hEdma, *pLCh);\r
- result = EDMA3_DRV_E_TCC_REGISTER_FAIL;\r
- }\r
- }\r
-\r
- if (result == EDMA3_DRV_SOK)\r
- {\r
-#ifndef EDMA3_PROGRAM_QUEUE_NUM_REGISTER_INIT_TIME\r
- unsigned int intState=0;\r
- edma3OsProtectEntry(EDMA3_OS_PROTECT_INTERRUPT, &intState);\r
-\r
- /* Associate Channel to Event Queue */\r
- if ((*pLCh) < drvObject->gblCfgParams.numDmaChannels)\r
- {\r
- globalRegs->DMAQNUM[(*pLCh) >> 3u] &= EDMA3_DRV_DMAQNUM_CLR_MASK(*pLCh);\r
- globalRegs->DMAQNUM[(*pLCh) >> 3u] |= EDMA3_DRV_DMAQNUM_SET_MASK((*pLCh),evtQueue);\r
- }\r
- else if (((*pLCh) >= EDMA3_DRV_QDMA_CH_MIN_VAL)\r
- && ((*pLCh) <= EDMA3_DRV_QDMA_CH_MAX_VAL))\r
- {\r
- globalRegs->QDMAQNUM &=\r
- EDMA3_DRV_QDMAQNUM_CLR_MASK((*pLCh)-EDMA3_DRV_QDMA_CH_MIN_VAL);\r
- globalRegs->QDMAQNUM |=\r
- EDMA3_DRV_QDMAQNUM_SET_MASK((*pLCh)-EDMA3_DRV_QDMA_CH_MIN_VAL,evtQueue);\r
- }\r
-\r
- edma3OsProtectExit(EDMA3_OS_PROTECT_INTERRUPT,intState);\r
-#endif \r
-\r
- /**\r
- * Map the allocated PaRAM Set to the logical\r
- * DMa/QDMA channel.\r
- */\r
- if (chType == EDMA3_DRV_CHANNEL_TYPE_QDMA)\r
- {\r
- result = EDMA3_RM_mapQdmaChannel (drvInst->resMgrInstance,\r
- ((*pLCh)-EDMA3_DRV_QDMA_CH_MIN_VAL),\r
- paRAMId,\r
- EDMA3_RM_QDMA_TRIG_DEFAULT);\r
- }\r
- else\r
- {\r
- /**\r
- * First check whether the mapping feature is supported on the underlying\r
- * platform. In case it is not supported, dont call this API, because this\r
- * API returns error in case the feature is not there.\r
- */\r
- if (TRUE == drvObject->gblCfgParams.dmaChPaRAMMapExists)\r
- {\r
- result = EDMA3_RM_mapEdmaChannel (drvInst->resMgrInstance,\r
- *pLCh,\r
- paRAMId);\r
- }\r
- }\r
-\r
- if (result != EDMA3_DRV_SOK)\r
- {\r
- EDMA3_DRV_freeChannel (hEdma, *pLCh);\r
- result = EDMA3_DRV_E_CH_PARAM_BIND_FAIL;\r
- }\r
- else\r
- {\r
- /* Bind the resources PaRAM Set and TCC */\r
- /* Set TCC of Param Set corresponding to specified paramId */\r
- globalRegs->PARAMENTRY [paRAMId].OPT &= EDMA3_DRV_OPT_TCC_CLR_MASK;\r
- globalRegs->PARAMENTRY [paRAMId].OPT |= EDMA3_DRV_OPT_TCC_SET_MASK(*pTcc);\r
-\r
- edma3DrvChBoundRes[drvObject->phyCtrllerInstId][*pLCh].tcc = *pTcc;\r
- }\r
- }\r
- }\r
- }\r
- }\r
-\r
- if (result == EDMA3_DRV_SOK)\r
- {\r
- /* Save the PaRAM Id and Trigger mode */\r
- edma3DrvChBoundRes[drvObject->phyCtrllerInstId][*pLCh].paRAMId = paRAMId;\r
- edma3DrvChBoundRes[drvObject->phyCtrllerInstId][*pLCh].trigMode =\r
- EDMA3_DRV_TRIG_MODE_NONE;\r
-\r
- /* Make the Link field NULL */\r
- /* Get the Link-bcntReload PaRAM set entry */\r
- linkBcntReld = (unsigned int)(*((&globalRegs->PARAMENTRY [paRAMId].OPT) +\r
- (unsigned int)EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD));\r
-\r
- /* Remove any linking */\r
- linkBcntReld |= 0xFFFFu;\r
-\r
- /* Store it back */\r
- *((&globalRegs->PARAMENTRY[paRAMId].OPT)\r
- + (unsigned int)EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD) = linkBcntReld;\r
-\r
- /*\r
- * For QDMA channels, Enable the transfer.\r
- * So that user doesn't have to call EDMA3_DRV_enableTransfer() again.\r
- */\r
- if (((*pLCh) >= EDMA3_DRV_QDMA_CH_MIN_VAL)\r
- && ((*pLCh) <= EDMA3_DRV_QDMA_CH_MAX_VAL))\r
- {\r
- drvInst->shadowRegs->QEESR = (1u<<((*pLCh)-EDMA3_DRV_QDMA_CH_MIN_VAL));\r
- /* save the trigger mode for future use */\r
- edma3DrvChBoundRes[drvObject->phyCtrllerInstId][*pLCh].trigMode = EDMA3_DRV_TRIG_MODE_QDMA;\r
- }\r
- }\r
- }\r
- }\r
- }\r
- }\r
-\r
-#ifdef EDMA3_INSTRUMENTATION_ENABLED\r
- EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",\r
- EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,\r
- EDMA3_DVT_dCOUNTER,\r
- EDMA3_DVT_dNONE,\r
- EDMA3_DVT_dNONE));\r
-#endif /* EDMA3_INSTRUMENTATION_ENABLED */\r
-\r
- return result;\r
-}\r
-\r
-\r
-/**\r
- * \brief Free the specified channel (DMA/QDMA/Link) and its associated\r
- * resources (PaRAM Set, TCC etc) and removes various mappings.\r
- *\r
- * This API internally uses EDMA3_RM_freeResource () to free the desired\r
- * resources.\r
- *\r
- * For Link channels, this API only frees the associated PaRAM Set.\r
- *\r
- * For DMA/QDMA channels, it does the following operations:\r
- * a) Disable any ongoing transfer on the channel,\r
- * b) Unregister the TCC Callback function and disable the interrupts,\r
- * c) Remove the channel to Event Queue mapping,\r
- * d) For DMA channels, clear the DCHMAP register, if available\r
- * e) For QDMA channels, clear the QCHMAP register,\r
- * f) Frees the DMA/QDMA channel in the end.\r
- *\r
- * \param hEdma [IN] Handle to the EDMA Driver Instance.\r
- * \param channelId [IN] Logical Channel number to be freed.\r
- *\r
- * \return EDMA3_DRV_SOK or EDMA3_DRV Error code\r
- *\r
- * \note This function disables the global interrupts while modifying\r
- * the global CC registers and while modifying global data structures,\r
- * to prevent simultaneous access to the global pool of resources.\r
- * It internally calls EDMA3_RM_freeResource () for resource\r
- * de-allocation. It is re-entrant.\r
- */\r
-EDMA3_DRV_Result EDMA3_DRV_freeChannel (EDMA3_DRV_Handle hEdma,\r
- unsigned int channelId)\r
- {\r
- EDMA3_RM_ResDesc resObj;\r
- EDMA3_DRV_Result result = EDMA3_DRV_SOK;\r
- EDMA3_DRV_Instance *drvInst = NULL;\r
- EDMA3_DRV_Object *drvObject = NULL;\r
- int paRAMId;\r
- unsigned int tcc;\r
- EDMA3_DRV_ChannelType chType = EDMA3_DRV_CHANNEL_TYPE_NONE;\r
-\r
-#ifdef EDMA3_INSTRUMENTATION_ENABLED\r
- EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",\r
- EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,\r
- EDMA3_DVT_dCOUNTER,\r
- EDMA3_DVT_dNONE,\r
- EDMA3_DVT_dNONE));\r
-#endif /* EDMA3_INSTRUMENTATION_ENABLED */\r
-\r
- /* If parameter checking is enabled... */\r
-#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE\r
- if ((channelId > EDMA3_DRV_LOG_CH_MAX_VAL) || (hEdma == NULL))\r
- {\r
- result = EDMA3_DRV_E_INVALID_PARAM;\r
- }\r
-#endif\r
-\r
- if (result == EDMA3_DRV_SOK)\r
- {\r
- drvInst = (EDMA3_DRV_Instance *)hEdma;\r
- drvObject = drvInst->pDrvObjectHandle;\r
-\r
- if (drvObject == NULL)\r
- {\r
- result = EDMA3_DRV_E_INVALID_PARAM;\r
- }\r
- }\r
-\r
- if (result == EDMA3_DRV_SOK)\r
- {\r
- /* Check the channel type */\r
- if (channelId <= EDMA3_DRV_DMA_CH_MAX_VAL)\r
- {\r
- /* DMA Channel */\r
- chType = EDMA3_DRV_CHANNEL_TYPE_DMA;\r
- }\r
-\r
- if ((channelId >= EDMA3_DRV_LINK_CH_MIN_VAL) && (channelId <= EDMA3_DRV_LINK_CH_MAX_VAL))\r
- {\r
- /* LINK Channel */\r
- chType = EDMA3_DRV_CHANNEL_TYPE_LINK;\r
- }\r
-\r
- if ((channelId >= EDMA3_DRV_QDMA_CH_MIN_VAL) && (channelId <= EDMA3_DRV_QDMA_CH_MAX_VAL))\r
- {\r
- /* QDMA Channel */\r
- chType = EDMA3_DRV_CHANNEL_TYPE_QDMA;\r
- }\r
-\r
- if (chType == 0)\r
- {\r
- result = EDMA3_DRV_E_INVALID_PARAM;\r
- }\r
- }\r
-\r
-\r
- if (result == EDMA3_DRV_SOK)\r
- {\r
- if (chType == EDMA3_DRV_CHANNEL_TYPE_LINK)\r
- {\r
- /* LINK Channel */\r
- resObj.type = EDMA3_RM_RES_PARAM_SET;\r
-\r
- /* Get the PaRAM id from the book-keeping info. */\r
- resObj.resId = (unsigned int)(edma3DrvChBoundRes[drvObject->phyCtrllerInstId][channelId].paRAMId);\r
-\r
- result = EDMA3_RM_freeResource(drvInst->resMgrInstance,\r
- (EDMA3_RM_ResDesc *)&resObj);\r
-\r
- if (result == EDMA3_DRV_SOK)\r
- {\r
- edma3DrvChBoundRes[drvObject->phyCtrllerInstId][channelId].paRAMId = -1;\r
- }\r
- }\r
- else\r
- {\r
- /* DMA/QDMA Channel */\r
- paRAMId = edma3DrvChBoundRes[drvObject->phyCtrllerInstId][channelId].paRAMId;\r
- tcc = edma3DrvChBoundRes[drvObject->phyCtrllerInstId][channelId].tcc;\r
-\r
- /* Check the paRAMId and tcc values first */\r
- if ((paRAMId < 0) || (paRAMId >= drvObject->gblCfgParams.numPaRAMSets))\r
- {\r
- result = EDMA3_DRV_E_INVALID_PARAM;\r
- }\r
-\r
- if (tcc >= drvObject->gblCfgParams.numTccs)\r
- {\r
- result = EDMA3_DRV_E_INVALID_PARAM;\r
- }\r
-\r
- if (result == EDMA3_DRV_SOK)\r
- {\r
- /* Disable the transfer and remove various mappings. */\r
- result = edma3RemoveMapping(hEdma, channelId);\r
- }\r
-\r
- if (result == EDMA3_DRV_SOK)\r
- {\r
- /* Now Free the PARAM set and TCC */\r
- resObj.type = EDMA3_RM_RES_PARAM_SET;\r
- resObj.resId = (unsigned int)paRAMId;\r
- result = EDMA3_RM_freeResource(drvInst->resMgrInstance, (EDMA3_RM_ResDesc *)&resObj);\r
-\r
- if (result == EDMA3_DRV_SOK)\r
- {\r
- /* PaRAM Set Freed */\r
- edma3DrvChBoundRes[drvObject->phyCtrllerInstId][channelId].paRAMId = -1;\r
-\r
- /* Free the TCC */\r
- resObj.type = EDMA3_RM_RES_TCC;\r
- resObj.resId = tcc;\r
- result = EDMA3_RM_freeResource(drvInst->resMgrInstance,\r
- (EDMA3_RM_ResDesc *)&resObj);\r
- }\r
-\r
- if (result == EDMA3_DRV_SOK)\r
- {\r
- /* TCC Freed. */\r
- edma3DrvChBoundRes[drvObject->phyCtrllerInstId][channelId].tcc = 0;\r
-\r
- /* Now free the DMA/QDMA Channel in the end. */\r
- if (chType == EDMA3_DRV_CHANNEL_TYPE_QDMA)\r
- {\r
- resObj.type = EDMA3_RM_RES_QDMA_CHANNEL;\r
- resObj.resId = (channelId - EDMA3_DRV_QDMA_CH_MIN_VAL);\r
- result = EDMA3_RM_freeResource(drvInst->resMgrInstance,\r
- (EDMA3_RM_ResDesc *)&resObj);\r
- }\r
- else\r
- {\r
- resObj.type = EDMA3_RM_RES_DMA_CHANNEL;\r
- resObj.resId = channelId;\r
- result = EDMA3_RM_freeResource(drvInst->resMgrInstance,\r
- (EDMA3_RM_ResDesc *)&resObj);\r
- }\r
- }\r
- }\r
- }\r
- }\r
-\r
-\r
-#ifdef EDMA3_INSTRUMENTATION_ENABLED\r
- EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",\r
- EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,\r
- EDMA3_DVT_dCOUNTER,\r
- EDMA3_DVT_dNONE,\r
- EDMA3_DVT_dNONE));\r
-#endif /* EDMA3_INSTRUMENTATION_ENABLED */\r
-\r
- return result;\r
- }\r
-\r
-\r
-/**\r
- * \brief Disables the DMA Channel by clearing the Event Enable Register and \r
- * clears Error Register & Secondary Event Register for a specific DMA channel.\r
- *\r
- * This API clears the Event Enable register, Event Miss register and Secondary\r
- * Event register for a specific DMA channel. It also clears the CC Error \r
- * register.\r
- *\r
- * \param hEdma [IN] Handle to the EDMA Driver Instance.\r
- * \param channelId [IN] DMA Channel needs to be cleaned.\r
- *\r
- * \return EDMA3_DRV_SOK or EDMA3_DRV Error code\r
- *\r
- * \note This function is re-entrant for unique channelId values. It is non-\r
- * re-entrant for same channelId value.\r
- */\r
-EDMA3_DRV_Result EDMA3_DRV_clearErrorBits (EDMA3_DRV_Handle hEdma,\r
- unsigned int channelId)\r
-{\r
- EDMA3_DRV_Result result = EDMA3_DRV_SOK;\r
- EDMA3_DRV_Instance *drvInst = NULL;\r
- EDMA3_DRV_Object *drvObject = NULL;\r
- volatile EDMA3_CCRL_Regs *globalRegs = NULL;\r
- unsigned int count;\r
- unsigned int value = 0;\r
-\r
-#ifdef EDMA3_INSTRUMENTATION_ENABLED\r
- EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",\r
- EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,\r
- EDMA3_DVT_dCOUNTER,\r
- EDMA3_DVT_dNONE,\r
- EDMA3_DVT_dNONE));\r
-#endif /* EDMA3_INSTRUMENTATION_ENABLED */\r
-\r
- /* If parameter checking is enabled... */\r
-#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE\r
- if (hEdma == NULL)\r
- {\r
- result = EDMA3_DRV_E_INVALID_PARAM;\r
- }\r
-#endif\r
-\r
- /* Check if the parameters are OK. */\r
- if (EDMA3_DRV_SOK == result)\r
- {\r
- drvInst = (EDMA3_DRV_Instance *)hEdma;\r
- drvObject = drvInst->pDrvObjectHandle;\r
-\r
- if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL))\r
- {\r
- result = EDMA3_DRV_E_INVALID_PARAM;\r
- }\r
- else\r
- {\r
- /* If parameter checking is enabled... */\r
-#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE\r
- if (channelId > EDMA3_DRV_DMA_CH_MAX_VAL)\r
- {\r
- result = EDMA3_DRV_E_INVALID_PARAM;\r
- }\r
-#endif\r
-\r
- /* Check if the parameters are OK. */\r
- if (EDMA3_DRV_SOK == result)\r
- {\r
- globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);\r
-\r
-#ifdef EDMA3_DRV_DEBUG\r
- EDMA3_DRV_PRINTF("EMR =%l\r\n", globalRegs->EMR);\r
-#endif\r
- if(channelId < 32u)\r
- {\r
- /* Disables the DMA channels */\r
- drvInst->shadowRegs->EECR = (1u << channelId);\r
- /* Write to EMCR to clear the corresponding EMR bit */\r
- globalRegs->EMCR = (1u << channelId);\r
- /* Clears the SER */\r
- drvInst->shadowRegs->SECR = (1u << channelId);\r
- }\r
- else\r
- {\r
-#ifdef EDMA3_DRV_DEBUG\r
- EDMA3_DRV_PRINTF("EMRH =%l\r\n", globalRegs->EMRH);\r
-#endif\r
- /* Disables the DMA channels */\r
- drvInst->shadowRegs->EECRH = (1u << (channelId - 32u));\r
- /* Write to EMCR to clear the corresponding EMR bit */\r
- globalRegs->EMCRH = (1u << (channelId - 32u));\r
- /* Clears the SER */\r
- drvInst->shadowRegs->SECRH = (1u << (channelId - 32u));\r
- }\r
-\r
- /* Clear the global CC Error Register */\r
- for (count = 0; count < drvObject->gblCfgParams.numEvtQueue; count++)\r
- {\r
- value |= (1u << count);\r
- }\r
-\r
- globalRegs->CCERRCLR = (EDMA3_CCRL_CCERR_TCCERR_MASK | value);\r
- }\r
- }\r
- }\r
-\r
-#ifdef EDMA3_INSTRUMENTATION_ENABLED\r
- EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",\r
- EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,\r
- EDMA3_DVT_dCOUNTER,\r
- EDMA3_DVT_dNONE,\r
- EDMA3_DVT_dNONE));\r
-#endif /* EDMA3_INSTRUMENTATION_ENABLED */\r
-\r
- return result;\r
- }\r
-\r
-\r
-/**\r
- * \brief Set a particular OPT field in the PaRAM set associated with the\r
- * logical channel 'lCh'.\r
- *\r
- * This API can be used to set various optional parameters for an EDMA3\r
- * transfer. Like enable/disable completion interrupts, enable/disable chaining,\r
- * setting the transfer mode (A/AB Sync), setting the FIFO width etc.\r
- *\r
- * \param hEdma [IN] Handle to the EDMA Driver Instance.\r
- * \param lCh [IN] Logical Channel, bound to which\r
- * PaRAM set OPT field needs to be set.\r
- * \param optField [IN] The particular field of OPT Word\r
- * that needs setting\r
- * \param newOptFieldVal [IN] The new OPT field value\r
- *\r
- * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code\r
- *\r
- * \note This function is re-entrant for unique lCh values. It is non-\r
- * re-entrant for same lCh value.\r
- */\r
-EDMA3_DRV_Result EDMA3_DRV_setOptField (EDMA3_DRV_Handle hEdma,\r
- unsigned int lCh,\r
- EDMA3_DRV_OptField optField,\r
- unsigned int newOptFieldVal)\r
- {\r
- EDMA3_DRV_Result result = EDMA3_DRV_SOK;\r
- EDMA3_DRV_Instance *drvInst = NULL;\r
- EDMA3_DRV_Object *drvObject = NULL;\r
- unsigned int newOptVal = 0;\r
- unsigned int oldOptVal = 0;\r
- int paRAMId = 0;\r
- volatile EDMA3_CCRL_Regs *globalRegs = NULL;\r
-\r
-#ifdef EDMA3_INSTRUMENTATION_ENABLED\r
- EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",\r
- EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,\r
- EDMA3_DVT_dCOUNTER,\r
- EDMA3_DVT_dNONE,\r
- EDMA3_DVT_dNONE));\r
-#endif /* EDMA3_INSTRUMENTATION_ENABLED */\r
-\r
- /* If parameter checking is enabled... */\r
-#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE\r
- if (((lCh > EDMA3_DRV_LOG_CH_MAX_VAL) || (hEdma == NULL))\r
- || ((optField < EDMA3_DRV_OPT_FIELD_SAM)\r
- || (optField > EDMA3_DRV_OPT_FIELD_ITCCHEN)))\r
- {\r
- result = EDMA3_DRV_E_INVALID_PARAM;\r
- }\r
-#endif\r
-\r
- /* Check if the parameters are OK. */\r
- if (EDMA3_DRV_SOK == result)\r
- {\r
- drvInst = (EDMA3_DRV_Instance *)hEdma;\r
- drvObject = drvInst->pDrvObjectHandle;\r
-\r
- if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL))\r
- {\r
- result = EDMA3_DRV_E_INVALID_PARAM;\r
- }\r
- else\r
- {\r
- paRAMId = edma3DrvChBoundRes[drvObject->phyCtrllerInstId][lCh].paRAMId;\r
- globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);\r
-\r
- if ((paRAMId < 0) || (paRAMId >= drvObject->gblCfgParams.numPaRAMSets))\r
- {\r
- result = EDMA3_DRV_E_INVALID_PARAM;\r
- }\r
-\r
- if (result == EDMA3_DRV_SOK)\r
- {\r
- oldOptVal = (unsigned int)(*(&globalRegs->PARAMENTRY [paRAMId].OPT));\r
-\r
- switch (optField)\r
- {\r
- case EDMA3_DRV_OPT_FIELD_SAM :\r
- newOptVal = (oldOptVal & EDMA3_DRV_OPT_SAM_CLR_MASK)\r
- |\r
- (EDMA3_DRV_OPT_SAM_SET_MASK(newOptFieldVal));\r
- break;\r
- case EDMA3_DRV_OPT_FIELD_DAM :\r
- newOptVal = (oldOptVal & EDMA3_DRV_OPT_DAM_CLR_MASK)\r
- |\r
- (EDMA3_DRV_OPT_DAM_SET_MASK(newOptFieldVal));\r
- break;\r
- case EDMA3_DRV_OPT_FIELD_SYNCDIM :\r
- newOptVal = (oldOptVal & EDMA3_DRV_OPT_SYNCDIM_CLR_MASK)\r
- |\r
- (EDMA3_DRV_OPT_SYNCDIM_SET_MASK(newOptFieldVal));\r
- break;\r
- case EDMA3_DRV_OPT_FIELD_STATIC :\r
- newOptVal = (oldOptVal & EDMA3_DRV_OPT_STATIC_CLR_MASK)\r
- |\r
- (EDMA3_DRV_OPT_STATIC_SET_MASK(newOptFieldVal));\r
- break;\r
- case EDMA3_DRV_OPT_FIELD_FWID :\r
- newOptVal = (oldOptVal & EDMA3_DRV_OPT_FWID_CLR_MASK)\r
- |\r
- (EDMA3_DRV_OPT_FWID_SET_MASK(newOptFieldVal));\r
- break;\r
- case EDMA3_DRV_OPT_FIELD_TCCMODE :\r
- newOptVal = (oldOptVal & EDMA3_DRV_OPT_TCCMODE_CLR_MASK)\r
- |\r
- (EDMA3_DRV_OPT_TCCMODE_SET_MASK(newOptFieldVal));\r
- break;\r
- case EDMA3_DRV_OPT_FIELD_TCC :\r
- newOptVal = (oldOptVal & EDMA3_DRV_OPT_TCC_CLR_MASK)\r
- |\r
- (EDMA3_DRV_OPT_TCC_SET_MASK(newOptFieldVal));\r
- break;\r
- case EDMA3_DRV_OPT_FIELD_TCINTEN :\r
- newOptVal = (oldOptVal & EDMA3_DRV_OPT_TCINTEN_CLR_MASK)\r
- |\r
- (EDMA3_DRV_OPT_TCINTEN_SET_MASK(newOptFieldVal));\r
- break;\r
- case EDMA3_DRV_OPT_FIELD_ITCINTEN :\r
- newOptVal = (oldOptVal & EDMA3_DRV_OPT_ITCINTEN_CLR_MASK)\r
- |\r
- (EDMA3_DRV_OPT_ITCINTEN_SET_MASK(newOptFieldVal));\r
- break;\r
- case EDMA3_DRV_OPT_FIELD_TCCHEN :\r
- newOptVal = (oldOptVal & EDMA3_DRV_OPT_TCCHEN_CLR_MASK)\r
- |\r
- (EDMA3_DRV_OPT_TCCHEN_SET_MASK(newOptFieldVal));\r
- break;\r
- case EDMA3_DRV_OPT_FIELD_ITCCHEN :\r
- newOptVal = (oldOptVal & EDMA3_DRV_OPT_ITCCHEN_CLR_MASK)\r
- |\r
- (EDMA3_DRV_OPT_ITCCHEN_SET_MASK(newOptFieldVal));\r
- break;\r
- default:\r
- break;\r
- }\r
-\r
- *(&globalRegs->PARAMENTRY[paRAMId].OPT) = newOptVal;\r
- }\r
- }\r
- }\r
-\r
-#ifdef EDMA3_INSTRUMENTATION_ENABLED\r
- EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",\r
- EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,\r
- EDMA3_DVT_dCOUNTER,\r
- EDMA3_DVT_dNONE,\r
- EDMA3_DVT_dNONE));\r
-#endif /* EDMA3_INSTRUMENTATION_ENABLED */\r
-\r
- return result;\r
- }\r
-\r
-\r
-/**\r
- * \brief Get a particular OPT field in the PaRAM set associated with the\r
- * logical channel 'lCh'.\r
- *\r
- * This API can be used to read various optional parameters for an EDMA3\r
- * transfer. Like enable/disable completion interrupts, enable/disable chaining,\r
- * setting the transfer mode (A/AB Sync), setting the FIFO width etc.\r
- *\r
- * \param hEdma [IN] Handle to the EDMA Driver Instance.\r
- * \param lCh [IN] Logical Channel, bound to which\r
- * PaRAM set OPT field is required.\r
- * \param optField [IN] The particular field of OPT Word\r
- * that is needed\r
- * \param optFieldVal [IN/OUT] Value of the OPT field\r
- *\r
- * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code\r
- *\r
- * \note This function is re-entrant.\r
- */\r
-EDMA3_DRV_Result EDMA3_DRV_getOptField (EDMA3_DRV_Handle hEdma,\r
- unsigned int lCh,\r
- EDMA3_DRV_OptField optField,\r
- unsigned int *optFieldVal)\r
- {\r
- EDMA3_DRV_Result result = EDMA3_DRV_SOK;\r
- EDMA3_DRV_Instance *drvInst = NULL;\r
- EDMA3_DRV_Object *drvObject = NULL;\r
- unsigned int optVal = 0;\r
- int paRAMId = 0;\r
- volatile EDMA3_CCRL_Regs *globalRegs = NULL;\r
-\r
-#ifdef EDMA3_INSTRUMENTATION_ENABLED\r
- EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",\r
- EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,\r
- EDMA3_DVT_dCOUNTER,\r
- EDMA3_DVT_dNONE,\r
- EDMA3_DVT_dNONE));\r
-#endif /* EDMA3_INSTRUMENTATION_ENABLED */\r
-\r
- /* If parameter checking is enabled... */\r
-#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE\r
- if (((lCh > EDMA3_DRV_LOG_CH_MAX_VAL)\r
- || ((hEdma == NULL) || (optFieldVal == NULL)))\r
- || ((optField < EDMA3_DRV_OPT_FIELD_SAM)\r
- || (optField > EDMA3_DRV_OPT_FIELD_ITCCHEN)))\r
- {\r
- result = EDMA3_DRV_E_INVALID_PARAM;\r
- }\r
-#endif\r
-\r
- /* Check if the parameters are OK. */\r
- if (EDMA3_DRV_SOK == result)\r
- {\r
- drvInst = (EDMA3_DRV_Instance *)hEdma;\r
- drvObject = drvInst->pDrvObjectHandle;\r
-\r
- if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL))\r
- {\r
- result = EDMA3_DRV_E_INVALID_PARAM;\r
- }\r
- else\r
- {\r
- paRAMId = edma3DrvChBoundRes[drvObject->phyCtrllerInstId][lCh].paRAMId;\r
- globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);\r
-\r
- if ((paRAMId < 0) || (paRAMId >= drvObject->gblCfgParams.numPaRAMSets))\r
- {\r
- result = EDMA3_DRV_E_INVALID_PARAM;\r
- }\r
-\r
- if (result == EDMA3_DRV_SOK)\r
- {\r
- optVal = (unsigned int)(*(&globalRegs->PARAMENTRY [paRAMId].OPT));\r
-\r
- switch (optField)\r
- {\r
- case EDMA3_DRV_OPT_FIELD_SAM :\r
- *optFieldVal = EDMA3_DRV_OPT_SAM_GET_MASK(optVal);\r
- break;\r
- case EDMA3_DRV_OPT_FIELD_DAM :\r
- *optFieldVal = EDMA3_DRV_OPT_DAM_GET_MASK(optVal);\r
- break;\r
- case EDMA3_DRV_OPT_FIELD_SYNCDIM :\r
- *optFieldVal = EDMA3_DRV_OPT_SYNCDIM_GET_MASK(optVal);\r
- break;\r
- case EDMA3_DRV_OPT_FIELD_STATIC :\r
- *optFieldVal = EDMA3_DRV_OPT_STATIC_GET_MASK(optVal);\r
- break;\r
- case EDMA3_DRV_OPT_FIELD_FWID :\r
- *optFieldVal = EDMA3_DRV_OPT_FWID_GET_MASK(optVal);\r
- break;\r
- case EDMA3_DRV_OPT_FIELD_TCCMODE :\r
- *optFieldVal = EDMA3_DRV_OPT_TCCMODE_GET_MASK(optVal);\r
- break;\r
- case EDMA3_DRV_OPT_FIELD_TCC :\r
- *optFieldVal = EDMA3_DRV_OPT_TCC_GET_MASK(optVal);\r
- break;\r
- case EDMA3_DRV_OPT_FIELD_TCINTEN :\r
- *optFieldVal = EDMA3_DRV_OPT_TCINTEN_GET_MASK(optVal);\r
- break;\r
- case EDMA3_DRV_OPT_FIELD_ITCINTEN :\r
- *optFieldVal = EDMA3_DRV_OPT_ITCINTEN_GET_MASK(optVal);\r
- break;\r
- case EDMA3_DRV_OPT_FIELD_TCCHEN :\r
- *optFieldVal = EDMA3_DRV_OPT_TCCHEN_GET_MASK(optVal);\r
- break;\r
- case EDMA3_DRV_OPT_FIELD_ITCCHEN :\r
- *optFieldVal = EDMA3_DRV_OPT_ITCCHEN_GET_MASK(optVal);\r
- break;\r
- default:\r
- break;\r
- }\r
- }\r
- }\r
- }\r
-\r
-#ifdef EDMA3_INSTRUMENTATION_ENABLED\r
- EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",\r
- EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,\r
- EDMA3_DVT_dCOUNTER,\r
- EDMA3_DVT_dNONE,\r
- EDMA3_DVT_dNONE));\r
-#endif /* EDMA3_INSTRUMENTATION_ENABLED */\r
-\r
- return result;\r
- }\r
-\r
-\r
-\r
-/**\r
- * \brief DMA source parameters setup\r
- *\r
- * It is used to program the source address, source side addressing mode\r
- * (INCR or FIFO) and the FIFO width in case the addressing mode is FIFO.\r
- *\r
- * In FIFO Addressing mode, memory location must be 32 bytes aligned.\r
- *\r
- * \param hEdma [IN] Handle to the EDMA Driver Instance\r
- * \param lCh [IN] Logical Channel for which the source parameters\r
- * are to be configured\r
- * \param srcAddr [IN] Source address\r
- * \param addrMode [IN] Address mode [FIFO or Increment]\r
- * \param fifoWidth [IN] Width of FIFO (Valid only if addrMode is FIFO)\r
- * -# 0 - 8 bit\r
- * -# 1 - 16 bit\r
- * -# 2 - 32 bit\r
- * -# 3 - 64 bit\r
- * -# 4 - 128 bit\r
- * -# 5 - 256 bit\r
- *\r
- * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code\r
- *\r
- * \note This function is re-entrant for unique lCh values. It is non-\r
- * re-entrant for same lCh value.\r
- */\r
-EDMA3_DRV_Result EDMA3_DRV_setSrcParams (EDMA3_DRV_Handle hEdma,\r
- unsigned int lCh,\r
- unsigned int srcAddr,\r
- EDMA3_DRV_AddrMode addrMode,\r
- EDMA3_DRV_FifoWidth fifoWidth)\r
- {\r
- EDMA3_DRV_Result result = EDMA3_DRV_SOK;\r
- unsigned int opt = 0;\r
- EDMA3_DRV_Instance *drvInst = NULL;\r
- EDMA3_DRV_Object *drvObject = NULL;\r
- int paRAMId = 0;\r
- volatile EDMA3_CCRL_Regs *globalRegs = NULL;\r
- unsigned int mappedEvtQ = 0;\r
- unsigned int defaultBurstSize = 0;\r
-\r
-#ifdef EDMA3_INSTRUMENTATION_ENABLED\r
- EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",\r
- EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,\r
- EDMA3_DVT_dCOUNTER,\r
- EDMA3_DVT_dNONE,\r
- EDMA3_DVT_dNONE));\r
-#endif /* EDMA3_INSTRUMENTATION_ENABLED */\r
-\r
- /* If parameter checking is enabled... */\r
-#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE\r
- if ((((lCh > EDMA3_DRV_LOG_CH_MAX_VAL) || (hEdma == NULL))\r
- || ((addrMode < EDMA3_DRV_ADDR_MODE_INCR) || (addrMode > EDMA3_DRV_ADDR_MODE_FIFO)))\r
- || ((fifoWidth < EDMA3_DRV_W8BIT) || (fifoWidth > EDMA3_DRV_W256BIT)))\r
- {\r
- result = EDMA3_DRV_E_INVALID_PARAM;\r
- }\r
-\r
- /** In FIFO Addressing mode, memory location must be 32 bytes aligned */\r
- if ((addrMode == EDMA3_DRV_ADDR_MODE_FIFO)\r
- && ((srcAddr & 0x1Fu) != NULL))\r
- {\r
- /** Memory is not 32 bytes aligned */\r
- result = EDMA3_DRV_E_ADDRESS_NOT_ALIGNED;\r
- }\r
-#endif\r
-\r
- /* Check if the parameters are OK. */\r
- if (EDMA3_DRV_SOK == result)\r
- {\r
- drvInst = (EDMA3_DRV_Instance *)hEdma;\r
- drvObject = drvInst->pDrvObjectHandle;\r
-\r
- if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL))\r
- {\r
- result = EDMA3_DRV_E_INVALID_PARAM;\r
- }\r
- else\r
- {\r
- paRAMId = edma3DrvChBoundRes[drvObject->phyCtrllerInstId][lCh].paRAMId;\r
- globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);\r
-\r
- if ((paRAMId < 0) || (paRAMId >= drvObject->gblCfgParams.numPaRAMSets))\r
- {\r
- result = EDMA3_DRV_E_INVALID_PARAM;\r
- }\r
-\r
- if (result == EDMA3_DRV_SOK)\r
- {\r
- /**\r
- * If request is for FIFO mode, check whether the FIFO size\r
- * is supported by the Transfer Controller which will be used for\r
- * this transfer or not.\r
- */\r
- if (addrMode == EDMA3_DRV_ADDR_MODE_FIFO)\r
- {\r
- if (lCh <= EDMA3_DRV_DMA_CH_MAX_VAL)\r
- {\r
- mappedEvtQ = ((globalRegs->DMAQNUM[lCh >> 3u])\r
- & (~(EDMA3_DRV_DMAQNUM_CLR_MASK(lCh))))\r
- >> ((lCh%8u)*4u);\r
- }\r
- else\r
- {\r
- if ((lCh >= EDMA3_DRV_QDMA_CH_MIN_VAL)\r
- &&(lCh <= EDMA3_DRV_QDMA_CH_MAX_VAL))\r
- {\r
- mappedEvtQ = ((globalRegs->QDMAQNUM)\r
- & (~(EDMA3_DRV_QDMAQNUM_CLR_MASK(lCh -EDMA3_DRV_QDMA_CH_MIN_VAL))))\r
- >> (lCh*4u);\r
- }\r
- }\r
-\r
- /**\r
- * mappedEvtQ contains the event queue and hence the TC which will\r
- * process this transfer request. Check whether this TC supports the\r
- * FIFO size or not.\r
- */\r
- defaultBurstSize = 1u << fifoWidth;\r
- if (defaultBurstSize > drvObject->gblCfgParams.tcDefaultBurstSize[mappedEvtQ])\r
- {\r
- result = EDMA3_DRV_E_FIFO_WIDTH_NOT_SUPPORTED;\r
- }\r
- }\r
-\r
- if (EDMA3_DRV_SOK == result)\r
- {\r
- /* Set Src Address */\r
- *((&globalRegs->PARAMENTRY[paRAMId].OPT) +\r
- (unsigned int)EDMA3_DRV_PARAM_ENTRY_SRC) = srcAddr;\r
-\r
- opt = (unsigned int)(*(&globalRegs->PARAMENTRY [paRAMId].OPT));\r
-\r
- /* Set SAM */\r
- opt &= EDMA3_DRV_OPT_SAM_CLR_MASK;\r
- opt |= EDMA3_DRV_OPT_SAM_SET_MASK(addrMode);\r
- /* Set FIFO Width */\r
- opt &= EDMA3_DRV_OPT_FWID_CLR_MASK;\r
- opt |= EDMA3_DRV_OPT_FWID_SET_MASK(fifoWidth);\r
-\r
- /* Set the OPT */\r
- *(&globalRegs->PARAMENTRY[paRAMId].OPT) = opt;\r
- }\r
- }\r
- }\r
- }\r
-\r
-#ifdef EDMA3_INSTRUMENTATION_ENABLED\r
- EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",\r
- EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,\r
- EDMA3_DVT_dCOUNTER,\r
- EDMA3_DVT_dNONE,\r
- EDMA3_DVT_dNONE));\r
-#endif /* EDMA3_INSTRUMENTATION_ENABLED */\r
-\r
- return result;\r
- }\r
-\r
-\r
-\r
-/**\r
- * \brief DMA Destination parameters setup\r
- *\r
- * It is used to program the destination address, destination side addressing\r
- * mode (INCR or FIFO) and the FIFO width in case the addressing mode is FIFO.\r
- *\r
- * In FIFO Addressing mode, memory location must be 32 bytes aligned.\r
- *\r
- * \param hEdma [IN] Handle to the EDMA Driver Instance\r
- * \param lCh [IN] Logical Channel for which the destination\r
- * parameters are to be configured\r
- * \param destAddr [IN] Destination address\r
- * \param addrMode [IN] Address mode [FIFO or Increment]\r
- * \param fifoWidth [IN] Width of FIFO (Valid only if addrMode is FIFO)\r
- * -# 0 - 8 bit\r
- * -# 1 - 16 bit\r
- * -# 2 - 32 bit\r
- * -# 3 - 64 bit\r
- * -# 4 - 128 bit\r
- * -# 5 - 256 bit\r
- *\r
- * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code\r
- *\r
- * \note This function is re-entrant for unique lCh values. It is non-\r
- * re-entrant for same lCh value.\r
- */\r
-EDMA3_DRV_Result EDMA3_DRV_setDestParams (EDMA3_DRV_Handle hEdma,\r
- unsigned int lCh,\r
- unsigned int destAddr,\r
- EDMA3_DRV_AddrMode addrMode,\r
- EDMA3_DRV_FifoWidth fifoWidth)\r
- {\r
- EDMA3_DRV_Result result = EDMA3_DRV_SOK;\r
- unsigned int opt = 0;\r
- EDMA3_DRV_Instance *drvInst = NULL;\r
- EDMA3_DRV_Object *drvObject = NULL;\r
- int paRAMId = 0;\r
- volatile EDMA3_CCRL_Regs *globalRegs = NULL;\r
- unsigned int mappedEvtQ = 0;\r
- unsigned int defaultBurstSize = 0;\r
-\r
-#ifdef EDMA3_INSTRUMENTATION_ENABLED\r
- EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",\r
- EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,\r
- EDMA3_DVT_dCOUNTER,\r
- EDMA3_DVT_dNONE,\r
- EDMA3_DVT_dNONE));\r
-#endif /* EDMA3_INSTRUMENTATION_ENABLED */\r
-\r
- /* If parameter checking is enabled... */\r
-#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE\r
- if ((((lCh > EDMA3_DRV_LOG_CH_MAX_VAL) || (hEdma == NULL))\r
- || ((addrMode < EDMA3_DRV_ADDR_MODE_INCR) || (addrMode > EDMA3_DRV_ADDR_MODE_FIFO)))\r
- || ((fifoWidth < EDMA3_DRV_W8BIT) || (fifoWidth > EDMA3_DRV_W256BIT)))\r
- {\r
- result = EDMA3_DRV_E_INVALID_PARAM;\r
- }\r
-\r
- /** In FIFO Addressing mode, memory location must be 32 bytes aligned */\r
- if ((addrMode == EDMA3_DRV_ADDR_MODE_FIFO)\r
- && ((destAddr & 0x1Fu)!=NULL))\r
- {\r
- /** Memory is not 32 bytes aligned */\r
- result = EDMA3_DRV_E_ADDRESS_NOT_ALIGNED;\r
- }\r
-#endif\r
-\r
- /* Check if the parameters are OK. */\r
- if (EDMA3_DRV_SOK == result)\r
- {\r
- drvInst = (EDMA3_DRV_Instance *)hEdma;\r
- drvObject = drvInst->pDrvObjectHandle;\r
-\r
- if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL))\r
- {\r
- result = EDMA3_DRV_E_INVALID_PARAM;\r
- }\r
- else\r
- {\r
- paRAMId = edma3DrvChBoundRes[drvObject->phyCtrllerInstId][lCh].paRAMId;\r
- globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);\r
-\r
- if ((paRAMId < 0) || (paRAMId >= drvObject->gblCfgParams.numPaRAMSets))\r
- {\r
- result = EDMA3_DRV_E_INVALID_PARAM;\r
- }\r
-\r
- if (result == EDMA3_DRV_SOK)\r
- {\r
- /**\r
- * If request is for FIFO mode, check whether the FIFO size\r
- * is supported by the Transfer Controller which will be used for\r
- * this transfer or not.\r
- */\r
- if (addrMode == EDMA3_DRV_ADDR_MODE_FIFO)\r
- {\r
- if (lCh <= EDMA3_DRV_DMA_CH_MAX_VAL)\r
- {\r
- mappedEvtQ = ((globalRegs->DMAQNUM[lCh >> 3u])\r
- & (~(EDMA3_DRV_DMAQNUM_CLR_MASK(lCh))))\r
- >> ((lCh%8u)*4u);\r
- }\r
- else\r
- {\r
- if ((lCh >= EDMA3_DRV_QDMA_CH_MIN_VAL)\r
- &&(lCh <= EDMA3_DRV_QDMA_CH_MAX_VAL))\r
- {\r
- mappedEvtQ = ((globalRegs->QDMAQNUM)\r
- & (~(EDMA3_DRV_QDMAQNUM_CLR_MASK(lCh -EDMA3_DRV_QDMA_CH_MIN_VAL))))\r
- >> (lCh*4u);\r
- }\r
- }\r
-\r
- /**\r
- * mappedEvtQ contains the event queue and hence the TC which will\r
- * process this transfer request. Check whether this TC supports the\r
- * FIFO size or not.\r
- */\r
- defaultBurstSize = 1u << fifoWidth;\r
- if (defaultBurstSize > drvObject->gblCfgParams.tcDefaultBurstSize[mappedEvtQ])\r
- {\r
- result = EDMA3_DRV_E_FIFO_WIDTH_NOT_SUPPORTED;\r
- }\r
- }\r
-\r
- if (EDMA3_DRV_SOK == result)\r
- {\r
- /* Set the Dest address */\r
- *((&globalRegs->PARAMENTRY[paRAMId].OPT) +\r
- (unsigned int)EDMA3_DRV_PARAM_ENTRY_DST) = destAddr;\r
-\r
- opt = (unsigned int)(*(&globalRegs->PARAMENTRY [paRAMId].OPT));\r
-\r
- /* Set DAM */\r
- opt &= EDMA3_DRV_OPT_DAM_CLR_MASK;\r
- opt |= EDMA3_DRV_OPT_DAM_SET_MASK(addrMode);\r
- /* Set FIFO Width */\r
- opt &= EDMA3_DRV_OPT_FWID_CLR_MASK;\r
- opt |= EDMA3_DRV_OPT_FWID_SET_MASK(fifoWidth);\r
-\r
- /* Set the OPT */\r
- *(&globalRegs->PARAMENTRY[paRAMId].OPT) = opt;\r
- }\r
- }\r
- }\r
- }\r
-\r
-#ifdef EDMA3_INSTRUMENTATION_ENABLED\r
- EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",\r
- EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,\r
- EDMA3_DVT_dCOUNTER,\r
- EDMA3_DVT_dNONE,\r
- EDMA3_DVT_dNONE));\r
-#endif /* EDMA3_INSTRUMENTATION_ENABLED */\r
-\r
- return result;\r
- }\r
-\r
-\r
-\r
-/**\r
- * \brief DMA source index setup\r
- *\r
- * It is used to program the source B index and source C index.\r
- *\r
- * SRCBIDX is a 16-bit signed value (2s complement) used for source address\r
- * modification between each array in the 2nd dimension. Valid values for\r
- * SRCBIDX are between -32768 and 32767. It provides a byte address offset\r
- * from the beginning of the source array to the beginning of the next source\r
- * array. It applies to both A-synchronized and AB-synchronized transfers.\r
- *\r
- * SRCCIDX is a 16-bit signed value (2s complement) used for source address\r
- * modification in the 3rd dimension. Valid values for SRCCIDX are between\r
- * -32768 and 32767. It provides a byte address offset from the beginning of\r
- * the current array (pointed to by SRC address) to the beginning of the first\r
- * source array in the next frame. It applies to both A-synchronized and\r
- * AB-synchronized transfers. Note that when SRCCIDX is applied, the current\r
- * array in an A-synchronized transfer is the last array in the frame, while\r
- * the current array in an AB-synchronized transfer is the first array in the\r
- * frame.\r
- *\r
- * \param hEdma [IN] Handle to the EDMA Driver Instance\r
- * \param lCh [IN] Logical Channel for which source\r
- * indices are to be configured\r
- * \param srcBIdx [IN] Source B index\r
- * \param srcCIdx [IN] Source C index\r
- *\r
- * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code\r
- *\r
- * \note This function is re-entrant for unique lCh values. It is non-\r
- * re-entrant for same lCh value.\r
- */\r
-EDMA3_DRV_Result EDMA3_DRV_setSrcIndex (EDMA3_DRV_Handle hEdma,\r
- unsigned int lCh,\r
- int srcBIdx, int srcCIdx)\r
- {\r
- EDMA3_DRV_Result result = EDMA3_DRV_SOK;\r
- unsigned int srcDstBidx;\r
- unsigned int srcDstCidx;\r
- EDMA3_DRV_Instance *drvInst = NULL;\r
- EDMA3_DRV_Object *drvObject = NULL;\r
- int paRAMId = 0;\r
- volatile EDMA3_CCRL_Regs *globalRegs = NULL;\r
-\r
-#ifdef EDMA3_INSTRUMENTATION_ENABLED\r
- EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",\r
- EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,\r
- EDMA3_DVT_dCOUNTER,\r
- EDMA3_DVT_dNONE,\r
- EDMA3_DVT_dNONE));\r
-#endif /* EDMA3_INSTRUMENTATION_ENABLED */\r
-\r
- /* If parameter checking is enabled... */\r
-#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE\r
- if ((lCh > EDMA3_DRV_LOG_CH_MAX_VAL) || (hEdma == NULL))\r
- {\r
- result = EDMA3_DRV_E_INVALID_PARAM;\r
- }\r
-\r
- if (((srcBIdx > EDMA3_DRV_SRCBIDX_MAX_VAL)\r
- || (srcBIdx < EDMA3_DRV_SRCBIDX_MIN_VAL))\r
- || ((srcCIdx > EDMA3_DRV_SRCCIDX_MAX_VAL)\r
- || (srcCIdx < EDMA3_DRV_SRCCIDX_MIN_VAL)))\r
- {\r
- result = EDMA3_DRV_E_INVALID_PARAM;\r
- }\r
-#endif\r
-\r
- /* Check if the parameters are OK. */\r
- if (EDMA3_DRV_SOK == result)\r
- {\r
- drvInst = (EDMA3_DRV_Instance *)hEdma;\r
- drvObject = drvInst->pDrvObjectHandle;\r
-\r
- if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL))\r
- {\r
- result = EDMA3_DRV_E_INVALID_PARAM;\r
- }\r
- else\r
- {\r
- paRAMId = edma3DrvChBoundRes[drvObject->phyCtrllerInstId][lCh].paRAMId;\r
- globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);\r
-\r
- if ((paRAMId < 0) || (paRAMId >= drvObject->gblCfgParams.numPaRAMSets))\r
- {\r
- result = EDMA3_DRV_E_INVALID_PARAM;\r
- }\r
-\r
- if (result == EDMA3_DRV_SOK)\r
- {\r
- /* Get SrcDestBidx PaRAM Set entry */\r
- srcDstBidx = (unsigned int)(*((&globalRegs->PARAMENTRY [paRAMId].OPT) +\r
- (unsigned int)EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX));\r
-\r
- srcDstBidx &= 0xFFFF0000u;\r
- /* Update it */\r
- srcDstBidx |= (unsigned int)(srcBIdx & 0xFFFF);\r
-\r
- /* Store it back */\r
- *((&globalRegs->PARAMENTRY[paRAMId].OPT)\r
- + (unsigned int)EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX) = srcDstBidx;\r
-\r
- /* Get SrcDestCidx PaRAM Set entry */\r
- srcDstCidx = (unsigned int)(*((&globalRegs->PARAMENTRY [paRAMId].OPT) +\r
- (unsigned int)EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX));\r
-\r
- srcDstCidx &= 0xFFFF0000u;\r
- /* Update it */\r
- srcDstCidx |= (unsigned int)(srcCIdx & 0xFFFF);\r
-\r
- /* Store it back */\r
- *((&globalRegs->PARAMENTRY[paRAMId].OPT)\r
- + (unsigned int)EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX) = srcDstCidx;\r
- }\r
- }\r
- }\r
-\r
-#ifdef EDMA3_INSTRUMENTATION_ENABLED\r
- EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",\r
- EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,\r
- EDMA3_DVT_dCOUNTER,\r
- EDMA3_DVT_dNONE,\r
- EDMA3_DVT_dNONE));\r
-#endif /* EDMA3_INSTRUMENTATION_ENABLED */\r
-\r
- return result;\r
- }\r
-\r
-\r
-\r
-/**\r
- * \brief DMA destination index setup\r
- *\r
- * It is used to program the destination B index and destination C index.\r
- *\r
- * DSTBIDX is a 16-bit signed value (2s complement) used for destination\r
- * address modification between each array in the 2nd dimension. Valid values\r
- * for DSTBIDX are between -32768 and 32767. It provides a byte address offset\r
- * from the beginning of the destination array to the beginning of the next\r
- * destination array within the current frame. It applies to both\r
- * A-synchronized and AB-synchronized transfers.\r
- *\r
- * DSTCIDX is a 16-bit signed value (2s complement) used for destination address\r
- * modification in the 3rd dimension. Valid values are between -32768 and 32767.\r
- * It provides a byte address offset from the beginning of the current array\r
- * (pointed to by DST address) to the beginning of the first destination array\r
- * TR in the next frame. It applies to both A-synchronized and AB-synchronized\r
- * transfers. Note that when DSTCIDX is applied, the current array in an\r
- * A-synchronized transfer is the last array in the frame, while the current\r
- * array in a AB-synchronized transfer is the first array in the frame\r
- *\r
- * \param hEdma [IN] Handle to the EDMA Driver Instance\r
- * \param lCh [IN] Logical Channel for which dest\r
- * indices are to be configured\r
- * \param destBIdx [IN] Destination B index\r
- * \param destCIdx [IN] Destination C index\r
- *\r
- * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code\r
- *\r
- * \note This function is re-entrant for unique lCh values. It is non-\r
- * re-entrant for same lCh value.\r
- */\r
-EDMA3_DRV_Result EDMA3_DRV_setDestIndex (EDMA3_DRV_Handle hEdma, unsigned int lCh,\r
- int destBIdx, int destCIdx)\r
- {\r
- EDMA3_DRV_Result result = EDMA3_DRV_SOK;\r
- unsigned int srcDstBidx;\r
- unsigned int srcDstCidx;\r
- EDMA3_DRV_Instance *drvInst = NULL;\r
- EDMA3_DRV_Object *drvObject = NULL;\r
- int paRAMId = 0;\r
- volatile EDMA3_CCRL_Regs *globalRegs = NULL;\r
-\r
-#ifdef EDMA3_INSTRUMENTATION_ENABLED\r
- EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",\r
- EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,\r
- EDMA3_DVT_dCOUNTER,\r
- EDMA3_DVT_dNONE,\r
- EDMA3_DVT_dNONE));\r
-#endif /* EDMA3_INSTRUMENTATION_ENABLED */\r
-\r
- /* If parameter checking is enabled... */\r
-#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE\r
- if ((lCh > EDMA3_DRV_LOG_CH_MAX_VAL) || (hEdma == NULL))\r
- {\r
- result = EDMA3_DRV_E_INVALID_PARAM;\r
- }\r
-\r
- if (((destBIdx > EDMA3_DRV_DSTBIDX_MAX_VAL)\r
- || (destBIdx < EDMA3_DRV_DSTBIDX_MIN_VAL))\r
- || ((destCIdx > EDMA3_DRV_DSTCIDX_MAX_VAL)\r
- || (destCIdx < EDMA3_DRV_DSTCIDX_MIN_VAL)))\r
- {\r
- result = EDMA3_DRV_E_INVALID_PARAM;\r
- }\r
-#endif\r
-\r
- /* Check if the parameters are OK. */\r
- if (EDMA3_DRV_SOK == result)\r
- {\r
- drvInst = (EDMA3_DRV_Instance *)hEdma;\r
- drvObject = drvInst->pDrvObjectHandle;\r
-\r
- if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL))\r
- {\r
- result = EDMA3_DRV_E_INVALID_PARAM;\r
- }\r
- else\r
- {\r
- paRAMId = edma3DrvChBoundRes[drvObject->phyCtrllerInstId][lCh].paRAMId;\r
- globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);\r
-\r
- if ((paRAMId < 0) || (paRAMId >= drvObject->gblCfgParams.numPaRAMSets))\r
- {\r
- result = EDMA3_DRV_E_INVALID_PARAM;\r
- }\r
-\r
- if (result == EDMA3_DRV_SOK)\r
- {\r
- /* Get SrcDestBidx PaRAM Set entry */\r
- srcDstBidx = (unsigned int)(*((&globalRegs->PARAMENTRY [paRAMId].OPT) +\r
- (unsigned int)EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX));\r
-\r
- srcDstBidx &= 0xFFFFu;\r
- /* Update it */\r
- srcDstBidx |= (unsigned int)((destBIdx & 0xFFFF) << 16u);\r
-\r
- /* Store it back */\r
- *((&globalRegs->PARAMENTRY[paRAMId].OPT)\r
- + (unsigned int)EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX) = srcDstBidx;\r
-\r
- /* Get SrcDestCidx PaRAM Set entry */\r
- srcDstCidx = (unsigned int)(*((&globalRegs->PARAMENTRY [paRAMId].OPT) +\r
- (unsigned int)EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX));\r
-\r
- srcDstCidx &= 0xFFFFu;\r
- /* Update it */\r
- srcDstCidx |= (unsigned int)((destCIdx & 0xFFFF) << 16u);\r
-\r
- /* Store it back */\r
- *((&globalRegs->PARAMENTRY[paRAMId].OPT)\r
- + (unsigned int)EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX) = srcDstCidx;\r
- }\r
- }\r
- }\r
-\r
-#ifdef EDMA3_INSTRUMENTATION_ENABLED\r
- EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",\r
- EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,\r
- EDMA3_DVT_dCOUNTER,\r
- EDMA3_DVT_dNONE,\r
- EDMA3_DVT_dNONE));\r
-#endif /* EDMA3_INSTRUMENTATION_ENABLED */\r
-\r
- return result;\r
- }\r
-\r
-\r
-/**\r
- * \brief DMA transfer parameters setup\r
- *\r
- * It is used to specify the various counts (ACNT, BCNT and CCNT), B count\r
- * reload and the synchronization type\r
- *\r
- * ACNT represents the number of bytes within the 1st dimension of a transfer.\r
- * ACNT is a 16-bit unsigned value with valid values between 0 and 65535.\r
- * Therefore, the maximum number of bytes in an array is 65535 bytes (64K - 1\r
- * bytes). ACNT must be greater than or equal to 1 for a TR to be submitted to\r
- * EDMA3 Transfer Controller.\r
- * An ACNT equal to 0 is considered either a null or dummy transfer. A dummy or\r
- * null transfer generates a completion code depending on the settings of the\r
- * completion bit fields in OPT.\r
-\r
- * BCNT is a 16-bit unsigned value that specifies the number of arrays of length\r
- * ACNT. For normal operation, valid values for BCNT are between 1 and 65535.\r
- * Therefore, the maximum number of arrays in a frame is 65535 (64K - 1 arrays).\r
- * A BCNT equal to 0 is considered either a null or dummy transfer. A dummy or\r
- * null transfer generates a completion code depending on the settings of the\r
- * completion bit fields in OPT.\r
- *\r
- * CCNT is a 16-bit unsigned value that specifies the number of frames in a\r
- * block. Valid values for CCNT are between 1 and 65535. Therefore, the maximum\r
- * number of frames in a block is 65535 (64K - 1 frames). A CCNT equal to 0 is\r
- * considered either a null or dummy transfer. A dummy or null transfer\r
- * generates a completion code depending on the settings of the completion bit\r
- * fields in OPT. A CCNT value of 0 is considered either a null or dummy\r
- * transfer.\r
- *\r
- * BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the\r
- * last array in the 2nd dimension is transferred. This field is only used for\r
- * A-synchronized transfers. In this case, the EDMA3CC decrements the BCNT\r
- * value by 1 on each TR submission. When BCNT (conceptually) reaches 0, the\r
- * EDMA3CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT\r
- * value.\r
- * For AB-synchronized transfers, the EDMA3CC submits the BCNT in the TR and the\r
- * EDMA3TC decrements BCNT appropriately. For AB-synchronized transfers,\r
- * BCNTRLD is not used.\r
-\r
- * \param hEdma [IN] Handle to the EDMA Driver Instance\r
- * \param lCh [IN] Logical Channel for which transfer\r
- * parameters are to be configured\r
- * \param aCnt [IN] Count for 1st Dimension.\r
- * \param bCnt [IN] Count for 2nd Dimension.\r
- * \param cCnt [IN] Count for 3rd Dimension.\r
- * \param bCntReload [IN] Reload value for bCnt.\r
- * \param syncType [IN] Transfer synchronization dimension\r
- * 0: A-synchronized. Each event triggers\r
- * the transfer of a single array of\r
- * ACNT bytes.\r
- * 1: AB-synchronized. Each event triggers\r
- * the transfer of BCNT arrays of ACNT\r
- * bytes.\r
- *\r
- * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code\r
- *\r
- * \note This function is re-entrant for unique lCh values. It is non-\r
- * re-entrant for same lCh value.\r
- */\r
-EDMA3_DRV_Result EDMA3_DRV_setTransferParams (EDMA3_DRV_Handle hEdma,\r
- unsigned int lCh, unsigned int aCnt, unsigned int bCnt, unsigned int cCnt,\r
- unsigned int bCntReload, EDMA3_DRV_SyncType syncType)\r
- {\r
- EDMA3_DRV_Result result = EDMA3_DRV_SOK;\r
- unsigned int abCnt = 0;\r
- unsigned int linkBCntReld = 0;\r
- unsigned int opt = 0;\r
- EDMA3_DRV_Instance *drvInst = NULL;\r
- EDMA3_DRV_Object *drvObject = NULL;\r
- int paRAMId = 0;\r
- volatile EDMA3_CCRL_Regs *globalRegs = NULL;\r
-\r
-#ifdef EDMA3_INSTRUMENTATION_ENABLED\r
- EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",\r
- EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,\r
- EDMA3_DVT_dCOUNTER,\r
- EDMA3_DVT_dNONE,\r
- EDMA3_DVT_dNONE));\r
-#endif /* EDMA3_INSTRUMENTATION_ENABLED */\r
-\r
- /* If parameter checking is enabled... */\r
-#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE\r
- if ((lCh > EDMA3_DRV_LOG_CH_MAX_VAL) || (hEdma == NULL))\r
- {\r
- result = EDMA3_DRV_E_INVALID_PARAM;\r
- }\r
-\r
- if ((((aCnt > EDMA3_DRV_ACNT_MAX_VAL)\r
- || (bCnt > EDMA3_DRV_BCNT_MAX_VAL))\r
- || ((cCnt > EDMA3_DRV_CCNT_MAX_VAL)\r
- || (bCntReload > EDMA3_DRV_BCNTRELD_MAX_VAL)))\r
- || ((syncType < EDMA3_DRV_SYNC_A) || (syncType > EDMA3_DRV_SYNC_AB)))\r
- {\r
- result = EDMA3_DRV_E_INVALID_PARAM;\r
- }\r
-#endif\r
-\r
- /* Check if the parameters are OK. */\r
- if (EDMA3_DRV_SOK == result)\r
- {\r
- drvInst = (EDMA3_DRV_Instance *)hEdma;\r
- drvObject = drvInst->pDrvObjectHandle;\r
-\r
- if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL))\r
- {\r
- result = EDMA3_DRV_E_INVALID_PARAM;\r
- }\r
- else\r
- {\r
- abCnt = aCnt | ((bCnt&0xFFFFu) << 16u);\r
- paRAMId = edma3DrvChBoundRes[drvObject->phyCtrllerInstId][lCh].paRAMId;\r
- globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);\r
-\r
- if ((paRAMId < 0) || (paRAMId >= drvObject->gblCfgParams.numPaRAMSets))\r
- {\r
- result = EDMA3_DRV_E_INVALID_PARAM;\r
- }\r
-\r
- if (result == EDMA3_DRV_SOK)\r
- {\r
- /* Set aCnt and bCnt */\r
- *((&globalRegs->PARAMENTRY[paRAMId].OPT)\r
- + (unsigned int)EDMA3_DRV_PARAM_ENTRY_ACNT_BCNT) = abCnt;\r
-\r
- /* Set cCnt */\r
- *((&globalRegs->PARAMENTRY[paRAMId].OPT)\r
- + (unsigned int)EDMA3_DRV_PARAM_ENTRY_CCNT) = cCnt;\r
-\r
-\r
- linkBCntReld = (unsigned int)(*((&globalRegs->PARAMENTRY [paRAMId].OPT) +\r
- (unsigned int)EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD));\r
-\r
- linkBCntReld |= ((bCntReload & 0xFFFFu) << 16u);\r
-\r
- /* Set bCntReload */\r
- *((&globalRegs->PARAMENTRY[paRAMId].OPT)\r
- + (unsigned int)EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD) = linkBCntReld;\r
-\r
- opt = (unsigned int)(*(&globalRegs->PARAMENTRY [paRAMId].OPT));\r
-\r
- /* Set Sync Type */\r
- opt &= EDMA3_DRV_OPT_SYNCDIM_CLR_MASK;\r
- opt |= EDMA3_DRV_OPT_SYNCDIM_SET_MASK(syncType);\r
-\r
- *(&globalRegs->PARAMENTRY[paRAMId].OPT) = opt;\r
- }\r
- }\r
- }\r
-\r
-#ifdef EDMA3_INSTRUMENTATION_ENABLED\r
- EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",\r
- EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,\r
- EDMA3_DVT_dCOUNTER,\r
- EDMA3_DVT_dNONE,\r
- EDMA3_DVT_dNONE));\r
-#endif /* EDMA3_INSTRUMENTATION_ENABLED */\r
-\r
- return result;\r
- }\r
-\r
-\r
-/**\r
- * \brief Start EDMA transfer on the specified channel.\r
- *\r
- * There are multiple ways to trigger an EDMA3 transfer. The triggering mode\r
- * option allows choosing from the available triggering modes: Event,\r
- * Manual or QDMA.\r
- *\r
- * In event triggered, a peripheral or an externally generated event triggers\r
- * the transfer. This API clears the Event and Event Miss Register and then\r
- * enables the DMA channel by writing to the EESR.\r
- *\r
- * In manual triggered mode, CPU manually triggers a transfer by writing a 1\r
- * in the Event Set Register (ESR/ESRH). This API writes to the ESR/ESRH to\r
- * start the transfer.\r
- *\r
- * In QDMA triggered mode, a QDMA transfer is triggered when a CPU (or other\r
- * EDMA3 programmer) writes to the trigger word of the QDMA channel PaRAM set\r
- * (auto-triggered) or when the EDMA3CC performs a link update on a PaRAM set\r
- * that has been mapped to a QDMA channel (link triggered). This API enables\r
- * the QDMA channel by writing to the QEESR register.\r
- *\r
- * \param hEdma [IN] Handle to the EDMA Driver Instance\r
- * \param lCh [IN] Channel on which transfer has to be started\r
- * \param trigMode [IN] Mode of triggering start of transfer (Manual,\r
- * QDMA or Event)\r
- *\r
- * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code\r
- *\r
- * \note This function is re-entrant for unique lCh values. It is non-\r
- * re-entrant for same lCh value.\r
- */\r
-EDMA3_DRV_Result EDMA3_DRV_enableTransfer (EDMA3_DRV_Handle hEdma,\r
- unsigned int lCh,\r
- EDMA3_DRV_TrigMode trigMode)\r
- {\r
- EDMA3_DRV_Instance *drvInst = NULL;\r
- EDMA3_DRV_Object *drvObject = NULL;\r
- EDMA3_DRV_Result result = EDMA3_DRV_SOK;\r
- volatile EDMA3_CCRL_Regs *globalRegs = NULL;\r
-\r
-#ifdef EDMA3_INSTRUMENTATION_ENABLED\r
- EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",\r
- EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,\r
- EDMA3_DVT_dCOUNTER,\r
- EDMA3_DVT_dNONE,\r
- EDMA3_DVT_dNONE));\r
-#endif /* EDMA3_INSTRUMENTATION_ENABLED */\r
-\r
- /* If parameter checking is enabled... */\r
-#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE\r
- if ((lCh > EDMA3_DRV_LOG_CH_MAX_VAL) || (hEdma == NULL))\r
- {\r
- result = EDMA3_DRV_E_INVALID_PARAM;\r
- }\r
-\r
- /* Trigger type is Manual */\r
- if ((EDMA3_DRV_TRIG_MODE_MANUAL == trigMode)\r
- && (lCh > EDMA3_DRV_DMA_CH_MAX_VAL))\r
- {\r
- /* Channel Id lies outside DMA channel range */\r
- result = EDMA3_DRV_E_INVALID_PARAM;\r
- }\r
-\r
- /* Trigger type is QDMA */\r
- if ((EDMA3_DRV_TRIG_MODE_QDMA == trigMode)\r
- && ((lCh < EDMA3_DRV_QDMA_CH_MIN_VAL)\r
- || (lCh > EDMA3_DRV_QDMA_CH_MAX_VAL)))\r
- {\r
- /* Channel Id lies outside QDMA channel range */\r
- result = EDMA3_DRV_E_INVALID_PARAM;\r
- }\r
-#endif\r
-\r
- /* Check if the parameters are OK. */\r
- if (EDMA3_DRV_SOK == result)\r
- {\r
- drvInst = (EDMA3_DRV_Instance *)hEdma;\r
- drvObject = drvInst->pDrvObjectHandle;\r
-\r
- if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL))\r
- {\r
- result = EDMA3_DRV_E_INVALID_PARAM;\r
- }\r
- else\r
- {\r
- globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);\r
-\r
- switch (trigMode)\r
- {\r
- case EDMA3_DRV_TRIG_MODE_MANUAL :\r
- {\r
- if (lCh < 32u)\r
- {\r
- drvInst->shadowRegs->ESR = (1UL << lCh);\r
- }\r
- else\r
- {\r
- drvInst->shadowRegs->ESRH = (1UL << (lCh-32u));\r
- }\r
- edma3DrvChBoundRes[drvObject->phyCtrllerInstId][lCh].trigMode = EDMA3_DRV_TRIG_MODE_MANUAL;\r
- }\r
- break;\r
-\r
- case EDMA3_DRV_TRIG_MODE_QDMA :\r
- {\r
- drvInst->shadowRegs->QEESR = (1u<<(lCh - EDMA3_DRV_QDMA_CH_MIN_VAL));\r
- edma3DrvChBoundRes[drvObject->phyCtrllerInstId][lCh].trigMode = EDMA3_DRV_TRIG_MODE_QDMA;\r
- }\r
- break;\r
-\r
- case EDMA3_DRV_TRIG_MODE_EVENT :\r
- {\r
- /* Trigger type is Event */\r
-/* If parameter checking is enabled... */\r
-#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE\r
- if (((drvObject->gblCfgParams.dmaChannelHwEvtMap [lCh/32u]\r
- & (1u<<(lCh%32u))) == FALSE))\r
- {\r
- /* Channel was not mapped to any Hw Event. */\r
- result = EDMA3_DRV_E_INVALID_PARAM;\r
- }\r
-#endif\r
-\r
- if (EDMA3_DRV_SOK == result)\r
- {\r
- if (lCh < 32u)\r
- {\r
- /*clear SECR to clean any previous NULL request */\r
- drvInst->shadowRegs->SECR = (1UL << lCh);\r
-\r
- /*clear EMCR to clean any previous NULL request */\r
- globalRegs->EMCR = (1UL << lCh);\r
-\r
- drvInst->shadowRegs->EESR = (1UL << lCh);\r
- }\r
- else\r
- {\r
- /*clear SECR to clean any previous NULL request */\r
- drvInst->shadowRegs->SECRH = (1UL << (lCh-32u));\r
-\r
- /*clear EMCR to clean any previous NULL request */\r
- globalRegs->EMCRH = (1UL << (lCh-32u));\r
-\r
- drvInst->shadowRegs->EESRH = (1UL << (lCh-32u));\r
- }\r
-\r
- edma3DrvChBoundRes[drvObject->phyCtrllerInstId][lCh].trigMode = EDMA3_DRV_TRIG_MODE_EVENT;\r
- }\r
- }\r
- break;\r
-\r
- default :\r
- result = EDMA3_DRV_E_INVALID_PARAM;\r
- break;\r
- }\r
- }\r
- }\r
-\r
-#ifdef EDMA3_INSTRUMENTATION_ENABLED\r
- EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",\r
- EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,\r
- EDMA3_DVT_dCOUNTER,\r
- EDMA3_DVT_dNONE,\r
- EDMA3_DVT_dNONE));\r
-#endif /* EDMA3_INSTRUMENTATION_ENABLED */\r
-\r
- return result;\r
- }\r
-\r
-\r
-/**\r
- * \brief Disable DMA transfer on the specified channel\r
- *\r
- * There are multiple ways by which an EDMA3 transfer could be triggered.\r
- * The triggering mode option allows choosing from the available triggering\r
- * modes: Event, Manual or QDMA.\r
- *\r
- * To disable a channel which was previously triggered in manual mode,\r
- * this API clears the Secondary Event Register and Event Miss Register,\r
- * if set, for the specific DMA channel.\r
- *\r
- * To disable a channel which was previously triggered in QDMA mode, this\r
- * API clears the QDMA Event Enable Register, for the specific QDMA channel.\r
- *\r
- * To disable a channel which was previously triggered in event mode, this API\r
- * clears the Event Enable Register, Event Register, Secondary Event Register\r
- * and Event Miss Register, if set, for the specific DMA channel.\r
-\r
- * \param hEdma [IN] Handle to the EDMA Driver Instance\r
- * \param lCh [IN] Channel on which transfer has to be stopped\r
- * \param trigMode [IN] Mode of triggering start of transfer\r
- *\r
- * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code\r
- *\r
- * \note This function is re-entrant for unique lCh values. It is non-\r
- * re-entrant for same lCh value.\r
- */\r
-EDMA3_DRV_Result EDMA3_DRV_disableTransfer (EDMA3_DRV_Handle hEdma,\r
- unsigned int lCh, EDMA3_DRV_TrigMode trigMode)\r
-{\r
- EDMA3_DRV_Result result = EDMA3_DRV_SOK;\r
- EDMA3_DRV_Instance *drvInst = NULL;\r
- EDMA3_DRV_Object *drvObject = NULL;\r
- volatile EDMA3_CCRL_Regs *globalRegs = NULL;\r
-\r
-#ifdef EDMA3_INSTRUMENTATION_ENABLED\r
- EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",\r
- EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,\r
- EDMA3_DVT_dCOUNTER,\r
- EDMA3_DVT_dNONE,\r
- EDMA3_DVT_dNONE));\r
-#endif /* EDMA3_INSTRUMENTATION_ENABLED */\r
-\r
- /* If parameter checking is enabled... */\r
-#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE\r
- if ((lCh > EDMA3_DRV_LOG_CH_MAX_VAL) || (hEdma == NULL))\r
- {\r
- result = EDMA3_DRV_E_INVALID_PARAM;\r
- }\r
-\r
- /* Trigger type is Manual */\r
- if ((EDMA3_DRV_TRIG_MODE_MANUAL == trigMode)\r
- && (lCh > EDMA3_DRV_DMA_CH_MAX_VAL))\r
- {\r
- /* Channel Id lies outside DMA channel range */\r
- result = EDMA3_DRV_E_INVALID_PARAM;\r
- }\r
-\r
- /* Trigger type is QDMA */\r
- if ((EDMA3_DRV_TRIG_MODE_QDMA == trigMode)\r
- && ((lCh < EDMA3_DRV_QDMA_CH_MIN_VAL)\r
- || (lCh > EDMA3_DRV_QDMA_CH_MAX_VAL)))\r
- {\r
- /* Channel Id lies outside QDMA channel range */\r
- result = EDMA3_DRV_E_INVALID_PARAM;\r
- }\r
-#endif\r
-\r
- /* Check if the parameters are OK. */\r
- if (EDMA3_DRV_SOK == result)\r
- {\r
- drvInst = (EDMA3_DRV_Instance *)hEdma;\r
- drvObject = drvInst->pDrvObjectHandle;\r
-\r
- if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL))\r
- {\r
- result = EDMA3_DRV_E_INVALID_PARAM;\r
- }\r
- else\r
- {\r
- globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);\r
-\r
- switch (trigMode)\r
- {\r
- case EDMA3_DRV_TRIG_MODE_MANUAL :\r
- {\r
- if (lCh < 32u)\r
- {\r
- if((drvInst->shadowRegs->SER & (1u<<lCh))!=FALSE)\r
- {\r
- drvInst->shadowRegs->SECR = (1u<<lCh);\r
- }\r
- if((globalRegs->EMR & (1u<<lCh))!=FALSE)\r
- {\r
- globalRegs->EMCR = (1u<<lCh);\r
- }\r
- }\r
- else\r
- {\r
- if((drvInst->shadowRegs->SERH & (1u<<(lCh-32u)))!=FALSE)\r
- {\r
- drvInst->shadowRegs->SECRH = (1u<<(lCh-32u));\r
- }\r
-\r
- if((globalRegs->EMRH & (1u<<(lCh-32u)))!=FALSE)\r
- {\r
- globalRegs->EMCRH = (1u<<(lCh-32u));\r
- }\r
- }\r
- }\r
- break;\r
-\r
- case EDMA3_DRV_TRIG_MODE_QDMA :\r
- {\r
- drvInst->shadowRegs->QEECR = (1u<<(lCh - EDMA3_DRV_QDMA_CH_MIN_VAL));\r
- }\r
- break;\r
-\r
- case EDMA3_DRV_TRIG_MODE_EVENT :\r
- {\r
- /* Trigger type is Event */\r
-/* If parameter checking is enabled... */\r
-#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE\r
- if (((drvObject->gblCfgParams.dmaChannelHwEvtMap [lCh/32u]\r
- & (1u<<(lCh%32u))) == FALSE))\r
- {\r
- /* Channel was not mapped to any Hw Event. */\r
- result = EDMA3_DRV_E_INVALID_PARAM;\r
- }\r
-#endif\r
-\r
- if (EDMA3_DRV_SOK == result)\r
- {\r
- if (lCh < 32u)\r
- {\r
- drvInst->shadowRegs->EECR = (1u << lCh);\r
-\r
- if((drvInst->shadowRegs->ER & (1u<<lCh))!=FALSE)\r
- {\r
- drvInst->shadowRegs->ECR = (1u<<lCh);\r
- }\r
- if((drvInst->shadowRegs->SER & (1u<<lCh))!=FALSE)\r
- {\r
- drvInst->shadowRegs->SECR = (1u<<lCh);\r
- }\r
- if((globalRegs->EMR & (1u<<lCh))!=FALSE)\r
- {\r
- globalRegs->EMCR = (1u<<lCh);\r
- }\r
- }\r
- else\r
- {\r
- drvInst->shadowRegs->EECRH = (1u << (lCh-32u));\r
- if((drvInst->shadowRegs->ERH & (1u<<(lCh-32u)))!=FALSE)\r
- {\r
- drvInst->shadowRegs->ECRH = (1u<<(lCh-32u));\r
- }\r
-\r
- if((drvInst->shadowRegs->SERH & (1u<<(lCh-32u)))!=FALSE)\r
- {\r
- drvInst->shadowRegs->SECRH = (1u<<(lCh-32u));\r
- }\r
-\r
- if((globalRegs->EMRH & (1u<<(lCh-32u)))!=FALSE)\r
- {\r
- globalRegs->EMCRH = (1u<<(lCh-32u));\r
- }\r
- }\r
- }\r
- }\r
- break;\r
-\r
- default :\r
- result = EDMA3_DRV_E_INVALID_PARAM;\r
- break;\r
- }\r
- }\r
- }\r
-\r
-#ifdef EDMA3_INSTRUMENTATION_ENABLED\r
- EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",\r
- EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,\r
- EDMA3_DVT_dCOUNTER,\r
- EDMA3_DVT_dNONE,\r
- EDMA3_DVT_dNONE));\r
-#endif /* EDMA3_INSTRUMENTATION_ENABLED */\r
-\r
- return result;\r
- }\r
-\r
-/**\r
- * \brief Disable the event driven DMA channel or QDMA channel\r
- *\r
- * This API disables the DMA channel (which was previously triggered in event \r
- * mode) by clearing the Event Enable Register; it disables the QDMA channel by\r
- * clearing the QDMA Event Enable Register.\r
- *\r
- * This API should NOT be used for DMA channels which are not mapped to any\r
- * hardware events and are used for memory-to-memory copy based transfers. In \r
- * case of that, this API returns error.\r
- *\r
- * \param hEdma [IN] Handle to the EDMA Driver Instance\r
- * \param lCh [IN] DMA/QDMA Channel which needs to be disabled\r
- * \param trigMode [IN] Mode of triggering start of transfer\r
- *\r
- * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code\r
- *\r
- * \note This function is re-entrant for unique lCh values. It is non-\r
- * re-entrant for same lCh value.\r
- */\r
-EDMA3_DRV_Result EDMA3_DRV_disableLogicalChannel (EDMA3_DRV_Handle hEdma,\r
- unsigned int lCh, EDMA3_DRV_TrigMode trigMode)\r
-{\r
- EDMA3_DRV_Result result = EDMA3_DRV_SOK;\r
- EDMA3_DRV_Instance *drvInst = NULL;\r
- EDMA3_DRV_Object *drvObject = NULL;\r
-\r
-#ifdef EDMA3_INSTRUMENTATION_ENABLED\r
- EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",\r
- EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,\r
- EDMA3_DVT_dCOUNTER,\r
- EDMA3_DVT_dNONE,\r
- EDMA3_DVT_dNONE));\r
-#endif /* EDMA3_INSTRUMENTATION_ENABLED */\r
-\r
- /* If parameter checking is enabled... */\r
-#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE\r
- if ((lCh > EDMA3_DRV_LOG_CH_MAX_VAL) || (hEdma == NULL))\r
- {\r
- result = EDMA3_DRV_E_INVALID_PARAM;\r
- }\r
-\r
- /* Trigger type is Manual */\r
- if (EDMA3_DRV_TRIG_MODE_MANUAL == trigMode)\r
- result = EDMA3_DRV_E_INVALID_PARAM;\r
- \r
- /* Trigger type is QDMA */\r
- if ((EDMA3_DRV_TRIG_MODE_QDMA == trigMode)\r
- && ((lCh < EDMA3_DRV_QDMA_CH_MIN_VAL)\r
- || (lCh > EDMA3_DRV_QDMA_CH_MAX_VAL)))\r
- {\r
- /* Channel Id lies outside QDMA channel range */\r
- result = EDMA3_DRV_E_INVALID_PARAM;\r
- }\r
-#endif\r
-\r
- /* Check if the parameters are OK. */\r
- if (EDMA3_DRV_SOK == result)\r
- {\r
- drvInst = (EDMA3_DRV_Instance *)hEdma;\r
- drvObject = drvInst->pDrvObjectHandle;\r
-\r
- if (drvObject == NULL)\r
- {\r
- result = EDMA3_DRV_E_INVALID_PARAM;\r
- }\r
- else\r
- {\r
- switch (trigMode)\r
- {\r
- case EDMA3_DRV_TRIG_MODE_QDMA:\r
- {\r
- drvInst->shadowRegs->QEECR = (1u<<(lCh - EDMA3_DRV_QDMA_CH_MIN_VAL));\r
- }\r
- break;\r
-\r
- case EDMA3_DRV_TRIG_MODE_EVENT:\r
- {\r
- /* Trigger type is Event */\r
-/* If parameter checking is enabled... */\r
-#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE\r
- if (((drvObject->gblCfgParams.dmaChannelHwEvtMap [lCh/32u]\r
- & (1u<<(lCh%32u))) == FALSE))\r
- {\r
- /* Channel was not mapped to any Hw Event. */\r
- result = EDMA3_DRV_E_INVALID_PARAM;\r
- }\r
-#endif\r
-\r
- if (EDMA3_DRV_SOK == result)\r
- {\r
- if (lCh < 32u)\r
- drvInst->shadowRegs->EECR = (1u << lCh);\r
- else\r
- drvInst->shadowRegs->EECRH = (1u << (lCh-32u));\r
- }\r
- }\r
- break;\r
-\r
- default :\r
- result = EDMA3_DRV_E_INVALID_PARAM;\r
- break;\r
- }\r
- }\r
- }\r
-\r
-#ifdef EDMA3_INSTRUMENTATION_ENABLED\r
- EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",\r
- EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,\r
- EDMA3_DVT_dCOUNTER,\r
- EDMA3_DVT_dNONE,\r
- EDMA3_DVT_dNONE));\r
-#endif /* EDMA3_INSTRUMENTATION_ENABLED */\r
-\r
- return result;\r
- }\r
-\r
-/* Definitions of Local functions - Start */\r
-/** Remove various mappings and do cleanup for DMA/QDMA channels */\r
-static EDMA3_DRV_Result edma3RemoveMapping (EDMA3_DRV_Handle hEdma,\r
- unsigned int channelId)\r
- {\r
- unsigned int intState;\r
- EDMA3_DRV_Instance *drvInst = NULL;\r
- EDMA3_DRV_Object *drvObject = NULL;\r
- EDMA3_DRV_Result result = EDMA3_DRV_SOK;\r
- volatile EDMA3_CCRL_Regs *globalRegs = NULL;\r
- EDMA3_RM_ResDesc channelObj;\r
-\r
- assert ((hEdma != NULL) && (channelId <= EDMA3_DRV_LOG_CH_MAX_VAL));\r
-\r
- drvInst = (EDMA3_DRV_Instance *)hEdma;\r
- drvObject = drvInst->pDrvObjectHandle;\r
-\r
- if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL))\r
- {\r
- result = EDMA3_DRV_E_INVALID_PARAM;\r
- }\r
- else\r
- {\r
- globalRegs = (volatile EDMA3_CCRL_Regs *)\r
- (drvObject->gblCfgParams.globalRegs);\r
-\r
- /**\r
- * Disable any ongoing transfer on the channel, if transfer was\r
- * enabled earlier.\r
- */\r
- if (EDMA3_DRV_TRIG_MODE_NONE !=\r
- edma3DrvChBoundRes[drvObject->phyCtrllerInstId][channelId].trigMode)\r
- {\r
- result = EDMA3_DRV_disableTransfer(hEdma, channelId,\r
- edma3DrvChBoundRes[drvObject->phyCtrllerInstId][channelId].trigMode);\r
- }\r
-\r
- if (result == EDMA3_DRV_SOK)\r
- {\r
- /*\r
- * Unregister the TCC Callback function and disable the interrupts.\r
- */\r
- if (channelId < drvObject->gblCfgParams.numDmaChannels)\r
- {\r
- /* DMA channel */\r
- channelObj.type = EDMA3_RM_RES_DMA_CHANNEL;\r
- channelObj.resId = channelId;\r
- }\r
- else\r
- {\r
- /* QDMA channel */\r
- channelObj.type = EDMA3_RM_RES_QDMA_CHANNEL;\r
- channelObj.resId = channelId - EDMA3_DRV_QDMA_CH_MIN_VAL;\r
- }\r
-\r
- result = EDMA3_RM_unregisterTccCb(drvInst->resMgrInstance,\r
- (EDMA3_RM_ResDesc *)&channelObj);\r
-\r
- if (result == EDMA3_RM_SOK)\r
- {\r
- edma3OsProtectEntry(EDMA3_OS_PROTECT_INTERRUPT, &intState);\r
-\r
- if (channelId <= EDMA3_DRV_DMA_CH_MAX_VAL)\r
- {\r
- /* DMA channel */\r
-#ifndef EDMA3_PROGRAM_QUEUE_NUM_REGISTER_INIT_TIME\r
- /* Remove the channel to Event Queue mapping */\r
- globalRegs->DMAQNUM[channelId >> 3u] &=\r
- EDMA3_DRV_DMAQNUM_CLR_MASK(channelId);\r
-#endif\r
-\r
- /**\r
- * If DMA channel to PaRAM Set mapping exists,\r
- * remove it too.\r
- */\r
- if (TRUE == drvObject->gblCfgParams.dmaChPaRAMMapExists)\r
- {\r
- globalRegs->DCHMAP[channelId] &=\r
- EDMA3_RM_DCH_PARAM_CLR_MASK;\r
- }\r
- }\r
- else\r
- {\r
- /* QDMA channel */\r
-#ifndef EDMA3_PROGRAM_QUEUE_NUM_REGISTER_INIT_TIME\r
- /* Remove the channel to Event Queue mapping */\r
- globalRegs->QDMAQNUM = (globalRegs->QDMAQNUM) &\r
- (EDMA3_DRV_QDMAQNUM_CLR_MASK(channelId-EDMA3_DRV_QDMA_CH_MIN_VAL));\r
-#endif\r
-\r
- /* Remove the channel to PARAM set mapping */\r
- /* Unmap PARAM Set Number for specified channelId */\r
- globalRegs->QCHMAP[channelId-EDMA3_DRV_QDMA_CH_MIN_VAL] &=\r
- EDMA3_RM_QCH_PARAM_CLR_MASK;\r
-\r
- /* Reset the Trigger Word */\r
- globalRegs->QCHMAP[channelId-EDMA3_DRV_QDMA_CH_MIN_VAL] &=\r
- EDMA3_RM_QCH_TRWORD_CLR_MASK;\r
- }\r
-\r
- edma3OsProtectExit(EDMA3_OS_PROTECT_INTERRUPT, intState);\r
- }\r
- }\r
- }\r
-\r
- return result;\r
- }\r
-/* Definitions of Local functions - End */\r
-\r
-/* End of File */\r
+/*
+ * edma3_drv_basic.c
+ *
+ * EDMA3 Driver Basic Interface Implementation. This file contains
+ * beginner-level EDMA3 Driver APIs which are required to:
+ * a) Request/free a DMA, QDMA and Link channel.
+ * b) Program various fields in the PaRAM Set like source/destination
+ * parameters, transfer parameters etc.
+ * c) Enable/disable a transfer.
+ * These APIs are provided to program a DMA/QDMA channel for simple use-cases
+ * and don't expose all the features of EDMA3 hardware. Users who want to go
+ * beyond this and have complete control on the EDMA3 hardware are advised
+ * to refer edma3_drv_adv.c source file.
+ *
+ * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+/* EDMa3 Driver Internal Header Files */
+#include <ti/sdo/edma3/drv/src/edma3.h>
+/* Resource Manager Internal Header Files */
+#include <ti/sdo/edma3/rm/src/edma3resmgr.h>
+
+/* Instrumentation Header File */
+#ifdef EDMA3_INSTRUMENTATION_ENABLED
+#include <ti/sdo/edma3/rm/src/edma3_log.h>
+#endif
+
+/* For assert() */
+/**
+ * Define NDEBUG to ignore assert().
+ * NDEBUG should be defined before including assert.h header file.
+ */
+#include <assert.h>
+
+
+/* Externel Variables */
+/*---------------------------------------------------------------------------*/
+/**
+ * Maximum Resource Manager Instances supported by the EDMA3 Package.
+ */
+extern const uint32_t EDMA3_MAX_RM_INSTANCES;
+
+
+/**
+ * \brief EDMA3 Resource Manager Objects, tied to each EDMA3 HW Controller.
+ *
+ * Typically one RM object will cater to one EDMA3 HW controller
+ * and will have all the global config information.
+ */
+extern EDMA3_RM_Obj resMgrObj[EDMA3_MAX_EDMA3_INSTANCES];
+
+
+/**
+ * \brief Region Specific Configuration structure for
+ * EDMA3 controller, to provide region specific Information.
+ *
+ * This configuration info can also be provided by the user at run-time,
+ * while calling EDMA3_RM_open (). If not provided at run-time,
+ * this info will be taken from the config file "edma3_<PLATFORM_NAME>_cfg.c",
+ * for the specified platform.
+ */
+#ifdef BUILD_C6XDSP
+extern far EDMA3_RM_InstanceInitConfig *ptrInitCfgArray;
+#else
+extern EDMA3_RM_InstanceInitConfig *ptrInitCfgArray;
+#endif
+
+/**
+ * Handles of EDMA3 Resource Manager Instances.
+ *
+ * Used to maintain information of the EDMA3 RM Instances
+ * for each HW controller.
+ * There could be a maximum of EDMA3_MAX_RM_INSTANCES instances per
+ * EDMA3 HW.
+ */
+#ifdef BUILD_C6XDSP
+extern far EDMA3_RM_Instance *ptrRMIArray;
+#else
+extern EDMA3_RM_Instance *ptrRMIArray;
+#endif
+
+/** Local MemSet function */
+extern void edma3MemZero(void *dst, uint32_t len);
+/** Local MemCpy function */
+extern void edma3MemCpy(void *dst, const void *src, uint32_t len);
+
+/**
+ * \brief EDMA3 Driver Objects, tied to each EDMA3 HW Controller.
+ *
+ * Typically one object will cater to one EDMA3 HW controller
+ * and will have all regions' (ARM, DSP etc) specific config information.
+ */
+extern EDMA3_DRV_Object drvObj [EDMA3_MAX_EDMA3_INSTANCES];
+
+
+/**
+ * Handles of EDMA3 Driver Instances.
+ *
+ * Used to maintain information of the EDMA3 Driver Instances for
+ * each region, for each HW controller.
+ * There could be as many Driver Instances as there are shadow
+ * regions. Multiple EDMA3 Driver instances on the same shadow
+ * region are NOT allowed.
+ */
+extern EDMA3_DRV_Instance drvInstance [EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGIONS];
+
+
+/**
+ * \brief Resources bound to a Channel
+ *
+ * When a request for a channel is made, the resources PaRAM Set and TCC
+ * get bound to that channel. This information is needed internally by the
+ * driver when a request is made to free the channel (Since it is the
+ * responsibility of the driver to free up the channel-associated resources
+ * from the Resource Manager layer).
+ */
+extern EDMA3_DRV_ChBoundResources edma3DrvChBoundRes [EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_LOGICAL_CH];
+
+/** Max of DMA Channels */
+extern uint32_t edma3_dma_ch_max_val[EDMA3_MAX_EDMA3_INSTANCES];
+/** Min of Link Channels */
+extern uint32_t edma3_link_ch_min_val[EDMA3_MAX_EDMA3_INSTANCES];
+/** Max of Link Channels */
+extern uint32_t edma3_link_ch_max_val[EDMA3_MAX_EDMA3_INSTANCES];
+/** Min of QDMA Channels */
+extern uint32_t edma3_qdma_ch_min_val[EDMA3_MAX_EDMA3_INSTANCES];
+/** Max of QDMA Channels */
+extern uint32_t edma3_qdma_ch_max_val[EDMA3_MAX_EDMA3_INSTANCES];
+/** Max of Logical Channels */
+extern uint32_t edma3_log_ch_max_val[EDMA3_MAX_EDMA3_INSTANCES];
+
+/* Local functions prototypes */
+/*---------------------------------------------------------------------------*/
+/** Remove various mappings and do cleanup for DMA/QDMA channels */
+static EDMA3_DRV_Result edma3RemoveMapping (EDMA3_DRV_Handle hEdma,
+ uint32_t channelId);
+
+/** @brief Global Variable which describes the EDMA3 LLD Version Information */
+const char edma3LldVersionStr[] = EDMA3_LLD_DRV_VERSION_STR ":" __DATE__ ":" __TIME__;
+/*---------------------------------------------------------------------------*/
+
+EDMA3_DRV_Result EDMA3_DRV_requestChannel (EDMA3_DRV_Handle hEdma,
+ uint32_t *pLCh,
+ uint32_t *pTcc,
+ EDMA3_RM_EventQueue evtQueue,
+ EDMA3_RM_TccCallback tccCb,
+ void *cbData)
+ {
+ EDMA3_RM_ResDesc resObj;
+ EDMA3_RM_ResDesc channelObj;
+ EDMA3_DRV_Result result = EDMA3_DRV_SOK;
+ EDMA3_DRV_Instance *drvInst = NULL;
+ EDMA3_DRV_Object *drvObject = NULL;
+ uint32_t mappedTcc = EDMA3_DRV_CH_NO_TCC_MAP;
+ int32_t paRAMId = (int32_t)EDMA3_RM_RES_ANY;
+ EDMA3_DRV_ChannelType chType = EDMA3_DRV_CHANNEL_TYPE_NONE;
+ volatile EDMA3_CCRL_Regs *globalRegs = NULL;
+ int32_t mappedPaRAMId;
+ uint32_t edma3Id;
+ uint32_t freeDmaQdmaChannel = FALSE;
+ uint32_t mapXbarEvtToChanFlag = FALSE;
+ uint32_t xBarEvtBeforeMap = 0;
+
+#ifdef EDMA3_INSTRUMENTATION_ENABLED
+ EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
+ EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,
+ EDMA3_DVT_dCOUNTER,
+ EDMA3_DVT_dNONE,
+ EDMA3_DVT_dNONE));
+#endif /* EDMA3_INSTRUMENTATION_ENABLED */
+
+
+ /* If parameter checking is enabled... */
+#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
+ if ((pLCh == NULL) || (hEdma == NULL))
+ {
+ result = EDMA3_DRV_E_INVALID_PARAM;
+ }
+#endif
+
+ if (EDMA3_DRV_SOK == result)
+ {
+ drvInst = (EDMA3_DRV_Instance *)hEdma;
+ drvObject = drvInst->pDrvObjectHandle;
+
+ if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL))
+ {
+ result = EDMA3_DRV_E_INVALID_PARAM;
+ }
+ }
+ if (EDMA3_DRV_SOK == result)
+ {
+ if ( drvInst->mapXbarToChan != NULL)
+ {
+ xBarEvtBeforeMap = *pLCh;
+ edma3Id = drvObject->phyCtrllerInstId;
+ if ((xBarEvtBeforeMap > edma3_dma_ch_max_val [edma3Id]) &&
+ (xBarEvtBeforeMap < EDMA3_DRV_DMA_CHANNEL_ANY) &&
+ ((*pLCh) == (*pTcc)))
+ {
+ result = drvInst->mapXbarToChan(xBarEvtBeforeMap,
+ pLCh,
+ &drvInst->drvXbarToEvtMapConfig);
+ if (EDMA3_DRV_SOK == result)
+ {
+ *pTcc = *pLCh;
+ mapXbarEvtToChanFlag = TRUE;
+ }
+ }
+ }
+ }
+
+ if (EDMA3_DRV_SOK == result)
+ {
+ edma3Id = drvObject->phyCtrllerInstId;
+ globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);
+
+ /* Identify the request type and validate the appropriate arguments.
+ * Starting in the order of PaRAM Set availability,
+ * check for a specific DMA channel request first.
+ */
+ if ((*pLCh) <= edma3_dma_ch_max_val [edma3Id])
+ {
+ /* A 'Specific' DMA channel is requested */
+ chType = EDMA3_DRV_CHANNEL_TYPE_DMA;
+ /* Fill the resObj structure as well */
+ resObj.type = EDMA3_RM_RES_DMA_CHANNEL;
+ resObj.resId = *pLCh;
+
+ /* Check the TCC and Event Queue number */
+ if ((evtQueue >= drvObject->gblCfgParams.numEvtQueue)
+ || (pTcc == NULL))
+ {
+ result = EDMA3_DRV_E_INVALID_PARAM;
+ }
+ }
+
+ if ((*pLCh) == EDMA3_DRV_DMA_CHANNEL_ANY)
+ {
+ /* 'Any' DMA channel is requested */
+ chType = EDMA3_DRV_CHANNEL_TYPE_DMA;
+ resObj.type = EDMA3_RM_RES_DMA_CHANNEL;
+ resObj.resId = EDMA3_RM_RES_ANY;
+
+ /* Check the TCC and Event Queue number */
+ if ((evtQueue >= drvObject->gblCfgParams.numEvtQueue)
+ || (pTcc == NULL))
+ {
+ result = EDMA3_DRV_E_INVALID_PARAM;
+ }
+ }
+
+ if (((*pLCh) >= edma3_link_ch_min_val[edma3Id]) &&
+ ((*pLCh) <= edma3_link_ch_max_val[edma3Id]))
+ {
+ /* A 'Specific' Link channel is requested, TCC may or may not be
+ * required.
+ */
+ /* Save the PaRAM Id for future use */
+ paRAMId = *pLCh;
+
+ if (pTcc != NULL)
+ {
+ if (*pTcc < drvObject->gblCfgParams.numTccs)
+ {
+ /* Argument passed as *pTcc is a valid TCC number */
+ chType = EDMA3_DRV_CHANNEL_TYPE_LINK_TCC;
+ resObj.type = EDMA3_RM_RES_PARAM_SET;
+ }
+ else
+ {
+ /* Argument passed as *pTcc is Invalid TCC number */
+ result = EDMA3_DRV_E_INVALID_PARAM;
+ }
+ }
+ else
+ {
+ /* pTcc is NULL, only Link Channel required */
+ chType = EDMA3_DRV_CHANNEL_TYPE_LINK;
+ resObj.type = EDMA3_RM_RES_PARAM_SET;
+ }
+ }
+
+ if ((*pLCh) == EDMA3_DRV_LINK_CHANNEL)
+ {
+ /* 'Any' Link channel is requested, TCC is not required */
+ chType = EDMA3_DRV_CHANNEL_TYPE_LINK;
+ resObj.type = EDMA3_RM_RES_PARAM_SET;
+ }
+
+ if ((*pLCh) == EDMA3_DRV_LINK_CHANNEL_WITH_TCC)
+ {
+ if (pTcc != NULL)
+ {
+ /* 'Any' Link channel is requested, TCC is required */
+ if (*pTcc < drvObject->gblCfgParams.numTccs)
+ {
+ /* Argument passed as *pTcc is a valid TCC number */
+ chType = EDMA3_DRV_CHANNEL_TYPE_LINK_TCC;
+ resObj.type = EDMA3_RM_RES_PARAM_SET;
+ }
+ else
+ {
+ /* Argument passed as *pTcc is Invalid TCC number */
+ result = EDMA3_DRV_E_INVALID_PARAM;
+ }
+ }
+ else
+ {
+ /* pTcc is NULL */
+ result = EDMA3_DRV_E_INVALID_PARAM;
+ }
+ }
+
+ if (((*pLCh) >= EDMA3_DRV_QDMA_CHANNEL_0) &&
+ ((*pLCh) <= EDMA3_DRV_QDMA_CHANNEL_7))
+ {
+ /* A 'Specific' QDMA channel is requested */
+ chType = EDMA3_DRV_CHANNEL_TYPE_QDMA;
+ resObj.type = EDMA3_RM_RES_QDMA_CHANNEL;
+ resObj.resId = *pLCh - EDMA3_DRV_QDMA_CHANNEL_0;
+
+ /* Check the TCC and Event Queue number */
+ if ((evtQueue >= drvObject->gblCfgParams.numEvtQueue)
+ || (pTcc == NULL))
+ {
+ result = EDMA3_DRV_E_INVALID_PARAM;
+ }
+ }
+
+ if ((*pLCh) == EDMA3_DRV_QDMA_CHANNEL_ANY)
+ {
+ /* 'Any' QDMA channel is requested */
+ chType = EDMA3_DRV_CHANNEL_TYPE_QDMA;
+ resObj.type = EDMA3_RM_RES_QDMA_CHANNEL;
+ resObj.resId = EDMA3_RM_RES_ANY;
+
+ /* Check the TCC and Event Queue number */
+ if ((evtQueue >= drvObject->gblCfgParams.numEvtQueue)
+ || (pTcc == NULL))
+ {
+ result = EDMA3_DRV_E_INVALID_PARAM;
+ }
+ }
+
+ if (EDMA3_DRV_CHANNEL_TYPE_NONE == chType)
+ {
+ /* Invalid request */
+ result = EDMA3_DRV_E_INVALID_PARAM;
+ }
+ }
+
+ /* Step 1: Allocate the DMA/QDMA channel first, if required */
+ if (EDMA3_DRV_SOK == result)
+ {
+ switch (chType)
+ {
+ case EDMA3_DRV_CHANNEL_TYPE_DMA:
+ result = EDMA3_RM_allocResource(drvInst->resMgrInstance,
+ (EDMA3_RM_ResDesc *)&resObj);
+ if (result == EDMA3_RM_SOK)
+ {
+ *pLCh = resObj.resId;
+
+ mappedPaRAMId = drvObject->gblCfgParams.dmaChannelPaRAMMap[*pLCh];
+ if (mappedPaRAMId != (int32_t)EDMA3_DRV_CH_NO_PARAM_MAP)
+ {
+ paRAMId = mappedPaRAMId;
+ }
+
+ if (*pTcc == EDMA3_DRV_TCC_ANY)
+ {
+ mappedTcc = drvObject->gblCfgParams.dmaChannelTccMap[*pLCh];
+ if (mappedTcc == EDMA3_DRV_CH_NO_TCC_MAP)
+ {
+ mappedTcc = EDMA3_RM_RES_ANY;
+ }
+ }
+ else
+ {
+ mappedTcc = *pTcc;
+ }
+
+ /* Save the Resource Type/ID for TCC registeration */
+ channelObj.type = EDMA3_RM_RES_DMA_CHANNEL;
+ channelObj.resId = *pLCh;
+
+ /* Free DMA channel in case the function fails in future */
+ freeDmaQdmaChannel = TRUE;
+ }
+ else
+ {
+ result = EDMA3_DRV_E_DMA_CHANNEL_UNAVAIL;
+ }
+
+ break;
+
+ case EDMA3_DRV_CHANNEL_TYPE_QDMA:
+ result = EDMA3_RM_allocResource(drvInst->resMgrInstance,
+ (EDMA3_RM_ResDesc *)&resObj);
+ if (result == EDMA3_DRV_SOK)
+ {
+ (*pLCh) = resObj.resId + edma3_qdma_ch_min_val[edma3Id];
+
+ if (*pTcc == EDMA3_DRV_TCC_ANY)
+ {
+ mappedTcc = EDMA3_RM_RES_ANY;
+ }
+ else
+ {
+ mappedTcc = *pTcc;
+ }
+
+ /* Save the Resource Type/ID for TCC registeration */
+ channelObj.type = EDMA3_RM_RES_QDMA_CHANNEL;
+ channelObj.resId = resObj.resId;
+
+ /* Free DMA channel in case the function fails in future */
+ freeDmaQdmaChannel = TRUE;
+ }
+ else
+ {
+ result = EDMA3_DRV_E_QDMA_CHANNEL_UNAVAIL;
+ }
+ break;
+
+ default:
+ break;
+ }
+ }
+
+ /* Step 2: Allocate the PaRAM Set */
+ if (EDMA3_DRV_SOK == result)
+ {
+ resObj.type = EDMA3_RM_RES_PARAM_SET;
+ resObj.resId = (uint32_t)paRAMId;
+ result = EDMA3_RM_allocResource(drvInst->resMgrInstance, (EDMA3_RM_ResDesc *)&resObj);
+ }
+
+ if (EDMA3_DRV_SOK == result)
+ {
+ paRAMId = (int32_t)resObj.resId;
+
+ if (chType == EDMA3_DRV_CHANNEL_TYPE_LINK)
+ {
+ /* Link channel number should be same as the PaRAM Set */
+ *pLCh = resObj.resId;
+ edma3DrvChBoundRes[edma3Id][*pLCh].paRAMId = paRAMId;
+ edma3DrvChBoundRes[edma3Id][*pLCh].trigMode = EDMA3_DRV_TRIG_MODE_NONE;
+ }
+
+ if (chType == EDMA3_DRV_CHANNEL_TYPE_LINK_TCC)
+ {
+ /* Link channel number should be same as the PaRAM Set */
+ *pLCh = resObj.resId;
+ edma3DrvChBoundRes[edma3Id][*pLCh].paRAMId = paRAMId;
+ edma3DrvChBoundRes[edma3Id][*pLCh].trigMode = EDMA3_DRV_TRIG_MODE_NONE;
+
+ /* save the tcc now */
+ edma3DrvChBoundRes[edma3Id][*pLCh].tcc = *pTcc;
+
+ /* Set TCC in ParamSet.OPT field */
+ globalRegs->PARAMENTRY [paRAMId].OPT &= EDMA3_DRV_OPT_TCC_CLR_MASK;
+ globalRegs->PARAMENTRY [paRAMId].OPT |= EDMA3_DRV_OPT_TCC_SET_MASK(*pTcc);
+ }
+ }
+ else
+ {
+ /* PaRAM allocation failed, free the previously allocated DMA/QDMA
+ * channel, if required
+ */
+ if (((chType == EDMA3_DRV_CHANNEL_TYPE_DMA)
+ || (chType == EDMA3_DRV_CHANNEL_TYPE_QDMA)) &&
+ (TRUE == freeDmaQdmaChannel))
+ {
+ EDMA3_RM_freeResource(drvInst->resMgrInstance, (EDMA3_RM_ResDesc *)&channelObj);
+ }
+ }
+
+ /* Step 3: Allocate TCC only for DMA/QDMA channels */
+ if ((EDMA3_DRV_SOK == result) &&
+ ((chType == EDMA3_DRV_CHANNEL_TYPE_DMA) || (chType == EDMA3_DRV_CHANNEL_TYPE_QDMA)))
+ {
+ resObj.type = EDMA3_RM_RES_TCC;
+ resObj.resId = mappedTcc;
+ result = EDMA3_RM_allocResource(drvInst->resMgrInstance, (EDMA3_RM_ResDesc *)&resObj);
+
+ if (EDMA3_DRV_SOK == result)
+ {
+ *pTcc = resObj.resId;
+
+ /* Save TCC and PaRAM set */
+ edma3DrvChBoundRes[edma3Id][*pLCh].tcc = *pTcc;
+ edma3DrvChBoundRes[edma3Id][*pLCh].paRAMId = paRAMId;
+
+ switch (chType)
+ {
+ case EDMA3_DRV_CHANNEL_TYPE_DMA:
+ {
+ /* Step 4: Register the callback function, if required */
+ if (NULL != tccCb)
+ {
+ result = EDMA3_RM_registerTccCb (drvInst->resMgrInstance,
+ (EDMA3_RM_ResDesc *)&channelObj,
+ *pTcc, tccCb, cbData);
+ }
+ if (result != EDMA3_DRV_SOK)
+ {
+ EDMA3_DRV_freeChannel (hEdma, *pLCh);
+ result = EDMA3_DRV_E_TCC_REGISTER_FAIL;
+ }
+ else
+ {
+#ifndef EDMA3_PROGRAM_QUEUE_NUM_REGISTER_INIT_TIME
+ uint32_t intState = 0;
+ edma3OsProtectEntry(edma3Id, (int32_t)EDMA3_OS_PROTECT_INTERRUPT,
+ &intState);
+ /* Step 5: Associate DMA Channel to Event Queue */
+ globalRegs->DMAQNUM[(*pLCh) >> 3U] &= EDMA3_DRV_DMAQNUM_CLR_MASK(*pLCh);
+ globalRegs->DMAQNUM[(*pLCh) >> 3U] |= EDMA3_DRV_DMAQNUM_SET_MASK((*pLCh), evtQueue);
+
+ edma3OsProtectExit(edma3Id, (int32_t)EDMA3_OS_PROTECT_INTERRUPT,
+ intState);
+#endif
+
+ /* Step 6: Map PaRAM Set to DMA Channel */
+ if (TRUE == drvObject->gblCfgParams.dmaChPaRAMMapExists)
+ {
+ globalRegs->DCHMAP[*pLCh] &= EDMA3_DRV_DCH_PARAM_CLR_MASK;
+ globalRegs->DCHMAP[*pLCh] |= EDMA3_DRV_DCH_PARAM_SET_MASK((uint32_t)paRAMId);
+ }
+
+ /* Step 7: Set TCC in ParamSet.OPT field */
+ globalRegs->PARAMENTRY [paRAMId].OPT &= EDMA3_DRV_OPT_TCC_CLR_MASK;
+ globalRegs->PARAMENTRY [paRAMId].OPT |= EDMA3_DRV_OPT_TCC_SET_MASK(*pTcc);
+
+ edma3DrvChBoundRes[edma3Id][*pLCh].trigMode = EDMA3_DRV_TRIG_MODE_NONE;
+ }
+ }
+ break;
+
+ case EDMA3_DRV_CHANNEL_TYPE_QDMA:
+ {
+ uint32_t qdmaChannel = channelObj.resId;
+
+ /* Step 4: Register the callback function, if required */
+ if (NULL != tccCb)
+ {
+ result = EDMA3_RM_registerTccCb (drvInst->resMgrInstance,
+ (EDMA3_RM_ResDesc *)&channelObj,
+ *pTcc, tccCb, cbData);
+ }
+ if (result != EDMA3_DRV_SOK)
+ {
+ EDMA3_DRV_freeChannel (hEdma, *pLCh);
+ result = EDMA3_DRV_E_TCC_REGISTER_FAIL;
+ }
+ else
+ {
+#ifndef EDMA3_PROGRAM_QUEUE_NUM_REGISTER_INIT_TIME
+ uint32_t intState = 0;
+ edma3OsProtectEntry(edma3Id, (int32_t)EDMA3_OS_PROTECT_INTERRUPT,
+ &intState);
+ /* Step 5: Associate QDMA Channel to Event Queue */
+ globalRegs->QDMAQNUM &= EDMA3_DRV_QDMAQNUM_CLR_MASK(qdmaChannel);
+ globalRegs->QDMAQNUM |= EDMA3_DRV_QDMAQNUM_SET_MASK(qdmaChannel, evtQueue);
+
+ edma3OsProtectExit(edma3Id, (int32_t)EDMA3_OS_PROTECT_INTERRUPT,
+ intState);
+#endif
+
+ /* Step 6: Map PaRAM Set to DMA Channel and set the Default Trigger Word */
+ globalRegs->QCHMAP[qdmaChannel] &= EDMA3_DRV_QCH_PARAM_TRWORD_CLR_MASK;
+ globalRegs->QCHMAP[qdmaChannel] |= EDMA3_DRV_QCH_PARAM_SET_MASK((uint32_t)paRAMId);
+ globalRegs->QCHMAP[qdmaChannel] |= EDMA3_DRV_QCH_TRWORD_SET_MASK(EDMA3_RM_QDMA_TRIG_DEFAULT);
+
+ /* Step 7: Set TCC in ParamSet.OPT field */
+ globalRegs->PARAMENTRY [paRAMId].OPT &= EDMA3_DRV_OPT_TCC_CLR_MASK;
+ globalRegs->PARAMENTRY [paRAMId].OPT |= EDMA3_DRV_OPT_TCC_SET_MASK(*pTcc);
+
+ edma3DrvChBoundRes[edma3Id][*pLCh].trigMode = EDMA3_DRV_TRIG_MODE_QDMA;
+
+ /* Step 8: Enable the QDMA Channel */
+ drvInst->shadowRegs->QEESR = 1U << qdmaChannel;
+ }
+ }
+ break;
+ default:
+ break;
+ }
+ }
+ else
+ {
+ /* TCC allocation failed, free the PaRAM Set, */
+ resObj.type = EDMA3_RM_RES_PARAM_SET;
+ resObj.resId = (uint32_t)paRAMId;
+ EDMA3_RM_freeResource(drvInst->resMgrInstance, (EDMA3_RM_ResDesc *)&resObj);
+
+ /* And free the DMA/QDMA channel */
+ EDMA3_RM_freeResource(drvInst->resMgrInstance, (EDMA3_RM_ResDesc *)&channelObj);
+
+ result = EDMA3_DRV_E_TCC_UNAVAIL;
+ }
+ }
+
+ if (EDMA3_DRV_SOK == result)
+ {
+ if ((drvInst->configScrMapXbarToEvt != NULL) &&
+ (mapXbarEvtToChanFlag == TRUE))
+ {
+ drvInst->configScrMapXbarToEvt(xBarEvtBeforeMap, *pLCh);
+ }
+ }
+
+#ifdef EDMA3_INSTRUMENTATION_ENABLED
+ EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
+ EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,
+ EDMA3_DVT_dCOUNTER,
+ EDMA3_DVT_dNONE,
+ EDMA3_DVT_dNONE));
+#endif /* EDMA3_INSTRUMENTATION_ENABLED */
+
+ return result;
+}
+
+EDMA3_DRV_Result EDMA3_DRV_freeChannel (EDMA3_DRV_Handle hEdma,
+ uint32_t channelId)
+ {
+ EDMA3_RM_ResDesc resObj;
+ EDMA3_DRV_Result result = EDMA3_DRV_SOK;
+ EDMA3_DRV_Instance *drvInst = NULL;
+ EDMA3_DRV_Object *drvObject = NULL;
+ int32_t paRAMId;
+ uint32_t tcc;
+ EDMA3_DRV_ChannelType chType = EDMA3_DRV_CHANNEL_TYPE_NONE;
+ uint32_t edma3Id;
+
+#ifdef EDMA3_INSTRUMENTATION_ENABLED
+ EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
+ EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,
+ EDMA3_DVT_dCOUNTER,
+ EDMA3_DVT_dNONE,
+ EDMA3_DVT_dNONE));
+#endif /* EDMA3_INSTRUMENTATION_ENABLED */
+
+ /* If parameter checking is enabled... */
+#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
+ if (hEdma == NULL)
+ {
+ result = EDMA3_DRV_E_INVALID_PARAM;
+ }
+#endif
+
+ if (EDMA3_DRV_SOK == result)
+ {
+ drvInst = (EDMA3_DRV_Instance *)hEdma;
+ drvObject = drvInst->pDrvObjectHandle;
+
+ if (drvObject == NULL)
+ {
+ result = EDMA3_DRV_E_INVALID_PARAM;
+ }
+ else
+ {
+ edma3Id = drvObject->phyCtrllerInstId;
+ }
+ }
+
+ if (EDMA3_DRV_SOK == result)
+ {
+ /* Check the channel type */
+ if (channelId <= edma3_dma_ch_max_val [edma3Id])
+ {
+ /* DMA Channel */
+ chType = EDMA3_DRV_CHANNEL_TYPE_DMA;
+ }
+
+ if ((channelId >= edma3_link_ch_min_val[edma3Id])
+ && (channelId <= edma3_link_ch_max_val[edma3Id]))
+ {
+ /* LINK Channel */
+ chType = EDMA3_DRV_CHANNEL_TYPE_LINK;
+ }
+
+ if ((channelId >= edma3_qdma_ch_min_val[edma3Id])
+ && (channelId <= edma3_qdma_ch_max_val[edma3Id]))
+ {
+ /* QDMA Channel */
+ chType = EDMA3_DRV_CHANNEL_TYPE_QDMA;
+ }
+
+ if (chType == EDMA3_DRV_CHANNEL_TYPE_NONE)
+ {
+ result = EDMA3_DRV_E_INVALID_PARAM;
+ }
+ }
+
+
+ if (EDMA3_DRV_SOK == result)
+ {
+ if(channelId < EDMA3_MAX_LOGICAL_CH)
+ {
+ if (chType == EDMA3_DRV_CHANNEL_TYPE_LINK)
+ {
+ /* LINK Channel */
+ resObj.type = EDMA3_RM_RES_PARAM_SET;
+
+ /* Get the PaRAM id from the book-keeping info. */
+ resObj.resId = (uint32_t)(edma3DrvChBoundRes[edma3Id][channelId].paRAMId);
+
+ result = EDMA3_RM_freeResource(drvInst->resMgrInstance,
+ (EDMA3_RM_ResDesc *)&resObj);
+
+ if (EDMA3_DRV_SOK == result)
+ {
+ edma3DrvChBoundRes[edma3Id][channelId].paRAMId = -1;
+ }
+ }
+ else
+ {
+ /* DMA/QDMA Channel */
+ paRAMId = edma3DrvChBoundRes[edma3Id][channelId].paRAMId;
+ tcc = edma3DrvChBoundRes[edma3Id][channelId].tcc;
+
+ /* Check the paRAMId and tcc values first */
+ if ((paRAMId < 0) || (paRAMId >= drvObject->gblCfgParams.numPaRAMSets))
+ {
+ result = EDMA3_DRV_E_INVALID_PARAM;
+ }
+
+ if (tcc >= drvObject->gblCfgParams.numTccs)
+ {
+ result = EDMA3_DRV_E_INVALID_PARAM;
+ }
+
+ if (EDMA3_DRV_SOK == result)
+ {
+ /* Disable the transfer and remove various mappings. */
+ result = edma3RemoveMapping(hEdma, channelId);
+ }
+
+ if (EDMA3_DRV_SOK == result)
+ {
+ /* Now Free the PARAM set and TCC */
+ resObj.type = EDMA3_RM_RES_PARAM_SET;
+ resObj.resId = (uint32_t)paRAMId;
+ result = EDMA3_RM_freeResource(drvInst->resMgrInstance, (EDMA3_RM_ResDesc *)&resObj);
+
+ if (EDMA3_DRV_SOK == result)
+ {
+ /* PaRAM Set Freed */
+ edma3DrvChBoundRes[edma3Id][channelId].paRAMId = -1;
+
+ /* Free the TCC */
+ resObj.type = EDMA3_RM_RES_TCC;
+ resObj.resId = tcc;
+ result = EDMA3_RM_freeResource(drvInst->resMgrInstance,
+ (EDMA3_RM_ResDesc *)&resObj);
+ }
+
+ if (EDMA3_DRV_SOK == result)
+ {
+ /* TCC Freed. */
+ edma3DrvChBoundRes[edma3Id][channelId].tcc = EDMA3_MAX_TCC;
+
+ /* Now free the DMA/QDMA Channel in the end. */
+ if (chType == EDMA3_DRV_CHANNEL_TYPE_QDMA)
+ {
+ resObj.type = EDMA3_RM_RES_QDMA_CHANNEL;
+ resObj.resId = (channelId - edma3_qdma_ch_min_val[edma3Id]);
+ result = EDMA3_RM_freeResource(drvInst->resMgrInstance,
+ (EDMA3_RM_ResDesc *)&resObj);
+ }
+ else
+ {
+ resObj.type = EDMA3_RM_RES_DMA_CHANNEL;
+ resObj.resId = channelId;
+ result = EDMA3_RM_freeResource(drvInst->resMgrInstance,
+ (EDMA3_RM_ResDesc *)&resObj);
+ }
+ }
+ }
+ }
+ }
+ }
+
+#ifdef EDMA3_INSTRUMENTATION_ENABLED
+ EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
+ EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,
+ EDMA3_DVT_dCOUNTER,
+ EDMA3_DVT_dNONE,
+ EDMA3_DVT_dNONE));
+#endif /* EDMA3_INSTRUMENTATION_ENABLED */
+
+ return result;
+ }
+
+EDMA3_DRV_Result EDMA3_DRV_clearErrorBits (EDMA3_DRV_Handle hEdma,
+ uint32_t channelId)
+{
+ EDMA3_DRV_Result result = EDMA3_DRV_SOK;
+ EDMA3_DRV_Instance *drvInst = NULL;
+ EDMA3_DRV_Object *drvObject = NULL;
+ volatile EDMA3_CCRL_Regs *globalRegs = NULL;
+ uint32_t count;
+ uint32_t value = 0;
+ uint32_t edma3Id;
+
+#ifdef EDMA3_INSTRUMENTATION_ENABLED
+ EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
+ EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,
+ EDMA3_DVT_dCOUNTER,
+ EDMA3_DVT_dNONE,
+ EDMA3_DVT_dNONE));
+#endif /* EDMA3_INSTRUMENTATION_ENABLED */
+
+ /* If parameter checking is enabled... */
+#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
+ if (hEdma == NULL)
+ {
+ result = EDMA3_DRV_E_INVALID_PARAM;
+ }
+#endif
+
+ /* Check if the parameters are OK. */
+ if (EDMA3_DRV_SOK == result)
+ {
+ drvInst = (EDMA3_DRV_Instance *)hEdma;
+ drvObject = drvInst->pDrvObjectHandle;
+
+ if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL))
+ {
+ result = EDMA3_DRV_E_INVALID_PARAM;
+ }
+ else
+ {
+ edma3Id = drvObject->phyCtrllerInstId;
+
+ /* If parameter checking is enabled... */
+#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
+ if (channelId > edma3_dma_ch_max_val [edma3Id])
+ {
+ result = EDMA3_DRV_E_INVALID_PARAM;
+ }
+#endif
+
+ /* Check if the parameters are OK. */
+ if (EDMA3_DRV_SOK == result)
+ {
+ globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);
+
+#ifdef EDMA3_DRV_DEBUG
+ EDMA3_DRV_PRINTF("EMR =%l\r\n", globalRegs->EMR);
+#endif
+ if(channelId < 32U)
+ {
+ /* Disables the DMA channels */
+ drvInst->shadowRegs->EECR = (1U << channelId);
+ /* Write to EMCR to clear the corresponding EMR bit */
+ globalRegs->EMCR = (1U << channelId);
+ /* Clears the SER */
+ drvInst->shadowRegs->SECR = (1U << channelId);
+ }
+ else
+ {
+#ifdef EDMA3_DRV_DEBUG
+ EDMA3_DRV_PRINTF("EMRH =%l\r\n", globalRegs->EMRH);
+#endif
+ /* Disables the DMA channels */
+ drvInst->shadowRegs->EECRH = (1U << (channelId - 32U));
+ /* Write to EMCR to clear the corresponding EMR bit */
+ globalRegs->EMCRH = (1U << (channelId - 32U));
+ /* Clears the SER */
+ drvInst->shadowRegs->SECRH = (1U << (channelId - 32U));
+ }
+
+ /* Clear the global CC Error Register */
+ for (count = 0; count < drvObject->gblCfgParams.numEvtQueue; count++)
+ {
+ value |= (((uint32_t)1U) << count);
+ }
+
+ globalRegs->CCERRCLR = (EDMA3_CCRL_CCERR_TCCERR_MASK | value);
+ }
+ }
+ }
+
+#ifdef EDMA3_INSTRUMENTATION_ENABLED
+ EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
+ EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,
+ EDMA3_DVT_dCOUNTER,
+ EDMA3_DVT_dNONE,
+ EDMA3_DVT_dNONE));
+#endif /* EDMA3_INSTRUMENTATION_ENABLED */
+
+ return result;
+ }
+
+EDMA3_DRV_Result EDMA3_DRV_setOptField (EDMA3_DRV_Handle hEdma,
+ uint32_t lCh,
+ EDMA3_DRV_OptField optField,
+ uint32_t newOptFieldVal)
+ {
+ EDMA3_DRV_Result result = EDMA3_DRV_SOK;
+ EDMA3_DRV_Instance *drvInst = NULL;
+ EDMA3_DRV_Object *drvObject = NULL;
+ uint32_t newOptVal = 0;
+ uint32_t oldOptVal = 0;
+ int32_t paRAMId = 0;
+ volatile EDMA3_CCRL_Regs *globalRegs = NULL;
+ uint32_t edma3Id;
+
+#ifdef EDMA3_INSTRUMENTATION_ENABLED
+ EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
+ EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,
+ EDMA3_DVT_dCOUNTER,
+ EDMA3_DVT_dNONE,
+ EDMA3_DVT_dNONE));
+#endif /* EDMA3_INSTRUMENTATION_ENABLED */
+
+ /* If parameter checking is enabled... */
+#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
+ if ((hEdma == NULL)
+ || (((int32_t)optField < (int32_t)EDMA3_DRV_OPT_FIELD_SAM)
+ || (optField > EDMA3_DRV_OPT_FIELD_ITCCHEN)))
+ {
+ result = EDMA3_DRV_E_INVALID_PARAM;
+ }
+#endif
+
+ /* Check if the parameters are OK. */
+ if (EDMA3_DRV_SOK == result)
+ {
+ drvInst = (EDMA3_DRV_Instance *)hEdma;
+ drvObject = drvInst->pDrvObjectHandle;
+
+ if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL))
+ {
+ result = EDMA3_DRV_E_INVALID_PARAM;
+ }
+ else
+ {
+ edma3Id = drvObject->phyCtrllerInstId;
+ globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);
+ }
+ }
+
+ if (EDMA3_DRV_SOK == result)
+ {
+ /* If parameter checking is enabled... */
+#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
+ if (lCh > edma3_log_ch_max_val [edma3Id])
+ {
+ result = EDMA3_DRV_E_INVALID_PARAM;
+ }
+#endif
+ }
+
+ if (EDMA3_DRV_SOK == result)
+ {
+ paRAMId = edma3DrvChBoundRes[edma3Id][lCh].paRAMId;
+ if ((paRAMId < 0) || (paRAMId >= drvObject->gblCfgParams.numPaRAMSets))
+ {
+ result = EDMA3_DRV_E_INVALID_PARAM;
+ }
+ }
+
+ if (EDMA3_DRV_SOK == result)
+ {
+ oldOptVal = (uint32_t)(*(&globalRegs->PARAMENTRY [paRAMId].OPT));
+
+ switch (optField)
+ {
+ case EDMA3_DRV_OPT_FIELD_SAM :
+ newOptVal = (oldOptVal & EDMA3_DRV_OPT_SAM_CLR_MASK)
+ |
+ (EDMA3_DRV_OPT_SAM_SET_MASK(newOptFieldVal));
+ break;
+ case EDMA3_DRV_OPT_FIELD_DAM :
+ newOptVal = (oldOptVal & EDMA3_DRV_OPT_DAM_CLR_MASK)
+ |
+ (EDMA3_DRV_OPT_DAM_SET_MASK(newOptFieldVal));
+ break;
+ case EDMA3_DRV_OPT_FIELD_SYNCDIM :
+ newOptVal = (oldOptVal & EDMA3_DRV_OPT_SYNCDIM_CLR_MASK)
+ |
+ (EDMA3_DRV_OPT_SYNCDIM_SET_MASK(newOptFieldVal));
+ break;
+ case EDMA3_DRV_OPT_FIELD_STATIC :
+ newOptVal = (oldOptVal & EDMA3_DRV_OPT_STATIC_CLR_MASK)
+ |
+ (EDMA3_DRV_OPT_STATIC_SET_MASK(newOptFieldVal));
+ break;
+ case EDMA3_DRV_OPT_FIELD_FWID :
+ newOptVal = (oldOptVal & EDMA3_DRV_OPT_FWID_CLR_MASK)
+ |
+ (EDMA3_DRV_OPT_FWID_SET_MASK(newOptFieldVal));
+ break;
+ case EDMA3_DRV_OPT_FIELD_TCCMODE :
+ newOptVal = (oldOptVal & EDMA3_DRV_OPT_TCCMODE_CLR_MASK)
+ |
+ (EDMA3_DRV_OPT_TCCMODE_SET_MASK(newOptFieldVal));
+ break;
+ case EDMA3_DRV_OPT_FIELD_TCC :
+ newOptVal = (oldOptVal & EDMA3_DRV_OPT_TCC_CLR_MASK)
+ |
+ (EDMA3_DRV_OPT_TCC_SET_MASK(newOptFieldVal));
+ break;
+ case EDMA3_DRV_OPT_FIELD_TCINTEN :
+ newOptVal = (oldOptVal & EDMA3_DRV_OPT_TCINTEN_CLR_MASK)
+ |
+ (EDMA3_DRV_OPT_TCINTEN_SET_MASK(newOptFieldVal));
+ break;
+ case EDMA3_DRV_OPT_FIELD_ITCINTEN :
+ newOptVal = (oldOptVal & EDMA3_DRV_OPT_ITCINTEN_CLR_MASK)
+ |
+ (EDMA3_DRV_OPT_ITCINTEN_SET_MASK(newOptFieldVal));
+ break;
+ case EDMA3_DRV_OPT_FIELD_TCCHEN :
+ newOptVal = (oldOptVal & EDMA3_DRV_OPT_TCCHEN_CLR_MASK)
+ |
+ (EDMA3_DRV_OPT_TCCHEN_SET_MASK(newOptFieldVal));
+ break;
+ case EDMA3_DRV_OPT_FIELD_ITCCHEN :
+ newOptVal = (oldOptVal & EDMA3_DRV_OPT_ITCCHEN_CLR_MASK)
+ |
+ (EDMA3_DRV_OPT_ITCCHEN_SET_MASK(newOptFieldVal));
+ break;
+ default:
+ break;
+ }
+
+ *(&globalRegs->PARAMENTRY[paRAMId].OPT) = newOptVal;
+ }
+
+#ifdef EDMA3_INSTRUMENTATION_ENABLED
+ EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
+ EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,
+ EDMA3_DVT_dCOUNTER,
+ EDMA3_DVT_dNONE,
+ EDMA3_DVT_dNONE));
+#endif /* EDMA3_INSTRUMENTATION_ENABLED */
+
+ return result;
+ }
+
+EDMA3_DRV_Result EDMA3_DRV_getOptField (EDMA3_DRV_Handle hEdma,
+ uint32_t lCh,
+ EDMA3_DRV_OptField optField,
+ uint32_t *optFieldVal)
+ {
+ EDMA3_DRV_Result result = EDMA3_DRV_SOK;
+ EDMA3_DRV_Instance *drvInst = NULL;
+ EDMA3_DRV_Object *drvObject = NULL;
+ uint32_t optVal = 0;
+ int32_t paRAMId = 0;
+ volatile EDMA3_CCRL_Regs *globalRegs = NULL;
+ uint32_t edma3Id;
+
+#ifdef EDMA3_INSTRUMENTATION_ENABLED
+ EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
+ EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,
+ EDMA3_DVT_dCOUNTER,
+ EDMA3_DVT_dNONE,
+ EDMA3_DVT_dNONE));
+#endif /* EDMA3_INSTRUMENTATION_ENABLED */
+
+ /* If parameter checking is enabled... */
+#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
+ if (((hEdma == NULL) || (optFieldVal == NULL))
+ || (((int32_t)optField < (int32_t)EDMA3_DRV_OPT_FIELD_SAM)
+ || (optField > EDMA3_DRV_OPT_FIELD_ITCCHEN)))
+ {
+ result = EDMA3_DRV_E_INVALID_PARAM;
+ }
+#endif
+
+ /* Check if the parameters are OK. */
+ if (EDMA3_DRV_SOK == result)
+ {
+ drvInst = (EDMA3_DRV_Instance *)hEdma;
+ drvObject = drvInst->pDrvObjectHandle;
+
+ if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL))
+ {
+ result = EDMA3_DRV_E_INVALID_PARAM;
+ }
+ else
+ {
+ edma3Id = drvObject->phyCtrllerInstId;
+ globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);
+ }
+ }
+
+ if (EDMA3_DRV_SOK == result)
+ {
+ /* If parameter checking is enabled... */
+#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
+ if (lCh > edma3_log_ch_max_val [edma3Id])
+ {
+ result = EDMA3_DRV_E_INVALID_PARAM;
+ }
+#endif
+ }
+
+ if (EDMA3_DRV_SOK == result)
+ {
+ paRAMId = edma3DrvChBoundRes[edma3Id][lCh].paRAMId;
+ if ((paRAMId < 0) || (paRAMId >= drvObject->gblCfgParams.numPaRAMSets))
+ {
+ result = EDMA3_DRV_E_INVALID_PARAM;
+ }
+ }
+
+ if (EDMA3_DRV_SOK == result)
+ {
+ optVal = (uint32_t)(*(&globalRegs->PARAMENTRY [paRAMId].OPT));
+
+ switch (optField)
+ {
+ case EDMA3_DRV_OPT_FIELD_SAM :
+ *optFieldVal = EDMA3_DRV_OPT_SAM_GET_MASK(optVal);
+ break;
+ case EDMA3_DRV_OPT_FIELD_DAM :
+ *optFieldVal = EDMA3_DRV_OPT_DAM_GET_MASK(optVal);
+ break;
+ case EDMA3_DRV_OPT_FIELD_SYNCDIM :
+ *optFieldVal = EDMA3_DRV_OPT_SYNCDIM_GET_MASK(optVal);
+ break;
+ case EDMA3_DRV_OPT_FIELD_STATIC :
+ *optFieldVal = EDMA3_DRV_OPT_STATIC_GET_MASK(optVal);
+ break;
+ case EDMA3_DRV_OPT_FIELD_FWID :
+ *optFieldVal = EDMA3_DRV_OPT_FWID_GET_MASK(optVal);
+ break;
+ case EDMA3_DRV_OPT_FIELD_TCCMODE :
+ *optFieldVal = EDMA3_DRV_OPT_TCCMODE_GET_MASK(optVal);
+ break;
+ case EDMA3_DRV_OPT_FIELD_TCC :
+ *optFieldVal = EDMA3_DRV_OPT_TCC_GET_MASK(optVal);
+ break;
+ case EDMA3_DRV_OPT_FIELD_TCINTEN :
+ *optFieldVal = EDMA3_DRV_OPT_TCINTEN_GET_MASK(optVal);
+ break;
+ case EDMA3_DRV_OPT_FIELD_ITCINTEN :
+ *optFieldVal = EDMA3_DRV_OPT_ITCINTEN_GET_MASK(optVal);
+ break;
+ case EDMA3_DRV_OPT_FIELD_TCCHEN :
+ *optFieldVal = EDMA3_DRV_OPT_TCCHEN_GET_MASK(optVal);
+ break;
+ case EDMA3_DRV_OPT_FIELD_ITCCHEN :
+ *optFieldVal = EDMA3_DRV_OPT_ITCCHEN_GET_MASK(optVal);
+ break;
+ default:
+ break;
+ }
+ }
+
+#ifdef EDMA3_INSTRUMENTATION_ENABLED
+ EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
+ EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,
+ EDMA3_DVT_dCOUNTER,
+ EDMA3_DVT_dNONE,
+ EDMA3_DVT_dNONE));
+#endif /* EDMA3_INSTRUMENTATION_ENABLED */
+
+ return result;
+ }
+
+EDMA3_DRV_Result EDMA3_DRV_setSrcParams (EDMA3_DRV_Handle hEdma,
+ uint32_t lCh,
+ uint32_t srcAddr,
+ EDMA3_DRV_AddrMode addrMode,
+ EDMA3_DRV_FifoWidth fifoWidth)
+ {
+ EDMA3_DRV_Result result = EDMA3_DRV_SOK;
+ uint32_t opt = 0;
+ EDMA3_DRV_Instance *drvInst = NULL;
+ EDMA3_DRV_Object *drvObject = NULL;
+ int32_t paRAMId = 0;
+ volatile EDMA3_CCRL_Regs *globalRegs = NULL;
+ uint32_t mappedEvtQ = 0;
+ uint32_t defaultBurstSize = 0;
+ uint32_t edma3Id;
+
+#ifdef EDMA3_INSTRUMENTATION_ENABLED
+ EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
+ EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,
+ EDMA3_DVT_dCOUNTER,
+ EDMA3_DVT_dNONE,
+ EDMA3_DVT_dNONE));
+#endif /* EDMA3_INSTRUMENTATION_ENABLED */
+
+ /* If parameter checking is enabled... */
+#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
+ if ((hEdma == NULL)
+ || ((((int32_t)addrMode < (int32_t)EDMA3_DRV_ADDR_MODE_INCR) || (addrMode > EDMA3_DRV_ADDR_MODE_FIFO))
+ || (((int32_t)fifoWidth < (int32_t)EDMA3_DRV_W8BIT) || (fifoWidth > EDMA3_DRV_W256BIT))))
+ {
+ result = EDMA3_DRV_E_INVALID_PARAM;
+ }
+
+ /** In FIFO Addressing mode, memory location must be 32 bytes aligned */
+ if ((addrMode == EDMA3_DRV_ADDR_MODE_FIFO)
+ && ((srcAddr & 0x1FU) != 0x0))
+ {
+ /** Memory is not 32 bytes aligned */
+ result = EDMA3_DRV_E_ADDRESS_NOT_ALIGNED;
+ }
+#endif
+
+ /* Check if the parameters are OK. */
+ if (EDMA3_DRV_SOK == result)
+ {
+ drvInst = (EDMA3_DRV_Instance *)hEdma;
+ drvObject = drvInst->pDrvObjectHandle;
+
+ if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL))
+ {
+ result = EDMA3_DRV_E_INVALID_PARAM;
+ }
+ else
+ {
+ edma3Id = drvObject->phyCtrllerInstId;
+ globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);
+ }
+ }
+
+ if (EDMA3_DRV_SOK == result)
+ {
+ /* If parameter checking is enabled... */
+#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
+ if (lCh > edma3_log_ch_max_val [edma3Id])
+ {
+ result = EDMA3_DRV_E_INVALID_PARAM;
+ }
+#endif
+ }
+
+ if (EDMA3_DRV_SOK == result)
+ {
+ paRAMId = edma3DrvChBoundRes[edma3Id][lCh].paRAMId;
+ if ((paRAMId < 0) || (paRAMId >= drvObject->gblCfgParams.numPaRAMSets))
+ {
+ result = EDMA3_DRV_E_INVALID_PARAM;
+ }
+ }
+
+ if (EDMA3_DRV_SOK == result)
+ {
+ /**
+ * If request is for FIFO mode, check whether the FIFO size
+ * is supported by the Transfer Controller which will be used for
+ * this transfer or not.
+ */
+ if (addrMode == EDMA3_DRV_ADDR_MODE_FIFO)
+ {
+ if (lCh <= edma3_dma_ch_max_val [edma3Id])
+ {
+ mappedEvtQ = ((globalRegs->DMAQNUM[lCh >> 3U])
+ & (~(EDMA3_DRV_DMAQNUM_CLR_MASK(lCh))))
+ >> ((lCh%8U)*4U);
+ }
+ else
+ {
+ if ((lCh >= edma3_qdma_ch_min_val[edma3Id])
+ &&(lCh <= edma3_qdma_ch_max_val[edma3Id]))
+ {
+ mappedEvtQ = ((globalRegs->QDMAQNUM)
+ & (~(EDMA3_DRV_QDMAQNUM_CLR_MASK(lCh - edma3_qdma_ch_min_val[edma3Id]))))
+ >> (lCh*4U);
+ }
+ }
+
+ /**
+ * mappedEvtQ contains the event queue and hence the TC which will
+ * process this transfer request. Check whether this TC supports the
+ * FIFO size or not.
+ */
+ defaultBurstSize = (uint32_t)1U << fifoWidth;
+ if (defaultBurstSize > drvObject->gblCfgParams.tcDefaultBurstSize[mappedEvtQ])
+ {
+ result = EDMA3_DRV_E_FIFO_WIDTH_NOT_SUPPORTED;
+ }
+ }
+ }
+
+ if (EDMA3_DRV_SOK == result)
+ {
+ /* Set Src Address */
+ *((&globalRegs->PARAMENTRY[paRAMId].OPT) +
+ (uint32_t)EDMA3_DRV_PARAM_ENTRY_SRC) = srcAddr;
+
+ opt = (uint32_t)(*(&globalRegs->PARAMENTRY [paRAMId].OPT));
+
+ /* Set SAM */
+ opt &= EDMA3_DRV_OPT_SAM_CLR_MASK;
+ opt |= EDMA3_DRV_OPT_SAM_SET_MASK(addrMode);
+ /* Set FIFO Width */
+ opt &= EDMA3_DRV_OPT_FWID_CLR_MASK;
+ opt |= EDMA3_DRV_OPT_FWID_SET_MASK(fifoWidth);
+
+ /* Set the OPT */
+ *(&globalRegs->PARAMENTRY[paRAMId].OPT) = opt;
+ }
+
+#ifdef EDMA3_INSTRUMENTATION_ENABLED
+ EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
+ EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,
+ EDMA3_DVT_dCOUNTER,
+ EDMA3_DVT_dNONE,
+ EDMA3_DVT_dNONE));
+#endif /* EDMA3_INSTRUMENTATION_ENABLED */
+
+ return result;
+ }
+
+EDMA3_DRV_Result EDMA3_DRV_setDestParams (EDMA3_DRV_Handle hEdma,
+ uint32_t lCh,
+ uint32_t destAddr,
+ EDMA3_DRV_AddrMode addrMode,
+ EDMA3_DRV_FifoWidth fifoWidth)
+ {
+ EDMA3_DRV_Result result = EDMA3_DRV_SOK;
+ uint32_t opt = 0;
+ EDMA3_DRV_Instance *drvInst = NULL;
+ EDMA3_DRV_Object *drvObject = NULL;
+ int32_t paRAMId = 0;
+ volatile EDMA3_CCRL_Regs *globalRegs = NULL;
+ uint32_t mappedEvtQ = 0;
+ uint32_t defaultBurstSize = 0;
+ uint32_t edma3Id;
+
+#ifdef EDMA3_INSTRUMENTATION_ENABLED
+ EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
+ EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,
+ EDMA3_DVT_dCOUNTER,
+ EDMA3_DVT_dNONE,
+ EDMA3_DVT_dNONE));
+#endif /* EDMA3_INSTRUMENTATION_ENABLED */
+
+ /* If parameter checking is enabled... */
+#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
+ if ((hEdma == NULL)
+ || ((((int32_t)addrMode < (int32_t)EDMA3_DRV_ADDR_MODE_INCR) || (addrMode > EDMA3_DRV_ADDR_MODE_FIFO))
+ || (((int32_t)fifoWidth < (int32_t)EDMA3_DRV_W8BIT) || (fifoWidth > EDMA3_DRV_W256BIT))))
+ {
+ result = EDMA3_DRV_E_INVALID_PARAM;
+ }
+
+ /** In FIFO Addressing mode, memory location must be 32 bytes aligned */
+ if ((addrMode == EDMA3_DRV_ADDR_MODE_FIFO)
+ && ((destAddr & 0x1FU)!=0x0))
+ {
+ /** Memory is not 32 bytes aligned */
+ result = EDMA3_DRV_E_ADDRESS_NOT_ALIGNED;
+ }
+#endif
+
+ /* Check if the parameters are OK. */
+ if (EDMA3_DRV_SOK == result)
+ {
+ drvInst = (EDMA3_DRV_Instance *)hEdma;
+ drvObject = drvInst->pDrvObjectHandle;
+
+ if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL))
+ {
+ result = EDMA3_DRV_E_INVALID_PARAM;
+ }
+ else
+ {
+ edma3Id = drvObject->phyCtrllerInstId;
+ globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);
+ }
+ }
+
+ if (EDMA3_DRV_SOK == result)
+ {
+ /* If parameter checking is enabled... */
+#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
+ if (lCh > edma3_log_ch_max_val [edma3Id])
+ {
+ result = EDMA3_DRV_E_INVALID_PARAM;
+ }
+#endif
+ }
+
+ if (EDMA3_DRV_SOK == result)
+ {
+ paRAMId = edma3DrvChBoundRes[edma3Id][lCh].paRAMId;
+ if ((paRAMId < 0) || (paRAMId >= drvObject->gblCfgParams.numPaRAMSets))
+ {
+ result = EDMA3_DRV_E_INVALID_PARAM;
+ }
+ }
+
+ if (EDMA3_DRV_SOK == result)
+ {
+ /**
+ * If request is for FIFO mode, check whether the FIFO size
+ * is supported by the Transfer Controller which will be used for
+ * this transfer or not.
+ */
+ if (addrMode == EDMA3_DRV_ADDR_MODE_FIFO)
+ {
+ if (lCh <= edma3_dma_ch_max_val [edma3Id])
+ {
+ mappedEvtQ = ((globalRegs->DMAQNUM[lCh >> 3U])
+ & (~(EDMA3_DRV_DMAQNUM_CLR_MASK(lCh))))
+ >> ((lCh%8U)*4U);
+ }
+ else
+ {
+ if ((lCh >= edma3_qdma_ch_min_val[edma3Id])
+ &&(lCh <= edma3_qdma_ch_max_val[edma3Id]))
+ {
+ mappedEvtQ = ((globalRegs->QDMAQNUM)
+ & (~(EDMA3_DRV_QDMAQNUM_CLR_MASK(lCh - edma3_qdma_ch_min_val[edma3Id]))))
+ >> (lCh*4U);
+ }
+ }
+
+ /**
+ * mappedEvtQ contains the event queue and hence the TC which will
+ * process this transfer request. Check whether this TC supports the
+ * FIFO size or not.
+ */
+ defaultBurstSize = (uint32_t)1U << fifoWidth;
+ if (defaultBurstSize > drvObject->gblCfgParams.tcDefaultBurstSize[mappedEvtQ])
+ {
+ result = EDMA3_DRV_E_FIFO_WIDTH_NOT_SUPPORTED;
+ }
+ }
+ }
+
+ if (EDMA3_DRV_SOK == result)
+ {
+ /* Set the Dest address */
+ *((&globalRegs->PARAMENTRY[paRAMId].OPT) +
+ (uint32_t)EDMA3_DRV_PARAM_ENTRY_DST) = destAddr;
+
+ opt = (uint32_t)(*(&globalRegs->PARAMENTRY [paRAMId].OPT));
+
+ /* Set DAM */
+ opt &= EDMA3_DRV_OPT_DAM_CLR_MASK;
+ opt |= EDMA3_DRV_OPT_DAM_SET_MASK(addrMode);
+ /* Set FIFO Width */
+ opt &= EDMA3_DRV_OPT_FWID_CLR_MASK;
+ opt |= EDMA3_DRV_OPT_FWID_SET_MASK(fifoWidth);
+
+ /* Set the OPT */
+ *(&globalRegs->PARAMENTRY[paRAMId].OPT) = opt;
+ }
+
+#ifdef EDMA3_INSTRUMENTATION_ENABLED
+ EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
+ EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,
+ EDMA3_DVT_dCOUNTER,
+ EDMA3_DVT_dNONE,
+ EDMA3_DVT_dNONE));
+#endif /* EDMA3_INSTRUMENTATION_ENABLED */
+
+ return result;
+ }
+
+EDMA3_DRV_Result EDMA3_DRV_setSrcIndex (EDMA3_DRV_Handle hEdma,
+ uint32_t lCh,
+ int32_t srcBIdx, int32_t srcCIdx)
+ {
+ EDMA3_DRV_Result result = EDMA3_DRV_SOK;
+ uint32_t srcDstBidx;
+ uint32_t srcDstCidx;
+ EDMA3_DRV_Instance *drvInst = NULL;
+ EDMA3_DRV_Object *drvObject = NULL;
+ int32_t paRAMId = 0;
+ volatile EDMA3_CCRL_Regs *globalRegs = NULL;
+ uint32_t edma3Id;
+
+#ifdef EDMA3_INSTRUMENTATION_ENABLED
+ EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
+ EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,
+ EDMA3_DVT_dCOUNTER,
+ EDMA3_DVT_dNONE,
+ EDMA3_DVT_dNONE));
+#endif /* EDMA3_INSTRUMENTATION_ENABLED */
+
+ /* If parameter checking is enabled... */
+#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
+ if (hEdma == NULL)
+ {
+ result = EDMA3_DRV_E_INVALID_PARAM;
+ }
+
+ if (((srcBIdx > EDMA3_DRV_SRCBIDX_MAX_VAL)
+ || (srcBIdx < EDMA3_DRV_SRCBIDX_MIN_VAL))
+ || ((srcCIdx > EDMA3_DRV_SRCCIDX_MAX_VAL)
+ || (srcCIdx < EDMA3_DRV_SRCCIDX_MIN_VAL)))
+ {
+ result = EDMA3_DRV_E_INVALID_PARAM;
+ }
+#endif
+
+ /* Check if the parameters are OK. */
+ if (EDMA3_DRV_SOK == result)
+ {
+ drvInst = (EDMA3_DRV_Instance *)hEdma;
+ drvObject = drvInst->pDrvObjectHandle;
+
+ if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL))
+ {
+ result = EDMA3_DRV_E_INVALID_PARAM;
+ }
+ else
+ {
+ edma3Id = drvObject->phyCtrllerInstId;
+ globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);
+ }
+ }
+
+ if (EDMA3_DRV_SOK == result)
+ {
+ /* If parameter checking is enabled... */
+#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
+ if (lCh > edma3_log_ch_max_val [edma3Id])
+ {
+ result = EDMA3_DRV_E_INVALID_PARAM;
+ }
+#endif
+ }
+
+ if (EDMA3_DRV_SOK == result)
+ {
+ paRAMId = edma3DrvChBoundRes[edma3Id][lCh].paRAMId;
+ if ((paRAMId < 0) || (paRAMId >= drvObject->gblCfgParams.numPaRAMSets))
+ {
+ result = EDMA3_DRV_E_INVALID_PARAM;
+ }
+ else
+ {
+ /* Get SrcDestBidx PaRAM Set entry */
+ srcDstBidx = (uint32_t)(*((&globalRegs->PARAMENTRY [paRAMId].OPT)
+ + (uint32_t)EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX));
+
+ srcDstBidx &= 0xFFFF0000U;
+ /* Update it */
+ srcDstBidx |= ((uint32_t)srcBIdx & (uint32_t)0xFFFF);
+
+ /* Store it back */
+ *((&globalRegs->PARAMENTRY[paRAMId].OPT)
+ + (uint32_t)EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX) = srcDstBidx;
+
+ /* Get SrcDestCidx PaRAM Set entry */
+ srcDstCidx = (uint32_t)(*((&globalRegs->PARAMENTRY [paRAMId].OPT)
+ + (uint32_t)EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX));
+
+ srcDstCidx &= 0xFFFF0000U;
+ /* Update it */
+ srcDstCidx |= ((uint32_t)srcCIdx & (uint32_t)0xFFFF);
+
+ /* Store it back */
+ *((&globalRegs->PARAMENTRY[paRAMId].OPT)
+ + (uint32_t)EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX) = srcDstCidx;
+ }
+ }
+
+#ifdef EDMA3_INSTRUMENTATION_ENABLED
+ EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
+ EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,
+ EDMA3_DVT_dCOUNTER,
+ EDMA3_DVT_dNONE,
+ EDMA3_DVT_dNONE));
+#endif /* EDMA3_INSTRUMENTATION_ENABLED */
+
+ return result;
+ }
+
+EDMA3_DRV_Result EDMA3_DRV_setDestIndex (EDMA3_DRV_Handle hEdma, uint32_t lCh,
+ int32_t destBIdx, int32_t destCIdx)
+ {
+ EDMA3_DRV_Result result = EDMA3_DRV_SOK;
+ uint32_t srcDstBidx;
+ uint32_t srcDstCidx;
+ EDMA3_DRV_Instance *drvInst = NULL;
+ EDMA3_DRV_Object *drvObject = NULL;
+ int32_t paRAMId = 0;
+ volatile EDMA3_CCRL_Regs *globalRegs = NULL;
+ uint32_t edma3Id;
+
+#ifdef EDMA3_INSTRUMENTATION_ENABLED
+ EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
+ EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,
+ EDMA3_DVT_dCOUNTER,
+ EDMA3_DVT_dNONE,
+ EDMA3_DVT_dNONE));
+#endif /* EDMA3_INSTRUMENTATION_ENABLED */
+
+ /* If parameter checking is enabled... */
+#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
+ if (hEdma == NULL)
+ {
+ result = EDMA3_DRV_E_INVALID_PARAM;
+ }
+
+ if (((destBIdx > EDMA3_DRV_DSTBIDX_MAX_VAL)
+ || (destBIdx < EDMA3_DRV_DSTBIDX_MIN_VAL))
+ || ((destCIdx > EDMA3_DRV_DSTCIDX_MAX_VAL)
+ || (destCIdx < EDMA3_DRV_DSTCIDX_MIN_VAL)))
+ {
+ result = EDMA3_DRV_E_INVALID_PARAM;
+ }
+#endif
+
+ /* Check if the parameters are OK. */
+ if (EDMA3_DRV_SOK == result)
+ {
+ drvInst = (EDMA3_DRV_Instance *)hEdma;
+ drvObject = drvInst->pDrvObjectHandle;
+
+ if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL))
+ {
+ result = EDMA3_DRV_E_INVALID_PARAM;
+ }
+ else
+ {
+ edma3Id = drvObject->phyCtrllerInstId;
+ globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);
+ }
+ }
+
+ if (EDMA3_DRV_SOK == result)
+ {
+ /* If parameter checking is enabled... */
+#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
+ if (lCh > edma3_log_ch_max_val [edma3Id])
+ {
+ result = EDMA3_DRV_E_INVALID_PARAM;
+ }
+#endif
+ }
+
+ if (EDMA3_DRV_SOK == result)
+ {
+ paRAMId = edma3DrvChBoundRes[edma3Id][lCh].paRAMId;
+ if ((paRAMId < 0) || (paRAMId >= drvObject->gblCfgParams.numPaRAMSets))
+ {
+ result = EDMA3_DRV_E_INVALID_PARAM;
+ }
+ else
+ {
+ /* Get SrcDestBidx PaRAM Set entry */
+ srcDstBidx = (uint32_t)(*((&globalRegs->PARAMENTRY [paRAMId].OPT)
+ + (uint32_t)EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX));
+
+ srcDstBidx &= 0xFFFFU;
+ /* Update it */
+ srcDstBidx |= (((uint32_t)destBIdx & (uint32_t)0xFFFF) << 16U);
+
+ /* Store it back */
+ *((&globalRegs->PARAMENTRY[paRAMId].OPT)
+ + (uint32_t)EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX) = srcDstBidx;
+
+ /* Get SrcDestCidx PaRAM Set entry */
+ srcDstCidx = (uint32_t)(*((&globalRegs->PARAMENTRY [paRAMId].OPT)
+ + (uint32_t)EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX));
+
+ srcDstCidx &= 0xFFFFU;
+ /* Update it */
+ srcDstCidx |= (((uint32_t)destCIdx & (uint32_t)0xFFFF) << 16U);
+
+ /* Store it back */
+ *((&globalRegs->PARAMENTRY[paRAMId].OPT)
+ + (uint32_t)EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX) = srcDstCidx;
+ }
+ }
+
+#ifdef EDMA3_INSTRUMENTATION_ENABLED
+ EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
+ EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,
+ EDMA3_DVT_dCOUNTER,
+ EDMA3_DVT_dNONE,
+ EDMA3_DVT_dNONE));
+#endif /* EDMA3_INSTRUMENTATION_ENABLED */
+
+ return result;
+ }
+
+EDMA3_DRV_Result EDMA3_DRV_setTransferParams (EDMA3_DRV_Handle hEdma,
+ uint32_t lCh, uint32_t aCnt, uint32_t bCnt, uint32_t cCnt,
+ uint32_t bCntReload, EDMA3_DRV_SyncType syncType)
+ {
+ EDMA3_DRV_Result result = EDMA3_DRV_SOK;
+ uint32_t abCnt = 0;
+ uint32_t linkBCntReld = 0;
+ uint32_t opt = 0;
+ EDMA3_DRV_Instance *drvInst = NULL;
+ EDMA3_DRV_Object *drvObject = NULL;
+ int32_t paRAMId = 0;
+ volatile EDMA3_CCRL_Regs *globalRegs = NULL;
+ uint32_t edma3Id;
+
+#ifdef EDMA3_INSTRUMENTATION_ENABLED
+ EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
+ EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,
+ EDMA3_DVT_dCOUNTER,
+ EDMA3_DVT_dNONE,
+ EDMA3_DVT_dNONE));
+#endif /* EDMA3_INSTRUMENTATION_ENABLED */
+
+ /* If parameter checking is enabled... */
+#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
+ if (hEdma == NULL)
+ {
+ result = EDMA3_DRV_E_INVALID_PARAM;
+ }
+
+ if ((((aCnt > EDMA3_DRV_ACNT_MAX_VAL)
+ || (bCnt > EDMA3_DRV_BCNT_MAX_VAL))
+ || ((cCnt > EDMA3_DRV_CCNT_MAX_VAL)
+ || (bCntReload > EDMA3_DRV_BCNTRELD_MAX_VAL)))
+ || (((int32_t)syncType < (int32_t)EDMA3_DRV_SYNC_A) || (syncType > EDMA3_DRV_SYNC_AB)))
+ {
+ result = EDMA3_DRV_E_INVALID_PARAM;
+ }
+#endif
+
+ /* Check if the parameters are OK. */
+ if (EDMA3_DRV_SOK == result)
+ {
+ drvInst = (EDMA3_DRV_Instance *)hEdma;
+ drvObject = drvInst->pDrvObjectHandle;
+
+ if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL))
+ {
+ result = EDMA3_DRV_E_INVALID_PARAM;
+ }
+ else
+ {
+ edma3Id = drvObject->phyCtrllerInstId;
+ globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);
+ }
+ }
+
+ if (EDMA3_DRV_SOK == result)
+ {
+ /* If parameter checking is enabled... */
+#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
+ if (lCh > edma3_log_ch_max_val [edma3Id])
+ {
+ result = EDMA3_DRV_E_INVALID_PARAM;
+ }
+#endif
+ }
+
+ if (EDMA3_DRV_SOK == result)
+ {
+ paRAMId = edma3DrvChBoundRes[edma3Id][lCh].paRAMId;
+ if ((paRAMId < 0) || (paRAMId >= drvObject->gblCfgParams.numPaRAMSets))
+ {
+ result = EDMA3_DRV_E_INVALID_PARAM;
+ }
+ else
+ {
+ abCnt = aCnt | ((bCnt&0xFFFFU) << 16U);
+
+ /* Set aCnt and bCnt */
+ *((&globalRegs->PARAMENTRY[paRAMId].OPT)
+ + (uint32_t)EDMA3_DRV_PARAM_ENTRY_ACNT_BCNT) = abCnt;
+
+ /* Set cCnt */
+ *((&globalRegs->PARAMENTRY[paRAMId].OPT)
+ + (uint32_t)EDMA3_DRV_PARAM_ENTRY_CCNT) = cCnt;
+
+
+ linkBCntReld = (uint32_t)(*((&globalRegs->PARAMENTRY [paRAMId].OPT)
+ + (uint32_t)EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD));
+
+ linkBCntReld |= ((bCntReload & 0xFFFFU) << 16U);
+
+ /* Set bCntReload */
+ *((&globalRegs->PARAMENTRY[paRAMId].OPT)
+ + (uint32_t)EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD) = linkBCntReld;
+
+ opt = (uint32_t)(*(&globalRegs->PARAMENTRY [paRAMId].OPT));
+
+ /* Set Sync Type */
+ opt &= EDMA3_DRV_OPT_SYNCDIM_CLR_MASK;
+ opt |= EDMA3_DRV_OPT_SYNCDIM_SET_MASK(syncType);
+
+ *(&globalRegs->PARAMENTRY[paRAMId].OPT) = opt;
+ }
+ }
+
+#ifdef EDMA3_INSTRUMENTATION_ENABLED
+ EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
+ EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,
+ EDMA3_DVT_dCOUNTER,
+ EDMA3_DVT_dNONE,
+ EDMA3_DVT_dNONE));
+#endif /* EDMA3_INSTRUMENTATION_ENABLED */
+
+ return result;
+ }
+
+EDMA3_DRV_Result EDMA3_DRV_enableTransfer (EDMA3_DRV_Handle hEdma,
+ uint32_t lCh,
+ EDMA3_DRV_TrigMode trigMode)
+ {
+ EDMA3_DRV_Instance *drvInst = NULL;
+ EDMA3_DRV_Object *drvObject = NULL;
+ EDMA3_DRV_Result result = EDMA3_DRV_SOK;
+ volatile EDMA3_CCRL_Regs *globalRegs = NULL;
+ uint32_t edma3Id;
+
+#ifdef EDMA3_INSTRUMENTATION_ENABLED
+ EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
+ EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,
+ EDMA3_DVT_dCOUNTER,
+ EDMA3_DVT_dNONE,
+ EDMA3_DVT_dNONE));
+#endif /* EDMA3_INSTRUMENTATION_ENABLED */
+
+ /* If parameter checking is enabled... */
+#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
+ if (hEdma == NULL)
+ {
+ result = EDMA3_DRV_E_INVALID_PARAM;
+ }
+#endif
+
+ if (EDMA3_DRV_SOK == result)
+ {
+ drvInst = (EDMA3_DRV_Instance *)hEdma;
+ drvObject = drvInst->pDrvObjectHandle;
+
+ if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL))
+ {
+ result = EDMA3_DRV_E_INVALID_PARAM;
+ }
+ else
+ {
+ edma3Id = drvObject->phyCtrllerInstId;
+ globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);
+ }
+ }
+
+ if (EDMA3_DRV_SOK == result)
+ {
+ /* If parameter checking is enabled... */
+#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
+ if (lCh > edma3_log_ch_max_val [edma3Id])
+ {
+ result = EDMA3_DRV_E_INVALID_PARAM;
+ }
+
+ /* Trigger type is Manual */
+ if ((EDMA3_DRV_TRIG_MODE_MANUAL == trigMode)
+ && (lCh > edma3_dma_ch_max_val [edma3Id]))
+ {
+ /* Channel Id lies outside DMA channel range */
+ result = EDMA3_DRV_E_INVALID_PARAM;
+ }
+
+ /* Trigger type is QDMA */
+ if ((EDMA3_DRV_TRIG_MODE_QDMA == trigMode)
+ && ((lCh < edma3_qdma_ch_min_val[edma3Id])
+ || (lCh > edma3_qdma_ch_max_val[edma3Id])))
+ {
+ /* Channel Id lies outside QDMA channel range */
+ result = EDMA3_DRV_E_INVALID_PARAM;
+ }
+
+ /* Trigger type is Event */
+ if ((EDMA3_DRV_TRIG_MODE_EVENT == trigMode)
+ && ((drvObject->gblCfgParams.dmaChannelHwEvtMap [lCh/32U]
+ & ((uint32_t)1U<<(lCh%32U))) == FALSE))
+ {
+ /* Channel was not mapped to any Hw Event. */
+ result = EDMA3_DRV_E_INVALID_PARAM;
+ }
+#endif
+ }
+
+ if (EDMA3_DRV_SOK == result)
+ {
+ switch (trigMode)
+ {
+ case EDMA3_DRV_TRIG_MODE_MANUAL :
+ {
+ if (lCh < 32U)
+ {
+ drvInst->shadowRegs->ESR = (1UL << lCh);
+ }
+ else
+ {
+ drvInst->shadowRegs->ESRH = (1UL << (lCh-32U));
+ }
+ edma3DrvChBoundRes[edma3Id][lCh].trigMode =
+ EDMA3_DRV_TRIG_MODE_MANUAL;
+ }
+ break;
+
+ case EDMA3_DRV_TRIG_MODE_QDMA :
+ {
+ drvInst->shadowRegs->QEESR = (1U<<(lCh - edma3_qdma_ch_min_val[edma3Id]));
+ edma3DrvChBoundRes[edma3Id][lCh].trigMode =
+ EDMA3_DRV_TRIG_MODE_QDMA;
+ }
+ break;
+
+ case EDMA3_DRV_TRIG_MODE_EVENT :
+ {
+ if (lCh < 32U)
+ {
+ /*clear SECR to clean any previous NULL request */
+ drvInst->shadowRegs->SECR = (1UL << lCh);
+
+ /*clear EMCR to clean any previous NULL request */
+ globalRegs->EMCR = (1UL << lCh);
+
+ drvInst->shadowRegs->EESR = (1UL << lCh);
+ }
+ else
+ {
+ /*clear SECR to clean any previous NULL request */
+ drvInst->shadowRegs->SECRH = (1UL << (lCh-32U));
+
+ /*clear EMCR to clean any previous NULL request */
+ globalRegs->EMCRH = (1UL << (lCh-32U));
+
+ drvInst->shadowRegs->EESRH = (1UL << (lCh-32U));
+ }
+
+ edma3DrvChBoundRes[edma3Id][lCh].trigMode =
+ EDMA3_DRV_TRIG_MODE_EVENT;
+ }
+ break;
+
+ default :
+ result = EDMA3_DRV_E_INVALID_PARAM;
+ break;
+ }
+ }
+
+#ifdef EDMA3_INSTRUMENTATION_ENABLED
+ EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
+ EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,
+ EDMA3_DVT_dCOUNTER,
+ EDMA3_DVT_dNONE,
+ EDMA3_DVT_dNONE));
+#endif /* EDMA3_INSTRUMENTATION_ENABLED */
+
+ return result;
+ }
+
+EDMA3_DRV_Result EDMA3_DRV_disableTransfer (EDMA3_DRV_Handle hEdma,
+ uint32_t lCh, EDMA3_DRV_TrigMode trigMode)
+{
+ EDMA3_DRV_Result result = EDMA3_DRV_SOK;
+ EDMA3_DRV_Instance *drvInst = NULL;
+ EDMA3_DRV_Object *drvObject = NULL;
+ volatile EDMA3_CCRL_Regs *globalRegs = NULL;
+ uint32_t edma3Id;
+
+#ifdef EDMA3_INSTRUMENTATION_ENABLED
+ EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
+ EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,
+ EDMA3_DVT_dCOUNTER,
+ EDMA3_DVT_dNONE,
+ EDMA3_DVT_dNONE));
+#endif /* EDMA3_INSTRUMENTATION_ENABLED */
+
+ /* If parameter checking is enabled... */
+#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
+ if (hEdma == NULL)
+ {
+ result = EDMA3_DRV_E_INVALID_PARAM;
+ }
+#endif
+
+ /* Check if the parameters are OK. */
+ if (EDMA3_DRV_SOK == result)
+ {
+ drvInst = (EDMA3_DRV_Instance *)hEdma;
+ drvObject = drvInst->pDrvObjectHandle;
+
+ if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL))
+ {
+ result = EDMA3_DRV_E_INVALID_PARAM;
+ }
+ else
+ {
+ edma3Id = drvObject->phyCtrllerInstId;
+ globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);
+ }
+ }
+ if (EDMA3_DRV_SOK == result)
+ {
+ /* If parameter checking is enabled... */
+#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
+ if (lCh > edma3_log_ch_max_val [edma3Id])
+ {
+ result = EDMA3_DRV_E_INVALID_PARAM;
+ }
+
+ /* Trigger type is Manual */
+ if ((EDMA3_DRV_TRIG_MODE_MANUAL == trigMode)
+ && (lCh > edma3_dma_ch_max_val [edma3Id]))
+ {
+ /* Channel Id lies outside DMA channel range */
+ result = EDMA3_DRV_E_INVALID_PARAM;
+ }
+
+ /* Trigger type is QDMA */
+ if ((EDMA3_DRV_TRIG_MODE_QDMA == trigMode)
+ && ((lCh < edma3_qdma_ch_min_val[edma3Id])
+ || (lCh > edma3_qdma_ch_max_val[edma3Id])))
+ {
+ /* Channel Id lies outside QDMA channel range */
+ result = EDMA3_DRV_E_INVALID_PARAM;
+ }
+
+ /* Trigger type is Event */
+ if ((EDMA3_DRV_TRIG_MODE_EVENT == trigMode)
+ && ((drvObject->gblCfgParams.dmaChannelHwEvtMap [lCh/32U]
+ & ((uint32_t)1U<<(lCh%32U))) == FALSE))
+ {
+ /* Channel was not mapped to any Hw Event. */
+ result = EDMA3_DRV_E_INVALID_PARAM;
+ }
+#endif
+ }
+
+ if (EDMA3_DRV_SOK == result)
+ {
+ switch (trigMode)
+ {
+ case EDMA3_DRV_TRIG_MODE_MANUAL :
+ {
+ if (lCh < 32U)
+ {
+ if((drvInst->shadowRegs->SER & ((uint32_t)1U<<lCh))!=FALSE)
+ {
+ drvInst->shadowRegs->SECR = (1U<<lCh);
+ }
+ if((globalRegs->EMR & ((uint32_t)1U<<lCh))!=FALSE)
+ {
+ globalRegs->EMCR = (1U<<lCh);
+ }
+ }
+ else
+ {
+ if((drvInst->shadowRegs->SERH & ((uint32_t)1U<<(lCh-32U)))!=FALSE)
+ {
+ drvInst->shadowRegs->SECRH = (1U<<(lCh-32U));
+ }
+
+ if((globalRegs->EMRH & ((uint32_t)1U<<(lCh-32U)))!=FALSE)
+ {
+ globalRegs->EMCRH = (1U<<(lCh-32U));
+ }
+ }
+ }
+ break;
+
+ case EDMA3_DRV_TRIG_MODE_QDMA :
+ {
+ drvInst->shadowRegs->QEECR = (1U<<(lCh - edma3_qdma_ch_min_val[edma3Id]));
+ }
+ break;
+
+ case EDMA3_DRV_TRIG_MODE_EVENT :
+ {
+ if (lCh < 32U)
+ {
+ drvInst->shadowRegs->EECR = (1U << lCh);
+
+ if((drvInst->shadowRegs->ER & ((uint32_t)1U<<lCh))!=FALSE)
+ {
+ drvInst->shadowRegs->ECR = (1U<<lCh);
+ }
+ if((drvInst->shadowRegs->SER & ((uint32_t)1U<<lCh))!=FALSE)
+ {
+ drvInst->shadowRegs->SECR = (1U<<lCh);
+ }
+ if((globalRegs->EMR & ((uint32_t)1U<<lCh))!=FALSE)
+ {
+ globalRegs->EMCR = (1U<<lCh);
+ }
+ }
+ else
+ {
+ drvInst->shadowRegs->EECRH = (1U << (lCh-32U));
+ if((drvInst->shadowRegs->ERH & ((uint32_t)1U<<(lCh-32U)))!=FALSE)
+ {
+ drvInst->shadowRegs->ECRH = (1U<<(lCh-32U));
+ }
+
+ if((drvInst->shadowRegs->SERH & ((uint32_t)1U<<(lCh-32U)))!=FALSE)
+ {
+ drvInst->shadowRegs->SECRH = (1U<<(lCh-32U));
+ }
+
+ if((globalRegs->EMRH & ((uint32_t)1U<<(lCh-32U)))!=FALSE)
+ {
+ globalRegs->EMCRH = (1U<<(lCh-32U));
+ }
+ }
+ }
+ break;
+
+ default :
+ result = EDMA3_DRV_E_INVALID_PARAM;
+ break;
+ }
+ }
+
+#ifdef EDMA3_INSTRUMENTATION_ENABLED
+ EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
+ EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,
+ EDMA3_DVT_dCOUNTER,
+ EDMA3_DVT_dNONE,
+ EDMA3_DVT_dNONE));
+#endif /* EDMA3_INSTRUMENTATION_ENABLED */
+
+ return result;
+ }
+
+EDMA3_DRV_Result EDMA3_DRV_disableLogicalChannel (EDMA3_DRV_Handle hEdma,
+ uint32_t lCh, EDMA3_DRV_TrigMode trigMode)
+{
+ EDMA3_DRV_Result result = EDMA3_DRV_SOK;
+ EDMA3_DRV_Instance *drvInst = NULL;
+ EDMA3_DRV_Object *drvObject = NULL;
+ uint32_t edma3Id;
+
+#ifdef EDMA3_INSTRUMENTATION_ENABLED
+ EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
+ EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,
+ EDMA3_DVT_dCOUNTER,
+ EDMA3_DVT_dNONE,
+ EDMA3_DVT_dNONE));
+#endif /* EDMA3_INSTRUMENTATION_ENABLED */
+
+ /* If parameter checking is enabled... */
+#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
+ if (hEdma == NULL)
+ {
+ result = EDMA3_DRV_E_INVALID_PARAM;
+ }
+#endif
+
+ /* Check if the parameters are OK. */
+ if (EDMA3_DRV_SOK == result)
+ {
+ drvInst = (EDMA3_DRV_Instance *)hEdma;
+ drvObject = drvInst->pDrvObjectHandle;
+
+ if (drvObject == NULL)
+ {
+ result = EDMA3_DRV_E_INVALID_PARAM;
+ }
+ else
+ {
+ edma3Id = drvObject->phyCtrllerInstId;
+ }
+ }
+
+ if (EDMA3_DRV_SOK == result)
+ {
+ /* If parameter checking is enabled... */
+#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
+ if (lCh > edma3_log_ch_max_val [edma3Id])
+ {
+ result = EDMA3_DRV_E_INVALID_PARAM;
+ }
+
+ /* Trigger type is QDMA */
+ if ((EDMA3_DRV_TRIG_MODE_QDMA == trigMode)
+ && ((lCh < edma3_qdma_ch_min_val[edma3Id])
+ || (lCh > edma3_qdma_ch_max_val[edma3Id])))
+ {
+ /* Channel Id lies outside QDMA channel range */
+ result = EDMA3_DRV_E_INVALID_PARAM;
+ }
+
+ /* Trigger type is Event */
+ if ((EDMA3_DRV_TRIG_MODE_EVENT == trigMode)
+ && ((drvObject->gblCfgParams.dmaChannelHwEvtMap [lCh/32U]
+ & ((uint32_t)1U<<(lCh%32U))) == FALSE))
+ {
+ /* Channel was not mapped to any Hw Event. */
+ result = EDMA3_DRV_E_INVALID_PARAM;
+ }
+#endif
+ }
+
+ if (EDMA3_DRV_SOK == result)
+ {
+ switch (trigMode)
+ {
+ case EDMA3_DRV_TRIG_MODE_QDMA:
+ {
+ drvInst->shadowRegs->QEECR = (1U<<(lCh - edma3_qdma_ch_min_val[edma3Id]));
+ }
+ break;
+
+ case EDMA3_DRV_TRIG_MODE_EVENT:
+ {
+ if (lCh < 32U)
+ {
+ drvInst->shadowRegs->EECR = (1U << lCh);
+ }
+ else
+ {
+ drvInst->shadowRegs->EECRH = (1U << (lCh-32U));
+ }
+ }
+ break;
+
+ default :
+ result = EDMA3_DRV_E_INVALID_PARAM;
+ break;
+ }
+ }
+
+#ifdef EDMA3_INSTRUMENTATION_ENABLED
+ EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
+ EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,
+ EDMA3_DVT_dCOUNTER,
+ EDMA3_DVT_dNONE,
+ EDMA3_DVT_dNONE));
+#endif /* EDMA3_INSTRUMENTATION_ENABLED */
+
+ return result;
+ }
+
+/* Definitions of Local functions - Start */
+/** Remove various mappings and do cleanup for DMA/QDMA channels */
+static EDMA3_DRV_Result edma3RemoveMapping (EDMA3_DRV_Handle hEdma,
+ uint32_t channelId)
+ {
+ uint32_t intState=0;
+ EDMA3_DRV_Instance *drvInst = NULL;
+ EDMA3_DRV_Object *drvObject = NULL;
+ EDMA3_DRV_Result result = EDMA3_DRV_SOK;
+ volatile EDMA3_CCRL_Regs *globalRegs = NULL;
+ EDMA3_RM_ResDesc channelObj;
+ uint32_t edma3Id;
+
+ assert (hEdma != NULL);
+
+ drvInst = (EDMA3_DRV_Instance *)hEdma;
+ drvObject = drvInst->pDrvObjectHandle;
+
+ if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL))
+ {
+ result = EDMA3_DRV_E_INVALID_PARAM;
+ }
+ else
+ {
+ edma3Id = drvObject->phyCtrllerInstId;
+ globalRegs = (volatile EDMA3_CCRL_Regs *)
+ (drvObject->gblCfgParams.globalRegs);
+ }
+
+ if (EDMA3_DRV_SOK == result)
+ {
+ assert (channelId <= edma3_log_ch_max_val [edma3Id]);
+ }
+
+ if (EDMA3_DRV_SOK == result)
+ {
+
+ /**
+ * Disable any ongoing transfer on the channel, if transfer was
+ * enabled earlier.
+ */
+ if (EDMA3_DRV_TRIG_MODE_NONE !=
+ edma3DrvChBoundRes[edma3Id][channelId].trigMode)
+ {
+ result = EDMA3_DRV_disableTransfer(hEdma, channelId,
+ edma3DrvChBoundRes[edma3Id][channelId].trigMode);
+ }
+ }
+
+ if (EDMA3_DRV_SOK == result)
+ {
+ /*
+ * Unregister the TCC Callback function and disable the interrupts.
+ */
+ if (channelId < drvObject->gblCfgParams.numDmaChannels)
+ {
+ /* DMA channel */
+ channelObj.type = EDMA3_RM_RES_DMA_CHANNEL;
+ channelObj.resId = channelId;
+ }
+ else
+ {
+ /* QDMA channel */
+ channelObj.type = EDMA3_RM_RES_QDMA_CHANNEL;
+ channelObj.resId = channelId - edma3_qdma_ch_min_val[edma3Id];
+ }
+
+ result = EDMA3_RM_unregisterTccCb(drvInst->resMgrInstance,
+ (EDMA3_RM_ResDesc *)&channelObj);
+ }
+
+ if (result == EDMA3_RM_SOK)
+ {
+ edma3OsProtectEntry(edma3Id, (int32_t)EDMA3_OS_PROTECT_INTERRUPT, &intState);
+
+ if (channelId <= edma3_dma_ch_max_val [edma3Id])
+ {
+ if((channelId >> 3U) < 8)
+ {
+ /* DMA channel */
+#ifndef EDMA3_PROGRAM_QUEUE_NUM_REGISTER_INIT_TIME
+ /* Remove the channel to Event Queue mapping */
+ globalRegs->DMAQNUM[channelId >> 3U] &=
+ EDMA3_DRV_DMAQNUM_CLR_MASK(channelId);
+#endif
+ /**
+ * If DMA channel to PaRAM Set mapping exists,
+ * remove it too.
+ */
+ if (TRUE == drvObject->gblCfgParams.dmaChPaRAMMapExists)
+ {
+ globalRegs->DCHMAP[channelId] &=
+ EDMA3_RM_DCH_PARAM_CLR_MASK;
+ }
+ }
+ else
+ {
+ result = EDMA3_DRV_E_INVALID_PARAM;
+ }
+ }
+ else
+ {
+ /* QDMA channel */
+#ifndef EDMA3_PROGRAM_QUEUE_NUM_REGISTER_INIT_TIME
+ /* Remove the channel to Event Queue mapping */
+ globalRegs->QDMAQNUM = (globalRegs->QDMAQNUM) &
+ (EDMA3_DRV_QDMAQNUM_CLR_MASK(channelId-edma3_qdma_ch_min_val[edma3Id]));
+#endif
+ /* Remove the channel to PARAM set mapping */
+ /* Unmap PARAM Set Number for specified channelId */
+ globalRegs->QCHMAP[channelId-edma3_qdma_ch_min_val[edma3Id]] &=
+ EDMA3_RM_QCH_PARAM_CLR_MASK;
+
+ /* Reset the Trigger Word */
+ globalRegs->QCHMAP[channelId-edma3_qdma_ch_min_val[edma3Id]] &=
+ EDMA3_RM_QCH_TRWORD_CLR_MASK;
+ }
+
+ edma3OsProtectExit(edma3Id,
+ (int32_t)EDMA3_OS_PROTECT_INTERRUPT,
+ intState);
+ }
+
+ return result;
+ }
+uint32_t EDMA3_DRV_getVersion (void)
+{
+ return EDMA3_LLD_DRV_VERSION_ID;
+}
+
+const char* EDMA3_DRV_getVersionStr (void)
+{
+ return edma3LldVersionStr;
+}
+/* Definitions of Local functions - End */
+
+/* End of File */