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<div class="contents">
-<h1>EDMA3_RM_InstanceInitConfig Struct Reference<br/>
+<h1>EDMA3_RM_InstanceInitConfig Struct Reference<br>
<small>
[<a class="el" href="group___e_d_m_a3___l_l_d___r_m___d_a_t_a_s_t_r_u_c_t.html">EDMA3 Resource Manager Data Structures</a>]</small>
-</h1><!-- doxytag: class="EDMA3_RM_InstanceInitConfig" -->
-<p>Init-time Region Specific Configuration structure for EDMA3 RM, to provide region specific Information.
-<a href="#_details">More...</a></p>
-
-<p><code>#include <edma3_rm.h></code></p>
+</h1><!-- doxytag: class="EDMA3_RM_InstanceInitConfig" -->Init-time Region Specific Configuration structure for EDMA3 RM, to provide region specific Information.
+<a href="#_details">More...</a>
+<p>
+<code>#include <edma3_rm.h></code>
+<p>
<table border="0" cellpadding="0" cellspacing="0">
-<tr><td colspan="2"><h2>Data Fields</h2></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#a195712f03e6c92f0a386dd036422f956">ownPaRAMSets</a> [EDMA3_MAX_PARAM_DWRDS]</td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#afea6ae753bce07d64d92f6521bb489e5">ownDmaChannels</a> [EDMA3_MAX_DMA_CHAN_DWRDS]</td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#a836f8f25e8a2e01d6649034b7cc92d50">ownQdmaChannels</a> [EDMA3_MAX_QDMA_CHAN_DWRDS]</td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#a38b3b42404f41e978c3b682ccf63fa8f">ownTccs</a> [EDMA3_MAX_TCC_DWRDS]</td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#ab97d5476ee84765b1cb26216af673cfc">resvdPaRAMSets</a> [EDMA3_MAX_PARAM_DWRDS]</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">Reserved PaRAM Sets. <a href="#ab97d5476ee84765b1cb26216af673cfc"></a><br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#a6df76275220d03b4b42c9161b4d670ff">resvdDmaChannels</a> [EDMA3_MAX_DMA_CHAN_DWRDS]</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">Reserved DMA channels. <a href="#a6df76275220d03b4b42c9161b4d670ff"></a><br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#ae7909518f9ba93b32c496193e797bf3b">resvdQdmaChannels</a> [EDMA3_MAX_QDMA_CHAN_DWRDS]</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">Reserved QDMA channels. <a href="#ae7909518f9ba93b32c496193e797bf3b"></a><br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#a7996562a8045cf6b7f33e40aa9b49313">resvdTccs</a> [EDMA3_MAX_TCC_DWRDS]</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">Reserved TCCs. <a href="#a7996562a8045cf6b7f33e40aa9b49313"></a><br/></td></tr>
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#195712f03e6c92f0a386dd036422f956">ownPaRAMSets</a> [EDMA3_MAX_PARAM_DWRDS]</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#fea6ae753bce07d64d92f6521bb489e5">ownDmaChannels</a> [EDMA3_MAX_DMA_CHAN_DWRDS]</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#836f8f25e8a2e01d6649034b7cc92d50">ownQdmaChannels</a> [EDMA3_MAX_QDMA_CHAN_DWRDS]</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#38b3b42404f41e978c3b682ccf63fa8f">ownTccs</a> [EDMA3_MAX_TCC_DWRDS]</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#b97d5476ee84765b1cb26216af673cfc">resvdPaRAMSets</a> [EDMA3_MAX_PARAM_DWRDS]</td></tr>
+
+<tr><td class="mdescLeft"> </td><td class="mdescRight">Reserved PaRAM Sets. <a href="#b97d5476ee84765b1cb26216af673cfc"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#6df76275220d03b4b42c9161b4d670ff">resvdDmaChannels</a> [EDMA3_MAX_DMA_CHAN_DWRDS]</td></tr>
+
+<tr><td class="mdescLeft"> </td><td class="mdescRight">Reserved DMA channels. <a href="#6df76275220d03b4b42c9161b4d670ff"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#e7909518f9ba93b32c496193e797bf3b">resvdQdmaChannels</a> [EDMA3_MAX_QDMA_CHAN_DWRDS]</td></tr>
+
+<tr><td class="mdescLeft"> </td><td class="mdescRight">Reserved QDMA channels. <a href="#e7909518f9ba93b32c496193e797bf3b"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#7996562a8045cf6b7f33e40aa9b49313">resvdTccs</a> [EDMA3_MAX_TCC_DWRDS]</td></tr>
+
+<tr><td class="mdescLeft"> </td><td class="mdescRight">Reserved TCCs. <a href="#7996562a8045cf6b7f33e40aa9b49313"></a><br></td></tr>
</table>
-<hr/><a name="_details"></a><h2>Detailed Description</h2>
-<p>Init-time Region Specific Configuration structure for EDMA3 RM, to provide region specific Information. </p>
-<p>This configuration structure is used to specify which EDMA3 resources are owned and reserved by the EDMA3 RM instance. This configuration structure is shadow region specific and will be provided by the user at run-time while calling EDMA3_RM_open ().</p>
-<p>Owned resources: ****************</p>
-<p>EDMA3 RM Instances are tied to different shadow regions and hence different masters. Regions could be:</p>
-<p>a) ARM, b) DSP, c) IMCOP (Imaging Co-processor) etc.</p>
-<p>User can assign each EDMA3 resource to a shadow region using this structure. In this way, user specifies which resources are owned by the specific EDMA3 RM Instance. This assignment should also ensure that the same resource is not assigned to more than one shadow regions (unless desired in that way). Any assignment not following the above mentioned approach may have catastrophic consequences.</p>
-<p>Reserved resources: *******************</p>
-<p>During EDMA3 RM initialization, user can reserve some of the EDMA3 resources for future use, by specifying which resources to reserve in the configuration data structure. These (critical) resources are reserved in advance so that they should not be allocated to someone else and thus could be used in future for some specific purpose.</p>
-<p>User can request different EDMA3 resources using two methods: a) By passing the resource type and the actual resource id, b) By passing the resource type and ANY as resource id</p>
-<p>For e.g. to request DMA channel 31, user will pass 31 as the resource id. But to request ANY available DMA channel (mainly used for memory-to-memory data transfer operations), user will pass EDMA3_DRV_DMA_CHANNEL_ANY as the resource id.</p>
-<p>During initialization, user may have reserved some of the DMA channels for some specific purpose (mainly for peripherals using EDMA). These reserved DMA channels then will not be returned when user requests ANY as the resource id.</p>
-<p>Same logic applies for QDMA channels and TCCs.</p>
-<p>For PaRAM Set, there is one difference. If the DMA channels are one-to-one tied to their respective PaRAM Sets (i.e. user cannot 'choose' the PaRAM Set for a particular DMA channel), EDMA3 RM automatically reserves all those PaRAM Sets which are tied to the DMA channels. Then those PaRAM Sets would not be returned when user requests for ANY PaRAM Set (specifically for linking purpose). This is done in order to avoid allocating the PaRAM Set, tied to a particular DMA channel, for linking purpose. If this constraint is not there, that DMA channel thus could not be used at all, because of the unavailability of the desired PaRAM Set. </p>
-<hr/><h2>Field Documentation</h2>
-<a class="anchor" id="a195712f03e6c92f0a386dd036422f956"></a><!-- doxytag: member="EDMA3_RM_InstanceInitConfig::ownPaRAMSets" ref="a195712f03e6c92f0a386dd036422f956" args="[EDMA3_MAX_PARAM_DWRDS]" -->
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+Init-time Region Specific Configuration structure for EDMA3 RM, to provide region specific Information.
+<p>
+This configuration structure is used to specify which EDMA3 resources are owned and reserved by the EDMA3 RM instance. This configuration structure is shadow region specific and will be provided by the user at run-time while calling EDMA3_RM_open ().<p>
+Owned resources: ****************<p>
+EDMA3 RM Instances are tied to different shadow regions and hence different masters. Regions could be:<p>
+a) ARM, b) DSP, c) IMCOP (Imaging Co-processor) etc.<p>
+User can assign each EDMA3 resource to a shadow region using this structure. In this way, user specifies which resources are owned by the specific EDMA3 RM Instance. This assignment should also ensure that the same resource is not assigned to more than one shadow regions (unless desired in that way). Any assignment not following the above mentioned approach may have catastrophic consequences.<p>
+Reserved resources: *******************<p>
+During EDMA3 RM initialization, user can reserve some of the EDMA3 resources for future use, by specifying which resources to reserve in the configuration data structure. These (critical) resources are reserved in advance so that they should not be allocated to someone else and thus could be used in future for some specific purpose.<p>
+User can request different EDMA3 resources using two methods: a) By passing the resource type and the actual resource id, b) By passing the resource type and ANY as resource id<p>
+For e.g. to request DMA channel 31, user will pass 31 as the resource id. But to request ANY available DMA channel (mainly used for memory-to-memory data transfer operations), user will pass EDMA3_DRV_DMA_CHANNEL_ANY as the resource id.<p>
+During initialization, user may have reserved some of the DMA channels for some specific purpose (mainly for peripherals using EDMA). These reserved DMA channels then will not be returned when user requests ANY as the resource id.<p>
+Same logic applies for QDMA channels and TCCs.<p>
+For PaRAM Set, there is one difference. If the DMA channels are one-to-one tied to their respective PaRAM Sets (i.e. user cannot 'choose' the PaRAM Set for a particular DMA channel), EDMA3 RM automatically reserves all those PaRAM Sets which are tied to the DMA channels. Then those PaRAM Sets would not be returned when user requests for ANY PaRAM Set (specifically for linking purpose). This is done in order to avoid allocating the PaRAM Set, tied to a particular DMA channel, for linking purpose. If this constraint is not there, that DMA channel thus could not be used at all, because of the unavailability of the desired PaRAM Set. <hr><h2>Field Documentation</h2>
+<a class="anchor" name="195712f03e6c92f0a386dd036422f956"></a><!-- doxytag: member="EDMA3_RM_InstanceInitConfig::ownPaRAMSets" ref="195712f03e6c92f0a386dd036422f956" args="[EDMA3_MAX_PARAM_DWRDS]" -->
<div class="memitem">
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- <td class="memname">unsigned int <a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#a195712f03e6c92f0a386dd036422f956">EDMA3_RM_InstanceInitConfig::ownPaRAMSets</a>[EDMA3_MAX_PARAM_DWRDS]</td>
+ <td class="memname">unsigned int <a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#195712f03e6c92f0a386dd036422f956">EDMA3_RM_InstanceInitConfig::ownPaRAMSets</a>[EDMA3_MAX_PARAM_DWRDS] </td>
</tr>
</table>
</div>
<div class="memdoc">
-<p>PaRAM Sets owned by the EDMA3 RM Instance. </p>
+<p>
+PaRAM Sets owned by the EDMA3 RM Instance.
</div>
-</div>
-<a class="anchor" id="afea6ae753bce07d64d92f6521bb489e5"></a><!-- doxytag: member="EDMA3_RM_InstanceInitConfig::ownDmaChannels" ref="afea6ae753bce07d64d92f6521bb489e5" args="[EDMA3_MAX_DMA_CHAN_DWRDS]" -->
+</div><p>
+<a class="anchor" name="fea6ae753bce07d64d92f6521bb489e5"></a><!-- doxytag: member="EDMA3_RM_InstanceInitConfig::ownDmaChannels" ref="fea6ae753bce07d64d92f6521bb489e5" args="[EDMA3_MAX_DMA_CHAN_DWRDS]" -->
<div class="memitem">
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- <td class="memname">unsigned int <a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#afea6ae753bce07d64d92f6521bb489e5">EDMA3_RM_InstanceInitConfig::ownDmaChannels</a>[EDMA3_MAX_DMA_CHAN_DWRDS]</td>
+ <td class="memname">unsigned int <a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#fea6ae753bce07d64d92f6521bb489e5">EDMA3_RM_InstanceInitConfig::ownDmaChannels</a>[EDMA3_MAX_DMA_CHAN_DWRDS] </td>
</tr>
</table>
</div>
<div class="memdoc">
-<p>DMA Channels owned by the EDMA3 RM Instance. </p>
+<p>
+DMA Channels owned by the EDMA3 RM Instance.
</div>
-</div>
-<a class="anchor" id="a836f8f25e8a2e01d6649034b7cc92d50"></a><!-- doxytag: member="EDMA3_RM_InstanceInitConfig::ownQdmaChannels" ref="a836f8f25e8a2e01d6649034b7cc92d50" args="[EDMA3_MAX_QDMA_CHAN_DWRDS]" -->
+</div><p>
+<a class="anchor" name="836f8f25e8a2e01d6649034b7cc92d50"></a><!-- doxytag: member="EDMA3_RM_InstanceInitConfig::ownQdmaChannels" ref="836f8f25e8a2e01d6649034b7cc92d50" args="[EDMA3_MAX_QDMA_CHAN_DWRDS]" -->
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- <td class="memname">unsigned int <a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#a836f8f25e8a2e01d6649034b7cc92d50">EDMA3_RM_InstanceInitConfig::ownQdmaChannels</a>[EDMA3_MAX_QDMA_CHAN_DWRDS]</td>
+ <td class="memname">unsigned int <a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#836f8f25e8a2e01d6649034b7cc92d50">EDMA3_RM_InstanceInitConfig::ownQdmaChannels</a>[EDMA3_MAX_QDMA_CHAN_DWRDS] </td>
</tr>
</table>
</div>
<div class="memdoc">
-<p>QDMA Channels owned by the EDMA3 RM Instance. </p>
+<p>
+QDMA Channels owned by the EDMA3 RM Instance.
</div>
-</div>
-<a class="anchor" id="a38b3b42404f41e978c3b682ccf63fa8f"></a><!-- doxytag: member="EDMA3_RM_InstanceInitConfig::ownTccs" ref="a38b3b42404f41e978c3b682ccf63fa8f" args="[EDMA3_MAX_TCC_DWRDS]" -->
+</div><p>
+<a class="anchor" name="38b3b42404f41e978c3b682ccf63fa8f"></a><!-- doxytag: member="EDMA3_RM_InstanceInitConfig::ownTccs" ref="38b3b42404f41e978c3b682ccf63fa8f" args="[EDMA3_MAX_TCC_DWRDS]" -->
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- <td class="memname">unsigned int <a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#a38b3b42404f41e978c3b682ccf63fa8f">EDMA3_RM_InstanceInitConfig::ownTccs</a>[EDMA3_MAX_TCC_DWRDS]</td>
+ <td class="memname">unsigned int <a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#38b3b42404f41e978c3b682ccf63fa8f">EDMA3_RM_InstanceInitConfig::ownTccs</a>[EDMA3_MAX_TCC_DWRDS] </td>
</tr>
</table>
</div>
<div class="memdoc">
-<p>TCCs owned by the EDMA3 RM Instance. </p>
+<p>
+TCCs owned by the EDMA3 RM Instance.
</div>
-</div>
-<a class="anchor" id="ab97d5476ee84765b1cb26216af673cfc"></a><!-- doxytag: member="EDMA3_RM_InstanceInitConfig::resvdPaRAMSets" ref="ab97d5476ee84765b1cb26216af673cfc" args="[EDMA3_MAX_PARAM_DWRDS]" -->
+</div><p>
+<a class="anchor" name="b97d5476ee84765b1cb26216af673cfc"></a><!-- doxytag: member="EDMA3_RM_InstanceInitConfig::resvdPaRAMSets" ref="b97d5476ee84765b1cb26216af673cfc" args="[EDMA3_MAX_PARAM_DWRDS]" -->
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- <td class="memname">unsigned int <a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#ab97d5476ee84765b1cb26216af673cfc">EDMA3_RM_InstanceInitConfig::resvdPaRAMSets</a>[EDMA3_MAX_PARAM_DWRDS]</td>
+ <td class="memname">unsigned int <a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#b97d5476ee84765b1cb26216af673cfc">EDMA3_RM_InstanceInitConfig::resvdPaRAMSets</a>[EDMA3_MAX_PARAM_DWRDS] </td>
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</table>
</div>
<div class="memdoc">
-<p>Reserved PaRAM Sets. </p>
-<p>PaRAM Sets reserved during initialization for future use. These will not be given when user requests for ANY available PaRAM Set using 'EDMA3_RM_PARAM_ANY' as resource/channel id. </p>
-
+<p>
+Reserved PaRAM Sets.
+<p>
+PaRAM Sets reserved during initialization for future use. These will not be given when user requests for ANY available PaRAM Set using 'EDMA3_RM_PARAM_ANY' as resource/channel id.
</div>
-</div>
-<a class="anchor" id="a6df76275220d03b4b42c9161b4d670ff"></a><!-- doxytag: member="EDMA3_RM_InstanceInitConfig::resvdDmaChannels" ref="a6df76275220d03b4b42c9161b4d670ff" args="[EDMA3_MAX_DMA_CHAN_DWRDS]" -->
+</div><p>
+<a class="anchor" name="6df76275220d03b4b42c9161b4d670ff"></a><!-- doxytag: member="EDMA3_RM_InstanceInitConfig::resvdDmaChannels" ref="6df76275220d03b4b42c9161b4d670ff" args="[EDMA3_MAX_DMA_CHAN_DWRDS]" -->
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- <td class="memname">unsigned int <a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#a6df76275220d03b4b42c9161b4d670ff">EDMA3_RM_InstanceInitConfig::resvdDmaChannels</a>[EDMA3_MAX_DMA_CHAN_DWRDS]</td>
+ <td class="memname">unsigned int <a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#6df76275220d03b4b42c9161b4d670ff">EDMA3_RM_InstanceInitConfig::resvdDmaChannels</a>[EDMA3_MAX_DMA_CHAN_DWRDS] </td>
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</div>
<div class="memdoc">
-<p>Reserved DMA channels. </p>
-<p>DMA channels reserved during initialization for future use. These will not be given when user requests for ANY available DMA channel using 'EDMA3_RM_DMA_CHANNEL_ANY' as resource/channel id. </p>
-
+<p>
+Reserved DMA channels.
+<p>
+DMA channels reserved during initialization for future use. These will not be given when user requests for ANY available DMA channel using 'EDMA3_RM_DMA_CHANNEL_ANY' as resource/channel id.
</div>
-</div>
-<a class="anchor" id="ae7909518f9ba93b32c496193e797bf3b"></a><!-- doxytag: member="EDMA3_RM_InstanceInitConfig::resvdQdmaChannels" ref="ae7909518f9ba93b32c496193e797bf3b" args="[EDMA3_MAX_QDMA_CHAN_DWRDS]" -->
+</div><p>
+<a class="anchor" name="e7909518f9ba93b32c496193e797bf3b"></a><!-- doxytag: member="EDMA3_RM_InstanceInitConfig::resvdQdmaChannels" ref="e7909518f9ba93b32c496193e797bf3b" args="[EDMA3_MAX_QDMA_CHAN_DWRDS]" -->
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<tr>
- <td class="memname">unsigned int <a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#ae7909518f9ba93b32c496193e797bf3b">EDMA3_RM_InstanceInitConfig::resvdQdmaChannels</a>[EDMA3_MAX_QDMA_CHAN_DWRDS]</td>
+ <td class="memname">unsigned int <a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#e7909518f9ba93b32c496193e797bf3b">EDMA3_RM_InstanceInitConfig::resvdQdmaChannels</a>[EDMA3_MAX_QDMA_CHAN_DWRDS] </td>
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</table>
</div>
<div class="memdoc">
-<p>Reserved QDMA channels. </p>
-<p>QDMA channels reserved during initialization for future use. These will not be given when user requests for ANY available QDMA channel using 'EDMA3_RM_QDMA_CHANNEL_ANY' as resource/channel id. </p>
-
-</div>
+<p>
+Reserved QDMA channels.
+<p>
+QDMA channels reserved during initialization for future use. These will not be given when user requests for ANY available QDMA channel using 'EDMA3_RM_QDMA_CHANNEL_ANY' as resource/channel id.
</div>
-<a class="anchor" id="a7996562a8045cf6b7f33e40aa9b49313"></a><!-- doxytag: member="EDMA3_RM_InstanceInitConfig::resvdTccs" ref="a7996562a8045cf6b7f33e40aa9b49313" args="[EDMA3_MAX_TCC_DWRDS]" -->
+</div><p>
+<a class="anchor" name="7996562a8045cf6b7f33e40aa9b49313"></a><!-- doxytag: member="EDMA3_RM_InstanceInitConfig::resvdTccs" ref="7996562a8045cf6b7f33e40aa9b49313" args="[EDMA3_MAX_TCC_DWRDS]" -->
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- <td class="memname">unsigned int <a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#a7996562a8045cf6b7f33e40aa9b49313">EDMA3_RM_InstanceInitConfig::resvdTccs</a>[EDMA3_MAX_TCC_DWRDS]</td>
+ <td class="memname">unsigned int <a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#7996562a8045cf6b7f33e40aa9b49313">EDMA3_RM_InstanceInitConfig::resvdTccs</a>[EDMA3_MAX_TCC_DWRDS] </td>
</tr>
</table>
</div>
<div class="memdoc">
-<p>Reserved TCCs. </p>
-<p>TCCs reserved during initialization for future use. These will not be given when user requests for ANY available TCC using 'EDMA3_RM_TCC_ANY' as resource/channel id. </p>
-
-</div>
+<p>
+Reserved TCCs.
+<p>
+TCCs reserved during initialization for future use. These will not be given when user requests for ANY available TCC using 'EDMA3_RM_TCC_ANY' as resource/channel id.
</div>
-<hr/>The documentation for this struct was generated from the following file:<ul>
-<li>edma3_rm.h</li>
-</ul>
+</div><p>
+<hr>The documentation for this struct was generated from the following file:<ul>
+<li>edma3_rm.h</ul>
</div>
-<hr size="1"/><address style="text-align: right;"><small>Generated on Tue Dec 1 15:24:06 2009 for EDMA3 Resource Manager by
+<hr size="1"><address style="text-align: right;"><small>Generated on Wed Apr 7 12:02:44 2010 for EDMA3 Resource Manager by
<a href="http://www.doxygen.org/index.html">
-<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.6.1 </small></address>
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.5.5 </small></address>
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