-/******************************************************************************
-**+-------------------------------------------------------------------------+**
-**| **** |**
-**| **** |**
-**| ******o*** |**
-**| ********_///_**** |**
-**| ***** /_//_/ **** |**
-**| ** ** (__/ **** |**
-**| ********* |**
-**| **** |**
-**| *** |**
-**| |**
-**| Copyright (c) 1998-2006 Texas Instruments Incorporated |**
-**| ALL RIGHTS RESERVED |**
-**| |**
-**| Permission is hereby granted to licensees of Texas Instruments |**
-**| Incorporated (TI) products to use this computer program for the sole |**
-**| purpose of implementing a licensee product based on TI products. |**
-**| No other rights to reproduce, use, or disseminate this computer |**
-**| program, whether in part or in whole, are granted. |**
-**| |**
-**| TI makes no representation or warranties with respect to the |**
-**| performance of this computer program, and specifically disclaims |**
-**| any responsibility for any damages, special or consequential, |**
-**| connected with the use of this program. |**
-**| |**
-**+-------------------------------------------------------------------------+**
-******************************************************************************/
-
-/** \file edma3_common.h
- \brief EDMA3 Common header provides generic defines/typedefs and
- debugging info.
-
- This file contains the generic defines and typedefs and the debugging
- info that are common across interfaces of EDMA Res Mgr and EDMA Driver
- and visible to the application.
-
- (C) Copyright 2006, Texas Instruments, Inc
+/*
+ * edma3_common.h
+ *
+ * EDMA3 common header providing generic defines/typedefs and debugging info.
+ *
+ * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
- */
+#ifndef EDMA3_COMMON_H_
+#define EDMA3_COMMON_H_
-#ifndef _EDMA3_COMMON_H_
-#define _EDMA3_COMMON_H_
+/***************************************************************\
+* Standard Definition Header File For Null Definition *
+\***************************************************************/
+#include <stddef.h>
#ifdef __cplusplus
extern "C" {
#endif
-
/** define to enable/disable Resource Manager debug messages*/
-#define EDMA3_RM_DEBUG
-#undef EDMA3_RM_DEBUG
+/* #define EDMA3_RM_DEBUG */
/** define to enable/disable EDMA3 Driver debug messages*/
-#define EDMA3_DRV_DEBUG
-#undef EDMA3_DRV_DEBUG
-
+/* #define EDMA3_DRV_DEBUG */
/** Debug mechanism used for Resource Manager */
#ifdef EDMA3_RM_DEBUG
#define EDMA3_DRV_PRINTF printf
#endif
-
/** Defines for boolean variables */
#ifndef TRUE
/** TRUE */
- #define TRUE (1u)
+ #define TRUE (1U)
/** FALSE */
- #define FALSE (0u)
+ #define FALSE (0U)
#endif
-
-/** Define for NULL values*/
-#ifndef NULL
-#define NULL 0u
-#endif
-
-
/** EDMA3_RM Result - return value of a function */
-typedef int EDMA3_RM_Result;
+typedef int32_t EDMA3_RM_Result;
/** EDMA3_DRV Result - return value of a function */
-typedef int EDMA3_DRV_Result;
-
+typedef int32_t EDMA3_DRV_Result;
/** EDMA3 Resource Manager Result OK */
-#define EDMA3_RM_SOK (0u)
+#define EDMA3_RM_SOK (0)
/** EDMA3 Driver Result OK */
-#define EDMA3_DRV_SOK (0u)
-
+#define EDMA3_DRV_SOK (0)
/**
* EDMA3 Resource Manager Handle.
*/
typedef void *EDMA3_DRV_Handle;
-
/**
* OS specific Semaphore Handle.
* Used to acquire/free the semaphore, used for sharing of resources
/** Blocking call without timeout */
#define EDMA3_OSSEM_NO_TIMEOUT (-1)
-
/**
* Defines used to support the maximum resources supported
* by the EDMA3 controller. These are used to allocate the maximum
* Manager.
*/
/** Maximum EDMA3 Controllers on the SoC */
-#define EDMA3_MAX_EDMA3_INSTANCES (1u)
+#define EDMA3_MAX_EDMA3_INSTANCES (5U)
/** Maximum DMA channels supported by the EDMA3 Controller */
-#define EDMA3_MAX_DMA_CH (64u)
+#define EDMA3_MAX_DMA_CH (64U)
/** Maximum QDMA channels supported by the EDMA3 Controller */
-#define EDMA3_MAX_QDMA_CH (8u)
+#define EDMA3_MAX_QDMA_CH (8U)
/** Maximum PaRAM Sets supported by the EDMA3 Controller */
-#define EDMA3_MAX_PARAM_SETS (512u)
+#define EDMA3_MAX_PARAM_SETS (512U)
/** Maximum Logical channels supported by the EDMA3 Package */
#define EDMA3_MAX_LOGICAL_CH (EDMA3_MAX_DMA_CH + \
EDMA3_MAX_PARAM_SETS + \
EDMA3_MAX_QDMA_CH)
/** Maximum TCCs (Interrupt Channels) supported by the EDMA3 Controller */
-#define EDMA3_MAX_TCC (64u)
+#define EDMA3_MAX_TCC (64U)
/** Maximum Event Queues supported by the EDMA3 Controller */
-#define EDMA3_MAX_EVT_QUE (8u)
+#define EDMA3_MAX_EVT_QUE (8U)
/** Maximum Transfer Controllers supported by the EDMA3 Controller */
-#define EDMA3_MAX_TC (8u)
+#define EDMA3_MAX_TC (8U)
/** Maximum Shadow Regions supported by the EDMA3 Controller */
-#define EDMA3_MAX_REGIONS (8u)
+#define EDMA3_MAX_REGIONS (8U)
/**
* Maximum Words (4-bytes region) required for the book-keeping information
* specific to the maximum possible DMA channels.
*/
-#define EDMA3_MAX_DMA_CHAN_DWRDS (EDMA3_MAX_DMA_CH / 32u)
+#define EDMA3_MAX_DMA_CHAN_DWRDS (EDMA3_MAX_DMA_CH / 32U)
/**
* Maximum Words (4-bytes region) required for the book-keeping information
* specific to the maximum possible QDMA channels.
*/
-#define EDMA3_MAX_QDMA_CHAN_DWRDS (1u)
+#define EDMA3_MAX_QDMA_CHAN_DWRDS (1U)
/**
* Maximum Words (4-bytes region) required for the book-keeping information
* specific to the maximum possible PaRAM Sets.
*/
-#define EDMA3_MAX_PARAM_DWRDS (EDMA3_MAX_PARAM_SETS / 32u)
+#define EDMA3_MAX_PARAM_DWRDS (EDMA3_MAX_PARAM_SETS / 32U)
/**
* Maximum Words (4-bytes region) required for the book-keeping information
* specific to the maximum possible TCCs.
*/
-#define EDMA3_MAX_TCC_DWRDS (EDMA3_MAX_TCC / 32u)
-
-
+#define EDMA3_MAX_TCC_DWRDS (EDMA3_MAX_TCC / 32U)
/**
* EDMA3 ISRs which need to be registered with the underlying OS by the user
* (Not all TC error ISRs need to be registered, register only for the
* available Transfer Controllers).
*/
-
/** EDMA3 Completion Handler ISR Routine */
-extern void lisrEdma3ComplHandler0 (unsigned int arg);
+extern void lisrEdma3ComplHandler0 (uint32_t edma3InstanceId);
/** EDMA3 CC Error Interrupt Handler ISR Routine */
-extern void lisrEdma3CCErrHandler0 (unsigned int arg);
+extern void lisrEdma3CCErrHandler0 (uint32_t edma3InstanceId);
/** EDMA3 TC0 Error Interrupt Handler ISR Routine */
-extern void lisrEdma3TC0ErrHandler0(unsigned int arg);
+extern void lisrEdma3TC0ErrHandler0(uint32_t edma3InstanceId);
/** EDMA3 TC1 Error Interrupt Handler ISR Routine */
-extern void lisrEdma3TC1ErrHandler0(unsigned int arg);
+extern void lisrEdma3TC1ErrHandler0(uint32_t edma3InstanceId);
/** EDMA3 TC2 Error Interrupt Handler ISR Routine */
-extern void lisrEdma3TC2ErrHandler0(unsigned int arg);
+extern void lisrEdma3TC2ErrHandler0(uint32_t edma3InstanceId);
/** EDMA3 TC3 Error Interrupt Handler ISR Routine */
-extern void lisrEdma3TC3ErrHandler0(unsigned int arg);
+extern void lisrEdma3TC3ErrHandler0(uint32_t edma3InstanceId);
/** EDMA3 TC4 Error Interrupt Handler ISR Routine */
-extern void lisrEdma3TC4ErrHandler0(unsigned int arg);
+extern void lisrEdma3TC4ErrHandler0(uint32_t edma3InstanceId);
/** EDMA3 TC5 Error Interrupt Handler ISR Routine */
-extern void lisrEdma3TC5ErrHandler0(unsigned int arg);
+extern void lisrEdma3TC5ErrHandler0(uint32_t edma3InstanceId);
/** EDMA3 TC6 Error Interrupt Handler ISR Routine */
-extern void lisrEdma3TC6ErrHandler0(unsigned int arg);
+extern void lisrEdma3TC6ErrHandler0(uint32_t edma3InstanceId);
/** EDMA3 TC7 Error Interrupt Handler ISR Routine */
-extern void lisrEdma3TC7ErrHandler0(unsigned int arg);
-
-
+extern void lisrEdma3TC7ErrHandler0(uint32_t edma3InstanceId);
/**
* Defines for the level of OS protection needed when calling
* edma3OsProtectEntry()
*/
-
/** Protection from All Interrupts required */
#define EDMA3_OS_PROTECT_INTERRUPT 1
/** Protection from scheduling required */
/** Protection from EDMA3 TC Error Interrupt required */
#define EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR 5
-
-
/**
* Critical section entry and exit functions (OS dependent) should be
* implemented by the application for proper linking with the EDMA3 Driver
* initialization routine or by the user itself.
*/
-/** \fn extern void edma3OsProtectEntry (int level, unsigned int *intState);
+/**
* \brief EDMA3 OS Protect Entry
*
* This function saves the current state of protection in 'intState'
* For EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR, '*intState' specifies the
* Transfer Controller number whose interrupt needs to be disabled.
*
+ * \param edma3InstanceId is EDMA3 hardware instance id.
* \param level is numeric identifier of the desired degree of protection.
* \param intState is memory location where current state of protection is
* saved for future use while restoring it via edma3OsProtectExit() (Only
*
* \return None
*/
-extern void edma3OsProtectEntry (int level, unsigned int *intState);
-
+extern void edma3OsProtectEntry (uint32_t edma3InstanceId,
+ int32_t level,
+ uint32_t *intState);
-/** \fn extern void edma3OsProtectExit (int level, unsigned int intState);
+/**
* \brief EDMA3 OS Protect Exit
*
* This function undoes the protection enforced to original state
* For EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR, 'intState' specifies the
* Transfer Controller number whose interrupt needs to be enabled.
*
+ * \param edma3InstanceId is EDMA3 hardware instance id.
* \param level is numeric identifier of the desired degree of protection.
* \param intState is original state of protection at time when the
* corresponding edma3OsProtectEntry() was called (Only
*
* \return None
*/
-extern void edma3OsProtectExit (int level, unsigned int intState);
-
+extern void edma3OsProtectExit (uint32_t edma3InstanceId,
+ int32_t level,
+ uint32_t intState);
/**
* Counting Semaphore related functions (OS dependent) should be
* to be provided by the application. Without the definitions being provided,
* the image won\92t get linked properly.
*/
-/** \fn extern EDMA3_DRV_Result edma3OsSemTake (EDMA3_OS_Sem_Handle hSem,
- * int mSecTimeout);
+
+/**
* \brief EDMA3 OS Semaphore Take
*
* This function takes a semaphore token if available.
* \return EDMA3_DRV_Result if successful else a suitable error code
*/
extern EDMA3_DRV_Result edma3OsSemTake (EDMA3_OS_Sem_Handle hSem,
- int mSecTimeout);
+ int32_t mSecTimeout);
-/** \fn extern EDMA3_DRV_Result edma3OsSemGive(EDMA3_OS_Sem_Handle hSem);
+/**
* \brief EDMA3 OS Semaphore Give
*
* This function gives or relinquishes an already
#endif /* extern "C" */
#endif /* _EDMA3_COMMON_H_ */
-