index 2025465ee912c7f3d4a1d1e2aaee3b8e3a81951f..262cd0a8f1388c4eed10b29c266cd8f4458985a7 100755 (executable)
*
*/
-#ifndef _EDMA3_COMMON_H_
-#define _EDMA3_COMMON_H_
+#ifndef EDMA3_COMMON_H_
+#define EDMA3_COMMON_H_
+
+/***************************************************************\
+* Standard Definition Header File For Null Definition *
+\***************************************************************/
+#include <stddef.h>
+
+/***************************************************************\
+* Standard Definition Header File For Bool Datatype *
+\***************************************************************/
+#include <stdbool.h>
#ifdef __cplusplus
extern "C" {
#endif
/** define to enable/disable Resource Manager debug messages*/
-#define EDMA3_RM_DEBUG
-#undef EDMA3_RM_DEBUG
+/* #define EDMA3_RM_DEBUG */
/** define to enable/disable EDMA3 Driver debug messages*/
-#define EDMA3_DRV_DEBUG
-#undef EDMA3_DRV_DEBUG
+/* #define EDMA3_DRV_DEBUG */
/** Debug mechanism used for Resource Manager */
#ifdef EDMA3_RM_DEBUG
/** Defines for boolean variables */
#ifndef TRUE
/** TRUE */
- #define TRUE (1u)
+ #define TRUE (1U)
/** FALSE */
- #define FALSE (0u)
-#endif
-
-/** Define for NULL values*/
-#ifndef NULL
-#define NULL 0u
+ #define FALSE (0U)
#endif
/** EDMA3_RM Result - return value of a function */
typedef int32_t EDMA3_RM_Result;
/** EDMA3_DRV Result - return value of a function */
typedef int32_t EDMA3_DRV_Result;
+/** EDMA3_Result - return value of a function for common functions of DRV and RM */
+typedef int32_t EDMA3_Result;
/** EDMA3 Resource Manager Result OK */
-#define EDMA3_RM_SOK (0u)
+#define EDMA3_RM_SOK (0)
/** EDMA3 Driver Result OK */
-#define EDMA3_DRV_SOK (0u)
+#define EDMA3_DRV_SOK (0)
/**
* EDMA3 Resource Manager Handle.
* Manager.
*/
/** Maximum EDMA3 Controllers on the SoC */
-#define EDMA3_MAX_EDMA3_INSTANCES (5u)
+#define EDMA3_MAX_EDMA3_INSTANCES (5U)
/** Maximum DMA channels supported by the EDMA3 Controller */
-#define EDMA3_MAX_DMA_CH (64u)
+#define EDMA3_MAX_DMA_CH (64U)
/** Maximum QDMA channels supported by the EDMA3 Controller */
-#define EDMA3_MAX_QDMA_CH (8u)
+#define EDMA3_MAX_QDMA_CH (8U)
/** Maximum PaRAM Sets supported by the EDMA3 Controller */
-#define EDMA3_MAX_PARAM_SETS (512u)
+#define EDMA3_MAX_PARAM_SETS (512U)
/** Maximum Logical channels supported by the EDMA3 Package */
#define EDMA3_MAX_LOGICAL_CH (EDMA3_MAX_DMA_CH + \
EDMA3_MAX_PARAM_SETS + \
EDMA3_MAX_QDMA_CH)
/** Maximum TCCs (Interrupt Channels) supported by the EDMA3 Controller */
-#define EDMA3_MAX_TCC (64u)
+#define EDMA3_MAX_TCC (64U)
/** Maximum Event Queues supported by the EDMA3 Controller */
-#define EDMA3_MAX_EVT_QUE (8u)
+#define EDMA3_MAX_EVT_QUE (8U)
/** Maximum Transfer Controllers supported by the EDMA3 Controller */
-#define EDMA3_MAX_TC (8u)
+#define EDMA3_MAX_TC (8U)
/** Maximum Shadow Regions supported by the EDMA3 Controller */
-#define EDMA3_MAX_REGIONS (8u)
+#define EDMA3_MAX_REGIONS (8U)
/**
* Maximum Words (4-bytes region) required for the book-keeping information
* specific to the maximum possible DMA channels.
*/
-#define EDMA3_MAX_DMA_CHAN_DWRDS (EDMA3_MAX_DMA_CH / 32u)
+#define EDMA3_MAX_DMA_CHAN_DWRDS (EDMA3_MAX_DMA_CH / 32U)
/**
* Maximum Words (4-bytes region) required for the book-keeping information
* specific to the maximum possible QDMA channels.
*/
-#define EDMA3_MAX_QDMA_CHAN_DWRDS (1u)
+#define EDMA3_MAX_QDMA_CHAN_DWRDS (1U)
/**
* Maximum Words (4-bytes region) required for the book-keeping information
* specific to the maximum possible PaRAM Sets.
*/
-#define EDMA3_MAX_PARAM_DWRDS (EDMA3_MAX_PARAM_SETS / 32u)
+#define EDMA3_MAX_PARAM_DWRDS (EDMA3_MAX_PARAM_SETS / 32U)
/**
* Maximum Words (4-bytes region) required for the book-keeping information
* specific to the maximum possible TCCs.
*/
-#define EDMA3_MAX_TCC_DWRDS (EDMA3_MAX_TCC / 32u)
+#define EDMA3_MAX_TCC_DWRDS (EDMA3_MAX_TCC / 32U)
/**
* EDMA3 ISRs which need to be registered with the underlying OS by the user
* available Transfer Controllers).
*/
/** EDMA3 Completion Handler ISR Routine */
-extern void lisrEdma3ComplHandler0 (uint32_t arg);
+extern void lisrEdma3ComplHandler0 (uint32_t edma3InstanceId);
/** EDMA3 CC Error Interrupt Handler ISR Routine */
-extern void lisrEdma3CCErrHandler0 (uint32_t arg);
+extern void lisrEdma3CCErrHandler0 (uint32_t edma3InstanceId);
/** EDMA3 TC0 Error Interrupt Handler ISR Routine */
-extern void lisrEdma3TC0ErrHandler0(uint32_t arg);
+extern void lisrEdma3TC0ErrHandler0(uint32_t edma3InstanceId);
/** EDMA3 TC1 Error Interrupt Handler ISR Routine */
-extern void lisrEdma3TC1ErrHandler0(uint32_t arg);
+extern void lisrEdma3TC1ErrHandler0(uint32_t edma3InstanceId);
/** EDMA3 TC2 Error Interrupt Handler ISR Routine */
-extern void lisrEdma3TC2ErrHandler0(uint32_t arg);
+extern void lisrEdma3TC2ErrHandler0(uint32_t edma3InstanceId);
/** EDMA3 TC3 Error Interrupt Handler ISR Routine */
-extern void lisrEdma3TC3ErrHandler0(uint32_t arg);
+extern void lisrEdma3TC3ErrHandler0(uint32_t edma3InstanceId);
/** EDMA3 TC4 Error Interrupt Handler ISR Routine */
-extern void lisrEdma3TC4ErrHandler0(uint32_t arg);
+extern void lisrEdma3TC4ErrHandler0(uint32_t edma3InstanceId);
/** EDMA3 TC5 Error Interrupt Handler ISR Routine */
-extern void lisrEdma3TC5ErrHandler0(uint32_t arg);
+extern void lisrEdma3TC5ErrHandler0(uint32_t edma3InstanceId);
/** EDMA3 TC6 Error Interrupt Handler ISR Routine */
-extern void lisrEdma3TC6ErrHandler0(uint32_t arg);
+extern void lisrEdma3TC6ErrHandler0(uint32_t edma3InstanceId);
/** EDMA3 TC7 Error Interrupt Handler ISR Routine */
-extern void lisrEdma3TC7ErrHandler0(uint32_t arg);
+extern void lisrEdma3TC7ErrHandler0(uint32_t edma3InstanceId);
/**
* Defines for the level of OS protection needed when calling
*
* \return EDMA3_DRV_Result if successful else a suitable error code
*/
-extern EDMA3_DRV_Result edma3OsSemTake (EDMA3_OS_Sem_Handle hSem,
+extern EDMA3_Result edma3OsSemTake (EDMA3_OS_Sem_Handle hSem,
int32_t mSecTimeout);
/**
*
* \return EDMA3_DRV_Result if successful else a suitable error code
*/
-extern EDMA3_DRV_Result edma3OsSemGive(EDMA3_OS_Sem_Handle hSem);
+extern EDMA3_Result edma3OsSemGive(EDMA3_OS_Sem_Handle hSem);
#ifdef __cplusplus
}