[keystone-rtos/edma3_lld.git] / packages / ti / sdo / edma3 / rm / sample / src / platforms / sample_tci6486_cfg.c
diff --git a/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_tci6486_cfg.c b/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_tci6486_cfg.c
index b3b56fb40531033ec64e836bbecad94794185e2b..20721e35429b24fca6c0e7f03152e244b6615d63 100644 (file)
extern cregister volatile unsigned int DNUM;
+#define MAP_LOCAL_TO_GLOBAL_ADDR(addr) ((1<<28)|(DNUM<<24)|(((unsigned int)addr)&0x00ffffff))
/* Determine the processor id by reading DNUM register. */
unsigned short determineProcId()
{
return (unsigned short)DNUM;
}
+signed char* getGlobalAddr(signed char* addr)
+{
+ if (((unsigned int)addr & (unsigned int)0xFF000000) != 0)
+ {
+ return (addr); /* The address is already a global address */
+ }
+
+ return((signed char*)(MAP_LOCAL_TO_GLOBAL_ADDR(addr)));
+}
+
+
/** Whether global configuration required for EDMA3 or not.
* This configuration should be done only once for the EDMA3 hardware by
* any one of the masters (i.e. DSPs).
* on the mapped channel.
*/
{
- 0u, 1u, 2u, 3u,
- 4u, 5u, 6u, 7u,
- 8u, 9u, 10u, 11u,
- 12u, 13u, 14u, 15u,
- 16u, 17u, 18u, 19u,
- 20u, 21u, 22u, 23u,
- 24u, 25u, 26u, 27u,
- 28u, 29u, 30u, 31u,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
* All channels need not be mapped, some can be free also.
*/
{
- 0xFFFFFFFFu,
+ 0x00000000u,
0x00000000u
}
}
@@ -379,7 +391,7 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
/* Resources owned by Region 0 */
/* ownPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x0000FFFFu, 0x00000000u,
+ {0x00000000u, 0x00000000u, 0xFFFFFFFFu, 0x00000000u,
/* 159 128 191 160 223 192 255 224 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 287 256 319 288 351 320 383 352 */
@@ -389,7 +401,7 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
/* ownDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x0000003Fu},
+ {0x0000FFFFu, 0x00000000u},
/* ownQdmaChannels */
/* 31 0 */
@@ -397,12 +409,12 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
/* ownTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x0000003Fu},
+ {0x0000FFFFu, 0x00000000u},
/* Resources reserved by Region 0 */
/* resvdPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
/* 159 128 191 160 223 192 255 224 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 287 256 319 288 351 320 383 352 */
@@ -412,7 +424,7 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
/* resvdDmaChannels */
/* 31 0 63 32 */
- {0xFFFFFFFFu, 0x00000000u},
+ {0x00000000u, 0x00000000u},
/* resvdQdmaChannels */
/* 31 0 */
@@ -420,14 +432,14 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
/* resvdTccs */
/* 31 0 63 32 */
- {0xFFFFFFFFu, 0x00000000u},
+ {0x00000000u, 0x00000000u},
},
{
/* Resources owned by Region 1 */
/* ownPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0xFFFF0000u, 0x00000000u,
+ {0x00000000u, 0x00000000u, 0x00000000u, 0xFFFFFFFFu,
/* 159 128 191 160 223 192 255 224 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 287 256 319 288 351 320 383 352 */
@@ -437,7 +449,7 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
/* ownDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00000FC0u},
+ {0xFFFF0000u, 0x00000000u},
/* ownQdmaChannels */
/* 31 0 */
@@ -445,12 +457,12 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
/* ownTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00000FC0u},
+ {0xFFFF0000u, 0x00000000u},
/* Resources reserved by Region 1 */
/* resvdPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
/* 159 128 191 160 223 192 255 224 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 287 256 319 288 351 320 383 352 */
@@ -460,7 +472,7 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
/* resvdDmaChannels */
/* 31 0 63 32 */
- {0xFFFFFFFFu, 0x00000000u},
+ {0x00000000u, 0x00000000u},
/* resvdQdmaChannels */
/* 31 0 */
@@ -468,16 +480,16 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
/* resvdTccs */
/* 31 0 63 32 */
- {0xFFFFFFFFu, 0x00000000u},
+ {0x00000000u, 0x00000000u},
},
{
/* Resources owned by Region 2 */
/* ownPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0xFFFFFFFFu,
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 159 128 191 160 223 192 255 224 */
- 0x00000003u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
/* 287 256 319 288 351 320 383 352 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 415 384 447 416 479 448 511 480 */
@@ -485,7 +497,7 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
/* ownDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x0003F000u},
+ {0x00000000u, 0x000000FFu},
/* ownQdmaChannels */
/* 31 0 */
@@ -493,12 +505,12 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
/* ownTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x0003F000u},
+ {0x00000000u, 0x000000FFu},
/* Resources reserved by Region 2 */
/* resvdPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
/* 159 128 191 160 223 192 255 224 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 287 256 319 288 351 320 383 352 */
@@ -508,7 +520,7 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
/* resvdDmaChannels */
/* 31 0 63 32 */
- {0xFFFFFFFFu, 0x00000000u},
+ {0x00000000u, 0x00000000u},
/* resvdQdmaChannels */
/* 31 0 */
@@ -516,7 +528,7 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
/* resvdTccs */
/* 31 0 63 32 */
- {0xFFFFFFFFu, 0x00000000u},
+ {0x00000000u, 0x00000000u},
},
{
@@ -525,7 +537,7 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
/* 31 0 63 32 95 64 127 96 */
{0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 159 128 191 160 223 192 255 224 */
- 0xFFFFFFFCu, 0x00000FFFu, 0x00000000u, 0x00000000u,
+ 0x00000000u, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
/* 287 256 319 288 351 320 383 352 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 415 384 447 416 479 448 511 480 */
@@ -533,7 +545,7 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
/* ownDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00FC0000u},
+ {0x00000000u, 0x0000FF00u},
/* ownQdmaChannels */
/* 31 0 */
@@ -541,12 +553,12 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
/* ownTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00FC0000u},
+ {0x00000000u, 0x0000FF00u},
/* Resources reserved by Region 3 */
/* resvdPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
/* 159 128 191 160 223 192 255 224 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 287 256 319 288 351 320 383 352 */
@@ -573,7 +585,7 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
/* 31 0 63 32 95 64 127 96 */
{0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0xFFFFF000u, 0x003FFFFFu, 0x00000000u,
+ 0x00000000u, 0x00000000u, 0xFFFFFFFFu, 0x00000000u,
/* 287 256 319 288 351 320 383 352 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 415 384 447 416 479 448 511 480 */
@@ -581,7 +593,7 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
/* ownDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x0F000000u},
+ {0x00000000u, 0x00FF0000u},
/* ownQdmaChannels */
/* 31 0 */
@@ -589,12 +601,12 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
/* ownTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x0F000000u},
+ {0x00000000u, 0x00FF0000u},
/* Resources reserved by Region 4 */
/* resvdPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
/* 159 128 191 160 223 192 255 224 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 287 256 319 288 351 320 383 352 */
@@ -621,7 +633,7 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
/* 31 0 63 32 95 64 127 96 */
{0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0xFFC00000u, 0xFFFFFFFFu,
+ 0x00000000u, 0x00000000u, 0x00000000u, 0xFFFFFFFFu,
/* 287 256 319 288 351 320 383 352 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 415 384 447 416 479 448 511 480 */
@@ -629,7 +641,7 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
/* ownDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0xF0000000u},
+ {0x00000000u, 0xFF000000u},
/* ownQdmaChannels */
/* 31 0 */
@@ -637,12 +649,12 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
/* ownTccs */
/* 31 0 63 32 */
- {0x00000000u, 0xF0000000u},
+ {0x00000000u, 0xFF000000u},
/* Resources reserved by Region 5 */
/* resvdPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
/* 159 128 191 160 223 192 255 224 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 287 256 319 288 351 320 383 352 */