[keystone-rtos/edma3_lld.git] / packages / ti / sdo / edma3 / rm / sample / src / platforms / sample_tda3xx_cfg.c
diff --git a/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_tda3xx_cfg.c b/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_tda3xx_cfg.c
index 8cc1dd5485d76da2b3e565fa7ca6c7cb5faa3388..6cb142a9c0b5cccafc7885ea07d14b733a059301 100644 (file)
/** Number of Regions */
#define EDMA3_NUM_REGIONS (8U)
+/* EDMA3 configuaration for EVE */
+
+/** Number of PaRAM Sets available */
+#define EDMA3_NUM_PARAMSET_EVE (64U)
+
+/** Number of TCCS available */
+#define EDMA3_NUM_TCC_EVE (16U)
+
+/** Number of DMA Channels available */
+#define EDMA3_NUM_DMA_CHANNELS_EVE (16U)
+
+/** Number of QDMA Channels available */
+#define EDMA3_NUM_QDMA_CHANNELS_EVE (8U)
+
+/** Number of Event Queues available */
+#define EDMA3_NUM_EVTQUE_EVE (2U)
+
+/** Number of Transfer Controllers available */
+#define EDMA3_NUM_TC_EVE (2U)
+
+/** Number of Regions */
+#define EDMA3_NUM_REGIONS_EVE (8U)
+
+
/** Interrupt no. for Transfer Completion */
#define EDMA3_CC_XFER_COMPLETION_INT_DSP (38U)
#define EDMA3_CC_XFER_COMPLETION_INT_IPU_C0 (34U)
{
/* EDMA3 INSTANCE# 2 */
/** Total number of DMA Channels supported by the EDMA3 Controller */
- EDMA3_NUM_DMA_CHANNELS,
+ EDMA3_NUM_DMA_CHANNELS_EVE,
/** Total number of QDMA Channels supported by the EDMA3 Controller */
- EDMA3_NUM_QDMA_CHANNELS,
+ EDMA3_NUM_QDMA_CHANNELS_EVE,
/** Total number of TCCs supported by the EDMA3 Controller */
- EDMA3_NUM_TCC,
+ EDMA3_NUM_TCC_EVE,
/** Total number of PaRAM Sets supported by the EDMA3 Controller */
- EDMA3_NUM_PARAMSET,
+ EDMA3_NUM_PARAMSET_EVE,
/** Total number of Event Queues in the EDMA3 Controller */
- EDMA3_NUM_EVTQUE,
+ EDMA3_NUM_EVTQUE_EVE,
/** Total number of Transfer Controllers (TCs) in the EDMA3 Controller*/
- EDMA3_NUM_TC,
+ EDMA3_NUM_TC_EVE,
/** Number of Regions on this EDMA3 controller */
- EDMA3_NUM_REGIONS,
+ EDMA3_NUM_REGIONS_EVE,
/**
* \brief Channel mapping existence